Blackfin Embedded Processor ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 FEATURES PERIPHERALS Up to 600 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs RISC-like register and instruction model Wide range of operating voltages and flexible booting options Programmable on-chip voltage regulator 400-ball CSP_BGA, RoHS compliant package High speed USB On-the-Go (OTG) with integrated PHY SD/SDIO controller ATA/ATAPI-6 controller Up to 4 synchronous serial ports (SPORTs) Up to 3 serial peripheral interfaces (SPI-compatible) Up to 4 UARTs, two with automatic H/W flow control Up to 2 CAN (controller area network) 2.0B interfaces Up to 2 TWI (2-wire interface) controllers 8- or 16-bit asynchronous host DMA interface Multiple enhanced parallel peripheral interfaces (EPPIs), supporting ITU-R BT.656 video formats and 18-/24-bit LCD connections Media transceiver (MXVR) for connection to a MOST network Pixel compositor for overlays, alpha blending, and color conversion Up to eleven 32-bit timers/counters with PWM support Real-time clock (RTC) and watchdog timer Up/down counter with support for rotary encoder Up to 152 general-purpose I/O (GPIOs) On-chip PLL capable of 0.5× to 64× frequency multiplication Debug/JTAG interface MEMORY Up to 324K bytes of on-chip memory comprised of instruction SRAM/cache; dedicated instruction SRAM; data SRAM/cache; dedicated data SRAM; scratchpad SRAM External sync memory controller supporting either DDR SDRAM or mobile DDR SDRAM External async memory controller supporting 8-/16-bit async memories and burst flash devices NAND flash controller 4 memory-to-memory DMA pairs, 2 with ext. requests Memory management unit providing memory protection Code security with Lockbox secure technology and 128-bit AES/ARC4 data encryption One-time-programmable (OTP) memory VOLTAGE REGULATOR CAN (0-1) JTAG TEST AND EMULATION RTC WATCHDOG TIMER OTP TWI (0-1) PAB 16 B TIMERS(0-10) PORTS HOST DMA INTERRUPTS UART (0-1) COUNTER UART (2-3) L2 SRAM KEYPAD L1 INSTR ROM L1 INSTR SRAM L1 DATA SRAM SPI (2) 32-BIT DMA MXVR DCB 32 EAB 64 DAB1 DEB 32 PORTS SPI (0-1) 32 SPORT (2-3) USB 16-BIT DMA DAB0 EXTERNAL PORT NOR, DDR, MDDR BOOT ROM 16 SPORT (0-1) SD / SDIO ATAPI DDR/MDDR 16 EPPI (0-2) ASYNC 16 NAND FLASH CONTROLLER PIXEL COMPOSITOR Figure 1. ADSP-BF549 Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2010 Analog Devices, Inc. All rights reserved. ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 TABLE OF CONTENTS General Description ................................................. 3 Booting Modes ................................................... 19 Low Power Architecture ......................................... 4 Instruction Set Description .................................... 22 System Integration ................................................ 4 Development Tools .............................................. 23 Blackfin Processor Peripherals ................................. 4 EZ-KIT Lite Evaluation Board ............................. 23 Blackfin Processor Core .......................................... 4 Designing an Emulator-Compatible Processor Board ... 23 Memory Architecture ............................................ 6 MXVR Board Layout Guidelines ............................. 23 DMA Controllers ................................................ 10 Related Documents .............................................. 24 Real-Time Clock ................................................. 11 Lockbox Secure Technology Disclaimer .................... 24 Watchdog Timer ................................................ 12 Pin Descriptions .................................................... 25 Timers ............................................................. 12 Specifications ........................................................ 34 Up/Down Counter and Thumbwheel Interface .......... 12 Operating Conditions ........................................... 34 Serial Ports (SPORTs) .......................................... 12 Electrical Characteristics ....................................... 36 Serial Peripheral Interface (SPI) Ports ...................... 13 Absolute Maximum Ratings ................................... 40 UART Ports (UARTs) .......................................... 13 ESD Sensitivity ................................................... 41 Controller Area Network (CAN) ............................ 13 Package Information ............................................ 41 TWI Controller Interface ...................................... 14 Timing Specifications ........................................... 42 Ports ................................................................ 14 Output Drive Currents ......................................... 86 Pixel Compositor (PIXC) ...................................... 14 Test Conditions .................................................. 88 Enhanced Parallel Peripheral Interface (EPPI) ........... 14 Capacitive Loading .............................................. 88 USB On-the-Go Dual-Role Device Controller ............ 15 Typical Rise and Fall Times ................................... 89 ATA/ATAPI-6 Interface ....................................... 15 Thermal Characteristics ........................................ 91 Keypad Interface ................................................. 15 400-Ball CSP_BGA Package ...................................... 92 Secure Digital (SD)/SDIO Controller ....................... 16 Outline Dimensions ................................................ 98 Code Security .................................................... 16 Surface-Mount Design .......................................... 98 Media Transceiver MAC Layer (MXVR) .................. 16 Automotive Products .............................................. 99 Dynamic Power Management ................................ 16 Ordering Guide ................................................... 100 Voltage Regulation .............................................. 18 Clock Signals ..................................................... 18 REVISION HISTORY 2/10—Rev. B to Rev. C Added VIHTWI and VILTWI data to Operating Conditions ...... 34 Added IOH/IOL per pin group data to Absolute Maximum Ratings .................................................... 40 Added Table 23 (Total Current Pin Groups) ........................ 40 Revised all timing diagrams for clarity/consistency in Timing Specifications ........................................................ 42 Updated specifications (reference PCN 09_0173) in the Clock and Reset Timing section to accurately describe processor coldstartup/reset timing.................................................. 42 Added tSCLKIW and tSCLK data to Table 42 (Serial Ports—Internal Clock) ..................................................................61 Added Figure 34 (Serial Port Start-Up with External Clock and Frame Sync) and Figure 36 (Serial Ports—Enable and ThreeState) ............................................................................................ 62 To view product/process change notifications (PCNs) related to this data sheet revision, please visit the processor's product page on the www.analog.com website and use the View PCN link. Added tSUDTE and tSUDRE data to Table 41 (Serial Ports—External Clock) .................................................................. 61 Rev. C | Page 2 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 GENERAL DESCRIPTION The ADSP-BF54x Blackfin® processors are members of the Blackfin family of products, incorporating the Analog Devices/ Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. Specific peripherals for ADSP-BF54x Blackfin processors are shown in Table 2. Module ADSP-BF549 ADSP-BF548 ADSP-BF547 ADSP-BF544 ADSP-BF542 Table 2. Specific Peripherals for ADSP-BF54x Processors EBIU (async) P P P P P NAND flash controller P P P P P P Specific performance, memory configurations, and features of ADSP-BF54x Blackfin processors are shown in Table 1. 1 1 1 1 128-bit AES/ ARC4 data encryption 1 1 1 1 1 EPPI2 P P P P P P P P – – ADSP-BF544 1 ADSP-BF547 Lockbox® 1code security EPPI1 Processor Features ADSP-BF548 ATAPI ADSP-BF549 ADSP-BF542 Table 1. ADSP-BF54x Processor Features P P P – Host DMA port (HOSTDP) P P P P – SD/SDIO controller P P P – P EPPI0 P P P P – P P P P P SD/SDIO controller 1 1 1 – 1 SPORT0 Pixel compositor 1 1 1 1 1 SPORT1 P P P P P P P P P P 18- or 24-bit EPPI0 with LCD 1 1 1 1 – SPORT2 16-bit EPPI1, 8-bit EPPI2 1 1 1 1 1 SPORT3 P P P P P – SPI0 P P P P P P P P P P Host DMA port 1 1 1 1 NAND flash controller 1 1 1 1 1 SPI1 ATAPI 1 1 1 – 1 SPI2 P P P – – P P P P P High Speed USB OTG 1 1 1 – 1 UART0 Keypad interface 1 1 1 – 1 UART1 P P P P P P P P – – P MXVR 1 – – – – UART2 CAN ports 2 2 – 2 1 UART3 P P P P 1 High Speed USB OTG P P P – P P P – P P TWI ports 2 2 2 2 SPI ports 3 3 3 2 2 CAN0 UART ports 4 4 4 3 3 CAN1 P P – P – P P P P P SPORTs 4 4 4 3 3 TWI0 Up/Down counter 1 1 1 1 1 TWI1 P P P P – 8 Timer 0–7 P P P P P Timers 11 General-Purpose I/O pins 152 152 152 152 152 Timer 8–10 P P P P – 16 16 16 16 16 Up/Down counter P P P P P 48 48 48 48 48 Keypad interface P P P – P 32 MXVR P – – – – 32 GPIOs P P P P P L1 Instruction SRAM/Cache Memory Configura- L1 Instruction SRAM tions L1 Data SRAM/Cache (K Bytes) L1 Data SRAM 32 11 32 11 32 11 32 32 32 32 32 L1 Scratchpad SRAM 4 4 4 4 4 L1 ROM2 64 64 64 64 64 L2 128 128 128 64 L3 Boot ROM2 Maximum Core Instruction Rate (MHz) 4 4 4 4 – 4 533 533 600 533 600 1 Lockbox is a registered trademark of Analog Devices, Inc. 2 This ROM is not customer-configurable. Rev. C | Page 3 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The ADSP-BF54x Blackfin processors are completely code- and pin-compatible. They differ only with respect to their performance, on-chip memory, and selection of I/O peripherals. Specific performance, memory, and feature configurations are shown in Table 1. memory spaces, including external DDR (either standard or mobile, depending on the device) and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package. The ADSP-BF54x Blackfin processors include an on-chip voltage regulator in support of the dynamic power management capability. The voltage regulator provides a range of core voltage levels when supplied from VDDEXT. The voltage regulator can be bypassed at the user’s discretion. LOW POWER ARCHITECTURE BLACKFIN PROCESSOR CORE Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature on-chip dynamic power management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Reducing both voltage and frequency can result in a substantial reduction in power consumption as compared to reducing only the frequency of operation. This translates into longer battery life for portable appliances. As shown in Figure 2 on Page 5, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-, 16-, or 32-bit data from the register file. SYSTEM INTEGRATION Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported. The ADSP-BF54x Blackfin processors are highly integrated system-on-a-chip solutions for the next generation of embedded network connected applications. By combining industrystandard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include a high speed USB OTG (On-the-Go) controller with integrated PHY, CAN 2.0B controllers, TWI controllers, UART ports, SPI ports, serial ports (SPORTs), ATAPI controller, SD/SDIO controller, a real-time clock, a watchdog timer, LCD controller, and multiple enhanced parallel peripheral interfaces. BLACKFIN PROCESSOR PERIPHERALS The ADSP-BF54x processors contain a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see Figure 1 on Page 1). The generalpurpose peripherals include functions such as UARTs, SPI, TWI, timers with pulse width modulation (PWM) and pulse measurement capability, general-purpose I/O pins, a real-time clock, and a watchdog timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. The ADSPBF54x processors contain dedicated network communication modules and high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the onchip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. All of the peripherals, except for general-purpose I/O, CAN, TWI, real-time clock, and timers, are supported by a flexible DMA structure. There are also separate memory DMA channels dedicated to data transfers between the processor's various Rev. C | Page 4 of 100 | The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields. The ALUs perform a traditional set of arithmetic and logical operations on 16- or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). By also using the second ALU, quad 16-bit operations are possible. The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations. ADDRESS ARITHMETIC UNIT I3 L3 B3 M3 I2 L2 B2 M2 I1 L1 B1 M1 I0 L0 B0 M0 SP FP P5 DAG1 P4 P3 DAG0 P2 DA1 32 DA0 32 P1 TO MEMORY P0 32 PREG 32 RAB SD 32 LD1 32 LD0 32 ASTAT 32 32 R7.H R6.H R7.L R6.L R5.H R5.L R4.H R4.L R3.H R3.L R2.H R2.L R1.H R1.L R0.H R0.L SEQUENCER ALIGN 16 16 8 8 8 8 DECODE BARREL SHIFTER 40 40 A0 32 40 40 A1 32 DATA ARITHMETIC UNIT Figure 2. Blackfin Processor Core Rev. C | Page 5 of 100 | February 2010 LOOP BUFFER CONTROL UNIT ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 MEMORY ARCHITECTURE The ADSP-BF54x processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip memory as cache or SRAM, and larger, lower-cost and performance off-chip memory systems. See Figure 3 on Page 6. 0xFFFF FFFF CORE MMR REGISTERS (2M BYTES) 0x FFE0 0000 SYSTEM MMR REGISTERS (2M BYTES) 0x FFC0 0000 RESERVED 0x FFB0 1000 SCRATCHPAD SRAM (4K BYTES) 0xFFB0 0000 RESERVED 0xFFA2 4000 L1 ROM (64K BYTE) 0xFFA1 4000 RESERVED The on-chip L1 memory system is the highest-performance memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit (EBIU), provides expansion with flash memory, SRAM, and double-rate SDRAM (standard or mobile DDR), optionally accessing up to 768M bytes of physical memory. 0x FFA0 C000 INSTRUCTION BANK B SRA M (16K BYTES) 0x FFA0 8000 INSTRUCTION BANK A SRA M (32K BYTES) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK B SRAM / CACHE (16K BYTES) 0x FF90 4000 DATA BANK B SRAM (16 K BYTES) Most of the ADSP-BF54x Blackfin processors also include an L2 SRAM memory array which provides up to 128K bytes of high speed SRAM, operating at one half the frequency of the core and with slightly longer latency than the L1 memory banks (for information on L2 memory in each processor, see Table 1). The L2 memory is a unified instruction and data memory and can hold any mixture of code and data required by the system design. The Blackfin cores share a dedicated low latency 64-bit data path port into the L2 SRAM memory. 0xFF90 0000 RESERVED 0xFF80 8000 DATA BANK A SRAM / CACHE (16K BYTES) 0xFF80 4000 DATA BANK A SRAM (16 K BYTES) 0x FF80 0000 RESERVED 0xFEB2 0000 L2 SRAM (128K BYTES) 0xFEB0 0000 RESERVED 0xEF00 1000 B OOT ROM (4K BYTES) 0xEF00 0000 The memory DMA controllers (DMAC1 and DMAC0) provide high-bandwidth data-movement capability. They can perform block transfers of code or data between the internal memory and the external memory spaces. ASYNC MEMORY BANK 3 (64M BYTES) 0x 2C00 0000 ASYNC MEMORY BANK 2 (64M BYTES) 0x2800 0000 ASYNC MEMORY BANK 1 (64M BYTES) 0x 2400 0000 ASYNC MEMORY BANK 0 (64M BYTES) 0x2000 0000 The ADSP-BF54x processors have several blocks of on-chip memory providing high bandwidth access to the core. TOP OF LAST DDR PAGE The first block is the L1 instruction memory, consisting of 64K bytes of SRAM, of which 16K bytes can be configured as a four-way set-associative cache or as SRAM. This memory is accessed at full processor speed. The third memory block is a 4K byte scratchpad SRAM, which runs at the same speed as the L1 memories. It is only accessible as data SRAM and cannot be configured as cache memory. The fourth memory block is the factory programmed L1 instruction ROM, operating at full processor speed. This ROM is not customer-configurable. The fifth memory block is the L2 SRAM, providing up to 128K bytes of unified instruction and data memory, operating at one half the frequency of the core. Finally, there is a 4K byte boot ROM connected as L3 memory. It operates at full SCLK rate. Rev. C | Page 6 of 100 | RESERVED DDR MEM BANK 1 (8M BYTES to 256M BYTES) EXTERNAL MEMORY MAP RESERVED 0x3000 0000 Internal (On-Chip) Memory The second on-chip memory block is the L1 data memory, consisting of 64K bytes of SRAM, of which 32K bytes can be configured as a two-way set-associative cache or as SRAM. This memory block is accessed at full processor speed. INTERNAL MEMORY MAP INSTRUCTION SRAM / CACHE (16K BYTES) 0xFFA1 0000 DDR MEM BANK 0 (8M BYTES to 256M BYTES) 0x 0000 0000 Figure 3. ADSP-BF547/ADSP-BF548/ADSP-BF549 Internal/External Memory Map1 1 For ADSP-BF544 processors, L2 SRAM is 64K Bytes (0xFEB0000–0xFEB0FFFF). For ADSP-BF542 processors, there is no L2 SRAM. External (Off-Chip) Memory Through the external bus interface unit (EBIU), the ADSP-BF54x Blackfin processors provide glueless connectivity to external 16-bit wide memories, such as DDR and mobile DDR SDRAM, SRAM, NOR flash, NAND flash, and FIFO devices. To provide the best performance, the bus system of the DDR and mobile DDR interface is completely separate from the other parallel interfaces. Furthermore, the DDR controller supports either standard DDR memory or mobile DDR memory. See the Ordering Guide on Page 100 for details. Throughout this document, references to “DDR” are intended to cover both the standard and mobile DDR standards. February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The DDR memory controller can gluelessly manage up to two banks of double-rate synchronous dynamic memory (DDR and mobile DDR SDRAM). The 16-bit interface operates at the SCLK frequency, enabling a maximum throughput of 532M bytes/s. The DDR and mobile DDR controller is augmented with a queuing mechanism that performs efficient bursts into the DDR and mobile DDR. The controller is an industry standard DDR and mobile DDR SDRAM controller with each bank supporting from 64M bit to 512M bit device sizes and 4-, 8-, or 16-bit widths. The controller supports up to 256M bytes per external bank. With 2 external banks, the controller supports up to 512M bytes total. Each bank is independently programmable and is contiguous with adjacent banks regardless of the sizes of the different banks or their placement. Traditional 16-bit asynchronous memories, such as SRAM, EPROM, and flash devices, can be connected to one of the four 64M byte asynchronous memory banks, represented by four memory select strobes. Alternatively, these strobes can function as bank-specific read or write strobes preventing further glue logic when connecting to asynchronous FIFO devices. See the Ordering Guide on Page 100 for a list of specific products that provide support for DDR memory. In addition, the external bus can connect to advanced flash device technologies, such as: • Support for SLC (single level cell) NAND flash devices unlimited in size, with page sizes of 256 bytes and 512 bytes. Larger page sizes can be supported in software. • The ability to release external bus interface pins during long accesses. • Support for internal bus requests of 16 bits or 32 bits. • A DMA engine to transfer data between internal memory and a NAND flash device. One-Time-Programmable Memory The ADSP-BF54x Blackfin processors have 64K bits of onetime-programmable (OTP) non-volatile memory that can be programmed by the developer only one time. It includes the array and logic to support read access and programming. Additionally, its pages can be write protected. OTP enables developers to store both public and private data on-chip. In addition to storing public and private key data for applications requiring security, it also allows developers to store completely user-definable data such as a customer ID, product ID, or a MAC address. By using this feature, generic parts can be shipped, which are then programmed and protected by the developer within this non-volatile memory. The OTP memory can be accessed through an API provided by the on-chip ROM. • Page-mode NOR flash devices I/O Memory Space • Synchronous burst-mode NOR flash devices The ADSP-BF54x Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one containing the control MMRs for all core functions and the other containing the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. • NAND flash devices Customers should consult the Ordering Guide when selecting a specific ADSP-BF54x component for the intended application. Products that provide support for mobile DDR memory are noted in the ordering guide footnotes. NAND Flash Controller (NFC) The ADSP-BF54x Blackfin processors provide a NAND Flash Controller (NFC) as part of the external bus interface. NAND flash devices provide high-density, low-cost memory. However, NAND flash devices also have long random access times, invalid blocks, and lower reliability over device lifetimes. Because of this, NAND flash is often used for read-only code storage. In this case, all DSP code can be stored in NAND flash and then transferred to a faster memory (such as DDR or SRAM) before execution. Another common use of NAND flash is for storage of multimedia files or other large data segments. In this case, a software file system may be used to manage reading and writing of the NAND flash device. The file system selects memory segments for storage with the goal of avoiding bad blocks and equally distributing memory accesses across all address locations. Hardware features of the NFC include: • Support for page program, page read, and block erase of NAND flash devices, with accesses aligned to page boundaries. Booting The ADSP-BF54x Blackfin processors contain a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF54x Blackfin processors are configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Booting Modes on Page 19. Event Handling The event controller on the ADSP-BF54x Blackfin processors handles all asynchronous and synchronous events to the processors. The ADSP-BF54x Blackfin processors provide event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a • Error checking and correction (ECC) hardware that facilitates error detection and correction. • A single 8-bit or 16-bit external bus interface for commands, addresses, and data. Rev. C | Page 7 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 higher-priority event takes precedence over servicing of a lowerpriority event. The controller provides support for five different types of events: • Emulation. An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. • Reset. This event resets the processor. • Non-maskable interrupt (NMI). The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system. • Exceptions. Events that occur synchronously to program flow (that is, the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts. Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The ADSP-BF54x Blackfin processor event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC and are then routed directly into the general-purpose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest-priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF54x Blackfin processors. Table 3 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities. Rev. C | Page 8 of 100 | Table 3. Core Event Controller (CEC) Priority (0 is Highest) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Event Class Emulation/Test Control Reset Nonmaskable Interrupt Exception Reserved Hardware Error Core Timer General Interrupt 7 General Interrupt 8 General Interrupt 9 General Interrupt 10 General Interrupt 11 General Interrupt 12 General Interrupt 13 General Interrupt 14 General Interrupt 15 EVT Entry EMU RST NMI EVX — IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15 System Interrupt Controller (SIC) The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF54x Blackfin processors provide a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (SIC_IARx). Table 4 describes the inputs into the SIC and the default mappings into the CEC. Table 4. System Interrupt Controller (SIC) Peripheral IRQ Source IRQ GP IRQ ID (at Reset) Core IRQ ID PLL Wakeup IRQ 0 IVG7 0 DMAC0 Status (Generic) 1 IVG7 0 EPPI0 Error IRQ 2 IVG7 0 SPORT0 Error IRQ 3 IVG7 0 SPORT1 Error IRQ 4 IVG7 0 SPI0 Status IRQ 5 IVG7 0 UART0 Status IRQ 6 IVG7 0 Real-Time Clock IRQ 7 IVG8 1 DMA12 IRQ (EPPI0) 8 IVG8 1 DMA0 IRQ (SPORT0 RX) 9 IVG9 2 DMA1 IRQ (SPORT0 TX) 10 IVG9 2 DMA2 IRQ (SPORT1 RX) 11 IVG9 2 DMA3 IRQ (SPORT1 TX) 12 IVG9 2 DMA4 IRQ (SPI0) 13 IVG10 3 February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 4. System Interrupt Controller (SIC) (Continued) Peripheral IRQ Source IRQ GP IRQ ID (at Reset) DMA6 IRQ (UART0 RX) 14 IVG10 DMA7 IRQ (UART0 TX) 15 Timer 8 IRQ 16 Timer 9 IRQ Table 4. System Interrupt Controller (SIC) (Continued) Core IRQ ID Peripheral IRQ Source IRQ GP IRQ ID (at Reset) Core IRQ ID 3 MXVR Asynchronous Packet IRQ 53 IVG11 4 IVG10 3 EPPI1 Error IRQ 54 IVG7 0 IVG11 4 EPPI2 Error IRQ 55 IVG7 0 17 IVG11 4 UART3 Status IRQ 56 IVG7 0 Timer 10 IRQ 18 IVG11 4 Host DMA Status 57 IVG7 0 Pin IRQ 0 (PINT0) 19 IVG12 5 Reserved 58 IVG7 0 Pin IRQ 1 (PINT1) 20 IVG12 5 Pixel Compositor (PIXC) Status IRQ 59 IVG7 0 MDMA Stream 0 IRQ 21 IVG13 6 NFC Status IRQ 60 IVG7 0 MDMA Stream 1 IRQ 22 IVG13 6 ATAPI Status IRQ 61 IVG7 0 Software Watchdog Timer IRQ 23 IVG13 6 CAN1 Status IRQ 62 IVG7 0 DMAC1 Status (Generic) 24 IVG7 0 DMAR0 Block IRQ 63 IVG7 0 SPORT2 Error IRQ 25 IVG7 0 DMAR1 Block IRQ 63 IVG7 0 SPORT3 Error IRQ 26 IVG7 0 DMAR0 Overflow Error IRQ 63 IVG7 0 MXVR Synchronous Data IRQ 27 IVG7 0 DMAR1 Overflow Error IRQ 63 IVG7 0 SPI1 Status IRQ 28 IVG7 0 DMA15 IRQ (PIXC IN0) 64 IVG8 1 SPI2 Status IRQ 29 IVG7 0 DMA16 IRQ (PIXC IN1) 65 IVG8 1 UART1 Status IRQ 30 IVG7 0 DMA17 IRQ (PIXC OUT) 66 IVG8 1 UART2 Status IRQ 31 IVG7 0 DMA22 IRQ (SDH/NFC) 67 IVG8 1 CAN0 Status IRQ 32 IVG7 0 Counter (CNT) IRQ 68 IVG8 1 DMA18 IRQ (SPORT2 RX) 33 IVG9 2 Keypad (KEY) IRQ 69 IVG8 1 DMA19 IRQ (SPORT2 TX) 34 IVG9 2 CAN1 RX IRQ 70 IVG11 4 DMA20 IRQ (SPORT3 RX) 35 IVG9 2 CAN1 TX IRQ 71 IVG11 4 DMA21 IRQ (SPORT3 TX) 36 IVG9 2 SDH Mask 0 IRQ 72 IVG11 4 DMA13 IRQ (EPPI1) 37 IVG9 2 SDH Mask 1 IRQ 73 IVG11 4 DMA14 IRQ (EPPI2, Host DMA) 38 IVG9 2 Reserved 74 IVG11 4 DMA5 IRQ (SPI1) 39 IVG10 3 USB_INT0 IRQ 75 IVG11 4 DMA23 IRQ (SPI2) 40 IVG10 3 USB_INT1 IRQ 76 IVG11 4 DMA8 IRQ (UART1 RX) 41 IVG10 3 USB_INT2 IRQ 77 IVG11 4 DMA9 IRQ (UART1 TX) 42 IVG10 3 USB_DMAINT IRQ 78 IVG11 4 DMA10 IRQ (ATAPI RX) 43 IVG10 3 OTPSEC IRQ 79 IVG11 4 DMA11 IRQ (ATAPI TX) 44 IVG10 3 Reserved 80 IVG11 4 TWI0 IRQ 45 IVG11 4 Reserved 81 IVG11 4 TWI1 IRQ 46 IVG11 4 Reserved 82 IVG11 4 CAN0 Receive IRQ 47 IVG11 4 Reserved 83 IVG11 4 CAN0 Transmit IRQ 48 IVG11 4 Reserved 84 IVG11 4 MDMA Stream 2 IRQ 49 IVG13 6 Reserved 85 IVG11 4 MDMA Stream 3 IRQ 50 IVG13 6 Timer 0 IRQ 86 IVG11 4 MXVR Status IRQ 51 IVG11 4 Timer 1 IRQ 87 IVG11 4 MXVR Control Message IRQ 52 IVG11 4 Timer 2 IRQ 88 IVG11 4 Rev. C | Page 9 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event. Table 4. System Interrupt Controller (SIC) (Continued) Peripheral IRQ Source IRQ GP IRQ ID (at Reset) Core IRQ ID Timer 3 IRQ 89 IVG11 4 Timer 4 IRQ 90 IVG11 4 Timer 5 IRQ 91 IVG11 4 Timer 6 IRQ 92 IVG11 4 Timer 7 IRQ 93 IVG11 4 Pin IRQ 2 (PINT2) 94 IVG12 5 Pin IRQ 3 (PINT3) 95 IVG12 5 Event Control The ADSP-BF54x Blackfin processors provide the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide: • CEC interrupt latch register (ILAT). The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared. • CEC interrupt mask register (IMASK). The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and is processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively. • CEC interrupt pending register (IPEND). The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates that the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 4 on Page 8. • SIC interrupt mask registers (SIC_IMASKx). These registers control the masking and unmasking of each peripheral interrupt event. When a bit is set in a register, that peripheral event is unmasked and is processed by the system when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servicing the event. • SIC interrupt status registers (SIC_ISRx). As multiple peripherals can be mapped to a single event, these registers allow the software to determine which peripheral event Rev. C | • SIC interrupt wakeup enable registers (SIC_IWRx). By enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled or in Sleep mode when the event is generated. (For more information, see Dynamic Power Management on Page 16.) Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected. (Detection requires two core clock cycles.) The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC recognizes and queues the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor. DMA CONTROLLERS ADSP-BF54x Blackfin processors have multiple, independent DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the ADSP-BF54x processors’ internal memories and any of the DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including DDR and asynchronous memory controllers. While the USB controller and MXVR have their own dedicated DMA controllers, the other on-chip peripherals are managed by two centralized DMA controllers, called DMAC1 (32-bit) and DMAC0 (16-bit). Both operate in the SCLK domain. Each DMA controller manages 12 independent peripheral DMA channels, as well as two independent memory DMA streams. The DMAC1 controller masters high-bandwidth peripherals over a dedicated 32-bit DMA access bus (DAB32). Similarly, the DMAC0 controller masters most serial interfaces over the 16-bit DAB16 bus. Individual DMA channels have fixed access priority on the DAB buses. DMA priority of peripherals is managed by a flexible peripheral-to-DMA channel assignment scheme. All four DMA controllers use the same 32-bit DCB bus to exchange data with L1 memory. This includes L1 ROM, but excludes scratchpad memory. Fine granulation of L1 memory and special DMA buffers minimize potential memory conflicts when the L1 memory is accessed simultaneously by the core. Similarly, there are dedicated DMA buses between the external bus interface unit (EBIU) and the three DMA controllers (DMAC1, DMAC0, and USB) that arbitrate DMA accesses to external memories and the boot ROM. Page 10 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The ADSP-BF54x Blackfin processors’ DMA controllers support both 1-dimensional (1D) and 2-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. configuration words in order to send/receive data to any valid internal or external memory location. The host DMA port controller includes the following features: • Allows an external master to configure DMA read/write data transfers and read port status The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly. • Uses a flexible asynchronous memory protocol for its external interface • Allows an 8- or 16-bit external data interface to the host device • Supports half-duplex operation Examples of DMA types supported by the ADSP-BF54x Blackfin processors’ DMA controllers include: • Supports little/big endian data transfers • A single, linear buffer that stops upon completion • Acknowledge mode allows flow control on host transactions • A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer • Interrupt mode guarantees a burst of FIFO depth host transactions • 1D or 2D DMA using a linked list of descriptors REAL-TIME CLOCK • 2D DMA using an array of descriptors, specifying only the base DMA address within a common page In addition to the dedicated peripheral DMA channels, the DMAC1 and DMAC0 controllers each feature two memory DMA channel pairs for transfers between the various memories of the ADSP-BF54x Blackfin processors. This enables transfers of blocks of data between any of the memories—including external DDR, ROM, SRAM, and flash memory—with minimal processor intervention. Like peripheral DMAs, memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. The memory DMA channels of the DMAC1 controller (MDMA2 and MDMA3) can be controlled optionally by the external DMA request input pins. When used in conjunction with the External Bus Interface Unit (EBIU), this handshaked memory DMA (HMDMA) scheme can be used to efficiently exchange data with block-buffered or FIFO-style devices connected externally. Users can select whether the DMA request pins control the source or the destination side of the memory DMA. It allows control of the number of data transfers for memory DMA. The number of transfers per edge is programmable. This feature can be programmed to allow memory DMA to have an increased priority on the external bus relative to the core. Host DMA Port Interface The host DMA port (HOSTDP) facilitates a host device external to the ADSP-BF54x Blackfin processors to be a DMA master and transfer data back and forth. The host device always masters the transactions, and the processor is always a DMA slave device. The ADSP-BF54x Blackfin processors’ real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the ADSP-BF54x Blackfin processors. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low-power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and a 32,768-day counter. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms. The first alarm is for a time of day. The second alarm is for a day and time of that day. The stopwatch function counts down from a programmed value with one-second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like the other peripherals, the RTC can wake up the ADSP-BF54x processor from sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the ADSP-BF54x processors from deep sleep mode, and it can wake up the on-chip internal voltage regulator from the hibernate state. The HOSTDP is enabled through the peripheral access bus. Once the port has been enabled, the transactions are controlled by the external host. The external host programs standard DMA Rev. C | Page 11 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Connect RTC pins RTXI and RTXO with external components as shown in Figure 4. RTXI The timers can generate interrupts to the processor core, providing periodic events for synchronization to either the system clock or to a count of external signals. RTXO R1 In addition to the general-purpose programmable timers, another timer is also provided by the processor core. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of periodic operating system interrupts. X1 C1 The timer units can be used in conjunction with the four UARTs and the CAN controllers to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. C2 SUGGESTED COMPONENTS: ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE) C1 = 22 pF C2 = 22 pF R1 = 10 M: UP/DOWN COUNTER AND THUMBWHEEL INTERFACE A 32-bit up/down counter is provided that can sense the 2-bit quadrature or binary codes typically emitted by industrial drives or manual thumb wheels. The counter can also operate in general-purpose up/down count modes. Then count direction is either controlled by a level-sensitive input pin or by two edge detectors. NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF. Figure 4. External Components for RTC WATCHDOG TIMER The ADSP-BF54x processors include a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system reliability by forcing the processor to a known state through generation of a hardware reset, non-maskable interrupt (NMI), or general-purpose interrupt if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, and then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. A third input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. All three pins have a programmable debouncing circuit. An internal signal forwarded to the timer unit enables one timer to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded. SERIAL PORTS (SPORTS) The ADSP-BF54x Blackfin processors incorporate up to four dual-channel synchronous serial ports (SPORT0, SPORT1, SPORT2, and SPORT3) for serial and multiprocessor communications. The SPORTs support the following features: If configured to generate a hardware reset, the watchdog timer resets both the core and the ADSP-BF54x processors’ peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. The timer is clocked by the system clock (SCLK) at a maximum frequency of fSCLK. TIMERS There are up to two timer units in the ADSP-BF54x Blackfin processors. One unit provides eight general-purpose programmable timers, and the other unit provides three. Each timer has an external pin that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input on the TMRx pins, an external clock TMRCLK input pin, or to the internal SCLK. Rev. C | Page 12 of 100 | • I2S capable operation. • Bidirectional operation. Each SPORT has two sets of independent transmit and receive pins, enabling up to eight channels of I2S stereo audio. • Buffered (8-deep) transmit and receive ports. Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers. • Clocking. Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. • Word length. Each SPORT supports serial data words from 3 to 32 bits in length, transferred most-significant-bit first or least-significant-bit first. • Framing. Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 • Companding in hardware. Each SPORT can perform A-law or μ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. includes support for five to eight data bits, one or two stop bits, and none, even, or odd parity. Each UART port supports two modes of operation: • PIO (programmed I/O). The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. • DMA operations with single-cycle overhead. Each SPORT can receive and transmit multiple buffers of memory data automatically. The processor can link or chain sequences of DMA transfers between a SPORT and memory. • DMA (direct memory access). The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. Each UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. Flexible interrupt timing options are available on the transmit side. • Interrupts. Each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA. • Multichannel capability. Each SPORT supports 128 channels out of a 1024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards. SERIAL PERIPHERAL INTERFACE (SPI) PORTS Each UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable: • Supporting bit rates ranging from (fSCLK/1,048,576) to (fSCLK) bits per second. The ADSP-BF54x Blackfin processors have up to three SPIcompatible ports that allow the processor to communicate with multiple SPI-compatible devices. Each SPI port uses three pins for transferring data: two data pins (master output slave input, SPIxMOSI, and master input-slave output, SPIxMISO) and a clock pin (serial clock, SPIxSCK). An SPI chip select input pin (SPIxSS) lets other SPI devices select the processor, and three SPI chip select output pins per SPI port SPIxSELy let the processor select other SPI devices. The SPI select pins are reconfigured general-purpose I/O pins. Using these pins, the SPI ports provide a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments. The SPI port’s baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. The SPI’s DMA controller can only service unidirectional accesses at any given time. The SPI port’s clock rate is calculated as f SCLK SPI Clock Rate = -----------------------------------2 × SPI_BAUD Where the 16-bit SPI_BAUD register contains a value of 2 to 65,535. During transfers, the SPI port transmits and receives simultaneously by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines. UART PORTS (UARTS) The ADSP-BF54x Blackfin processors provide up to four fullduplex universal asynchronous receiver/transmitter (UART) ports. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port Rev. C | • Supporting data formats from seven to 12 bits per frame. • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. The UART port’s clock rate is calculated as f SCLK UART Clock Rate = -----------------------------------------------------------------------------( 1 – EDBO ) 16 × UART_Divisor Where the 16-bit UART divisor comes from the UARTx_DLH register (most significant 8 bits) and UARTx_DLL register (least significant eight bits), and the EDBO is a bit in the UARTx_GCTL register. In conjunction with the general-purpose timer functions, autobaud detection is supported. UART1 and UART3 feature a pair of UARTxRTS (request to send) and UARTxCTS (clear to send) signals for hardware flow purposes. The transmitter hardware is automatically prevented from sending further data when the UARTxCTS input is deasserted. The receiver can automatically de-assert its UARTxRTS output when the enhanced receive FIFO exceeds a certain high-water level. The capabilities of the UARTs are further extended with support for the Infrared Data Association (IrDA®) Serial Infrared Physical Layer Link Specification (SIR) protocol. CONTROLLER AREA NETWORK (CAN) The ADSP-BF54x Blackfin processors offer up to two CAN controllers that are communication controllers that implement the controller area network (CAN) 2.0B (active) protocol. This protocol is an asynchronous communications protocol used in both industrial and automotive control systems. The CAN protocol is well suited for control applications due to its capability to communicate reliably over a network since the protocol incorporates CRC checking, message error tracking, and fault node confinement. Page 13 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The ADSP-BF54x Blackfin processors’ CAN controllers offer the following features: • 32 mailboxes (8 receive only, 8 transmit only, 16 configurable for receive or transmit). • Dedicated acceptance masks for each mailbox. • Additional data filtering on first two bytes. • Support for both the standard (11-bit) and extended (29bit) identifier (ID) message formats. • Support for remote frames. • Active or passive network support. • CAN wakeup from hibernation mode (lowest static power consumption mode). • Interrupts, including: TX complete, RX complete, error and global. The electrical characteristics of each network connection are very demanding, so the CAN interface is typically divided into two parts: a controller and a transceiver. This allows a single controller to support different drivers and CAN networks. The ADSP-BF54x Blackfin processors’ CAN module represents only the controller part of the interface. The controller interface supports connection to 3.3 V high speed, fault-tolerant, single-wire transceivers. An additional crystal is not required to supply the CAN clock, as the CAN clock is derived from the processor system clock (SCLK) through a programmable divider. TWI CONTROLLER INTERFACE The ADSP-BF54x Blackfin processors include up to two 2-wire interface (TWI) modules for providing a simple exchange method of control data between multiple devices. The modules are compatible with the widely used I2C bus standard. The TWI modules offer the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitration. Each TWI interface uses two pins for transferring clock (SCLx) and data (SDAx), and supports the protocol at speeds up to 400K bits/sec. The TWI interface pins are compatible with 5 V logic levels. Additionally, the ADSP-BF54x Blackfin processors’ TWI modules are fully compatible with serial camera control bus (SCCB) functionality for easier control of various CMOS camera sensor devices. PORTS Because of their rich set of peripherals, the ADSP-BF54x Blackfin processors group the many peripheral signals to ten ports—referred to as Port A to Port J. Most ports contain 16 pins, though some have fewer. Many of the associated pins are shared by multiple signals. The ports function as multiplexer controls. Every port has its own set of memory-mapped registers to control port muxing and GPIO functionality. Rev. C | General-Purpose I/O (GPIO) Every pin in Port A to Port J can function as a GPIO pin, resulting in a GPIO pin count up to 154. While it is unlikely that all GPIO pins will be used in an application, as all pins have multiple functions, the richness of GPIO functionality guarantees unrestrictive pin usage. Every pin that is not used by any function can be configured in GPIO mode on an individual basis. After reset, all pins are in GPIO mode by default. Since neither GPIO output nor input drivers are active by default, unused pins can be left unconnected. GPIO data and direction control registers provide flexible write-one-to-set and write-one-toclear mechanisms so that independent software threads do not need to protect against each other because of expensive readmodify-write operations when accessing the same port. Pin Interrupts Every port pin on ADSP-BF54x Blackfin processors can request interrupts in either an edge-sensitive or a level-sensitive manner with programmable polarity. Interrupt functionality is decoupled from GPIO operation. Four system-level interrupt channels (PINT0, PINT1, PINT2 and PINT3) are reserved for this purpose. Each of these interrupt channels can manage up to 32 interrupt pins. The assignment from pin to interrupt is not performed on a pin-by-pin basis. Rather, groups of eight pins (half ports) can be flexibly assigned to interrupt channels. Every pin interrupt channel features a special set of 32-bit memory-mapped registers that enables half-port assignment and interrupt management. This not only includes masking, identification, and clearing of requests, it also enables access to the respective pin states and use of the interrupt latches regardless of whether the interrupt is masked or not. Most control registers feature multiple MMR address entries to write-one-to-set or write-one-to-clear them individually. PIXEL COMPOSITOR (PIXC) The pixel compositor (PIXC) provides image overlays with transparent-color support, alpha blending, and color space conversion capabilities for output to TFT LCDs and NTSC/PAL video encoders. It provides all of the control to allow two data streams from two separate data buffers to be combined, blended, and converted into appropriate forms for both LCD panels and digital video outputs. The main image buffer provides the basic background image, which is presented in the data stream. The overlay image buffer allows the user to add multiple foreground text, graphics, or video objects on top of the main image or video data stream. ENHANCED PARALLEL PERIPHERAL INTERFACE (EPPI) The ADSP-BF54x Blackfin processors provide up to three enhanced parallel peripheral interfaces (EPPIs), supporting data widths up to 24 bits. The EPPI supports direct connection to TFT LCD panels, parallel analog-to-digital and digital-to-analog converters, video encoders and decoders, image sensor modules and other general-purpose peripherals. Page 14 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The following features are supported in the EPPI module: • Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits, 16 bits, 18 bits, and 24 bits per clock. • Bidirectional and half-duplex port. • Clock can be provided externally or can be generated internally. • Various framed and non-framed operating modes. Frame syncs can be generated internally or can be supplied by an external device. • Various general-purpose modes with zero to three frame syncs for both receive and transmit directions. • ITU-656 status word error detection and correction for ITU-656 receive modes. • ITU-656 preamble and status word decode. • Three different modes for ITU-656 receive modes: active video only, vertical blanking only, and entire field mode. • Horizontal and vertical windowing for GP 2 and 3 frame sync modes. • Optional packing and unpacking of data to/from 32 bits from/to 8, 16 and 24 bits. If packing/unpacking is enabled, endianness can be changed to change the order of packing/unpacking of bytes/words. • Optional sign extension or zero fill for receive modes. • During receive modes, alternate even or odd data samples can be filtered out. The USB clock (USB_XI) is provided through a dedicated external crystal or crystal oscillator. See Table 62 for related timing requirements. If using a fundamental mode crystal to provide the USB clock, connect the crystal between USB_XI and USB_XO with a circuit similar to that shown in Figure 7. Use a parallel-resonant, fundamental mode, microprocessor-grade crystal. If a third-overtone crystal is used, follow the circuit guidelines outlined in Clock Signals on Page 18 for third-overtone crystals. The USB On-the-Go dual-role device controller includes a Phase Locked Loop with programmable multipliers to generate the necessary internal clocking frequency for USB. The multiplier value should be programmed based on the USB_XI clock frequency to achieve the necessary 480 MHz internal clock for USB high speed operation. For example, for a USB_XI crystal frequency of 24 MHz, the USB_PLLOSC_CTRL register should be programmed with a multiplier value of 20 to generate a 480 MHz internal clock. ATA/ATAPI-6 INTERFACE The ATAPI interface connects to CD/DVD and HDD drives and is ATAPI-6 compliant. The controller implements the peripheral I/O mode, the multi-DMA mode, and the Ultra DMA mode. The DMA modes enable faster data transfer and reduced host management. The ATAPI controller supports PIO, multi-DMA, and ultra DMA ATAPI accesses. Key features include: • Supports PIO modes 0, 1, 2, 3, 4 • Supports multiword DMA modes 0, 1, 2 • Programmable clipping of data values for 8-bit transmit modes. • Supports ultra DMA modes 0, 1, 2, 3, 4, 5 (up to UDMA 100) • RGB888 can be converted to RGB666 or RGB565 for transmit modes. • Various de-interleaving/interleaving modes for receiving/transmitting 4:2:2 YCrCb data. • FIFO watermarks and urgent DMA features. • Clock gating by an external device asserting the clock gating control signal. • Configurable LCD data enable (DEN) output available on Frame Sync 3. USB ON-THE-GO DUAL-ROLE DEVICE CONTROLLER The USB OTG dual-role device controller (USBDRC) provides a low-cost connectivity solution for consumer mobile devices such as cell phones, digital still cameras, and MP3 players, allowing these devices to transfer data using a point-to-point USB connection without the need for a PC host. The USBDRC module can operate in a traditional USB peripheral-only mode as well as the host mode presented in the On-the-Go (OTG) supplement to the USB 2.0 specification. In host mode, the USB module supports transfers at high speed (480 Mbps), full speed (12 Mbps), and low speed (1.5 Mbps) rates. Peripheral-only mode supports the high and full speed transfer rates. Rev. C | • Programmable timing for ATA interface unit • Supports CompactFlash cards using true IDE mode By default, the ATAPI_A0-2 address signals and the ATAPI_D0-15 data signals are shared on the asynchronous memory interface with the asynchronous memory and NAND flash controllers. The data and address signals can be remapped to GPIO ports F and G, respectively, by setting PORTF_MUX[1:0] to b#01. KEYPAD INTERFACE The keypad interface is a 16-pin interface module that is used to detect the key pressed in a 8 × 8 (maximum) keypad matrix. The size of the input keypad matrix is programmable. The interface is capable of filtering the bounce on the input pins, which is common in keypad applications. The width of the filtered bounce is programmable. The module is capable of generating an interrupt request to the core once it identifies that any key has been pressed. The interface supports a press-release-press mode and infrastructure for a press-hold mode. The former mode identifies a press, release and press of a key as two consecutive presses of the same key, whereas the latter mode checks the input key’s state in periodic intervals to determine the number of times the same Page 15 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 key is meant to be pressed. It is possible to detect when multiple keys are pressed simultaneously and to provide limited key resolution capability when this happens. SECURE DIGITAL (SD)/SDIO CONTROLLER The SD/SDIO controller is a serial interface that stores data at a data rate of up to 10M bytes per second using a 4-bit data line. The SD/SDIO controller supports the SD memory mode only. The interface supports all the power modes and performs error checking by CRC. CODE SECURITY An OTP/security system, consisting of a blend of hardware and software, provides customers with a flexible and rich set of code security features with Lockbox® secure technology. Key features include: • OTP memory • Unique chip ID • Code authentication The MXVR peripheral can wake up the ADSP-BF549 Blackfin processor from sleep mode when a wakeup preamble is received over the network or based on any other MXVR interrupt event. Additionally, detection of network activity by the MXVR can be used to wake up the ADSP-BF549 Blackfin processor from the hibernate state. These features allow the ADSP-BF549 processor to operate in a low-power state when there is no network activity or when data is not currently being received or transmitted by the MXVR. The MXVR clock is provided through a dedicated external crystal or crystal oscillator. The frequency of the external crystal or crystal oscillator can be 256 Fs, 384 Fs, 512 Fs, or 1024 Fs for Fs = 38 kHz, 44.1 kHz, or 48 kHz. If using a crystal to provide the MXVR clock, use a parallel-resonant, fundamental mode, microprocessor-grade crystal. DYNAMIC POWER MANAGEMENT • Secure mode of operation The security scheme is based upon the concept of authentication of digital signatures using standards-based algorithms and provides a secure processing environment in which to execute code and protect assets. See Lockbox Secure Technology Disclaimer on Page 24. MEDIA TRANSCEIVER MAC LAYER (MXVR) The ADSP-BF549 Blackfin processors provide a media transceiver (MXVR) MAC layer, allowing the processor to be connected directly to a MOST® 1 network through an FOT. See Figure 5 on Page 17 for an example of a MXVR MOST connection. The MXVR is fully compatible with industry-standard standalone MOST controller devices, supporting 22.579 Mbps or 24.576 Mbps data transfer. It offers faster lock times, greater jitter immunity, and a sophisticated DMA scheme for data transfers. The high speed internal interface to the core and L1 memory allows the full bandwidth of the network to be utilized. The MXVR can operate as either the network master or as a network slave. The MXVR supports synchronous data, asynchronous packets, and control messages using dedicated DMA channels that operate autonomously from the processor core moving data to and from L1 and/or L2 memory. Synchronous data is transferred to or from the synchronous data physical channels on the MOST bus through eight programmable DMA channels. The synchronous data DMA channels can operate in various modes including modes that trigger DMA operation when data patterns are detected in the receive data stream. Furthermore, two DMA channels support asynchronous traffic, and two others support control message traffic. 1 Interrupts are generated when a user-defined amount of synchronous data has been sent or received by the processor or when asynchronous packets or control messages have been sent or received. The ADSP-BF54x Blackfin processors provide five operating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. Control of clocking to each of the ADSP-BF54x Blackfin processors’ peripherals also reduces power consumption. See Table 5 for a summary of the power settings for each mode. Full-On Operating Mode—Maximum Performance In the full-on mode, the PLL is enabled and is not bypassed, providing the capability to run at the maximum operational frequency. This is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed. Active Operating Mode—Moderate Power Savings In the active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. DMA access is available to appropriately configured L1 memories. In the active mode, it is possible to disable the control input to the PLL by setting the PLL_OFF bit in the PLL control register. This register can be accessed with a user-callable routine in the on-chip ROM called bfrom_SysControl(). For more information, see the “Dynamic Power Management” chapter in the ADSP-BF54x Blackfin Processor Hardware Reference. If disabled, the PLL must be re-enabled before transitioning to the full-on or sleep modes. MOST is a registered trademark of Standard Microsystems, Corp. Rev. C | Page 16 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 5.0V 1.25V 600Z RXVCC VDDINT ADSP-BF549 MOST FOT RXGND 10k6 GND PG11/MTXON MOST NETWORK 600Z 600Z 0.01MF TXVCC XN4114 VDDMP TXGND 0.1MF 27 6 PH5/MTX GNDMP TX_DATA 06 RX_DATA PH6/MRX MXO STATUS PH7/MRXON 24.576MHz MXI PC4/RFS0 336 L/RCLK MFS AUDIO DAC 336 MLF_P R1 330 6 1% PC5/MBCLK C2 330pF 2% PPS C1 0.047MF 2% PPS MCLK PC1/MMCLK 336 BCLK PC3/TSCLK0 AUDIO CHANNELS PC7/RSCLK0 MLF_M SDATA PC2/DT0PRI Figure 5. MXVR MOST Connection Core Clock (CCLK) System Clock (SCLK) Core Power Sleep Deep Sleep Hibernate Enabled Enabled/ Disabled Enabled Disabled Disabled PLL Bypassed Full On Active PLL Mode/State Table 5. Power Settings No Yes Enabled Enabled Enabled Enabled On On - Disabled Disabled Disabled Enabled Disabled Disabled On On Off Sleep Operating Mode—High Dynamic Power Savings The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the processor. In the sleep mode, assertion of a wakeup event enabled in the SIC_IWRx register causes the processor to sense the value of the BYPASS bit in the PLL control register (PLL_CTL). If BYPASS is disabled, the processor transitions to the full on mode. If BYPASS is enabled, the processor transitions to the active mode. In the sleep mode, system DMA access to L1 memory is not supported. Deep Sleep Operating Mode—Maximum Dynamic Power Savings The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals, Rev. C | such as the RTC, may still be running but will not be able to access internal resources or external memory. This powered-down mode can only be exited by assertion of the reset interrupt (RESET) or by an asynchronous interrupt generated by the RTC. In deep sleep mode, an asynchronous RTC interrupt causes the processor to transition to the active mode. Assertion of RESET while in deep sleep mode causes the processor to transition to the full on mode. Hibernate State—Maximum Static Power Savings The hibernate state maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by using the bfrom_SysControl() function in the on-chip ROM. This sets the internal power supply voltage (VDDINT) to 0 V to provide the greatest power savings mode. Any critical information stored internally (memory contents, register contents, and so on) must be written to a non-volatile storage device prior to removing power if the processor state is to be preserved. Since VDDEXT is still supplied in this mode, all of the external pins three-state, unless otherwise specified. This allows other devices that may be connected to the processor to have power still applied without drawing unwanted current. The internal supply regulator can be woken up by CAN, by the MXVR, by the keypad, by the up/down counter, by the USB, and by some GPIO pins. It can also be woken up by a real-time clock wakeup event or by asserting the RESET pin. Waking up from hibernate state initiates the hardware reset sequence. With the exception of the VR_CTL and the RTC registers, all internal registers and memories lose their content in hibernate state. State variables may be held in external SRAM or DDR memory. Page 17 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Power Domains 2.7V TO 3.6V INPUT VOLTAGE RANGE As shown in Table 6, the ADSP-BF54x Blackfin processors support different power domains. The use of multiple power domains maximizes flexibility while maintaining compliance with industry standards and conventions. By isolating the internal logic of the ADSP-BF54x Blackfin processors into its own power domain separate from the RTC and other I/O, the processors can take advantage of dynamic power management without affecting the RTC or other I/O devices. There are no sequencing requirements for the various power domains. VDDVR (LOW-INDUCTANCE) SET OF DECOUPLING CAPACITORS VDDVR 10μH 100nF + + 100μF VDDINT FDS9431A 100μF 10μF LOW ESR ZHCS1000 VR OUT Table 6. Power Domains Power Domain All internal logic, except RTC, DDR, and USB RTC internal logic and crystal I/O DDR external memory supply USB internal logic and crystal I/O Internal voltage regulator MXVR PLL and logic All other I/O VDD Range VDDINT VDDRTC VDDDDR VDDUSB VDDVR VDDMP VDDEXT VOLTAGE REGULATION The ADSP-BF54x Blackfin processors provide an on-chip voltage regulator that can generate processor core voltage levels from an external supply (see specifications in Operating Conditions on Page 34). Figure 6 on Page 18 shows the typical external components required to complete the power management system. The regulator controls the internal logic voltage levels and is programmable with the voltage regulator control register (VR_CTL) in increments of 50 mV. This register can be accessed using the bfrom_SysControl() function in the on-chip ROM. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power supplied. While in hibernate state, VDDEXT, VDDRTC, VDDDDR, VDDUSB, and VDDVR can still be applied, eliminating the need for external buffers. The voltage regulator can be activated from this power-down state by assertion of the RESET pin, which then initiates a boot sequence. The regulator can also be disabled and bypassed at the user’s discretion. For all 600 MHz speed grade models and all automotive grade models, the internal voltage regulator must not be used and VDDVR must be tied to VDDEXT. For additional information regarding design of the voltage regulator circuit, see Switching Regulator Design Considerations for the ADSPBF533 Blackfin Processors (EE-228). Rev. C | SHORT AND LOWINDUCTANCE WIRE NOTE: DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A. VR OUT GND Figure 6. Voltage Regulator Circuit CLOCK SIGNALS The ADSP-BF54x Blackfin processors can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If an external clock is used, it should be a TTL-compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor’s CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected. Alternatively, because the ADSP-BF54x Blackfin processors include an on-chip oscillator circuit, an external crystal may be used. For fundamental frequency operation, use the circuit shown in Figure 7. A parallel-resonant, fundamental frequency, microprocessor-grade crystal is connected across the CLKIN and XTAL pins. The on-chip resistance between CLKIN and the XTAL pin is in the 500 kΩ range. Typically, further parallel resistors are not recommended. The two capacitors and the series resistor shown in Figure 7 fine-tune phase and amplitude of the sine frequency. The 1MOhm pull-up resistor on the XTAL pin guarantees that the clock circuit is properly held inactive when the processor is in the hibernate state. The capacitor and resistor values shown in Figure 7 are typical values only. The capacitor values are dependent upon the crystal manufacturers’ load capacitance recommendations and the PCB physical layout. The resistor value depends on the drive level specified by the crystal manufacturer. System designs should verify the customized values based on careful investigations on multiple devices over temperature range. Page 18 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 7 illustrates typical system clock ratios. The default ratio is 4. BLACKFIN CLKOUT TO PLL CIRCUITRY EN CLKBUF 700 0 EN VDDEXT Table 7. Example System Clock Ratios XTAL CLKIN 0 * 18 pF* 1M 18 pF* Signal Name SSEL3–0 0010 0110 1010 FOR OVERTONE OPERATION ONLY NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. Figure 7. External Crystal Connections A third-overtone crystal can be used at frequencies above 25 MHz. The circuit is then modified to ensure crystal operation only at the third overtone by adding a tuned inductor circuit as shown in Figure 7. A design procedure for third-overtone operation is discussed in detail in an Application Note, Using Third Overtone Crystals (EE-168). The Blackfin core runs at a different clock rate than the on-chip peripherals. As shown in Figure 8 on Page 19, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a programmable 0.5× to 64× multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 8×, but it can be modified by a software instruction sequence. This sequence is managed by the bfrom_SysControl() function in the on-chip ROM. DYNAMIC MODIFICATION REQUIRES PLL SEQUENCING CLKIN PLL 0.5x - 64x DYNAMIC MODIFICATION ON-THE-FLY 1, 2, 4, 8 CCLK 1:15 SCLK The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1–0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 8. The default ratio is 1. This programmable core clock capability is useful for fast core frequency modifications. The maximum CCLK frequency not only depends on the part’s speed grade, it also depends on the applied VDDINT voltage. See Table 13 on Page 35 for details. Table 8. Core Clock Ratios Signal Name CSEL1–0 00 01 10 11 Divider Ratio VCO/CCLK 1:1 2:1 4:1 8:1 Example Frequency Ratios (MHz) VCO CCLK 300 300 300 150 500 125 200 25 BOOTING MODES The ADSP-BF54x Blackfin processors have many mechanisms (listed in Table 9) for automatically loading internal and external memory after a reset. The boot mode is specified by four BMODE input pins dedicated to this purpose. There are two categories of boot modes: master and slave. In master boot VCO Note: For CCLK and SCLK specifications, see Table 16. Figure 8. Frequency Modification Methods Rev. C | Example Frequency Ratios (MHz) VCO SCLK 200 100 300 50 500 50 Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be dynamically changed without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV) using the bfrom_SysControl() function in the on-chip ROM. On-the-fly CCLK and SCLK frequency changes can be applied by using the bfrom_SysControl() function in the on-chip ROM. Whereas the maximum allowed CCLK and SCLK rates depend on the applied voltages VDDINT and VDDEXT, the VCO is always permitted to run up to the frequency specified by the part’s speed grade. The CLKOUT pin reflects the SCLK frequency to the off-chip world. It functions as a reference for many timing specifications. While inactive by default, it can be enabled using the EBIU_AMGCTL register. Divider Ratio VCO/SCLK 2:1 6:1 10:1 Page 19 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 modes, the processor actively loads data from parallel or serial memories. In slave boot modes, the processor receives data from an external host device. performs an 8- or 16-bit boot or starts program execution at the address provided by the header. By default, all configuration settings are set for the slowest device possible (3cycle hold time; 15-cycle R/W access times; 4-cycle setup). Table 9. Booting Modes The ARDY pin is not enabled by default. It can, however, be enabled by OTP programming. Similarly, all interface behavior and timings can be customized through OTP programming. This includes activation of burst-mode or pagemode operation. In this mode, all asynchronous interface signals are enabled at the port muxing level. BMODE3–0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Idle-no boot Boot from 8- or 16-bit external flash memory Boot from 16-bit asynchronous FIFO Boot from serial SPI memory (EEPROM or flash) Boot from SPI host device Boot from serial TWI memory (EEPROM or flash) Boot from TWI host Boot from UART host Reserved Reserved Boot from DDR SDRAM/Mobile DDR SDRAM Boot from OTP memory Reserved Boot from 8- or 16-bit NAND flash memory via NFC Boot from 16-bit host DMA Boot from 8-bit host DMA The boot modes listed in Table 9 provide a number of mechanisms for automatically loading the processor’s internal and external memories after a reset. By default, all boot modes use the slowest allowed configuration settings. Default settings can be altered via the initialization code feature at boot time or by proper OTP programming at pre-boot time. Some boot modes require a boot host wait (HWAIT) signal, which is a GPIO output signal that is driven and toggled by the boot kernel at boot time. If pulled high through an external pull-up resistor, the HWAIT signal behaves active high and will be driven low when the processor is ready for data. Conversely, when pulled low, HWAIT is driven high when the processor is ready for data. When the boot sequence completes, the HWAIT pin can be used for other purposes. By default, HWAIT functionality is on GPIO port B (PB11). However, if PB11 is otherwise utilized in the system, an alternate boot host wait (HWAITA) signal can be enabled on GPIO port H (PH7) by programming the OTP_ALTERNATE_HWAIT bit in the PBS00L OTP memory page. The BMODE pins of the reset configuration register, sampled during power-on resets and software-initiated resets, implement the following modes: • Idle-no boot mode (BMODE = 0x0)—In this mode, the processor goes into the idle state. The idle boot mode helps to recover from illegal operating modes, in case the OTP memory is misconfigured. • Boot from 8- or 16-bit external flash memory— (BMODE = 0x1)—In this mode, the boot kernel loads the first block header from address 0x2000 0000 and, depending on instructions contained in the header, the boot kernel Rev. C | Page 20 of 100 | • Boot from 16-bit asynchronous FIFO (BMODE = 0x2)—In this mode, the boot kernel starts booting from address 0x2030 0000. Every 16-bit word that the boot kernel has to read from the FIFO must be requested by a low pulse on the DMAR1 pin. • Boot from serial SPI memory, EEPROM or flash (BMODE = 0x3)—8-, 16-, 24- or 32-bit addressable devices are supported. The processor uses the PE4 GPIO pin to select a single SPI EEPROM or flash device and uses SPI0 to submit a read command and successive address bytes (0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device is detected. Pull-up resistors are required on the SPI0SEL1 and SPI0MISO pins. By default, a value of 0x85 is written to the SPI0_BAUD register. • Boot from SPI host device (BMODE = 0x4)—The processor operates in SPI slave mode (using SPI0) and is configured to receive the bytes of the .LDR file from an SPI host (master) agent. The HWAIT signal must be interrogated by the host before every transmitted byte. A pull-up resistor is required on the SPI0SS input. A pull-down resistor on the serial clock (SPI0SCK) may improve signal quality and booting robustness. • Boot from serial TWI memory, EEPROM or flash (BMODE = 0x5)—The processor operates in master mode (using TWI0) and selects the TWI slave with the unique ID 0xA0. The processor submits successive read commands to the memory device starting at two-byte internal address 0x0000 and begins clocking data into the processor. The TWI memory device should comply with Philips I2C Bus Specification version 2.1 and have the capability to autoincrement its internal address counter such that the contents of the memory device can be read sequentially. By default, a prescale value of 0xA and CLKDIV value of 0x0811 is used. Unless altered by OTP settings, an I2C memory that takes two address bytes is assumed. Development tools ensure that data that is booted to memories that cannot be accessed by the Blackfin core is written to an intermediate storage place and then copied to the final destination via memory DMA. • Boot from TWI host (BMODE = 0x6)—The TWI host agent selects the slave with the unique ID 0x5F. The processor (using TWI0) replies with an acknowledgement, and the host can then download the boot stream. The TWI host agent should comply with Philips I2C Bus Specification ver- February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 sion 2.1. An I2C multiplexer can be used to select one processor at a time when booting multiple processors from a single TWI. If the NAND flash device requires only three address cycles, then the device must be capable of ignoring the additional address cycle. The small page NAND flash device must comply with the following command set: • Boot from UART host (BMODE = 0x7)—In this mode, the processor uses UART1 as the booting source. Using an autobaud handshake sequence, a boot-stream-formatted program is downloaded by the host. The host agent selects a bit rate within the UART’s clocking capabilities. Reset: 0xFF Read lower half of page: 0x00 Read upper half of page: 0x01 Read spare area: 0x50 When performing the autobaud, the UART expects an “@” (0x40) character (eight data bits, one start bit, one stop bit, no parity bit) on the UART1RX pin to determine the bit rate. It then replies with an acknowledgement, which is composed of four bytes (0xBF, the value of UART1_DLL, the value of UART1_DLH, and finally 0x00). The host can then download the boot stream. The processor deasserts the UART1RTS output to hold off the host; UART1CTS functionality is not enabled at boot time. • Boot from (DDR) SDRAM (BMODE = 0xA)—In this mode, the boot kernel starts booting from address 0x0000 0010. This is a warm boot scenario only. The SDRAM is expected to contain a valid boot stream and the SDRAM controller must have been configured by the OTP settings. For large page NAND flash devices, the 4-byte electronic signature is read in order to configure the kernel for booting. This allows support for multiple large page devices. The fourth byte of the electronic signature must comply with the specifications in Table 10. Any configuration from Table 10 that also complies with the command set listed below is directly supported by the boot kernel. There are no restrictions on the page size or block size as imposed by the small-page boot kernel. Table 10. Byte 4 Electronic Signature Specification • Boot from 8-bit and 16-bit external NAND flash memory (BMODE = 0xD)—In this mode, auto detection of the NAND flash device is performed. The processor configures PORTJ GPIO pins PJ1 and PJ2 to enable the ND_CE and ND_RB signals, respectively. For correct device operation, pull-up resistors are required on both ND_CE (PJ1) and ND_RB (PJ2) signals. By default, a value of 0x0033 is written to the NFC_CTL register. The booting procedure always starts by booting from byte 0 of block 0 of the NAND flash device. In this boot mode, the HWAIT signal does not toggle. The respective GPIO pin remains in the high-impedance state. Page Size (excluding spare area) 00 1K bytes 01 2K bytes 10 4K bytes 11 8K bytes 0 8 bytes/512 bytes 1 16 bytes/512 bytes 00 64K bytes 01 128K bytes • Device auto detection 10 256K bytes • Error detection and correction for maximum reliability 11 512K bytes 0 x8 1 x16 Spare Area Size Block Size (excluding spare area) NAND flash boot supports the following features: • No boot stream size limitation Bus Width D1:D0 D2 D5:4 D6 • Peripheral DMA via channel 22, providing efficient transfer of all data (excluding the ECC parity data) Not Used for Configuration • Software-configurable boot mode for booting from boot streams expanding multiple blocks, including bad blocks • Software-configurable boot mode for booting from multiple copies of the boot stream allowing for handling of bad blocks and uncorrectable errors Large page devices must support the following command set: Reset: 0xFF Read Electronic Signature: 0x90 Read: 0x00, 0x30 (confirm command) • Configurable timing via OTP memory Small page NAND flash devices must have a 512-byte page size, 32 pages per block, a 16-byte spare area size and a bus configuration of eight bits. By default, all read requests from the NAND flash are followed by four address cycles. Rev. C | D3, D7 Large page devices must not support or react to NAND flash command 0x50. This is a small page NAND flash command used for device auto detection. Page 21 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 SDRAM controller, which then returns using an RTS instruction. The routine may also be the final application, which will never return to the boot kernel. By default, the boot kernel will always issue five address cycles; therefore, if a large page device requires only four cycles, the device must be capable of ignoring the additional address cycle. 16-bit NAND flash memory devices must only support the issuing of command and address cycles via the lower eight bits of the data bus. Devices that use the full 16-bit bus for command and address cycles are not supported. • Boot from OTP memory (BMODE = 0xB)—This provides a standalone booting method. The boot stream is loaded from on-chip OTP memory. By default, the boot stream is expected to start from OTP page 0x40 and can occupy all public OTP memory up to page 0xDF (2560 bytes). Since the start page is programmable, the maximum size of the boot stream can be extended to 3072 bytes. • Boot from 16-bit host DMA (BMODE = 0xE)—In this mode, the host DMA port is configured in 16-bit acknowledge mode with little endian data format. Unlike other modes, the host is responsible for interpreting the boot stream. It writes data blocks individually into the host DMA port. Before configuring the DMA settings for each block, the host may either poll the ALLOW_CONFIG bit in HOST_STATUS or wait to be interrupted by the HWAIT signal. When using HWAIT, the host must still check ALLOW_CONFIG at least once before beginning to configure the host DMA port. After completing the configuration, the host is required to poll the READY bit in HOST_STATUS before beginning to transfer data. When the host sends an HIRQ control command, the boot kernel issues a CALL instruction to address 0xFFA0 0000. It is the host’s responsibility to ensure valid code has been placed at this address. The routine at address 0xFFA0 0000 can be a simple initialization routine to configure internal resources, such as the SDRAM controller, which then returns using an RTS instruction. The routine may also be the final application, which will never return to the boot kernel. • Boot from 8-bit host DMA (BMODE = 0xF)—In this mode, the host DMA port is configured in 8-bit interrupt mode with little endian data format. Unlike other modes, the host is responsible for interpreting the boot stream. It writes data blocks individually to the host DMA port. Before configuring the DMA settings for each block, the host may either poll the ALLOW_CONFIG bit in HOST_STATUS or wait to be interrupted by the HWAIT signal. When using HWAIT, the host must still check ALLOW_CONFIG at least once before beginning to configure the host DMA port. The host will receive an interrupt from the HOST_ACK signal every time it is allowed to send the next FIFO depth’s worth (sixteen 32-bit words) of information. When the host sends an HIRQ control command, the boot kernel issues a CALL instruction to address 0xFFA0 0000. It is the host's responsibility to ensure valid code has been placed at this address. The routine at address 0xFFA0 0000 can be a simple initialization routine to configure internal resources, such as the Rev. C | For each of the boot modes, a 16-byte header is first read from an external memory device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, program execution commences from the address stored in the EVT1 register. Prior to booting, the pre-boot routine interrogates the OTP memory. Individual boot modes can be customized or disabled based on OTP programming. External hardware, especially booting hosts, may monitor the HWAIT signal to determine when the pre-boot has finished and the boot kernel starts the boot process. However, the HWAIT signal does not toggle in NAND boot mode. By programming OTP memory, the user can instruct the preboot routine to also customize the PLL, voltage regulator, DDR controller, and/or asynchronous memory interface controller. The boot kernel differentiates between a regular hardware reset and a wakeup-from-hibernate event to speed up booting in the later case. Bits 6-4 in the system reset configuration (SYSCR) register can be used to bypass the pre-boot routine and/or boot kernel in case of a software reset. They can also be used to simulate a wakeup-from-hibernate boot in the software reset case. The boot process can be further customized by “initialization code.” This is a piece of code that is loaded and executed prior to the regular application boot. Typically, this is used to configure the DDR controller or to speed up booting by managing PLL, clock frequencies, wait states, and/or serial bit rates. The boot ROM also features C-callable function entries that can be called by the user application at run time. This enables second-stage boot or booting management schemes to be implemented with ease. INSTRUCTION SET DESCRIPTION The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources. Page 22 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages: • Seamlessly integrated DSP/MCU features are optimized for both 8-bit and 16-bit operations. • A multi-issue load/store modified-Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle. • All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model. • Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and supervisor stack pointers. • Code density enhancements, which include intermixing of 16- and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits. DEVELOPMENT TOOLS (EE-68) on the Analog Devices web site under www.analog.com/ee-notes. This document is updated regularly to keep pace with improvements to emulator support. MXVR BOARD LAYOUT GUIDELINES The MXVR Loop Filter RC network is connected between the MLF_P and MLF_M pins in the following manner: Capacitors: • C1: 0.047 µF (PPS type, 2% tolerance recommended) • C2: 330 pF (PPS type, 2% tolerance recommended) Resistor: • R1: 330 Ω (1% tolerance) The RC network should be located physically close to the MLF_P and MLF_M pins on the board. The RC network should be shielded using GNDMP traces. Avoid routing other switching signals near the RC network to avoid crosstalk. MXI driven with external clock oscillator IC: • MXI should be driven with the clock output of a clock oscillator IC running at a frequency of 49.152 MHz or 45.1584 MHz. The ADSP-BF54x Blackfin processors are supported with a complete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP-BF54x Blackfin processors. • MXO should be left unconnected. • Avoid routing other switching signals near the oscillator and clock output trace to avoid crosstalk. When not possible, shield traces with ground. EZ-KIT Lite Evaluation Board For evaluation of ADSP-BF54x Blackfin processors, use the ADSP-BF548 EZ-KIT Lite® board available from Analog Devices. Order part number ADZS-BF548-EZLITE. The board comes with on-chip emulation capabilities and is equipped to enable software development. Multiple daughter cards are available. MXI/MXO with external crystal: • The crystal must be a fundamental mode crystal running at a frequency of 49.152 MHz or 45.1584 MHz. • The crystal and load capacitors should be placed physically close to the MXI and MXO pins on the board. • Board trace capacitance on each lead should not be more than 3 pF. DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor is set running at full speed with no impact on system timing. • Trace capacitance plus load capacitance should equal the load capacitance specification for the crystal. • Avoid routing other switching signals near the crystal and components to avoid crosstalk. When not possible, shield traces and components with ground. VDDMP/GNDMP—MXVR PLL power domain: To use these emulators, the target board must include a header that connects the processor’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see Analog Devices JTAG Emulation Technical Reference Rev. C | Page 23 of 100 | • Route VDDMP and GNDMP with wide traces or as isolated power planes. • Drive VDDMP to same level as VDDINT. • Place a ferrite bead between the VDDINT power plane and the VDDMP pin for noise isolation. • Locally bypass VDDMP with 0.1 µF and 0.01 µF decoupling capacitors to GNDMP. • Avoid routing switching signals near to VDDMP and GNDMP traces to avoid crosstalk. February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Fiber optic transceiver (FOT) connections: • Keep the traces between the ADSP-BF549 processor and the FOT as short as possible. • The receive data trace connecting the FOT receive data output pin to the ADSP-BF549 PH6/MRX input pin should have a 0 Ω series termination resistor placed close to the FOT receive data output pin. Typically, the edge rate of the FOT receive data signal driven by the FOT is very slow, and further degradation of the edge rate is not desirable. • The transmit data trace connecting the ADSP-BF549 PH5/MTX output pin to the FOT transmit data input pin should have a 27 Ω series termination resistor placed close to the ADSP-BF549 PH5/MTX pin. • The receive data trace and the transmit data trace between the ADSP-BF549 processor and the FOT should not be routed close to each other in parallel over long distances to avoid crosstalk. RELATED DOCUMENTS The following publications that describe the ADSP-BF54x Blackfin processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on www.analog.com: • ADSP-BF54x Blackfin Processor Hardware Reference, Volume 1 and Volume 2 • Blackfin Processor Programming Reference • ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Anomaly List LOCKBOX SECURE TECHNOLOGY DISCLAIMER Analog Devices products containing Lockbox Secure Technology are warranted by Analog Devices as detailed in the Analog Devices Standard Terms and Conditions of Sale. To our knowledge, the Lockbox secure technology, when used in accordance with the data sheet and hardware reference manual specifications, provides a secure method of implementing code and data safeguards. However, Analog Devices does not guarantee that this technology provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE LOCKBOX SECURE TECHNOLOGY CANNOT BE BREACHED, COMPROMISED, OR OTHERWISE CIRCUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY. Rev. C | Page 24 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 PIN DESCRIPTIONS ADSP-BF54x Blackfin processors’ pin multiplexing scheme is listed in Table 11 and the pin definitions are listed in Table 12. Table 11. Pin Multiplexing Primary Pin Function (Number of Pins)1, 2 Port A GPIO (16 pins) First Peripheral Function Second Peripheral Function Third Peripheral Function SPORT2 (8 pins) TMR4 (1 pin) TMR5 (1 pin) TMR6 (1 pin) TMR7 (1 pin) TACI7 (1 pin) TACLK7–0 (8 pins) Interrupts (16 pins) TACI2-3 (2 pins) Interrupts (15 pins) SPORT3 (8 pins) Port B GPIO (15 pins) Port C GPIO (16 pins) TWI1 (2 pins) UART2 or 3 CTL (2 pins) UART2 (2 pins) UART3 (2 pins) SPI2 SEL1-3 (3 pins) TMR0–2 (3 pins) SPI2 (3 pins) TMR3 (1 pin) SPORT0 (8 pins) Fourth Peripheral Function HWAIT (1 pin) Interrupts (8 pins)3 MXVR MMCLK, MBCLK (2 pins) SDH (6 pins) Port D GPIO (16 pins) Port E GPIO (16 pins) PPI1 D0–15 (16 pins) SPI0 (7 pins) UART0 TX (1 pin) UART0 RX (1 pin) UART0 or 1 CTL (2 pins) PPI1 CLK,FS (3 pins) TWI0 (2 pins) Port F GPIO (16 pins) Port G GPIO (16 pins) Interrupt Capability Interrupts (8 pins) Host D0–15 (16 pins) Keypad Row 4–6 Col 4–7 (7 pins) Keypad R7 (1 pin) SPORT1 (8 pins) PPI0 D18– 23 (6 pins) Interrupts (8 pins) PPI2 D0–7 (8 pins) Keypad Row 0–3 Col 0–3 (8 pins) Interrupts (8 pins) TACI0 (1 pin) Interrupts (8 pins) Interrupts (8 pins) PPI0 D0–15 (16 pins) ATAPI D0-15A Interrupts (8 pins) Interrupts (8 pins) PPI0 CLK,FS (3 pins) DATA 16–17 (2 pins) TMRCLK (1 pin) ATAPI A0-2A Host CTL (3 pins) MXVR MTXON (1 pin) Interrupts (8 pins) SPI1 SEL1–3 (3 pins) SPI1 (4 pins) CAN0 (2 pins) CAN1 (2 pins) Rev. C | PPI2 CLK,FS (3 pins) TACI4-5 (2 pins) Page 25 of 100 | February 2010 CZM (1 pin) Interrupts (8 pins) ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 11. Pin Multiplexing (Continued) Primary Pin Function (Number of Pins)1, 2 Port H GPIO (14 pins) First Peripheral Function Second Peripheral Function Third Peripheral Function UART1 (2 pins) ATAPI_RESET (1 pin) HOST_ADDR (1 pin) PPI0-1_FS3 (2 pins) TMR8 (1 pin) TMR9 (1 pin) HOST_ACK (1 pin) TMR10 (1 pin) TACI1 (1 pin) PPI2_FS3 (1 pin) Counter Down/Gate (1 pin) Counter Up/Dir (1 pin) DMAR 0–1 (2 pins) MXVR MRX, MTX, MRXON/GPW (3 pins)4 Fourth Peripheral Function Interrupts (8 pins) TACI8–10 (3 pins) TACLK8–10 (3 pins) HWAITA AMC Addr 4-9 (6 pins) Port I GPIO (16 pins) Interrupt Capability Interrupts (6 pins) Async Addr10–25 (16 pins) Interrupts (8 pins) Interrupts (8 pins) Port J GPIO (14 pins) Async CTL and MISC Interrupts (8 pins) Interrupts (6 pins) 1 Port connections may be inputs or outputs after power up depending on the model and boot mode chosen. All port connections always power up as inputs for some period of time and require resistive termination to a safe condition if used as outputs in the system. 3 A total of 32 interrupts at once are available from ports C through J, configurable in byte-wide blocks. 4 GPW functionality available when MXVR is not present or unused. 2 ADSP-BF54x processor pin definitions are listed in Table 12. To see the pin multiplexing scheme, see Table 11. Table 12. Pin Descriptions Pin Name Port A: GPIO/SPORT2–3/TMR4–7 PA0/TFS2 PA1/DT2SEC/TMR4 PA2/DT2PRI PA3/TSCLK2 PA4/RFS2 PA5/DR2SEC/TMR5 PA6/DR2PRI PA7/RSCLK2/TACLK0 PA8/TFS3/TACLK1 PA9/DT3SEC/TMR6 PA10/DT3PRI/TACLK2 PA11/TSCLK3/TACLK3 PA12/RFS3/TACLK4 PA13/DR3SEC/TMR7/TACLK5 PA14/DR3PRI/TACLK6 PA15/RSCLK3/TACLK7 and TACI7 I/O1 Function (First/Second/Third/Fourth) Driver Type2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O C C C A C C C A C C C A C C C A Rev. C | GPIO/SPORT2 Transmit Frame Sync GPIO/SPORT2 Transmit Data Secondary/Timer 4 GPIO/SPORT2 Transmit Data Primary GPIO/SPORT2 Transmit Serial Clock GPIO/SPORT2 Receive Frame Sync GPIO/SPORT2 Receive Data Secondary/Timer 5 GPIO/SPORT2 Receive Data Primary GPIO/SPORT2 Receive Serial Clock/Alternate Input Clock 0 GPIO/SPORT3 Transmit Frame Sync/Alternate Input Clock 1 GPIO/SPORT3 Transmit Data Secondary/Timer 6 GPIO/SPORT3 Transmit Data Primary/Alternate Input Clock 2 GPIO/SPORT3 Transmit Serial Clock/Alternate Input Clock 3 GPIO/SPORT3 Receive Frame Sync/Alternate Input Clock 4 GPIO/SPORT3 Receive Data Secondary/Timer 7/Alternate Input Clock 5 GPIO/SPORT3 Receive Data Primary/Alternate Input Clock 6 GPIO/SPORT3 Receive Serial Clock/Alt Input Clock 7 and Alt Capture Input 7 Page 26 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Port B: GPIO/TWI1/UART2–3/SPI2/TMR0–3 PB0/SCL1 PB1/SDA1 PB2/UART3RTS PB3/UART3CTS PB4/UART2TX PB5/UART2RX/TACI2 PB6/UART3TX PB7/UART3RX/TACI3 PB8/SPI2SS /TMR0 PB9/SPI2SEL1/TMR1 PB10 SPI2SEL2/TMR2 PB11/SPI2SEL3/TMR3/ HWAIT PB12/SPI2SCK PB13/SPI2MOSI PB14/SPI2MISO Port C: GPIO/SPORT0/SD Controller/MXVR (MOST) PC0/TFS0 PC1/DT0SEC/MMCLK PC2/DT0PRI PC3/TSCLK0 PC4/RFS0 PC5/DR0SEC/MBCLK PC6/DR0PRI PC7/RSCLK0 PC8/SD_D0 PC9/SD_D1 PC10/SD_D2 PC11/SD_D3 PC12/SD_CLK PC13/SD_CMD I/O1 Function (First/Second/Third/Fourth) Driver Type2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO/TWI1 Serial Clock (Open-drain output: requires a pull-up resistor.) GPIO/TWI1 Serial Data (Open-drain output: requires a pull-up resistor.) GPIO/UART3 Request to Send GPIO/UART3 Clear to Send GPIO/UART2 Transmit GPIO/UART2 Receive/Alternate Capture Input 2 GPIO/UART3 Transmit GPIO/UART3 Receive/Alternate Capture Input 3 GPIO/SPI2 Slave Select Input/Timer 0 GPIO/SPI2 Slave Select Enable 1/Timer 1 GPIO/SPI2 Slave Select Enable 2/Timer 2 GPIO/SPI2 Slave Select Enable 3/Timer 3/Boot Host Wait GPIO/SPI2 Clock GPIO/SPI2 Master Out Slave In GPIO/SPI2 Master In Slave Out E E C A A A A A A A A A A C C I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO/SPORT0 Transmit Frame Sync GPIO/SPORT0 Transmit Data Secondary/MXVR Master Clock GPIO/SPORT0 Transmit Data Primary GPIO/SPORT0 Transmit Serial Clock GPIO/SPORT0 Receive Frame Sync GPIO/SPORT0 Receive Data Secondary/MXVR Bit Clock GPIO/SPORT0 Receive Data Primary GPIO/SPORT0 Receive Serial Clock GPIO/SD Data Bus GPIO/SD Data Bus GPIO/SD Data Bus GPIO/SD Data Bus GPIO/SD Clock Output GPIO/SD Command C C C A C C C C A A A A A A Rev. C | Page 27 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Port D: GPIO/PPI0–2/SPORT 1/Keypad/Host DMA PD0/PPI1_D0/HOST_D8/ TFS1/PPI0_D18 PD1/PPI1_D1/HOST_D9/ DT1SEC/PPI0_D19 PD2/PPI1_D2/HOST_D10/ DT1PRI/PPI0_D20 PD3/PPI1_D3/HOST_D11/ TSCLK1/PPI0_D21 PD4/PPI1_D4/HOST_D12/RFS1/PPI0_D22 PD5/PPI1_D5/HOST_D13/DR1SEC/PPI0_D23 PD6/PPI1_D6/HOST_D14/DR1PRI PD7/PPI1_D7/HOST_D15/RSCLK1 PD8/PPI1_D8/HOST_D0/ PPI2_D0/KEY_ROW0 PD9/PPI1_D9/HOST_D1/PPI2_D1/KEY_ROW1 PD10/PPI1_D10/HOST_D2/PPI2_D2/KEY_ROW2 PD11/PPI1_D11/HOST_D3/PPI2_D3/KEY_ROW3 PD12/PPI1_D12/HOST_D4/PPI2_D4/KEY_COL0 PD13/PPI1_D13/HOST_D5/PPI2_D5/KEY_COL1 PD14/PPI1_D14/HOST_D6/PPI2_D6/KEY_COL2 PD15/PPI1_D15/HOST_D7/PPI2_D7/KEY_COL3 Port E: GPIO/SPI0/UART0-1/PPI1/TWI0/Keypad PE0/SPI0SCK/KEY_COL73 PE1/SPI0MISO/KEY_ROW63 PE2/SPI0MOSI/KEY_COL6 PE3/SPI0SS/KEY_ROW5 PE4/SPI0SEL1/KEY_COL3 PE5/SPI0SEL2/KEY_ROW4 PE6/SPI0SEL3/KEY_COL4 PE7/UART0TX/KEY_ROW7 PE8/UART0RX/TACI0 PE9/UART1RTS PE10/UART1CTS PE11/PPI1_CLK PE12/PPI1_FS1 PE13/PPI1_FS2 PE14/SCL0 PE15/SDA0 I/O1 Function (First/Second/Third/Fourth) Driver Type2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Frame Sync/PPI0 Data GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Data Secondary/PPI0 Data GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Data Primary/PPI0 Data GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Serial Clock/PPI0 Data GPIO/PPI1 Data/Host DMA/SPORT1 Receive Frame Sync/PPI0 Data GPIO/PPI1 Data/Host DMA/SPORT1 Receive Data Secondary/PPI0 Data GPIO/PPI1 Data/Host DMA/SPORT1 Receive Data Primary GPIO/PPI1 Data /Host DMA/SPORT1 Receive Serial Clock GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Row Input GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Row Input GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Row Input GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Row Input GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Column Output GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Column Output GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Column Output GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Column Output C C C A C C C A A A A A A A A A I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO/SPI0 Clock/Keypad Column Output GPIO/SPI0 Master In Slave Out/Keypad Row Input GPIO/SPI0 Master Out Slave In/Keypad Column Output GPIO/SPI0 Slave Select Input/Keypad Row Input GPIO/SPI0 Slave Select Enable 1/Keypad Column Output GPIO/SPI0 Slave Select Enable 2/Keypad Row Input GPIO/SPI0 Slave Select Enable 3/Keypad Column Output GPIO/UART0 Transmit/Keypad Row Input GPIO/UART0 Receive/Alternate Capture Input 0 GPIO/UART1 Request to Send GPIO/UART1 Clear to Send GPIO / PPI1Clock GPIO/PPI1 Frame Sync 1 GPIO/PPI1 Frame Sync 2 GPIO/TWI0 Serial Clock (Open-drain output: requires a pull-up resistor.) GPIO/TWI0 Serial Data (Open-drain output: requires a pull-up resistor.) A C C A A A A A A A A A A A E E Rev. C | Page 28 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Port F: GPIO/PPI0/Alternate ATAPI Data PF0/PPI0_D0/ATAPI_D0A PF1/PPI0_D1/ATAPI_D1A PF2/PPI0_D2/ATAPI_D2A PF3/PPI0_D3/ATAPI_D3A PF4/PPI0_D4/ATAPI_D4A PF5/PPI0_D5/ATAPI_D5A PF6/PPI0_D6/ATAPI_D6A PF7/PPI0_D7/ATAPI_D7A PF8/PPI0_D8/ATAPI_D8A PF9/PPI0_D9/ATAPI_D9A PF10/PPI0_D10/ATAPI_D10A PF11/PPI0_D11/ATAPI_D11A PF12/PPI0_D12/ATAPI_D12A PF13/PPI0_D13/ATAPI_D13A PF14/PPI0_D14/ATAPI_D14A PF15/PPI0_D15/ATAPI_D15A Port G: GPIO/PPI0/SPI1/PPI2/Up-Down Counter/CAN0–1/Host DMA/MXVR (MOST)/ATAPI PG0/PPI0_CLK/TMRCLK PG1/PPI0_FS1 PG2/PPI0_FS2/ATAPI_A0A PG3/PPI0_D16/ATAPI_A1A PG4/PPI0_D17/ATAPI_A2A PG5/SPI1SEL1/HOST_CE/PPI2_FS2/CZM PG6/SPI1SEL2/HOST_RD/PPI2_FS1 PG7/SPI1SEL3/HOST_WR/PPI2_CLK PG8/SPI1SCK PG9/SPI1MISO PG10/SPI1MOSI PG11/SPI1SS/MTXON PG12/CAN0TX PG13/CAN0RX/TACI4 PG14/CAN1TX PG15/CAN1RX/TACI5 I/O1 Function (First/Second/Third/Fourth) Driver Type2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data A A A A A A A A A A A A A A A A I/O I/O I/O I/O I/O I/O GPIO/PPI0 Clock/External Timer Reference GPIO/PPI0 Frame Sync 1 GPIO/PPI0 Frame Sync 2/Alternate ATAPI Address GPIO/PPI0 Data/Alternate ATAPI Address GPIO/PPI0 Data/Alternate ATAPI Address GPIO/SPI1 Slave Select/Host DMA Chip Enable/PPI2 Frame Sync 2/Counter Zero Marker GPIO/SPI1 Slave Select/ Host DMA Read/PPI2 Frame Sync 1 GPIO/SPI1 Slave Select/Host DMA Write/PPI2 Clock GPIO/SPI1 Clock GPIO/SPI1 Master In Slave Out GPIO/SPI1 Master Out Slave In GPIO/SPI1 Slave Select Input/MXVR Transmit Phy On GPIO/CAN0 Transmit GPIO/CAN0 Receive/Alternate Capture Input 4 GPIO/CAN1 Transmit GPIO/CAN1 Receive/Alternate Capture Input 5 A A A A A A I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Rev. C | Page 29 of 100 | February 2010 A A C C C A A A A A ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name Port H: GPIO/AMC/EXTDMA/UART1/PPI0–2/ATAPI/UpDown Counter/TMR8-10/Host DMA/MXVR (MOST) PH0/UART1TX/PPI1_FS3_DEN PH1/UART1RX/PPI0_FS3_DEN/TACI1 PH2/ATAPI_RESET/TMR8/PPI2_FS3_DEN PH3/HOST_ADDR/TMR9/CDG PH4/HOST_ACK/TMR10/CUD PH5/MTX/DMAR0/TACI8 and TACLK8 PH6/MRX/DMAR1/TACI9 and TACLK9 PH7/MRXON/GPW/TACI10 and TACLK10/HWAITA 4,5 PH8/A46 PH9/A56 PH10/A66 PH11/A76 PH12/A86 PH13/A96 Port I: GPIO/AMC PI0/A106 PI1/A116 PI2/A126 PI3/A136 PI4/A146 PI5/A156 PI6/A166 PI7/A176 PI8/A186 PI9/A196 PI10/A206 PI11/A216 PI12/A226 PI13/A236 PI14/A246 PI15/A25/NR_CLK6 I/O1 Function (First/Second/Third/Fourth) Driver Type2 I/O I/O I/O I/O I/O I/O I/O I/O A A A A A C A A I/O I/O I/O I/O I/O I/O GPIO/UART1 Transmit/PPI1 Frame Sync 3 GPIO/UART 1 Receive/ PPI0 Frame Sync 3/Alternate Capture Input 1 GPIO/ATAPI Interface Hard Reset Signal/Timer 8/PPI2 Frame Sync 3 GPIO/HOST Address/Timer 9/Count Down and Gate GPIO/HOST Acknowledge/Timer 10/Count Up and Direction GPIO/MXVR Transmit Data/Ext. DMA Request/Alt Capt. In. 8 /Alt In. Clk 8 GPIO/MXVR Receive Data/Ext. DMA Request/Alt Capt. In. 9 /Alt In. Clk 9 GPIO/MXVR Receive Phy On /Alt Capt. In. 10 /Alt In. Clk 10/Alternate Boot Host Wait GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access GPIO/Address Bus for Async Access/ NOR clock A A A A A A A A A A A A A A A A Rev. C | Page 30 of 100 | February 2010 A A A A A A ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) I/O1 Function (First/Second/Third/Fourth) Driver Type2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO/ Async Ready/NOR Wait GPIO/NAND Chip Enable GPIO/NAND Ready Busy GPIO/ATAPI Read GPIO/ATAPI Write GPIO/ATAPI Chip Select/Command Block GPIO/ATAPI Chip Select GPIO/ATAPI DMA Acknowledge GPIO/ATAPI DMA Request GPIO/Interrupt Request from the Device GPIO/ATAPI Ready Handshake GPIO/Bus Request GPIO/Bus Grant GPIO/Bus Grant Hang A A A A A A A A A A A A A A O O I/O I/O O O O O O O O O I I DDR Address Bus DDR Bank Active Strobe DDR Data Bus DDR Data Strobe DDR Data Mask for Reads and Writes DDR Output Clock DDR Complementary Output Clock DDR Chip Selects DDR Clock Enable DDR Row Address Strobe DDR Column Address Strobe DDR Write Enable DDR Voltage Reference DDR Voltage Reference Shield (Must be connected to GND.) D D D D D D D D D D D D O I/O O O Address Bus for Async and ATAPI Addresses Data Bus for Async, NAND and ATAPI Accesses Bank Selects (Pull high with a resistor when used as chip select.) Byte Enables:Data Masks for Asynchronous Access/NAND Command Latch Enable Byte Enables:Data Masks for Asynchronous Access/NAND Address Latch Enable Output Enable/NOR Address Data Valid Read Enable/NOR Output Enable Write Enable A A A A Pin Name Port J: GPIO/AMC/ATAPI PJ0/ARDY/WAIT PJ1/ND_CE7 PJ2/ND_RB PJ3/ATAPI_DIOR PJ4/ATAPI_DIOW PJ5/ATAPI_CS0 PJ6/ATAPI_CS1 PJ7/ATAPI_DMACK PJ8/ATAPI_DMARQ PJ9/ATAPI_INTRQ PJ10/ATAPI_IORDY PJ11/BR8 PJ12/BG6 PJ13/BGH6 DDR Memory Interface DA0–12 DBA0–1 DQ0–15 DQS0–1 DQM0–1 DCLK0–1 DCLK0–1 DCS0–1 DCLKE9 DRAS DCAS DWE DDR_VREF DDR_VSSR Asynchronous Memory Interface A1-3 D0-15/ND_D0-15/ATAPI_D0-15 AMS0–3 ABE0 /ND_CLE ABE1/ND_ALE O AOE/NR_ADV ARE AWE ATAPI Controller Pins ATAPI_PDIAG O O O I Rev. C | Determines if an 80-pin cable is connected to the host. (Pull high or low when unused.) Page 31 of 100 | February 2010 A A A A ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) I/O1 Function (First/Second/Third/Fourth) Pin Name High Speed USB OTG Pins USB_DP USB_DM USB_XI USB_XO USB_ID10 USB_VBUS11 USB_VREF I/O I/O C C I I/O A USB_RSET A MXVR (MOST) Interface MFS MLF_P MLF_M MXI MXO Mode Control Pins BMODE0–3 JTAG Port Pins TDI TDO TRST TMS TCK EMU Voltage Regulator VROUT0, VROUT1 Real Time Clock RTXO RTXI Clock (PLL) Pins CLKIN CLKOUT XTAL CLKBUF EXT_WAKE RESET NMI Supplies VDDINT VDDEXT12 VDDDDR12 VDDUSB12 VDDRTC12 USB D+ Pin (Pull low when unused.) USB D- Pin (Pull low when unused.) Clock XTAL Input (Pull high or low when unused.) Clock XTAL Output (Leave unconnected when unused.) USB OTG ID Pin (Pull high when unused.) USB VBUS Pin (Pull high or low when unused.) USB Voltage Reference (Connect to GND through a 0.1 mF capacitor or leave unconnected when not used.) USB Resistance Set (Connect to GND through an unpopulated resistor pad.) O A A C C MXVR Frame Sync (Leave unconnected when unused.) MXVR Loop Filter Plus (Leave unconnected when unused.) MXVR Loop Filter Minus (Leave unconnected when unused.) MXVR Crystal Input (Pull high or low when unused.) MXVR Crystal Output (Pull high or low when unused.) I Boot Mode Strap 0–3 I O I I I O JTAG Serial Data In JTAG Serial Data Out JTAG Reset (Pull low when unused.) JTAG Mode Select JTAG Clock Emulation Output O External FET/BJT Drivers (Always connect together to reduce signal impedance.) C C RTC Crystal Output (Leave unconnected when unused.) RTC Crystal Input (Pull high or low when unused.) C O C O O I I Clock/Crystal Input Clock Output Crystal Output Buffered Oscillator Output External Wakeup from Hibernate Output Reset Non-maskable Interrupt (Pull high when unused.) P P P P P Internal Power Supply External Power Supply External DDR Power Supply External USB Power Supply RTC Clock Supply Rev. C | Driver Type2 Page 32 of 100 | February 2010 C C C B C A ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 12. Pin Descriptions (Continued) Pin Name VDDVR13 GND VDDMP12 GNDMP12 Driver I/O1 Function (First/Second/Third/Fourth) Type2 P Internal Voltage Regulator Power Supply (Connect to VDDEXT when unused.) G Ground P MXVR PLL Power Supply. (Must be driven to same level as VDDINT. Connect to VDDINT when unused or when MXVR is not present.) G MXVR PLL Ground (Connect to GND when unused or when MXVR is not present.) 1 I = Input, O = Output, P =Power, G = Ground, C = Crystal, A = Analog. Refer to Table 61 on Page 86 through Table 70 on Page 87 for driver types. 3 To use the SPI memory boot, SPI0SCK should have a pulldown, SPI0MISO should have a pullup, and SPI0SEL1 is used as the CS with a pullup. 4 HWAIT/HWAITA should be pulled high or low to configure polarity. See Booting Modes on Page 19. 5 GPW functionality is available when MXVR is not present or unused. 6 This pin should not be used as GPIO if booting in mode 1. 7 This pin should always be enabled as ND_CE in software and pulled high with a resistor when using NAND flash. 8 This pin should always be enabled as BR in software and pulled high to enable asynchronous access. 9 This pin must be pulled low through a 10kOhm resistor if self-refresh mode is desired during hibernate state or deep-sleep mode. 10 If the USB is used in device mode only, the USB_ID pin should be either pulled high or left unconnected. 11 This pin is an output only during initialization of USB OTG session request pulses. Therefore, host mode or OTG type A mode requires that an external voltage source of 5 V, at 8 mA or more per the OTG specification, be applied to this pin. Other OTG modes require that this external voltage be disabled. 12 To ensure proper operation, the power pins should be driven to their specified level even if the associated peripheral is not used in the application. 13 This pin must always be connected. If the internal voltage regulator is not being used, this pin may be connected to VDDEXT. Otherwise it should be powered according to the VDDVR specification. For automotive grade models, the internal voltage regulator must not be used and this pin must be tied to VDDEXT. 2 Rev. C | Page 33 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 SPECIFICATIONS Component specifications are subject to change without notice. OPERATING CONDITIONS Parameter VDDINT1, 2 VDDEXT3 VDDUSB VDDMP VDDRTC VDDDDR VDDVR4 VIH VIHDDR VIH5V12 VIHTWI VIHUSB VIL VIL5V VILDDR VILTWI VDDR_VREF TJ14 Internal Supply Voltage Internal Supply Voltage Internal Supply Voltage External Supply Voltage External Supply Voltage External Supply Voltage USB External Supply Voltage MXVR PLL Supply Voltage MXVR PLL Supply Voltage Real Time Clock Supply Voltage Real Time Clock Supply Voltage DDR Memory Supply Voltage DDR Memory Supply Voltage Internal Voltage Regulator Supply Voltage High Level Input Voltage5, 6 High Level Input Voltage7 High Level Input Voltage7 High Level Input Voltage8 High Level Input Voltage 9, 13 High Level Input Voltage10 Low Level Input Voltage5, 11 Low Level Input Voltage12 Low Level Input Voltage12 Low Level Input Voltage7 Low Level Input Voltage7 Low Level Input Voltage9, 13 DDR_VREF Pin Input Voltage Conditions Nonautomotive grade models Automotive grade models Mobile DDR SDRAM models Nonautomotive 3.3 V I/O Nonautomotive 2.5 V I/O Automotive grade models Min 0.9 1.0 1.14 2.7 2.25 2.7 3.0 0.9 1.0 2.25 2.7 2.5 1.8 2.7 Nonautomotive grade models Automotive grade models Nonautomotive grade models Automotive grade models DDR SDRAM models Mobile DDR SDRAM models VDDEXT = maximum DDR SDRAM models Mobile DDR SDRAM models VDDEXT = maximum VDDEXT = maximum 2.0 VDDR_VREF + 0.15 VDDR_VREF + 0.125 2.0 0.7 x VDDEXT VDDEXT = minimum 3.3 V I/O, VDDEXT = minimum 2.5 V I/O, VDDEXT = minimum DDR SDRAM models Mobile DDR SDRAM models –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 0.49 x VDDDDR Junction Temperature (400/533 MHz) 400-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @TAMBIENT = –40ºC to +85ºC Junction Temperature (600 MHz) 400-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @TAMBIENT = 0ºC to +70ºC 1 Nominal 3.3 2.5 3.3 3.3 3.3 2.6 1.875 3.3 Max 1.43 1.38 1.31 3.6 2.75 3.6 3.6 1.43 1.38 3.6 3.6 2.7 1.95 3.6 Unit V V V V V V V V V V V V V V 3.6 VDDDDR + 0.3 VDDDDR + 0.3 5.5 5.5 5.25 0.6 0.8 0.6 VDDR_VREF – 0.15 VDDR_VREF – 0.125 0.3 x VDDEXT 0.51 x VDDDDR V V V V V V V V V V V V V –40 +105 º C 0 +90 º C 0.50 x VDDDDR See Table 13 on Page 35 for frequency/voltage specifications. VDDINT maximum is 1.10 V during one-time-programmable (OTP) memory programming operations. 3 VDDEXT minimum is 3.0 V and maximum is 3.6 V during OTP memory programming operations. 4 Use of the internal voltage regulator is not supported on 600 MHz speed grade models or on automotive grade models. An external voltage regulator must be used. 5 Bidirectional pins (D15–0, PA15–0, PB14–0, PC15–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0) and input pins (ATAPI_PDIAG, USB_ID, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF54x Blackfin processors are 3.3 V-tolerant (always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. The regulator can generate VDDINT at levels of 0.90 V to 1.30 V with -5% to +5% tolerance. 6 Parameter value applies to all input and bidirectional pins except PB1-0, PE15-14, PG15–11, PH7-6, DQ0-15, and DQS0-1. 2 Rev. C | Page 34 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 7 Parameter value applies to pins DQ0–15 and DQS0–1. PB1-0, PE15-14, PG15-11, and PH7-6 are 5.0 V-tolerant (always accept up to 5.5 V maximum VIH when power is applied to VDDEXT pins). Voltage compliance (on output VOH) is limited by VDDEXT supply voltage. 9 SDA and SCL are 5.0V tolerant (always accept up to 5.5V maximum VIH). Voltage compliance on outputs (VOH) is limited by the VDDEXT supply voltage. 10 Parameter value applies to USB_DP, USB_DM, and USB_VBUS pins. See Absolute Maximum Ratings on Page 40. 11 Parameter value applies to all input and bidirectional pins, except PB1-0, PE15-14, PG15–11, and PH7-6. 12 Parameter value applies to pins PG15–11 and PH7-6. 13 Parameter value applies to pins PB1-0 and PE15-14. Consult the I2C specification version 2.1 for the proper resistor value and other open drain pin electrical parameters. 14 TJ must be in the range: 0°C < TJ < 55°C during OTP memory programming operations. 8 Table 13 and Table 16 describe the voltage/frequency requirements for the ADSP-BF54x Blackfin processors’ clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock. Table 15 describes the phase-locked loop operating conditions. Table 13. Core Clock Requirements—533 MHz and 600 MHz Speed Grade1 Parameter fCCLK fCCLK fCCLK fCCLK fCCLK fCCLK 1 2 Core Clock Frequency Core Clock Frequency Core Clock Frequency Core Clock Frequency Core Clock Frequency Core Clock Frequency Condition VDDINT = 1.30 V minimum VDDINT = 1.20 V minimum VDDINT = 1.14 V minimum VDDINT = 1.045 V minimum VDDINT = 0.95 V minimum VDDINT = 0.90 Vminimum Internal Regulator Setting2 N/A2 1.25 V 1.20 V 1.10 V 1.00 V 0.95 V Max 600 533 500 444 400 333 Unit MHz MHz MHz MHz MHz MHz See the Ordering Guide on Page 100. Use of an internal voltage regulator is not supported on automotive grade and 600 MHz speed grade models Table 14. Core Clock Requirements—400 MHz Speed Grade1 Parameter fCCLK fCCLK fCCLK fCCLK 1 2 Core Clock Frequency Core Clock Frequency Core Clock Frequency Core Clock Frequency Condition VDDINT = 1.14 V minimum VDDINT = 1.045 V minimum VDDINT = 0.95 V minimum VDDINT = 0.90 V minimum Internal Regulator Setting2 1.20 V 1.10 V 1.00 V 0.95 V Max 400 364 333 300 Unit MHz MHz MHz MHz See Ordering Guide on Page 100 Use of an internal voltage regulator is not supported on automotive grade models Table 15. Phase-Locked Loop Operating Conditions Parameter fVCO Min 50 Voltage Controlled Oscillator (VCO) Frequency Max Maximum fCCLK Table 16. System Clock Requirements Parameter fSCLK fSCLK DDR SDRAM Models Max 1332 100 Condition VDDINT ≥ 1.14 V1 VDDINT < 1.14 V1 Mobile DDR SDRAM Models Min Max 1203 1332 4 N/A N/A4 1 fSCLK must be less than or equal to fCCLK. Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 26 on Page 43. 3 Rounded number. Actual test specification is SCLK period of 8.33 ns. 4 VDDINT must be greater than or equal to 1.14 V for mobile DDR SDRAM models. See Operating Conditions on Page 34. 2 Rev. C | Page 35 of 100 | February 2010 Unit MHz MHz Unit MHz ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ELECTRICAL CHARACTERISTICS Parameter VOH VOHDDR VOL VOLDDR IIH IIHP IIHDDR_VREF IIL8 IOZH9 IOZL11 CIN IDDDEEPSLEEP13 IDDSLEEP IDD-IDLE High Level Output Voltage for 3.3 V I/O3 High Level Output Voltage for 2.5 V I/O3 High Level Output Voltage for DDR SDRAM4 High Level Output Voltage for Mobile DDR SDRAM4 Low Level Output Voltage for 3.3 V I/O3 Low Level Output Voltage for 2.5 V I/O3 Low Level Output Voltage for DDR SDRAM4 Low Level Output Voltage for Mobile DDR SDRAM4 High Level Input Current5 High Level Input Current6 High Level Input Current for DDR SDRAM7 High Level Input Current for Mobile DDR SDRAM7 Low Level Input Current Three-State Leakage Current10 Three-State Leakage Current10 Input Capacitance12 Nonautomotive 400 MHz1 Min Typ Max 2.4 All Other Devices2 Min Typ Max 2.4 Unit V 2.0 2.0 V VDDDDR = 2.5 V, IOH = –8.1 mA 1.74 1.74 V VDDDDR = 1.8 V, IOH = –0.1 mA 1.62 1.62 V Test Conditions VDDEXT = 2.7 V, IOH = –0.5 mA VDDEXT = 2.25 V, IOH = –0.5 mA VDDEXT = 2.7 V, IOL = 2.0 mA VDDEXT = 2.25 V, IOL = 2.0 mA 0.4 0.4 V 0.4 0.4 V VDDDDR = 2.5 V, IOL = 8.1 mA 0.56 0.56 V VDDDDR = 1.8 V, IOL = 0.1 mA 0.18 0.18 V VDDEXT =3.6 V, VIN = VIN Max VDDEXT =3.6 V, VIN = VIN Max VDDDDR =2.7 V, VIN = 0.51 × VDDDDR 10.0 10.0 μA 50.0 50.0 μA 30.0 30.0 μA VDDDDR =1.95 V, VIN = 0.51 × VDDDDR 30.0 30.0 μA VDDEXT =3.6 V, VIN = 0 V 10.0 10.0 μA VDDEXT =3.6 V, VIN = VIN Max VDDEXT =3.6 V, VIN = 0 V 10.0 10.0 μA 10.0 10.0 μA 812 pF 412 fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V VDDINT Current in Deep VDDINT = 1.0 V, Sleep Mode fCCLK = 0 MHz, fSCLK = 0 MHz, TJ = 25°C, ASF = 0.00 VDDINT Current in Sleep VDDINT = 1.0 V, Mode fSCLK = 25 MHz, TJ = 25°C VDDINT Current in Idle VDDINT = 1.0 V, fCCLK = 50 MHz, TJ = 25°C, ASF = 0.47 Rev. C | Page 36 of 100 | 812 412 22 37 mA 35 50 mA 44 59 mA February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Parameter IDD-TYP VDDINT Current IDD-TYP VDDINT Current IDD-TYP VDDINT Current IDD-TYP VDDINT Current IDDHIBERNATE13, 14 Hibernate State Current IDDRTC IDDUSB-FS VDDRTC Current VDDUSB Current in Full/Low Speed Mode IDDUSB-HS VDDUSB Current in High Speed Mode IDDDEEPSLEEP13, 15 VDDINT Current in Deep Sleep Mode IDDSLEEP13, 15 VDDINIT Current in Sleep Mode IDDINT15, 17 VDDINT Current Test Conditions VDDINT = 1.10 V, fCCLK = 300 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 1.00 VDDINT = 1.20 V, fCCLK = 400 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 1.00 VDDINT = 1.25 V, fCCLK = 533 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 1.00 VDDINT = 1.35 V, fCCLK = 600 MHz, fSCLK = 25 MHz, TJ = 25°C, ASF = 1.00 VDDEXT = VDDVR = VDDUSB = 3.30 V, VDDDDR = 2.5 V, TJ = 25°C, CLKIN= 0 MHz with voltage regulator off (VDDINT = 0 V) VDDRTC = 3.3 V, TJ = 25°C VDDUSB = 3.3 V, TJ = 25°C, Full Speed USB Transmit VDDUSB = 3.3 V, TJ = 25°C, High Speed USB Transmit fCCLK = 0 MHz, fSCLK = 0 MHz fCCLK = 0 MHz, fSCLK > 0 MHz Nonautomotive 400 MHz1 Min Typ Max 145 All Other Devices2 Min Typ Max 178 Unit mA 199 239 mA 301 mA 360 mA 60 60 µA 20 9 20 9 µA mA 25 25 mA fCCLK > 0 MHz, fSCLK > 0 MHz Table 17 Table 18 mA IDDDEEPSLEEP + (0.77 × VDDINT × fSCLK)16 IDDSLEEP + (Table 20 × ASF) IDDDEEPSLEEP mA16 + (0.77 × VDDINT × fSCLK)16 IDDSLEEP + mA (Table 20 × ASF) 1 Applies to all nonautomotive 400 MHz speed grade models. See Ordering Guide. Applies to all 533 MHz and 600 MHz speed grade models and automotive 400 MHz speed grade models. See Ordering Guide. 3 Applies to output and bidirectional pins, except USB_VBUS and the pins listed in table note 4. 4 Applies to pins DA0–12, DBA0–1, DQ0–15, DQS0–1, DQM0–1, DCLK1–2, DCLK1–2, DCS0–1, DCLKE, DRAS, DCAS, and DWE. 5 Applies to all input pins except JTAG inputs. 6 Applies to JTAG input pins (TCK, TDI, TMS, TRST). 7 Applies to DDR_VREF pin. 8 Absolute value. 9 For DDR pins (DQ0-15, DQS0-1), test conditions are VDDDDR = Maximum, VIN = VDDDDR Maximum. 10 Applies to three-statable pins. 11 For DDR pins (DQ0-15, DQS0-1), test conditions are VDDDDR = Maximum, VIN = 0V. 12 Guaranteed, but not tested 2 Rev. C | Page 37 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 13 See the ADSP-BF54x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. Includes current on VDDEXT, VDDUSB, VDDVR, and VDDDDR supplies. Clock inputs are tied high or low. 15 Guaranteed maximum specifications. 16 Unit for VDDINT is V (volts). Unit for fSCLK is MHz. Example: 1.2 V, 133 MHz would be 0.77 × 1.2 × 133 = 122.9 mA added to IDDDEEPSLEEP. 17 See Table 19 for the list of IDDINT power vectors covered. 14 IDDINT specifies the total power specification for the listed test conditions, including the dynamic component as a function of voltage (VDDINT) and frequency (Table 20). Total power dissipation has two components: • Static, including leakage current • Dynamic, due to transistor switching characteristics Many operating conditions can also affect power dissipation, including temperature, voltage, operating frequency, and processor activity. Electrical Characteristics on Page 36 shows the current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP specifies static power dissipation as a function of voltage (VDDINT) and temperature (see Table 17 and Table 18), and There are two parts to the dynamic component. The first part is due to transistor switching in the core clock (CCLK) domain. This part is subject to an activity scaling factor (ASF) which represents application code running on the processor core and L1/L2 memories (Table 19). The ASF is combined with the CCLK frequency and VDDINT dependent data in Table 20 to calculate this part. The second part is due to transistor switching in the system clock (SCLK) domain, which is included in the IDDINT specification equation. Table 17. Static Current—Nonautomotive 400 MHz Speed Grade Devices (mA)1 2 TJ (°C) -40 0 25 45 55 70 85 100 105 1 2 0.90 V 11.9 20.1 31.2 47.0 58.6 80.7 107.0 153.9 171.7 0.95 V 13.5 22.3 34.2 51.0 63.1 86.6 114.3 163.0 181.5 1.00 V 15.5 24.7 37.5 55.5 68.3 93.0 122.5 173.3 192.7 1.05 V 17.7 27.8 41.3 60.6 74.1 100.2 131.5 184.8 205.1 1.10 V 20.3 31.1 45.6 66.0 80.3 108.1 141.2 197.0 218.3 Voltage (VDDINT)2 1.15 V 1.20 V 1.25 V 23.3 26.8 30.6 34.9 39.3 44.2 50.3 55.7 61.7 72.0 78.8 86.1 87.1 94.9 103.0 116.7 125.9 136.0 151.7 163.1 175.3 210.0 224.1 239.0 232.4 247.5 263.6 1.30 V 35.0 49.6 68.2 94.2 112.0 146.8 188.5 255.1 280.9 1.35 V 39.9 55.7 75.4 102.9 122.0 158.7 202.7 272.4 299.3 1.38 V 43.2 59.8 80.3 108.9 128.4 166.4 211.8 283.4 308.7 1.40 V 45.5 62.5 83.6 112.8 132.8 171.6 218.0 290.8 314.9 1.43 V 49.5 67.2 88.6 118.2 140.0 179.5 226.7 300.6 325.7 1.38 V 61.2 121.0 196.1 284.0 343.1 449.4 584.2 737.0 798.5 1.40 V 64.0 125.8 203.3 293.6 354.6 463.9 602.0 758.5 821.6 1.43 V 70.4 135.0 218.0 312.0 374.0 489.0 629.0 793.0 864.0 Values are guaranteed maximum IDDDEEPSLEEP for nonautomotive 400 MHz speed-grade devices. Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 34. Table 18. Static Current—Automotive 400 MHz and All 533 MHz/600 MHz Speed Grade Devices (mA)1 2 TJ (°C) -40 0 25 45 55 70 85 100 105 1 2 0.90 V 19.7 45.2 80.0 124.2 154.6 209.8 281.8 366.5 403.8 0.95 V 22.1 49.9 87.5 134.8 167.2 225.6 301.3 390.5 428.3 1.00 V 24.8 55.2 96.2 147.1 181.7 243.9 323.5 419.4 459.5 1.05 V 27.9 61.3 105.8 160.7 197.7 264.1 350.2 452.1 494.3 1.10 V 31.4 67.9 116.4 175.3 214.9 285.8 378.5 486.9 531.7 Voltage (VDDINT)2 1.15 V 1.20 V 1.25 V 35.4 39.9 45.0 75.3 83.5 92.6 127.9 140.4 154.1 191.2 208.6 227.3 233.8 254.2 276.1 309.4 334.8 363.5 408.9 442.1 477.9 524.4 564.8 608.2 571.9 614.9 661.5 1.30 V 50.6 102.6 169.2 247.6 299.7 394.3 516.5 654.8 711.1 Values are guaranteed maximum IDDDEEPSLEEP for automotive 400 MHz and all 533 MHz and 600 MHz speed grade devices. Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 34. Rev. C | Page 38 of 100 | February 2010 1.35 V 57.0 113.6 185.4 269.6 325.9 427.7 557.5 704.7 763.9 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 19. Activity Scaling Factors1 IDDINT Power Vector IDD-PEAK IDD-HIGH IDD-TYP IDD-APP IDD-NOP IDD-IDLE 1 Activity Scaling Factor (ASF) 1.29 1.24 1.00 0.87 0.74 0.47 See Estimating Power for ADSP-BF534/BF536/BF537 Blackfin Processors (EE-297). The power vector information also applies to the ADSPBF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 processors. Table 20. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1 Voltage (VDDINT)2 fCCLK (MHz)2 100 200 300 400 500 533 600 1 2 0.90 V 29.7 55.3 80.8 N/A N/A N/A N/A 0.95 V 31.6 58.9 85.8 112.2 N/A N/A N/A 1.00 V 33.9 62.5 91.0 119.4 N/A N/A N/A 1.05 V 35.7 66.0 96.0 125.5 N/A N/A N/A 1.10 V 37.9 70.0 101.3 132.4 N/A N/A N/A 1.15 V 40.5 74.0 107.0 139.6 171.9 N/A N/A 1.20 V 42.9 78.3 112.8 146.9 180.6 191.9 N/A 1.25 V 45.5 82.5 118.7 154.6 189.9 201.6 N/A 1.30 V 48.2 86.7 124.6 162.3 199.1 211.5 233.1 1.35 V 50.8 91.3 130.9 170.0 205.7 218.0 241.4 1.38 V 52.0 93.3 133.8 173.8 210.3 222.8 246.7 1.40 V 53.5 95.6 137.0 177.8 213.0 225.7 252.7 1.43 V 54.6 97.6 140.0 181.6 217.6 230.5 258.1 The values are not guaranteed as stand-alone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 36. Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 34. Rev. C | Page 39 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 21 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 22 details the maximum duty cycle for input transient voltage. the Total Current Pin Groups table. Note that the VOL and VOH specifications have separate per-pin maximum current requirements, see the Electrical Characteristics table. Table 23. Total Current Pin Groups Group 1 2 Table 21. Absolute Maximum Ratings 3 Internal (Core) Supply Voltage (VDDINT) External (I/O) Supply Voltage (VDDEXT) Input Voltage1, 2, 3 Output Voltage Swing IOH/IOL Current per Single Pin4 IOH/IOL Current per Pin Group4 Storage Temperature Range Junction Temperature Underbias –0.3 V to +1.43 V –0.3 V to +3.8 V –0.5 V to +3.6 V –0.5 V to VDDEXT +0.5 V 40 mA (max) 80 mA (max) –65ºC to +150ºC +125ºC 1 Applies to all bidirectional and input only pins except PB1-0, PE15-14, PG15–11, and PH7-6, where the absolute maximum input voltage range is –0.5 V to +5.5 V. 2 Pins USB_DP, USB_DM, and USB_VBUS are 5 V-tolerant when VDDUSB is powered according to the operating conditions table. If VDDUSB supply voltage does not meet the specification in the operating conditions table, these pins could suffer long-term damage when driven to +5 V. If this condition is seen in the application, it can be corrected with additional circuitry to use the external host to power only the VDDUSB pins. Contact factory for application detail and reliability information. 3 Applies only when VDDEXT is within specifications. When VDDEXT is outside specifications, the range is VDDEXT ± 0.2 V. 4 For more information, see description preceding Table 23. Table 22. Maximum Duty Cycle for Input1 Transient Voltage VIN Max (V)2 3.63 3.80 3.90 4.00 4.10 4.20 4.30 VIN Min (V) –0.33 –0.50 –0.60 –0.70 –0.80 –0.90 –1.00 Maximum Duty Cycle 100% 48% 30% 20% 10% 8% 5% 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pins in Group PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11 PA12, PA13, PA14, PA15, PB8, PB9, PB10, PB11, PB12, PB13, PB14 PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, BMODE0, BMODE1, BMODE2, BMODE3 TCK, TDI, TDO, TMS, TRST, PD14, EMU PD8, PD9, PD10, PD11, PD12, PD13, PD15 PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7 PE11, PE12, PE13, PF12, PF13, PF14, PF15, PG3, PG4 PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11 PF0, PF1, PF2, PF3, PG0, PG1, PG2 PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7 PH5, PH6, PH7 A1, A2, A3 PH8, PH9, PH10, PH11, PH12, PH13 PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7 PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15 AMS0, AMS1, AMS2, AMS3, AOE, CLKBUF, NMI CLKIN, XTAL, RESET, RTXI, RTXO, ARE, AWE D0, D1, D2, D3, D4, D5, D6, D7 D8, D9, D10, D11, D12 D13, D14, D15, ABE0, ABE1 EXT_WAKE, CLKOUT, PJ11, PJ12, PJ13 PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, ATAPI_PDIAG PJ8, PJ9, PJ10, PE7, PG12, PG13 PE0, PE1, PE2, PE4, PE5, PE6, PE8, PE9, PE10, PH3, PH4 PH0, PH2, PE14, PE15, PG5, PG6, PG7, PG8, PG9, PG10, PG11 PC8, PC9, PC10, PC11, PC12, PC13, PE3, PG14, PG15, PH1 1 Does not apply to CLKIN. Absolute maximum for pins PB1-0, PE15-14, PG1511, and PH7-6 is +5.5V. 2 Only one of the listed options can apply to a particular design. The Absolute Maximum Ratings table specifies the maximum total source/sink (IOH/IOL) current for a group of pins. Permanent damage can occur if this value is exceeded. To understand this specification, if pins PA4, PA3, PA2, PA1 and PA0 from group 1 in the Total Current Pin Groups table were sourcing or sinking 2 mA each, the total current for those pins would be 10 mA. This would allow up to 70 mA total that could be sourced or sunk by the remaining pins in the group without damaging the device. For a list of all groups and their pins, see Rev. C | Page 40 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ESD SENSITIVITY ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. PACKAGE INFORMATION The information presented in Figure 9 and Table 24 provides information related to specific product features. For a complete listing of product offerings, see the Ordering Guide on Page 100. a ADSP-BF54x(M) tppZ-cc vvvvvv.x-q n.n # yywwcountry_of_origin B Figure 9. Product Information on Package Table 24. Package Information Brand Key BF54x (M) t pp Z cc vvvvvv.x-q n.n # yyww Description x = 2, 4, 7, 8 or 9 Mobile DDR Indicator (optional) Temperature Range Package Type RoHS Compliant part See Ordering Guide Assembly Lot Code Silicon Revision RoHS Compliant Designation Date Code Rev. C | Page 41 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 TIMING SPECIFICATIONS Timing specifications are detailed in this section. Clock and Reset Timing Table 25 and Figure 10 describe Clock Input and Reset Timing. Table 26 and Figure 11 describe Clock Out Timing. Table 25. Clock Input and Reset Timing Parameter Timing Requirements CLKIN Period1, 2, 3, 4 tCKIN tCKINL CLKIN Low Pulse2 tCKINH CLKIN High Pulse2 tBUFDLAY CLKIN to CLKBUF Delay tWRST RESET Asserted Pulsewidth Low5 tRHWFT RESET High to First HWAIT/HWAITA Transition (Boot Host Wait Mode)6,7,8,9 RESET High to First HWAIT/HWAITA Transition (Reset Output Mode)7,10,11 tRHWFT Min Max Unit 20.0 8.0 8.0 100.0 ns ns ns ns ns ns ns 10 11 tCKIN 6100 tCKIN + 7900 tSCLK 6100 tCKIN 7000 tCKIN 1 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 16 and Table 13 on Page 35. 2 Applies to PLL bypass mode and PLL non-bypass mode. 3 CLKIN frequency and duty cycle must not change on the fly. 4 If the DF bit in the PLL_CTL register is set, then the maximum tCKIN period is 50 ns. 5 Applies after power-up sequence is complete. See Table 27 and Figure 12 for more information about power-up reset timing. 6 Maximum value not specified due to variation resulting from boot mode selection and OTP memory programming. 7 Values specified assume no invalidation preboot settings in OTP page PBS00L. Invalidating a PBS set will increase the value by 1875 tCKIN (typically). 8 Applies only to boot modes BMODE=1, 2, 4, 6, 7, 10, 11, 14, 15. 9 Use default tSCLK value unless PLL is reprogrammed during preboot. In case of PLL reprogramming use the new tSCLK value and add PLL_LOCKCNT settle time. 10 When enabled by OTP_RESETOUT_HWAIT bit. If regular HWAIT is not required in an application, the OTP_RESETOUT_HWAIT bit in the same page instructs the HWAIT or HWAITA to simulate reset output functionality. Then an external resistor is expected to pull the signal to the reset level, as the pin itself is in high performance mode during reset. 11 Variances are mainly dominated by PLL programming instructions in PBS00L page and boot code differences between silicon revisions. The earlier is bypassed in boot mode BMODE = 0. Maximum value assumes PLL programming instructions do not cause the SCLK frequency to decrease. tCKIN CLKIN tCKINL tBUFDLAY tCKINH CLKBUF tWRST RESET tRHWFT HWAIT (A) Figure 10. Clock and Reset Timing Rev. C | Page 42 of 100 | February 2010 tBUFDLAY ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 26. Clock Out Timing Parameter Switching Characteristics tSCLK CLKOUT Period1,2 tSCLKH CLKOUT Width High tSCLKL CLKOUT Width Low 1 2 Min Max 7.5 2.5 2.5 Unit ns ns ns The tSCLK value is the inverse of the fSCLK specification. Reduced supply voltages affect the best-case value of 7.5 ns listed here. The tSCLK value does not account for the effects of jitter. tSCLK CLKOUT tSCLKL tSCLKH Figure 11. CLKOUT Interface Timing Table 27. Power-Up Reset Timing Parameter Min Max Unit Timing Requirements tRST_IN_PWR RESET Deasserted After the VDDINT, VDDEXT, VDDDDR,VDDUSB,VDDRTC,VDDVR,VDDMP, and CLKIN Pins Are Stable and Within Specification 3500 × tCKIN tRST_IN_PWR RESET CLKIN V DD_SUPPLIES In Figure 12, VDD_SUPPLIES is VDDINT, VDDEXT, VDDDDR, VDDUSB, VDDRTC, VDDVR, and VDDMP. Figure 12. Power-Up Reset Timing Rev. C | Page 43 of 100 | February 2010 ns ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Asynchronous Memory Read Cycle Timing Table 28 and Table 29 on Page 45 and Figure 13 and Figure 14 on Page 45 describe asynchronous memory read cycle operations for synchronous and for asynchronous ARDY. Table 28. Asynchronous Memory Read Cycle Timing with Synchronous ARDY Parameter Min Max Unit Timing Requirements tSDAT DATA15–0 Setup Before CLKOUT 5.0 ns ns tHDAT DATA15–0 Hold After CLKOUT 0.8 tSARDY ARDY Setup Before the Falling Edge of CLKOUT 5.0 ns tHARDY ARDY Hold After the Falling Edge of CLKOUT 0.0 ns Switching Characteristics tDO Output Delay After CLKOUT1 tHO Output Hold After CLKOUT1 1 6.0 0.3 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and ARE. SETUP 2 CYCLES PROGRAMMED READ ACCESS 4 CYCLES ACCESS EXTENDED 3 CYCLES HOLD 1 CYCLE CLKOUT tDO tHO AMSx ABE1–0 ADDR19–1 AOE tDO tHO ARE tSARDY tHARDY tHARDY ARDY tSARDY tSDAT tHDAT DATA 15–0 Figure 13. Asynchronous Memory Read Cycle Timing with Synchronous ARDY Rev. C | Page 44 of 100 | February 2010 ns ns ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 29. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY Parameter Min Max Unit Timing Requirements tSDAT DATA15–0 Setup Before CLKOUT 5.0 tHDAT DATA15–0 Hold After CLKOUT 0.8 tDANR ARDY Negated Delay from AMSx Asserted1 tHAA ARDY Asserted Hold After ARE Negated ns ns (S + RA – 2) × tSCLK ns 0.0 ns Switching Characteristics tDO Output Delay After CLKOUT2 tHO Output Hold After CLKOUT2 1 2 6.0 0.3 ns S = number of programmed setup cycles, RA = number of programmed read access cycles. Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and ARE. SETUP 2 CYCLES PROGRAMMED READ ACCESS 4 CYCLES ACCESS EXTENDED 3 CYCLES HOLD 1 CYCLE CLKOUT tDO tHO AMSx ABE1–0 ADDR19–1 AOE tDO tHO ARE tDANR tHAA ARDY tSDAT tHDAT DATA 15–0 Figure 14. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY Rev. C | Page 45 of 100 | February 2010 ns ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Asynchronous Memory Write Cycle Timing Table 30 and Table 31 on Page 47 and Figure 15 and Figure 16 on Page 47 describe asynchronous memory write cycle operations for synchronous and for asynchronous ARDY. Table 30. Asynchronous Memory Write Cycle Timing with Synchronous ARDY Parameter Min Max Unit Timing Requirements tSARDY ARDY Setup Before the Falling Edge of CLKOUT 5.0 ns tHARDY ARDY Hold After the Falling Edge of CLKOUT 0.0 ns Switching Characteristics tDDAT DATA15–0 Disable After CLKOUT tENDAT DATA15–0 Enable After CLKOUT tDO Output Delay After CLKOUT tHO Output Hold After CLKOUT1 1 6.0 0.0 1 Output pins include AMS3–0, ABE1–0, ADDR19–1, and AWE. PROGRAMMED ACCESS WRITE ACCESS EXTEND HOLD 2 CYCLES 1 CYCLE 1 CYCLE SETUP 2 CYCLES CLKOUT tDO tHO AMSx ABE1–0 ADDR19–1 tDO tHO AWE tSARDY tHARDY ARDY tENDAT ns 6.0 0.3 tSARDY tHARDY tDDAT DATA 15–0 Figure 15. Asynchronous Memory Write Cycle Timing with Synchronous ARDY Rev. C | Page 46 of 100 | February 2010 ns ns ns ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 31. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY Parameter Min Max Unit Timing Requirements tDANW ARDY Negated Delay from AMSx Asserted1 tHAA ARDY Asserted Hold After AWE Negated (S + WA – 2) × tSCLK ns 0.0 ns Switching Characteristics tDDAT DATA15–0 Disable After CLKOUT tENDAT DATA15–0 Enable After CLKOUT tDO Output Delay After CLKOUT tHO 2 Output Hold After CLKOUT 6.0 0.0 2 ns 6.0 0.3 1 S = number of programmed setup cycles, WA = number of programmed write access cycles. 2 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and AWE. SETUP 2 CYCLES PROGRAMMED WRITE ACCESS 2 CYCLES ACCESS EXTENDED 2 CYCLES HOLD 1 CYCLE CLKOUT tDO tHO AMSx ABE1–0 ADDR19–1 tDO tHO AWE tDANW tHAA ARDY tENDAT tDDAT DATA 15–0 Figure 16. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY Rev. C | Page 47 of 100 | February 2010 ns ns ns ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing Table 32 and Figure 17 describe DDR SDRAM/mobile DDR SDRAM clock and control cycle timing. Table 32. DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing Parameter Switching Characteristics tCK1 DCK0-1 Period tCH DCK0-1 High Pulse Width tCL DCK0-1 Low Pulse Width tAS2,3 Address and Control Output SETUP Time Relative to CK tAH2,3 Address and Control Output HOLD Time Relative to CK 2,3 tOPW Address and Control Output Pulse Width DDR SDRAM Min Max Mobile DDR SDRAM Min Max Unit 7.50 0.45 0.45 1.00 1.00 2.20 7.50 0.45 0.45 1.00 1.00 2.30 ns tCK tCK ns ns ns 0.55 0.55 1 The tCK specification does not account for the effects of jitter. Address pins include DA0-12 and DBA0-1. 3 Control pins include DCS0-1, DCLKE, DRAS, DCAS, and DWE. 2 tCK tCH tCL DCK0-1 tAS tAH ADDRESS CONTROL tOPW NOTE: CONTROL = DCS0-1, DCLKE, DRAS, DCAS, AND DWE. ADDRESS = DA0-12 AND DBA0-1. Figure 17. DDR SDRAM /Mobile DDR SDRAM Clock and Control Cycle Timing Rev. C | Page 48 of 100 | February 2010 8.33 0.55 0.55 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 DDR SDRAM/Mobile DDR SDRAM Timing Table 33 and Figure 18/Figure 19 describe DDR SDRAM/mobile DDR SDRAM read cycle timing. Table 33. DDR SDRAM/Mobile DDR SDRAM Read Cycle Timing Parameter Timing Requirements tAC Access Window of DQ0-15 to DCK0-1 tDQSCK Access Window of DQS0-1 to DCK0-1 tDQSQ DQS0-1 to DQ0-15 Skew, DQS0-1 to Last DQ0-15 Valid tQH DQ0-15 to DQS0-1 Hold, DQS0-1 to First DQ0-15 to Go Invalid tRPRE tRPST 1 2 DQS0-1 Read Preamble DQS0-1 Read Postamble DDR SDRAM Min Mobile DDR SDRAM Min Max Max –1.25 –1.25 +1.25 +1.25 0.90 tCK/2 – 1.251 tCK/2 – 1.752 0.9 0.4 0.0 0.0 tCK/2 – 1.25 1.1 0.6 0.9 0.4 For 7.50 ns ≤ tCK < 10 ns. For tCK ≥ 10 ns. tDQSCK DCK0-1 tAC DQS0-1 tRPRE tRPST DQ0-15 Dn Dn+1 Dn+2 Dn+3 tDQSQ tQH Figure 18. DDR SDRAM Controller Read Cycle Timing tDQSCK DCK0-1 tAC tRPRE tRPST DQS0-1 DQ0-15 Dn Dn+1 Dn+2 Dn+3 tDQSQ tQH Figure 19. Mobile DDR SDRAM Controller Read Cycle Timing Rev. C | Page 49 of 100 | 6.00 6.00 0.85 February 2010 Unit ns ns ns ns 1.1 0.6 tCK tCK ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing Table 34 and Figure 20 describe DDR SDRAM/mobile DDR SDRAM write cycle timing. Table 34. DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing DDR SDRAM Min Parameter Switching Characteristics tDQSS Write CMD to First DQS0-1 tDS DQ0-15/DQM0-1 Setup to DQS0-1 tDH DQ0-15/DQM0-1 Hold to DQS0-1 DQS0-1 Falling to DCK0-1 Rising (DQS0-1 Setup) tDSS tDSH DQS0-1 Falling from DCK0-1 Rising (DQS0-1 Hold) tDQSH DQS0-1 High Pulse Width tDQSL DQS0-1 Low Pulse Width tWPRE DQS0-1 Write Preamble tWPST DQS0-1 Write Postamble tDOPW DQ0-15 and DQM0-1 Output Pulse Width (for Each) Max 0.75 0.90 0.90 0.20 0.20 0.35 0.35 0.25 0.40 1.75 1.25 0.60 Mobile DDR SDRAM Min Max Unit 0.75 0.90 0.90 0.20 0.20 0.40 0.40 0.25 0.40 1.75 tCK ns ns tCK tCK tCK tCK tCK tCK ns 1.25 0.60 0.60 0.60 DCK0-1 tDSS tDSH tDQSS DQS0-1 tWPRE tDQSL tDQSH tWPST tDOPW DQ0-15/DQM0-1 Dn tDS CONTROL Dn+1 Dn+2 tDH Write CMD NOTE: CONTROL = DCS0-1, DCLKE, DRAS, DCAS, AND DWE. Figure 20. DDR SDRAM /Mobile DDR SDRAM Controller Write Cycle Timing Rev. C | Page 50 of 100 | February 2010 Dn+3 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 External Port Bus Request and Grant Cycle Timing Table 35 and Table 36 on Page 52 and Figure 21 and Figure 22 on Page 52 describe external port bus request and grant cycle operations for synchronous and for asynchronous BR. Table 35. External Port Bus Request and Grant Cycle Timing with Synchronous BR Parameter Min Max Unit Timing Requirements tBS BR Asserted to CLKOUT Low Setup 5.0 ns tBH CLKOUT Low to BR Deasserted Hold Time 0.0 ns Switching Characteristics tSD CLKOUT Low to AMSx, Address, and ARE/AWE Disable 5.0 ns tSE CLKOUT Low to AMSx, Address, and ARE/AWE Enable 5.0 ns tDBG CLKOUT Low to BG Asserted Output Delay 4.0 ns tEBG CLKOUT Low to BG Deasserted Output Hold 4.0 ns tDBH CLKOUT Low to BGH Asserted Output Delay 3.6 ns tEBH CLKOUT Low to BGH Deasserted Output Hold 3.6 ns CLKOUT tBH tBS BR tSD tSE tSD tSE tSD tSE AMSx ADDR 19-1 ABE1-0 AWE ARE t DBG tEBG tDBH tEBH BG BGH Figure 21. External Port Bus Request and Grant Cycle Timing with Synchronous BR Rev. C | Page 51 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 36. External Port Bus Request and Grant Cycle Timing with Asynchronous BR Parameter Min Max Unit Timing Requirements tWBR BR Pulsewidth 2 x tSCLK ns Switching Characteristics tSD CLKOUT Low to AMSx, Address, and ARE/AWE Disable 5.0 ns tSE CLKOUT Low to AMSx, Address, and ARE/AWE Enable 5.0 ns tDBG CLKOUT Low to BG Asserted Output Delay 4.0 ns tEBG CLKOUT Low to BG Deasserted Output Hold 4.0 ns tDBH CLKOUT Low to BGH Asserted Output Delay 3.6 ns tEBH CLKOUT Low to BGH Deasserted Output Hold 3.6 ns CLKOUT tWBR BR tSD tSE tSD tSE tSD tSE AMSx ADDR 19-1 ABE1-0 AWE ARE t DBG tEBG tDBH tEBH BG BGH Figure 22. External Port Bus Request and Grant Cycle Timing with Asynchronous BR Rev. C | Page 52 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 NAND Flash Controller Interface Timing Table 37 and Figure 23 on Page 54 through Figure 27 on Page 56 describe NAND flash controller interface operations. Table 37. NAND Flash Controller Interface Timing Parameter Write Cycle Switching Characteristics tCWL ND_CE Setup Time to AWE Low tCH ND_CE Hold Time from AWE High tCLHWL ND_CLE Setup Time High to AWE Low ND_CLE Hold Time from AWE High tCLH tALLWL ND_ALE Setup Time Low to AWE Low tALH ND_ALE Hold Time from AWE High tWP1 AWE Low to AWE High tWHWL AWE High to AWE Low 1 tWC AWE Low to AWE Low Data Setup Time for a Write Access tDWS1 tDWH Data Hold Time for a Write Access Read Cycle Switching Characteristics tCRL ND_CE Setup Time to ARE Low tCRH ND_CE Hold Time from ARE High ARE Low to ARE High tRP1 tRHRL ARE High to ARE Low 1 tRC ARE Low to ARE Low Timing Requirements tDRS Data Setup Time for a Read Transaction tDRH Data Hold Time for a Read Transaction Write Followed by Read Switching Characteristic tWHRL AWE High to ARE Low 1 Min Page 53 of 100 | Unit 1.0 × tSCLK – 4 3.0 × tSCLK – 4 0.0 2.5 × tSCLK – 4 0.0 2.5 × tSCLK – 4 (WR_DLY +1.0) × tSCLK – 4 4.0 × tSCLK – 4 (WR_DLY +5.0) × tSCLK – 4 (WR_DLY +1.5) × tSCLK – 4 2.5 × tSCLK – 4 ns ns ns ns ns ns ns ns ns ns ns 1.0 × tSCLK – 4 3.0 × tSCLK – 4 (RD_DLY +1.0) × tSCLK – 4 4.0 × tSCLK – 4 (RD_DLY + 5.0) × tSCLK – 4 ns ns ns ns ns 8.0 0.0 ns ns 5.0 × tSCLK – 4 ns WR_DLY and RD_DLY are defined in the NFC_CTL register. Rev. C | Max February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 tCWL tCH ND_CE ND_CLE tCLEWL tCLH tALEWL tALH ND_ALE tWP AWE tDWH tDWS ND_DATA In Figure 23, ND_DATA is ND_D0–D15. Figure 23. NAND Flash Controller Interface Timing—Command Wri Cycle tCWL ND_CE tCLEWL ND_CLE ND_ALE tALH tALEWL tALH tALEWL tWP tWHWL tWP AWE tWC tDWS tDWH tDWS ND_DATA In Figure 24, ND_DATA is ND_D0–D15. Figure 24. NAND Flash Controller Interface Timing—Address Write Cycle Rev. C | Page 54 of 100 | February 2010 tDWH ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 tCWL ND_CE tCLEWL ND_CLE tALEWL ND_ALE tWP tWC AWE tWP tDWS tWHWL tDWH tDWS tDWH ND_DATA In Figure 25, ND_DATA is ND_D0–D15. Figure 25. NAND Flash Controller Interface Timing—Data Write Operation tCRL tCRH ND_CE ND_CLE ND_ALE tRP tRC ARE tRHRL tRP tDRS tDRH tDRS ND_DATA In Figure 26, ND_DATA is ND_D0–D15. Figure 26. NAND Flash Controller Interface Timing—Data Read Operation Rev. C | Page 55 of 100 | February 2010 tDRH ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 tCLWL ND_CE ND_CLE tCLEWL tCLH tWP AWE tWHRL tRP ARE tDWS tDWH tDRS tDRH ND_DATA In Figure 27, ND_DATA is ND_D0–D15. Figure 27. NAND Flash Controller Interface Timing—Write Followed by Read Operation Rev. C | Page 56 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Synchronous Burst AC Timing Table 38 and Figure 28 on Page 57 describe Synchronous Burst AC operations. Table 38. Synchronous Burst AC Timing Parameter Timing Requirements tNDS DATA15-0 Setup Before NR_CLK tNDH DATA15-0 Hold After NR_CLK tNWS WAIT Setup Before NR_CLK tNWH WAIT Hold After NR_CLK Switching Characteristics tNDO AMSx, ABE1-0, ADDR19-1, NR_ADV, NR_OE Output Delay After NR_CLK tNHO ABE1-0, ADDR19-1 Output Hold After NR_CLK Min ns ns ns ns 6.0 –3.0 ns ns tNDO tNDO tNDO tNHO AMSx ABE1-0 tNHO ADDR19-1 tNDH tNDH tNDS DATA15-0 tNDS Dn Dn+1 Dn+2 Dn+3 tNDO tNDO NR_ADV tNWS tNWH WAIT tNDO tNDO NR_OE NOTE: NR_CLK dotted line represents a free running version of NR_CLK that is not visible on the NR_CLK pin. Figure 28. Synchronous Burst AC Interface Timing Rev. C | Page 57 of 100 | February 2010 Unit 4.0 2.0 8.0 0.0 NR_CLK tNDO Max ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 External DMA Request Timing Table 39 and Figure 29 describe the external DMA request timing operations. Table 39. External DMA Request Timing Parameter Timing Parameters tDR DMARx Asserted to CLKOUT High Setup tDH CLKOUT High to DMARx Deasserted Hold Time tDMARACT DMARx Active Pulse Width tDMARINACT DMARx Inactive Pulse Width Min 6.0 0.0 1.0 × tSCLK 1.75 × tSCLK CLKOUT tDS tDH DMAR0/1 (ACTIVE LOW) tDMARACT tDMARINACT DMAR0/1 (ACTIVE HIGH) Figure 29. External DMA Request Timing Rev. C | Page 58 of 100 | February 2010 Max Unit ns ns ns ns ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Enhanced Parallel Peripheral Interface Timing Table 40 and Figure 32 on Page 60, Figure 30 on Page 59, Figure 33 on Page 60, and Figure 31 on Page 59 describe enhanced parallel peripheral interface timing operations. Table 40. Enhanced Parallel Peripheral Interface Timing Parameter Timing Requirements PPIx_CLK Width tPCLKW tPCLK PPIx_CLK Period Timing Requirements—GP Input and Frame Capture Modes tSFSPE External Frame Sync Setup Before PPIx_CLK tHFSPE External Frame Sync Hold After PPIx_CLK tSDRPE Receive Data Setup Before PPIx_CLK Receive Data Hold After PPIx_CLK tHDRPE Switching Characteristics—GP Output and Frame Capture Modes tDFSPE Internal Frame Sync Delay After PPIx_CLK tHOFSPE Internal Frame Sync Hold After PPIx_CLK tDDTPE Transmit Data Delay After PPIx_CLK tHDTPE Transmit Data Hold After PPIx_CLK Min tPCLKW tPCLK PPI_FS1/2 tSDRPE tHDRPE PPI_DATA Figure 30. EPPI GP Rx Mode with External Frame Sync Timing DATA DRIVING/ FRAME SYNC SAMPLING EDGE PPI_CLK tHFSPE tPCLKW PPI_FS1/2 tDDTPE tHDTPE PPI_DATA Figure 31. EPPI GP Tx Mode with External Frame Sync Timing Rev. C | ns ns ns ns 9.9 tHFSPE tSFSPE 0.9 1.9 1.6 1.5 2.4 PPI_CLK DATA DRIVING/ FRAME SYNC SAMPLING EDGE ns ns 2.4 DATA1 IS SAMPLED Page 59 of 100 | February 2010 tPCLK Unit 6.0 13.3 10.5 DATA0 IS SAMPLED tSFSPE Max ns ns ns ns ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 FRAME SYNC IS DRIVEN OUT DATA0 IS SAMPLED PPI_CLK tDFSPE tHOFSPE tPCLKW tPCLK PPI_FS1/2 tSDRPE tHDRPE PPI_DATA Figure 32. EPPI GP Rx Mode with Internal Frame Sync Timing FRAME SYNC IS DRIVEN OUT DATA0 IS DRIVEN OUT tPCLK PPI_CLK tHOFSPE tDFSPE tPCLKW PPI_FS1/2 tDDTPE tHDTPE PPI_DATA Figure 33. EPPI GP Tx Mode with Internal Frame Sync Timing Rev. C | Page 60 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Serial Ports Timing Table 41 through Table 44 on Page 63 and Figure 34 on Page 62 through Figure 37 on Page 63 describe serial port operations. Table 41. Serial Ports—External Clock Parameter Min Max Unit Timing Requirements tSFSE TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1 tHFSE TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx) tSDRE Receive Data Setup Before RSCLKx1 1 1 3.0 ns 3.0 ns 3.0 ns 3.0 ns 4.5 ns tHDRE Receive Data Hold After RSCLKx tSCLKEW TSCLKx/RSCLKx Width tSCLKE TSCLKx/RSCLKx Period 15.0 ns tRCLKE RSCLKx Period2 11.1 ns tSUDTE Start-Up Delay From SPORT Enable To First External TFSx 4 × tSCLKE ns tSUDRE Start-Up Delay From SPORT Enable To First External RFSx 4 × tRCLKE ns Switching Characteristics tDFSE TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)3 tHOFSE TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx) tDDTE Transmit Data Delay After TSCLKx3 tHDTE Transmit Data Hold After TSCLKx3 3 10.0 ns 10.0 ns 0.0 ns 0.0 ns 1 Referenced to sample edge. 2 For serial port receive with external clock and external frame sync only. 3 Referenced to drive edge. Table 42. Serial Ports—Internal Clock Parameter Min Max Unit Timing Requirements tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1 tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx) tSDRI Receive Data Setup Before RSCLKx1 tHDRI Receive Data Hold After RSCLKx 1 1 10.0 ns –1.5 ns 10.0 ns –1.5 ns Switching Characteristics tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tDDTI Transmit Data Delay After TSCLKx2 tHDTI Transmit Data Hold After TSCLKx2 –2.0 ns tSCLKIW TSCLKx/RSCLKx Width 4.5 ns Referenced to sample edge. 2 Referenced to drive edge. Page 61 of 100 | February 2010 ns ns 3.0 1 Rev. C | 3.0 –1.0 ns ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 TSCLKx (INPUT) tSUDTE TFSx (INPUT) RSCLKx (INPUT) tSUDRE RFSx (INPUT) FIRST TSCLKx/RSCLKx EDGE AFTER SPORT ENABLED Figure 34. Serial Port Start-Up with External Clock and Frame Sync DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE tSCLKE tSCLKEW tSCLKIW RSCLKx RSCLKx tDFSE tDFSI tHOFSI tHOFSE RFSx (OUTPUT) RFSx (OUTPUT) tSFSI tHFSI RFSx (INPUT) tSFSE tHFSE tSDRE tHDRE RFSx (INPUT) tSDRI tHDRI DRx DRx DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE t SCLKEW TSCLKx tSCLKE TSCLKx tD FSI tDFSE tHOFSI tHOFSE TFSx (OUTPUT) TFSx (OUTPUT) tSFSI tHFSI TFSx (INPUT) tSFSE TFSx (INPUT) tDDTI tDDTE tHDTI tHDTE DTx DTx Figure 35. Serial Ports Rev. C | Page 62 of 100 | February 2010 tHFSE ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 43. Serial Ports—Enable and Three-State Parameter Min Max Unit Switching Characteristics tDTENE Data Enable Delay from External TSCLKx1 0 ns 1, 2 tDDTTE Data Disable Delay from External TSCLKx tDTENI Data Enable Delay from Internal TSCLKx1 tDDTTI Data Disable Delay from Internal TSCLKx1, 2 10.0 –2.0 ns ns 3.0 ns 1 Referenced to drive edge. 2 Applicable to multichannel mode only. DRIVE EDGE DRIVE EDGE TSCLKx tDTENE/I tDDTTE/I DTx Figure 36. Serial Ports—Enable and Three-State Table 44. Serial Ports—External Late Frame Sync Parameter Min Max Unit Switching Characteristics tDDTLFSE Data Delay from Late External TFSx or External RFSx in multi-channel mode with MFD = 011, 2 tDTENLFSE Data Enable from External RFSx in multi-channel mode with MFD = 01, 2 1 2 In multichannel mode, TFSx enable and TFSx valid follow tDTENLFS and tDDTLFSE. If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply. EXTERNAL RFSx IN MULTI-CHANNEL MODE SAMPLE DRIVE EDGE EDGE DRIVE EDGE RSCLKx tSFSE/I tHOFSE/I RFSx tDDTLFSE tDTENLFSE 1ST BIT DTx LATE EXTERNAL TFSx DRIVE EDGE SAMPLE EDGE DRIVE EDGE TSCLKx tSFSE/I tHOFSE/I TFSx tDDTLFSE 1ST BIT DTx Figure 37. Serial Ports—External Late Frame Sync Rev. C | Page 63 of 100 | February 2010 10.0 0 ns ns ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Serial Peripheral Interface (SPI) Port—Master Timing Table 45 and Figure 38 describe SPI port master operations. Table 45. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Timing Requirements tSSPIDM Data Input Valid to SPIxSCK Edge (Data Input Setup) tHSPIDM SPIxSCK Sampling Edge to Data Input Invalid Switching Characteristics tSDSCIM SPIxSELy Low to First SPIxSCK Edge tSPICHM SPIxSCK High Period tSPICLM SPIxSCK Low Period tSPICLK SPIxSCK Period tHDSM Last SPIxSCK Edge to SPIxSELy High Sequential Transfer Delay tSPITDM tDDSPIDM SPIxSCK Edge to Data Out Valid (Data Out Delay) tHDSPIDM SPIxSCK Edge to Data Out Invalid (Data Out Hold) Min Max 9.0 –1.5 ns ns 2tSCLK –1.5 2tSCLK –1.5 2tSCLK –1.5 4tSCLK –1.5 2tSCLK –1.5 2tSCLK–1.5 ns ns ns ns ns ns ns ns 6 –1.0 SPIxSELy (OUTPUT) tSDSCIM tSPICLM tSPICHM tSPICLK tHDSM SPIxSCK (OUTPUT) tHDSPIDM tDDSPIDM SPIxMOSI (OUTPUT) tSSPIDM CPHA = 1 tHSPIDM SPIxMISO (INPUT) tHDSPIDM tDDSPIDM SPIxMOSI (OUTPUT) CPHA = 0 tSSPIDM tHSPIDM SPIxMISO (INPUT) Figure 38. Serial Peripheral Interface (SPI) Port—Master Timing Rev. C | Page 64 of 100 | February 2010 Unit tSPITDM ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Serial Peripheral Interface (SPI) Port—Slave Timing Table 46 and Figure 39 describe SPI port slave operations. Table 46. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements tSPICHS SPIxSCK High Period tSPICLS SPIxSCK Low Period SPIxSCK Period tSPICLK tHDS Last SPIxSCK Edge to SPIxSS Not Asserted tSPITDS Sequential Transfer Delay tSDSCI SPIxSS Assertion to First SPIxSCK Edge tSSPID Data Input Valid to SPIxSCK Edge (Data Input Setup) tHSPID SPIxSCK Sampling Edge to Data Input Invalid Switching Characteristics tDSOE SPIxSS Assertion to Data Out Active tDSDHI SPIxSS Deassertion to Data High Impedance tDDSPID SPIxSCK Edge to Data Out Valid (Data Out Delay) tHDSPID SPIxSCK Edge to Data Out Invalid (Data Out Hold) Min Max 2tSCLK –1.5 2tSCLK –1.5 4tSCLK 2tSCLK –1.5 2tSCLK –1.5 2tSCLK –1.5 1.6 1.6 0 0 ns ns ns ns ns ns ns ns 8 8 10 0 SPIxSS (INPUT) tSDSCI tSPICLS tSPICHS tHDS tSPICLK SPIxSCK (INPUT) tDSOE tDDSPID tHDSPID tDDSPID tDSDHI SPIxMISO (OUTPUT) CPHA = 1 tSSPID tHSPID SPIxMOSI (INPUT) tDSOE tHDSPID tDDSPID tDSDHI SPIxMISO (OUTPUT) CPHA = 0 tSSPID SPIxMOSI (INPUT) Figure 39. Serial Peripheral Interface (SPI) Port—Slave Timing Rev. C | Page 65 of 100 | February 2010 tHSPID Unit tSPITDS ns ns ns ns ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing The UART ports have a maximum baud rate of SCLK/16. There is some latency between the generation of internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART. For more information, see the ADSP-BF54x Blackfin Processor Hardware Reference. General-Purpose Port Timing Table 47 and Figure 40 describe general-purpose port operations. Table 47. General-Purpose Port Timing Parameter Timing Requirement tWFI General-Purpose Port Pin Input Pulse Width Switching Characteristics tGPOD General-Purpose Port Pin Output Delay from CLKOUT Low CLKOUT tGPOD GPIO OUTPUT tWFI GPIO INPUT Figure 40. General-Purpose Port Timing Rev. C | Page 66 of 100 | February 2010 Min Max tSCLK + 1 –0.3 Unit ns 6 ns ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Timer Cycle Timing Table 48 and Figure 41 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input frequency of (fSCLK/2) MHz. Table 48. Timer Cycle Timing Parameter Timing Characteristics tWL Timer Pulse Width Input Low1 tWH Timer Pulse Width Input High1 Timer Input Setup Time Before CLKOUT Low2 tTIS tTIH Timer Input Hold Time After CLKOUT Low2 Switching Characteristics tHTO Timer Pulse Width Output tTOD Timer Output Delay After CLKOUT High 1 2 Min The minimum pulse widths apply for TMRx signals in width capture and external clock modes. Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize timer flag inputs. CLKOUT tTOD TMRx OUTPUT tTIS tTIH tHTO TMRx INPUT tWH,tWL Figure 41. Timer Cycle Timing Rev. C | Page 67 of 100 | February 2010 Max Unit tSCLK +1 tSCLK +1 6.5 –1 ns ns ns ns 1×tSCLK (232 – 1)×tSCLK ns 6 ns ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Up/Down Counter/Rotary Encoder Timing Table 49 and Figure 42 describe up/down counter/rotary encoder timing. Table 49. Up/Down Counter/Rotary Encoder Timing Parameter Timing Requirements tWCOUNT CUD/CDG/CZM Input Pulse Width tCIS CUD/CDG/CZM Input Setup Time Before CLKOUT High1 tCIH CUD/CDG/CZM Input Hold Time After CLKOUT High1 1 Min tSCLK + 1 7.2 0.0 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs. CLKOUT tCIS tCIH CUD/CDG/CZM tWCOUNT Figure 42. Up/Down Counter/Rotary Encoder Timing Rev. C | Page 68 of 100 | February 2010 Max Unit ns ns ns ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 SD/SDIO Controller Timing Table 50 and Figure 43 describe SD/SDIO controller timing. Table 51 and Figure 44 describe SD/SDIO controller (highspeed mode) timing. Table 50. SD/SDIO Controller Timing Parameter Timing Requirements SD_Dx and SD_CMD Input Setup Time tISU SD_Dx and SD_CMD Input Hold Time tIH Switching Characteristics SD_CLK Frequency During Data Transfer Mode1 fPP SD_CLK Frequency During Identification Mode fOD tWL SD_CLK Low Time SD_CLK High Time tWH SD_CLK Rise Time tTLH tTHL SD_CLK Fall Time SD_Dx and SD_CMD Output Delay Time During Data Transfer Mode tODLY SD_Dx and SD_CMD Output Delay Time During Identification Mode tODLY 1 2 Min Max Unit 7.2 2 0 1002 15 15 –1 –1 ns ns 20 400 MHz kHz ns ns ns ns ns ns 10 10 14 50 tPP=1/fPP Spec can be 0 kHz, meaning to stop the clock. The given minimum frequency range is for cases where a continuous clock is required. VOH (MIN) tPP SD_CLK tTHL tISU tTLH tWL tIH tWH INPUT tODLY OUTPUT NOTES: 1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS. 2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS. Figure 43. SD/SDIO Controller Timing Rev. C | Page 69 of 100 | February 2010 VOL (MAX) ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 51. SD/SDIO Controller Timing (High Speed Mode) Parameter Timing Requirements SD_Dx and SD_CMD Input Setup Time tISU tIH SD_Dx and SD_CMD Input Hold Time Switching Characteristics SD_CLK Frequency During Data Transfer Mode1 fPP tWL SD_CLK Low Time SD_CLK High Time tWH SD_CLK Rise Time tTLH tTHL SD_CLK Fall Time SD_Dx and SD_CMD Output Delay Time During Data Transfer Mode tODLY SD_Dx and SD_CMD Output Hold Time tOH 1 Min Max Unit 7.2 2 0 9.5 9.5 ns ns 40 MHz ns ns ns ns ns ns 3 3 2 2.5 tPP=1/fPP VOH (MIN) tPP SD_CLK tTHL tISU tTLH tWL tIH VOL (MAX) tWH INPUT tODLY tOH OUTPUT NOTES: 1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS. 2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS. Figure 44. SD/SDIO Controller Timing (High Speed Mode) Rev. C | Page 70 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 MXVR Timing Table 52 and Table 53 describe the MXVR timing requirements. Figure 5 illustrates the MOST connection. Table 52. MXVR Timing—MXI Center Frequency Requirements Parameter fMXI_256 fMXI_384 fMXI_512 fMXI_1024 Fs = 38 kHz 9.728 14.592 19.456 38.912 MXI Center Frequency (256 Fs) MXI Center Frequency (384 Fs) MXI Center Frequency (512 Fs) MXI Center Frequency (1024 Fs) Fs = 44.1 kHz 11.2896 16.9344 22.5792 45.1584 Fs = 48 kHz 12.288 18.432 24.576 49.152 Unit MHz MHz MHz MHz Min Max Unit –50 –300 +40 +50 +300 +60 ppm ppm % Table 53. MXVR Timing— MXI Clock Requirements Parameter Timing Requirements FSMXI MXI Clock Frequency Stability FTMXI MXI Frequency Tolerance Over Temperature DCMXI MXI Clock Duty Cycle Rev. C | Page 71 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 HOSTDP A/C Timing-Host Read Cycle Table 54 and Figure 45 describe the HOSTDP A/C host read cycle timing requirements. Table 54. Host Read Cycle Timing Requirements Parameter Timing Requirements tSADRDL HOST_ADDR and HOST_CE Setup Before HOST_RD Falling Edge tHADRDH HOST_ADDR and HOST_CE Hold After HOST_RD Rising Edge tRDWL HOST_RD Pulse Width Low (ACK Mode) tRDWL HOST_RD Pulse Width Low (INT Mode) tRDWH HOST_RD Pulse Width High or Time Between HOST_RD Rising Edge and HOST_WR Falling Edge tDRDHRDY HOST_RD Rising Edge Delay After HOST_ACK Rising Edge (ACK Mode) Switching Characteristics tSDATRDY HOST_D15–0 Valid Prior HOST_ACK Rising Edge (ACK Mode) tDRDYRDL HOST_ACK Falling Edge After HOST_CE (ACK Mode) tRDYPRD HOST_ACK Low Pulse-Width for Read Access (ACK Mode) tDDARWH HOST_D15–0 Disable After HOST_RD tACC HOST_D15–0 Valid After HOST_RD Falling Edge (INT Mode) tHDARWH HOST_D15–0 Hold After HOST_RD Rising Edge 1 Min Max Units 4 2.5 tDRDYRDL + tRDYPRD + tDRDHRDY 1.5 × tSCLK + 8.7 2 × tSCLK ns ns ns ns ns 0 ns tSCLK – 4.0 11.25 NM1 8.0 1.5 × tSCLK 1.0 ns ns ns ns ns ns NM (Not Measured) — This parameter is based on tSCLK. It is not measured because the number of SCLK cycles for which HOST_ACK remains low depends on the Host DMA FIFO status. This is system design dependent. HOST_ADDR HOST_CE tSADRDL tHADRDH tRDWL HOST_RD tSDATRDY tACC tRDWH tDDARWH tHDARWH HOST_DATA tDRDYRDL tDRDHRDY tRDYPRD HOST_ACK In Figure 45, HOST_DATA is HOST_D0–D15. Figure 45. HOSTDP A/C—Host Read Cycle Rev. C | Page 72 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 HOSTDP A/C Timing-Host Write Cycle Table 55 and Figure 46 describe the HOSTDP A/C host write cycle timing requirements. Table 55. Host Write Cycle Timing Requirements Parameter Timing Requirements tSADWRL HOST_ADDR/HOST_CE Setup Before HOST_WR Falling Edge tHADWRH HOST_ADDR/HOST_CE Hold After HOST_WR Rising Edge tWRWL HOST_WR Pulse Width Low (ACK Mode) HOST_WR Pulse Width Low (INT Mode) HOST_WR Pulse Width High or Time Between HOST_WR Rising Edge tWRWH and HOST_RD Falling Edge tDWRHRDY HOST_WR Rising Edge Delay After HOST_ACK Rising Edge (ACK Mode) HOST_D15–0 Hold After HOST_WR Rising Edge tHDATWH tSDATWH HOST_D15–0 Setup Before HOST_WR Rising Edge Switching Characteristics tDRDYWRL HOST_ACK Falling Edge After HOST_CE Asserted (ACK Mode) tRDYPWR HOST_ACK Low Pulse-Width for Write Access (ACK Mode) 1 Min Max Unit 4 2.5 tDRDYWRL + tRDYPRD + tDWRHRDY 1.5 × tSCLK + 8.7 2 × tSCLK ns ns ns ns ns 0 2.5 3.5 ns ns ns 11.25 NM1 ns ns NM (not measured)—This parameter is based on tSCLK. It is not measured because the number of SCLK cycles for which HOST_ACK remains low depends on the Host DMA FIFO status. This is system design dependent. HOST_ADDR HOST_CE tSADWRL tWRWL tHADWRH tWRWH HOST_WR tSDATWH tHDATWH HOST_DATA tDRDYWRL tRDYPWR tDWRHRDY HOST_ACK In Figure 46, HOST_DATA is HOST_D0–D15. Figure 46. HOSTDP A/C- Host Write Cycle Rev. C | Page 73 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ATA/ATAPI-6 Interface Timing The following tables and figures specify ATAPI timing parameters. For detailed parameter descriptions, refer to the ATAPI specification (ANSI INCITS 361-2002). Table 58 to Table 61 include ATAPI timing parameter equations. System designers should use these equations along with the parameters provided in Table 56 and Table 57. ATAPI timing control registers should be programmed such that ANSI INCITS 361-2002 specifications are met for the desired transfer type and mode. Table 56. ATA/ATAPI-6 Timing Parameters Parameter tSK1 Difference in output delay after CLKOUT for ATAPI output pins1 tOD Output delay after CLKOUT for outputs1 tSUD ATAPI_D0-15 or ATAPI_D0-15A Setup Before CLKOUT ATAPI_IORDY Setup Before CLKOUT tSUI tSUDU ATAPI_D0-15 or ATAPI_D0-15A Setup Before ATAPI_IORDY (UDMA-in only) tHDU ATAPI_D0-15 or ATAPI_D0-15A Hold After ATAPI_IORDY (UDMA-in only) 1 Min Max 6 12 6 6 2 2.6 Unit ns ns ns ns ns ns ATAPI output pins include ATAPI_CS0, ATAPI_CS1, A1-3, ATAPI_DIOR, ATAPI_DIOW, ATAPI_DMACK, ATAPI_D0-15, ATAPI_A0-2A, and ATAPI_D0-15A. Table 57. ATA/ATAPI-6 System Timing Parameters Parameter Maximum difference in board propagation delay between any 2 ATAPI output pins1 tSK2 tBD Maximum board propagation delay. tSK3 Maximum difference in board propagation delay during a read between ATAPI_IORDY and ATAPI_D015/ATAPI_D0-15A. tSK4 Maximum difference in ATAPI cable propagation delay between output pin group A and output pin group B2 tCDD ATAPI cable propagation delay for ATAPI_D0-15 and ATAPI_D0-15A signals. ATAPI cable propagation delay for ATAPI_DIOR, ATAPI_DIOW, ATAPI_IORDY, and ATAPI_DMACK signals. tCDC 1 2 Source System Design System Design System Design ATAPI Cable Specification ATAPI Cable Specification ATAPI Cable Specification ATAPI output pins include ATAPI_CS0, ATAPI_CS1, A1-3, ATAPI_DIOR, ATAPI_DIOW, ATAPI_DMACK, ATAPI_D0-15, ATAPI_A0-2A, and ATAPI_D0-15A. Output pin group A includes ATAPI_DIOR, ATAPI_DIOW, and ATAPI_DMACK. Output pin group B includes ATAPI_CS0, ATAPI_CS1, A1-3, ATAPI_D0-15, ATAPI_A0-2A, and ATAPI_D0-15A. Rev. C | Page 74 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Register and PIO Table 58 and Figure 47 describe the ATAPI register and the PIO data transfer timing. Table 58. ATAPI Register and PIO Data Transfer Timing ATAPI Parameter/Description Cycle time t0 t1 ATAPI_ADDR valid to ATAPI_DIOR/ATAPI_DIOW setup ATAPI_DIOR/ATAPI_DIOW pulse width t2 t2i ATAPI_DIOR/ATAPI_DIOW recovery time t3 ATAPI_DIOW data setup t4 ATAPI_DIOW data hold ATAPI_DIOR data setup t5 t6 ATAPI_DIOR data hold t9 ATAPI_DIOR/ATAPI_DIOW to ATAPI_ADDR valid hold ATAPI_IORDY setup time tA 1 ATAPI_REG/PIO_TIM_x Timing Register Setting1 Timing Equation T2_PIO, TEOC_PIO (T2_PIO + TEOC_PIO) × tSCLK T1 T1 × tSCLK – (tSK1 + tSK2 + tSK4) T2_PIO TEOC_PIO T2_PIO T4 N/A N/A TEOC_PIO T2_PIO × tSCLK TEOC_PIO × tSCLK T2_PIO × tSCLK – (tSK1 + tSK2 + tSK4) T4 × tSCLK – (tSK1 + tSK2 + tSK4) tOD + tSUD + 2 × tBD + tCDD + tCDC 0 TEOC_PIO × tSCLK – (tSK1 + tSK2 + tSK4) T2_PIO T2_PIO × tSCLK – (tOD + tSUI + 2 × tCDC + 2 × tBD) ATAPI timing register setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for the ATA device mode of operation. include ATAPI_A0A, ATAPI_A1A, ATAPI_A2A, ATAPI_CS0, and ATAPI_CS1. Note that an alternate ATAPI_D0-15 port bus is ATAPI_D0-15A Figure 47 displays the REG and PIO data transfer timing. Note that ATAPI_ADDR pins include A1-3, ATAPI_CS0, and ATAPI_CS1. Alternate ATAPI port ATAPI _ADDR pins t0 ATAPI ADDR t1 t9 t2 t2i ATAPI_DIOR/ ATAPI_DIOW ATAPI_D0–15 (WRITE) t3 t4 ATAPI_D0–15 (READ) tA t5 t6 ATAPI_IORDY ATAPI_IORDY Figure 47. REG and PIO Data Transfer Timing1 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. Rev. C | Page 75 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ATAPI Multiword DMA Transfer Timing Table 59 and Figure 48 through Figure 51 describe the ATAPI multiword DMA transfer timing. Table 59. ATAPI Multiword DMA Transfer Timing ATAPI Parameter/Description t0 Cycle time tD ATAPI_DIOR/ATAPI_DIOW asserted Pulse Width tF ATAPI_DIOR data hold tG(write) ATAPI_DIOW data setup tG(read) ATAPI_DIOR data setup tH ATAPI_DIOW data hold tI ATAPI_DMACK to ATAPI_DIOR/ATAPI_DIOW setup tJ ATAPI_DIOR/ATAPI_DIOW to ATAPI_DMACK hold tKR ATAPI_DIOR negated pulse width tKW ATAPI_DIOW negated pulse width tLR ATAPI_DIOR to ATAPI_DMARQ delay tM ATAPI_CS0-1 valid to ATAPI_DIOR/ATAPI_DIOW tN ATAPI_CS0-1 hold 1 ATAPI_MULTI_TIM_x Timing Register Setting1 TD, TK TD Timing Equation (TD + TK) × tSCLK TD × tSCLK N/A TD TD TK TM 0 TD × tSCLK – (tSK1 + tSK2 + tSK4) tOD + tSUD + 2 × tBD + tCDD + tCDC TK × tSCLK – (tSK1 + tSK2 + tSK4) TM × tSCLK – (tSK1 + tSK2 + tSK4) TK, TEOC_MDMA (TK + TEOC_MDMA) × tSCLK – (tSK1 + tSK2 + tSK4) TKR TKW N/A TM TKR × tSCLK TKW × tSCLK (TD + TK) × tSCLK – (tOD + 2 × tBD + 2 × tCDC) TM × tSCLK – (tSK1 + tSK2 + tSK4) TK, TEOC_MDMA (TK + TEOC_MDMA) × tSCLK – (tSK1 + tSK2 + tSK4) ATAPI timing register setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for an ATA device mode of operation. Rev. C | Page 76 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Figure 48 displays the initiation of a multiword DMA data burst. Note that an alternate ATAPI_D0-15 port bus is ATAPI_D0-15A. ATAPI_CS0 ATAPI_CS1 tM ATAPI_DMARQ tI ATAPI_DMACK tD ATAPI_DIOR ATAPI_DIOW tG tF ATAPI_D0–15 (READ) tG tH ATAPI_D0–15 (WRITE) Figure 48. Initiating a Multiword DMA Data Burst1 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. Figure 49 displays a sustained multiword DMA data burst. ATAPI_CS0 ATAPI_CS1 ATAPI_DMARQ ATAPI_DMACK t0 ATAPI_DIOR ATAPI_DIOW tD tK ATAPI_D0–15 (READ) tG tF tG tF ATAPI_D0–15 (WRITE) tG tH tG tH Figure 49. Sustained Multiword DMA Data Burst1 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. Rev. C | Page 77 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Figure 50 displays a device terminating a multiword DMA data burst. ATAPI_CS0 ATAPI_CS1 tN ATAPI_DMARQ tLR ATAPI_DMACK tKR tKW tD tJ ATAPI_DIOR ATAPI_DIOW t0 ATAPI_D0–15 (READ) tG tF ATAPI_D0–15 (WRITE) tG tH Figure 50. Device Terminating a Multiword DMA Data Burst 1 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. Figure 51 displays a host terminating a multiword DMA data burst. ATAPI_CS0 ATAPI_CS1 tN ATAPI_DMARQ ATAPI_DMACK tKR tKW tD tJ ATAPI_DIOR ATAPI_DIOW t0 ATAPI_D0–15 (READ) tG tF ATAPI_D0–15 (WRITE) tG tH Figure 51. Host Terminating a Multiword DMA Data Burst1 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. Rev. C | Page 78 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ATAPI Ultra DMA Data-In Transfer Timing Table 60 and Figure 52 through Figure 55 describe the ATAPI ultra DMA data-in data transfer timing. Table 60. ATAPI Ultra DMA Data-In Transfer Timing ATAPI Parameter tDS Data setup time at host tDH Data hold time at host tCVS CRC word valid setup time at host CRC word valid hold time at host tCVH tLI Limited interlock time tMLI Interlock time with minimum tAZ Maximum time allowed for output drivers to release tZAH Minimum delay time required for output tENV2 ATAPI_DMACK to ATAPI_DIOR/DIOW tRP ATAPI_DMACK to ATAPI_DIOR/DIOW tACK Setup and hold times for ATAPI_DMACK 1 2 ATAPI_ULTRA_TIM_x Timing Register Setting1 N/A N/A TDVS TACK N/A TZAH, TCVS N/A Timing Equation TSK3 + tSUDU TSK3 + tHDU TDVS × tSCLK – (tSK1 + tSK2) TACK × tSCLK – (tSK1 + tSK2) 2 × tBD + 2 × tSCLK + tOD (TZAH + TCVS) × tSCLK – (4 × tBD + 4 × tSCLK + 2 × tOD) 0 TZAH TENV TRP TACK 2 × tSCLK + TZAH × tSCLK + tSCLK (TENV × tSCLK) +/- (tSK1 + tSK2) TRP × tSCLK – (tSK1 + tSK2 + tSK4) TACK × tSCLK – (tSK1 + tSK2) ATAPI Timing Register Setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for ATA device mode of operation. This timing equation can be used to calculate both the minimum and maximum tENV. Rev. C | Page 79 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Figure 52 displays the initiation of an ultra DMA data-in burst. Note that an alternate ATAPI_D0-15 port bus is ATAPI_D0-15A. Also note that ATAPI_ADDR pins include A1-3, ATAPI_CS0, and ATAPI_CS1. Alternate ATAPI port ATAPI _ADDR pins include ATAPI_A0A, ATAPI_A1A, ATAPI_A2A, ATAPI_CS0, and ATAPI_CS1. ATAPI_DMARQ ATAPI_DMACK tACK tENV tACK tENV ATAPI_DIOW ATAPI_DIOR ATAPI_IORDY tAZ ATAPI_D0–15 tACK ATAPI ADDR Figure 52. Initiating an Ultra DMA Data-In Burst1 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. Figure 53 displays a sustained ultra DMA data-in burst. Note that an alternate ATAPI_D0-15 port bus is ATAPI_D0-15A. ATAPI_IORDY tDS tDH tDH tDS tDH ATAPI_D0–15 Figure 53. Sustained Ultra DMA Data-In Burst1 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. Rev. C | Page 80 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Figure 54 displays a device terminating an ultra DMA data-in burst. ATAPI_DMARQ ATAPI_DMACK tLI tLI tMLI tACK ATAPI_DIOW tLI tACK ATAPI_DIOR ATAPI_IORDY tAZ tCVS tCVH ATAPI_D0–15 tZAH tACK ATAPI ADDR Figure 54. Device Terminating an Ultra DMA Data-In Burst1 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. Figure 55 displays a host terminating an ultra DMA data-in burst. ATAPI_DMARQ tLI tMLI ATAPI_DMACK tACK ATAPI_DIOW tZAH tRP tACK ATAPI_DIOR tLI ATAPI_IORDY tCVS tCVH ATAPI_D0–15 tACK ATAPI ADDR Figure 55. Host Terminating an Ultra DMA Data-In Burst1 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. Rev. C | Page 81 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ATAPI Ultra DMA Data-Out Transfer Timing Table 61 and Figure 56 through Figure 59 describes the ATAPI ultra DMA data-out transfer timing. Table 61. ATAPI Ultra DMA Data-Out Transfer Timing ATAPI Parameter tCYC2 Cycle time t2CYC Two cycle time tDVS Data valid setup time at sender Data valid hold time at sender tDVH tCVS CRC word valid setup time at host tCVH CRC word valid hold time at host tDZFS Time from data output released-to-driving to first strobe timing tLI Limited interlock time tMLI Interlock time with minimum 3 tENV ATAPI_DMACK to ATAPI_DIOR/DIOW tRFS Ready to final strobe time tACK Setup and Hold time for ATAPI_DMACK tSS Time from STROBE edge to assertion of ATAPI_DIOW ATAPI_ULTRA_TIM_x Timing Register Setting1 TDVS, TCYC_TDVS TDVS, TCYC_TDVS TDVS TCYC_TDVS TDVS TACK TDVS Timing Equation (TDVS + TCYC_TDVS) × tSCLK 2 × (TDVS + TCYC_TDVS) × tSCLK TDVS × tSCLK – (tSK1 + tSK2) TCYC_TDVS × tSCLK – (tSK1 + tSK2) TDVS × tSCLK – (tSK1 + tSK2) TACK × tSCLK – (tSK1 + tSK2) TDVS × tSCLK – (tSK1 + tSK2) N/A TMLI TENV N/A TACK TSS 2 × tBD + 2 × tSCLK + tOD TMLI × tSCLK – (tSK1 + tSK2) (TENV × tSCLK) +/– (tSK1 + tSK2) 2 × tBD + 2 × tSCLK + tOD TACK × tSCLK – (tSK1 + tSK2) TSS × tSCLK – (tSK1 + tSK2) 1 ATAPI Timing Register Setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for ATA device mode of operation. ATA/ATAPI-6 compliant functionality with limited speed. 3 This timing equation can be used to calculate both the minimum and maximum tENV. 2 Rev. C | Page 82 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Figure 56 displays the initiation of an ultra DMA data-out burst. Note that an alternate ATAPI_D0-15 port bus is ATAPI_D015A. ATAPI_DMARQ ATAPI_DMACK tENV ATAPI_DIOW tLI ATAPI_IORDY tACK ATAPI_DIOR tDZFS tDVS tDVH ATAPI_D0–15 tACK ATAPI ADDR Figure 56. Initiating an Ultra DMA Data-Out Burst1 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. Figure 57 displays a sustained ultra DMA data-out burst. Note that an alternate ATAPI_D0-15 port bus is ATAPI_D0-15A. t2CYC tCYC tCYC t2CYC ATAPI_DIOR tDVH tDVS tDVH tDVS tDVH ATAPI_D0–15 Figure 57. Sustained Ultra DMA Data-Out Burst1 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. Rev. C | Page 83 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Figure 58 displays a host terminating an ultra DMA data-out burst. ATAPI_DMARQ ATAPI_DMACK tLI tLI tMLI tACK ATAPI_DIOW tSS tLI ATAPI_IORDY tACK ATAPI_DIOR tCVS tCVH ATAPI_D0–15 tACK ATAPI ADDR Figure 58. Host terminating an Ultra DMA Data-Out Burst1 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. Figure 59 displays a device terminating an ultra DMA data-out burst. ATAPI_DMARQ ATAPI_DMACK tLI tMLI tACK tLI tMLI tACK ATAPI_DIOW ATAPI_IORDY tRFS ATAPI_DIOR tCVS tCVH ATAPI_D0–15 tACK ATAPI ADDR Figure 59. Device Terminating an Ultra DMA Data-Out Burst1 1 This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI. Rev. C | Page 84 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 USB On-The-Go-Dual-Role Device Controller Timing Table 62 describes the USB On-The-Go Dual-Role Device Controller timing requirements. Table 62. USB On-The-Go Dual-Role Device Controller Timing Requirements Parameter Timing Requirements fUSB USB_XI frequency FSUSB USB_XI Clock Frequency Stability Min Max Unit 9 –50 33.3 +50 MHz ppm Min Max Unit JTAG Test And Emulation Port Timing Table 63 and Figure 60 describe JTAG port operations. Table 63. JTAG Port Timing Parameter Timing Parameters tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS System Inputs Setup Before TCK High1 System Inputs Hold After TCK High1 tHSYS tTRSTW TRST Pulse-Width2 (measured in TCK cycles) Switching Characteristics tDTDO TDO Delay from TCK Low tDSYS System Outputs Delay After TCK Low3 20 4 4 4 11 4 0 1 ns ns ns ns ns tTCK 10 16.5 ns ns System inputs = PA15–0, PB14–0, PC13–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ13–0, DQ15–0, DQS1–0, D15–0, ATAPI_PDIAG, RESET, NMI, and BMODE3–0. 50 MHz Maximum 3 System outputs = PA15–0, PB14–0, PC13–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ13–0, DQ15–0, DQS1–0, D15–0, DA12–0, DBA1–0, DQM1–0, DCLK0-1, DCLK0–1, DCS1–0, DCLKE, DRAS, DCAS, DWE, AMS3–0, ABE1–0, AOE, ARE, AWE, CLKOUT, A3–1, and MFS. 2 tTCK TCK tSTAP tHTAP TMS TDI tDTDO TDO tSSYS tHSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS Figure 60. JTAG Port Timing Rev. C | Page 85 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 OUTPUT DRIVE CURRENTS 200 100 SOURCE CURRENT (mA) 80 VOH 2.25V, +105°C 60 3.3V, +25°C 3.6V, –40°C 100 50 0 –50 –100 –150 2.5V, +25°C 2.7V, +105°C VOL 3.3V, +25°C –200 40 3.6V, –40°C 2.75V, –40°C –250 0 20 0.5 1.0 0 1.5 2.0 2.5 SOURCE VOLTAGE (V) 3.0 3.5 4.0 Figure 64. Drive Current B (High VDDEXT) –20 –40 VOL 60 –60 1.0 2.75V, –40°C 1.5 2.0 2.5 SOURCE VOLTAGE (V) 3.0 Figure 61. Drive Current A (Low VDDEXT) 150 2.7V, +105°C 100 SOURCE CURRENT (mA) 0.5 2.75V, –40°C 20 0 –20 –40 2.25V, +105°C VOL 3.3V, +25°C VOH VOH 2.5V, +25°C 40 2.5V, +25°C –100 0 SOURCE CURRENT (mA) 2.25V, +105°C 2.25V, +105°C –80 2.5V, +25°C –60 2.75V, –40°C 3.6V, –40°C 50 –80 0 0.5 1.0 1.5 2.0 2.5 3.0 SOURCE VOLTAGE (V) 0 Figure 65. Drive Current C (Low VDDEXT) –50 –100 2.7V, +105°C VOL 80 3.3V, +25°C 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V) 3.0 3.5 4.0 Figure 62. Drive Current A (High VDDEXT) 150 2.25V, +105°C 2.5V, +25°C 100 VOH OUTPUT CURRENT (mA) –150 0 2.7V, +105°C VOH 3.3V, +25°C 3.6V, –40°C SOURCE CURRENT (mA) VOH 2.7V, +105°C 150 SOURCE CURRENT (mA) Figure 61 through Figure 70 show typical current-voltage characteristics for the output drivers of the ADSP-BF54x Blackfin processors. The curves represent the current drive capability of the output drivers as a function of output voltage. 60 3.6V, –40°C 40 20 0 –20 –40 –60 2.75V, –40°C 2.7V, +105°C VOL –80 50 3.3V, +25°C 3.6V, –40°C –100 0 0.5 0 1.0 1.5 2.0 2.5 OUTPUT VOLTAGE (V) 3.0 Figure 66. Drive Current C (High VDDEXT) –50 –100 2.25V, +105°C VOL 2.5V, +25°C 2.75V, –40°C –150 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) 2.5 3.0 Figure 63. Drive Current B (Low VDDEXT) Rev. C | Page 86 of 100 | February 2010 3.5 4.0 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 50 10 VOH 2.5V, +105°C 2.6V, +25°C 40 SOURCE CURRENT (mA) SOURCE CURRENT (mA) 0 2.7V, –40°C 30 20 10 0 –10 –20 –10 –20 –30 2.25V, +105°C –40 VOL –30 VOL –40 2.5V, –105°C 2.6V, +25°C –50 0 2.5V, +25°C –50 0.5 1.0 1.5 2.7V, –40°C 2.0 2.75V, –40°C –60 0 3.0 2.5 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) SOURCE VOLTAGE (V) 2.5 3.0 Figure 69. Drive Current E (Low VDDEXT) Figure 67. Drive Current D (DDR SDRAM) 50 SOURCE CURRENT (mA) 1.875V, +25°C 30 VOH 0 SOURCE CURRENT (mA) 1.8V, +105°C 40 1.95V, –40°C 20 10 0 –10 –10 –20 –30 –40 2.7V, +105°C –50 –20 –60 –30 –70 3.3V, +25°C VOL 1.8V, +105°C –40 1.875V, +25°C –50 0 3.6V, –40°C –80 VOL 0.25 0.5 0.75 1.95V, –40°C 1.5 1.0 1.25 1.75 2.0 –90 0 0.5 SOURCE VOLTAGE (V) 1.5 2.0 2.5 SOURCE VOLTAGE (V) 3.0 Figure 70. Drive Current E (High VDDEXT) Figure 68. Drive Current D (Mobile DDR SDRAM) Rev. C | 1.0 Page 87 of 100 | February 2010 3.5 4.0 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 TEST CONDITIONS All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 71 shows the measurement point for AC measurements (except output enable/disable). The measurement point VMEAS is VDDEXT/2 or VDDDDR/2, depending on the pin under test. INPUT OR OUTPUT REFERENCE SIGNAL tDIS_MEASURED tDIS VOH (MEASURED) VOH (MEASURED) V VOH(MEASURED) VTRIP(HIGH) VOL (MEASURED) + V VTRIP(LOW) VOL (MEASURED) VOL (MEASURED) VMEAS VMEAS tENA_MEASURED tENA tDECAY Figure 71. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) tTRIP OUTPUT STOPS DRIVING OUTPUT STARTS DRIVING HIGH IMPEDANCE STATE Output Enable Time Figure 72. Output Enable/Disable Output pins are considered to be enabled when they have made a transition from a high-impedance state to the point when they start driving. The output enable time tENA is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown in the output enable/disable diagram (Figure 72). The time, tENA_MEASURED, is the interval from the point when the reference signal switches to the point when the output voltage reaches either 1.75 V (output high) or 1.25 V (output low). Time tTRIP is the interval from when the output starts driving to when the output reaches the 1.25 V or 1.75 V trip voltage. Time tENA is calculated as shown in the equation: Example System Hold Time Calculation To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose ∆V to be the difference between the ADSP-BF54x Blackfin processors’ output voltage and the input threshold for the device requiring the hold time. A typical ∆V will be 0.4 V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the minimum disable time (for example, tDDAT for an asynchronous memory write cycle). CAPACITIVE LOADING Output delays and holds are based on standard capacitive loads of an average of 6 pF on all balls (see Figure 73). t ENA = t ENA_MEASURED – t TRIP If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. TESTER PIN ELECTRONICS 50: Output Disable Time VLOAD Output pins are considered to be disabled when they stop driving, go into a high-impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ∆V is dependent on the capacitive load, CL and the load current, IL. This decay time can be approximated by the equation: T1 45: DUT OUTPUT 70: ZO = 50:(impedance) TD = 4.04 r 1.18 ns 50: 0.5pF 4pF 2pF 400: t DECAY = ( C L ∆V ) ⁄ I L The output disable time tDIS is the difference between tDIS_MEASURED and tDECAY as shown in Figure 72. The time tDIS_MEASURED is the interval from when the reference signal switches to when the output voltage decays ∆V from the measured output high or output low voltage. The time tDECAY is calculated with test loads CL and IL, and with ∆V equal to 0.25 V. NOTES: THE WORST-CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. Figure 73. Equivalent Device Loading for AC Measurements (Includes All Fixtures) Rev. C | Page 88 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 VLOAD is equal to VDDEXT/2 or VDDDDR/2, depending on the pin under test. Figure 74 through Figure 85 on Page 91 show how output rise time varies with capacitance. The delay and hold specifications given should be derated by a factor derived from these figures. The graphs in these figures may not be linear outside the ranges shown. RISE AND FALL TIME ns (10% to 90%) 12 TYPICAL RISE AND FALL TIMES RISE AND FALL TIME ns (10% to 90%) 14 12 10 RISE TIME 8 FALL TIME 6 4 2 RISE TIME 10 0 FALL TIME 8 6 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 76. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver B at VDDEXT = 2.25 V 4 2 0 50 100 150 LOAD CAPACITANCE (pF) 200 RISE AND FALL TIME ns (10% to 90%) 10 0 250 Figure 74. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver A at VDDEXT = 2.25 V RISE AND FALL TIME ns (10% to 90%) 12 10 RISE TIME 9 8 RISE TIME 7 6 FALL TIME 5 4 3 2 8 1 FALL TIME 0 6 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 4 Figure 77. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver B at VDDEXT = 3.65 V 2 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 75. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver A at VDDEXT = 3.65 V Rev. C | Page 89 of 100 | February 2010 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 6 RISE AND FALL TIME ns (10% to 90%) RISE AND FALL TIME ns (10% to 90%) 30 25 RISE TIME 20 15 FALL TIME 10 5 RISE/FALL TIME 4 3 2 5 1 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 0 0 250 10 20 30 40 50 60 70 LOAD CAPACITANCE (pF) Figure 78. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver C at VDDEXT = 2.25 V Figure 81. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver D DDR SDRAM at VDDDDR= 2.7V RISE AND FALL TIME ns (10% to 90%) RISE AND FALL TIME ns (10% to 90%) 20 18 16 RISE TIME 14 12 FALL TIME 10 8 6 4 4 3.5 3 RISE/FALL TIME 2.5 2 1.5 1 .5 0 0 10 20 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 40 50 60 70 Figure 82. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver D Mobile DDR SDRAM at VDDDDR = 1.8V 250 RISE AND FALL TIME ns (10% to 90%) Figure 79. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver C at VDDEXT = 3.65 V RISE AND FALL TIME ns (10% to 90%) 30 LOAD CAPACITANCE (pF) 2 6 5 4 RISE/FALL TIME 3 2 4 3.5 3 RISE/FALL TIME 2.5 2 1.5 1 .5 0 0 1 0 0 10 20 30 40 50 60 LOAD CAPACITANCE (pF) 10 20 30 40 50 60 70 LOAD CAPACITANCE (pF) Figure 83. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver D Mobile DDR SDRAM at VDDDDR = 1.95V Figure 80. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver D DDR SDRAM at VDDDDR= 2.5V Rev. C | Page 90 of 100 | February 2010 70 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 THERMAL CHARACTERISTICS 132 To determine the junction temperature on the application printed circuit board use FALL TIME ns (10% to 90%) 128 T J = T CASE + ( Ψ JT × P D ) 124 FALL TIME where: 120 TJ =junction temperature (C) 116 TCASE = case temperature (C) measured by customer at top center of package. 112 ΨJT = from Table 71 108 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 PD = power dissipation. (See Table 18 on Page 38 for a method to calculate PD.) Values of θJA are provided for package comparison and printed circuit board design considerations. θJA can be used for a first order approximation of TJ by the equation Figure 84. Typical Fall Time (10% to 90%) vs. Load Capacitance for Driver E at VDDEXT = 2.7 V T J = T A + ( θ JA × P D ) 124 120 FALL TIME ns (10% to 90%) where: 116 TA = ambient temperature (C) FALL TIME 112 108 104 100 0 50 100 150 200 250 LOAD CAPACITANCE (pF) Figure 85. Typical Fall Time (10% to 90%) vs. Load Capacitance for Driver E at VDDEXT = 3.65 V Table 64 lists values for θJC and θJB parameters. These values are provided for package comparison and printed circuit board design considerations. Airflow measurements in Table 64 comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board measurement complies with JESD51-8. The junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC testboard. Table 64. Thermal Characteristics, 400-Ball CSP_BGA Parameter θJA θJB θJC ΨJT Rev. C | Page 91 of 100 | February 2010 Condition 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Typical 18.4 15.8 15.0 9.75 6.37 0.27 0.60 0.66 Unit C/W C/W C/W C/W C/W C/W C/W C/W ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 400-BALL CSP_BGA PACKAGE Table 65 lists the CSP_BGA package by signal for the ADSP-BF549. Table 66 on Page 95 lists the CSP_BGA package by ball number. Table 65. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) Signal A1 A2 A3 ABE0 ABE1 AMS0 AMS1 AMS2 AMS3 AOE ARE ATAPI_PDIAG AWE BMODE0 BMODE1 BMODE2 BMODE3 CLKBUF CLKIN CLKOUT D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DA0 DA1 DA2 DA3 Ball No. B2 A2 B3 C17 C16 A10 D9 B10 D10 C10 B12 P19 D12 W1 W2 W3 W4 D11 A11 L16 D13 C13 B13 B15 A15 B16 A16 B17 C14 C15 A17 D14 D15 E15 E14 D17 G19 G17 E20 G18 Signal DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DBA0 DBA1 DCAS DCLK0 DCLK0 DCLK1 DCLK1 DCLKE DCS0 DCS1 DDR_VREF DDR_VSSR DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM0 DQM1 DQS0 Ball No. G16 F19 D20 C20 F18 E19 B20 F17 D19 H17 H16 F16 E16 D16 C18 D18 B18 C19 B19 M20 N20 L18 M19 L19 L20 L17 K16 K20 K17 K19 J20 K18 H20 J19 J18 J17 J16 G20 H19 F20 Rev. C | Signal DQS1 DRAS DWE EMU EXT_WAKE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Page 92 of 100 | Ball No. H18 E17 E18 R5 M18 A1 A13 A20 B11 D1 D4 E3 F3 F6 F14 G9 G10 G11 H7 H8 H9 H10 H11 H12 J7 J8 J9 J10 J11 J12 K7 K8 K9 K10 K11 K12 K13 L7 L8 L9 February 2010 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GNDMP MFS MLF_M Ball No. L10 L11 L12 L13 L14 M6 M7 M8 M9 M10 M11 M12 M13 M14 N6 N7 N8 N9 N10 N11 N12 N13 N14 P8 P9 P10 P11 P12 P13 R9 R13 R14 R16 U8 V6 Y1 Y20 E7 E6 F4 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 65. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) (Continued) Signal MLF_P MXI MXO NMI PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PC0 PC1 PC2 PC3 PC4 Ball No. E4 C2 C1 C11 U12 V12 W12 Y12 W11 V11 Y11 U11 U10 Y10 Y9 V10 Y8 W10 Y7 W9 W5 Y2 T6 U6 Y4 Y3 W6 V7 W8 V8 U7 W7 Y6 V9 Y5 H2 J3 J2 H1 G2 Signal PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 Ball No. G1 J5 H3 Y14 V13 U13 W14 Y15 W15 P3 P4 R1 R2 T1 R3 T2 R4 U1 U2 T3 V1 T4 V2 U4 U3 V19 T17 U18 V14 Y16 W20 W19 R17 V20 U19 T18 P2 M5 P5 U16 Rev. C | Signal PE15 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 PH0 PH1 PH2 PH3 PH4 PH5 PH6 Page 93 of 100 | Ball No. W17 K3 J1 K2 K1 L2 L1 L4 K4 L3 M1 M2 M3 M4 N4 N1 N2 J4 K5 L5 N3 P1 V15 Y17 W16 V16 Y19 Y18 U15 P16 R18 Y13 W13 W18 U14 V17 V18 U17 C3 D6 February 2010 Signal PH7 PH8 PH9 PH10 PH11 PH12 PH13 PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 PI8 PI9 PI10 PI11 PI12 PI13 PI14 PI15 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PJ8 PJ9 PJ10 PJ11 PJ12 PJ13 RESET RTXI RTXO Ball No. H4 D5 C4 C7 C5 D7 C6 A3 B4 A4 B5 A5 B6 A6 B7 A7 C8 B8 A8 A9 C9 D8 B9 R20 N18 M16 T20 N17 U20 P18 N16 R19 P17 T19 M17 P20 N19 C12 A14 B14 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 65. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) (Continued) Signal TCK TDI TDO TMS TRST USB_DM USB_DP USB_ID USB_RSET USB_VBUS USB_VREF USB_XI USB_XO VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR Ball No. V3 V5 V4 U5 T5 E2 E1 G3 D3 D2 B1 F1 F2 F10 F11 F12 G15 H13 H14 H15 Signal VDDDDR VDDDDR VDDDDR VDDDDR VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Ball No. J14 J15 K14 K15 E5 E9 E10 E11 E12 F7 F8 F13 G5 G6 G7 G14 H5 H6 K6 M15 Rev. C | Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT Page 94 of 100 | Ball No. N5 N15 P15 R6 R7 R8 R15 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 F9 G8 G12 February 2010 Signal VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDMP VDDRTC VDDUSB VDDUSB VDDVR VROUT0 VROUT1 XTAL Ball No. G13 J6 J13 L6 L15 P6 P7 P14 R10 R11 R12 U9 E8 E13 F5 G4 F15 A18 A19 A12 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 66 lists the CSP_BGA package by ball number for the ADSP-BF549. Table 65 on Page 92 lists the CSP_BGA package by signal. Table 66. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 Signal GND A2 PI0 PI2 PI4 PI6 PI8 PI11 PI12 AMS0 CLKIN XTAL GND RTXI D4 D6 D10 VROUT0 VROUT1 GND USB_VREF A1 A3 PI1 PI3 PI5 PI7 PI10 PI15 AMS2 GND ARE D2 RTXO D3 D5 D7 DCLKE DCS1 DA10 Ball No. C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 Signal MXO MXI PH5 PH9 PH11 PH13 PH10 PI9 PI13 AOE NMI RESET D1 D8 D9 ABE1 ABE0 DCLK1 DCS0 DA7 GND USB_VBUS USB_RSET GND PH8 PH6 PH12 PI14 AMS1 AMS3 CLKBUF AWE D0 D11 D12 DCLK0 D15 DCLK1 DA12 DA6 Rev. C | Ball No. E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 Page 95 of 100 | Signal USB_DP USB_DM GND MLF_P VDDEXT MFS GNDMP VDDMP VDDEXT VDDEXT VDDEXT VDDEXT VDDRTC D14 D13 DCLK0 DRAS DWE DA9 DA2 USB_XI USB_XO GND MLF_M VDDUSB GND VDDEXT VDDEXT VDDINT VDDDDR VDDDDR VDDDDR VDDEXT GND VDDVR DCAS DA11 DA8 DA5 DQS0 February 2010 Ball No. G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 Signal PC5 PC4 USB_ID VDDUSB VDDEXT VDDEXT VDDEXT VDDINT GND GND GND VDDINT VDDINT VDDEXT VDDDDR DA4 DA1 DA3 DA0 DQM0 PC3 PC0 PC7 PH7 VDDEXT VDDEXT GND GND GND GND GND GND VDDDDR VDDDDR VDDDDR DBA1 DBA0 DQS1 DQM1 DQ11 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 66. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) (Continued) Ball No. J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 Signal PF1 PC2 PC1 PG0 PC6 VDDINT GND GND GND GND GND GND VDDINT VDDDDR VDDDDR DQ15 DQ14 DQ13 DQ12 DQ9 PF3 PF2 PF0 PF7 PG1 VDDEXT GND GND GND GND GND GND GND VDDDDR VDDDDR DQ5 DQ7 DQ10 DQ8 DQ6 Ball No. L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 Signal PF5 PF4 PF8 PF6 PG2 VDDINT GND GND GND GND GND GND GND GND VDDINT CLKOUT DQ4 DQ0 DQ2 DQ3 PF9 PF10 PF11 PF12 PE12 GND GND GND GND GND GND GND GND GND VDDEXT PJ2 PJ11 EXT_WAKE DQ1 DDR_VREF Rev. C | Ball No. N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 Page 96 of 100 | Signal PF14 PF15 PG3 PF13 VDDEXT GND GND GND GND GND GND GND GND GND VDDEXT PJ7 PJ4 PJ1 PJ13 DDR_VSSR PG4 PE11 PD0 PD1 PE13 VDDINT VDDINT GND GND GND GND GND GND VDDINT VDDEXT PG12 PJ9 PJ6 ATAPI_PDIAG PJ12 February 2010 Ball No. R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 Signal PD2 PD3 PD5 PD7 EMU VDDEXT VDDEXT VDDEXT GND VDDINT VDDINT VDDINT GND GND VDDEXT GND PE7 PG13 PJ8 PJ0 PD4 PD6 PD10 PD12 TRST PB2 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT PE1 PE10 PJ10 PJ3 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Table 66. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) (Continued) Ball No. U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 Signal PD8 PD9 PD15 PD14 TMS PB3 PB10 GND VDDINT PA8 PA7 PA0 PC10 PH1 PG11 PE14 PH4 PE2 PE9 PJ5 Ball No. V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 Signal PD11 PD13 TCK TDO TDI GND PB7 PB9 PB13 PA11 PA5 PA1 PC9 PE3 PG5 PG8 PH2 PH3 PE0 PE8 Ball No. W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Signal BMODE0 BMODE1 BMODE2 BMODE3 PB0 PB6 PB11 PB8 PA15 PA13 PA4 PA2 PG15 PC11 PC13 PG7 PE15 PH0 PE6 PE5 Figure 86 lists the top view of the BGA ball configuration. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 V A V B R C D G S S S E S S S F S G S S H S S J S S K S S S L R M G N P R T U V W Y KEY: VDDINT S SUPPLIES: VDDDDR, VDDMP, VDDUSB , VDDRTC , VDDVR VDDEXT R REFERENCES: DDR_VREF , USB_VREF GND G GROUNDS: GNDMP, DDR_VSSR NC V VROUT I/O SIGNALS Figure 86. 400-Ball CSP_BGA Configuration (Top View) Rev. C | Page 97 of 100 | February 2010 Ball No. Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal GND PB1 PB5 PB4 PB14 PB12 PA14 PA12 PA10 PA9 PA6 PA3 PG14 PC8 PC12 PE4 PG6 PG10 PG9 GND ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 OUTLINE DIMENSIONS Dimensions for the 17 mm × 17 mm CSP_BGA package in Figure 87 are shown in millimeters. 15.20 BSC SQ 17.00 BSC SQ A1 BALL 0.80 BSC BALL PITCH A1 BALL INDICATOR A B C D E F G H J K L M N P R T U V W Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW TOP VIEW 0.28 MIN 0.12 MAX COPLANARITY 1.70 MAX SIDE VIEW 0.50 BALL DIAMETER 0.45 0.40 DETAIL A SEATING PLANE DETAIL A NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205, VARIATION AM, WITH THE EXCEPTION OF BALL DIAMETER. 3. CENTER DIMENSIONS ARE NOMINAL. Figure 87. 400-Ball, 17 mm × 17 mm CSP_BGA (Chip Scale Package Ball Grid Array) (BC-400-1) SURFACE-MOUNT DESIGN Table 67 is provided as an aid to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 67. BGA Data for Use with Surface-Mount Design Package Package Ball Attach Type 400-Ball CSP_BGA (Chip Scale Package Ball Grid Array) BC-400-1 Solder Mask Defined Rev. C | Page 98 of 100 | February 2010 Package Solder Mask Opening 0.40 mm Diameter Package Ball Pad Size 0.50 mm Diameter ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 AUTOMOTIVE PRODUCTS Some ADSP-BF54x Blackfin processor models are available for automotive applications with controlled manufacturing. Note that these special models may have specifications that differ from the general release models. The automotive grade products shown in Table 68 are available for use in automotive applications. Contact your local ADI account representative or authorized ADI product distributor for specific product ordering information. Note that all automotive products are RoHS compliant. Table 68. Automotive Products Product Family1 ADBF542WBBCZ-4xx ADBF542WBBCZ-5xx ADBF544WBBCZ-5xx ADBF549WBBCZ-5xx ADBF549MWBBCZ-5xx 1 2 Temperature Range2 –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Speed Grade (Max) 400 MHz 533 MHz 533 MHz 533 MHz 533 MHz Package Description 400-Ball CSP_BGA 400-Ball CSP_BGA 400-Ball CSP_BGA 400-Ball CSP_BGA 400-Ball CSP_BGA The use of xx designates silicon revision Referenced temperature is ambient temperature. Rev. C | Page 99 of 100 | February 2010 Package Option BC-400-1 BC-400-1 BC-400-1 BC-400-1 BC-400-1 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 ORDERING GUIDE Model1, 2, 3 ADSP-BF542BBCZ-4A ADSP-BF542BBCZ-5A ADSP-BF542MBBCZ-5M ADSP-BF542KBCZ-6A ADSP-BF544BBCZ-4A ADSP-BF544BBCZ-5A ADSP-BF544MBBCZ-5M ADSP-BF547BBCZ-5A ADSP-BF547MBBCZ-5M ADSP-BF547KBCZ-6A ADSP-BF548MBBCZ-5M ADSP-BF548BBCZ-5A Temperature Range4 –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to +70°C –40°C to +85°C –40°C to +85°C Speed Grade (Max) 400 MHz 533 MHz 533 MHz 600 MHz 400 MHz 533 MHz 533 MHz 533 MHz 533 MHz 600 MHz 533 MHz 533 MHz 1 Package Description 400-Ball CSP_BGA 400-Ball CSP_BGA 400-Ball CSP_BGA 400-Ball CSP_BGA 400-Ball CSP_BGA 400-Ball CSP_BGA 400-Ball CSP_BGA 400-Ball CSP_BGA 400-Ball CSP_BGA 400-Ball CSP_BGA 400-Ball CSP_BGA 400-Ball CSP_BGA Package Option BC-400-1 BC-400-1 BC-400-1 BC-400-1 BC-400-1 BC-400-1 BC-400-1 BC-400-1 BC-400-1 BC-400-1 BC-400-1 BC-400-1 Each ADSP-BF54xM model contains a mobile DDR controller and does not support the use of standard DDR memory. Z = RoHS Compliant Part. 3 The ADSP-BF549 is available for automotive use only. Please contact your local ADI product representative or authorized distributor for specific automotive product ordering information. 4 Referenced temperature is ambient temperature. 2 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06512-0-2/10(C) Rev. C | Page 100 of 100 | February 2010