AD AD8021 Low noise, high speed amplifier for 16-bit system Datasheet

Low Noise, High Speed Amplifier
for 16-Bit Systems
AD8021
FEATURES
Low Noise
2.1 nV/√Hz Input Voltage Noise
2.1 pA/√Hz Input Current Noise
Custom Compensation
Constant Bandwidth from G = –1 to G = –10
High Speed
200 MHz (G = –1)
190 MHz (G = –10)
Low Power
34 mW or 6.7 mA Typ for 5 V Supply
Output Disable Feature, 1.3 mA
Low Distortion
–93 dB Second Harmonic, fC = 1 MHz
–108 dB Third Harmonic, fC = 1 MHz
DC Precision
1 mV Max Input Offset Voltage
0.5 V/C Input Offset Voltage Drift
Wide Supply Range, 5 V to 24 V
Low Price
Small Packaging
Available in SOIC-8 and MSOP-8
APPLICATIONS
ADC Preamp and Driver
Instrumentation Preamp
Active Filters
Portable Instrumentation
Line Receivers
Precision Instruments
Ultrasound Signal Processing
High Gain Circuits
CONNECTION DIAGRAM
SOIC-8 (R-8)
MSOP-8 (RM-8)
AD8021
LOGIC
REFERENCE
1
8
DISABLE
–IN
2
7
+VS
+IN
3
6
VOUT
–VS
4
5
CCOMP
The AD8021 allows the user to choose the gain bandwidth
product that best suits the application. With a single capacitor,
the user can compensate the AD8021 for the desired gain with
little trade-off in bandwidth. The AD8021 is a very well behaved
amplifier that settles to 0.01% in 23 ns for a 1 V step. It has a fast
overload recovery of 50 ns.
The AD8021 is stable over temperature with low input offset
voltage drift and input bias current drift, 0.5 µV/°C and 10 nA/°C,
respectively. The AD8021 is also capable of driving a 75 Ω line
with ± 3 V video signals.
The AD8021 is not only technically superior, but also priced
considerably less than comparable amps drawing much higher
quiescent current. The AD8021 is a high speed, general-purpose
amplifier, ideal for a wide variety of gain configurations, and can
be used throughout a signal processing chain and in control loops.
The AD8021 is available in both standard 8-lead SOIC and MSOP
packages in the industrial temperature range of –40°C to +85°C.
24
VOUT = 50mV p-p
21
PRODUCT DESCRIPTION
G = –10, RF = 1k, RG = 100,
RIN = 100, C C = 0pF
18
CLOSED-LOOP GAIN – dB
The AD8021 is a very high performance, high speed voltage
feedback amplifier that can be used in 16-bit resolution systems.
It is designed to have low voltage and current noise (2.1 nV/√Hz
typ and 2.1 pA/√Hz typ) while operating at the lowest quiescent
supply current (7 mA @ ± 5 V) among today’s high speed, low
noise op amps. The AD8021 operates over a wide range of
supply voltages from ± 2.5 V to ± 12 V, as well as from single
5 V supplies, making it ideal for high speed, low power instruments. An output disable pin allows further reduction of the
quiescent supply current to 1.3 mA.
15
G = –5, RF = 1k, RG = 200,
RIN = 66.5, C C = 1.5pF
12
9
6
G = –2, RF = 499, RG = 249,
RIN = 63.4, C C = 4pF
3
0
G = –1, RF = 499, RG = 499,
RIN = 56.2, C C = 7pF
–3
–6
0.1M
1M
10M
FREQUENCY – Hz
100M
1G
Figure 1. Small Signal Frequency Response
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD8021–SPECIFICATIONS
VS = 5 V
(@ TA = 25C, VS = 5 V, RL = 1 k, Gain = +2, unless otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Slew Rate, 1 V Step
Settling Time to 0.01%
Overload Recovery (50%)
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2
HD3
f = 5 MHz
HD2
HD3
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Conditions
Min
G = +1, CC = 10 pF, VO = 0.05 V p-p
G = +2, CC = 7 pF, VO = 0.05 V p-p
G = +5, CC = 2 pF, VO = 0.05 V p-p
G = +10, CC = 0 pF, VO = 0.05 V p-p
G = +1, CC = 10 pF
G = +2, CC = 7 pF
G = +5, CC = 2 pF
G = +10, CC = 0 pF
VO = 1 V Step, RL = 500 Ω
355
160
150
110
95
120
250
380
AD8021AR/AD8021ARM
Typ
Max
490
205
185
150
120
150
300
420
23
MHz
MHz
MHz
MHz
V/µs
V/µs
V/µs
V/µs
ns
± 2.5 V Input Step, G = +2
50
ns
VO = 2 V p-p
VO = 2 V p-p
–93
–108
dBc
dBc
VO = 2 V p-p
VO = 2 V p-p
f = 50 kHz
f = 50 kHz
NTSC, RL = 150 Ω
–70
–80
2.1
2.1
0.03
dBc
dBc
nV/√Hz
pA/√Hz
%
NTSC, RL = 150 Ω
0.4
0.5
7.5
10
0.1
82
DISABLE Voltage—Off/On
Enabled Leakage Current
Disabled Leakage Current
POWER SUPPLY
Operating Range
Quiescent Current
+Power Supply Rejection Ratio
–Power Supply Rejection Ratio
1.0
10.5
0.5
mV
µV/°C
µA
nA/°C
±µA
dB
10
1
–4.1 to +4.6
MΩ
pF
V
–86
–98
dB
–3.5 to +3.2
–3.8 to +3.4
60
75
V
mA
mA
VO = 50 mV p-p/1 V p-p
15/120
pF
f = 10 MHz
VO = 0 V to 2 V, 50% Logic to 50% Output
VO = 0 V to 2 V, 50% Logic to 50% Output
–40
45
50
dB
ns
ns
VDISABLE – VLOGIC REFERENCE
Logic Ref = 0.4 V
DISABLE = 4.0 V
Logic Ref = 0.4 V
DISABLE = 0.4 V
1.75/1.90
70
2
30
33
V
µA
µA
µA
µA
VCM = ± 4 V
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Current
DISABLE CHARACTERISTICS
Off Isolation
Turn-On Time
Turn-Off Time
Degrees
86
INPUT CHARACTERISTICS
Input Resistance
Common-Mode Input Capacitance
Input Common-Mode Voltage Range
Capacitive Load Drive for 30% Overshoot
2.6
0.04
TMIN to TMAX
+Input or –Input
Open-Loop Gain
Common-Mode Rejection Ratio
Unit
± 2.25
Output Enabled
Output Disabled
VCC = +4 V to +6 V, VEE = –5 V
VCC = +5 V, VEE = –6 V to –4 V
–86
–86
±5
7.0
1.3
–95
–95
± 12.0
7.7
1.6
V
mA
mA
dB
dB
Specifications subject to change without notice.
–2–
REV. D
AD8021
VS = ⴞ12 V(@ T = 25ⴗC, R = 1 k⍀, Gain = +2, unless otherwise noted.)
A
L
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Slew Rate, 1 V Step
Settling Time to 0.01%
Overload Recovery (50%)
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2
HD3
f = 5 MHz
HD2
HD3
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Common-Mode Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Conditions
Min
G = +1, CC = 10 pF, VO = 0.05 V p-p
G = +2, CC = 7 pF, VO = 0.05 V p-p
G = +5, CC = 2 pF, VO = 0.05 V p-p
G = +10, CC = 0 pF, VO = 0.05 V p-p
G = +1, CC = 10 pF
G = +2, CC = 7 pF
G = +5, CC = 2 pF
G = +10, CC = 0 pF
VO = 1 V Step, RL = 500 Ω
± 6 V Input Step, G = +2
520
175
170
125
105
140
265
400
Disabled Leakage Current
POWER SUPPLY
Operating Range
Quiescent Current
+Power Supply Rejection Ratio
–Power Supply Rejection Ratio
MHz
MHz
MHz
MHz
V/µs
V/µs
V/µs
V/µs
ns
ns
VO = 2 V p-p
VO = 2 V p-p
–95
–116
dBc
dBc
VO = 2 V p-p
VO = 2 V p-p
f = 50 kHz
f = 50 kHz
NTSC, RL = 150 Ω
NTSC, RL = 150 Ω
–71
–83
2.1
2.1
0.03
0.04
dBc
dBc
nV/√Hz
pA/√Hz
%
Degrees
VCM = ± 10 V
84
–86
10
1
–11.1 to +11.6
–96
MΩ
pF
V
dB
–10.6 to +10.2
70
115
15/120
V
mA
mA
pF
–40
45
50
1.80/1.95
70
2
30
33
dB
ns
ns
V
µA
µA
µA
µA
–10.2 to +9.8
f = 10 MHz
VO = 0 V to 2 V, 50% Logic to 50% Output
VO = 0 V to 2 V, 50% Logic to 50% Output
VDISABLE – VLOGIC REFERENCE
Logic Ref = 0.4 V
DISABLE = 4.0 V
Logic Ref = 0.4 V
DISABLE= 0.4 V
± 2.25
Output Enabled
Output Disabled
VCC = +11 V to +13 V, VEE = –12 V
VCC = +12 V, VEE = –13 V to –11 V
–3–
2.6
0.4
0.2
8
10
0.1
88
TMIN to TMAX
+Input or –Input
Specifications subject to change without notice.
REV. D
Unit
560
220
200
165
130
170
340
460
21
90
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Current
Capacitive Load Drive for 30% Overshoot VO = 50 mV p-p/1 V p-p
DISABLE CHARACTERISTICS
Off Isolation
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off/On
Enabled Leakage Current
AD8021AR/AD8021ARM
Typ
Max
–86
–86
±5
7.8
1.7
–96
–100
1.0
11.3
0.5
mV
µV/°C
µA
nA/°C
±µA
dB
± 12.0 V
8.6
mA
2.0
mA
dB
dB
AD8021
VS = 5 V (@ T = 25C, R = 1 k, Gain = +2, unless otherwise noted.)
A
L
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Slew Rate, 1 V Step
Settling Time to 0.01%
Overload Recovery (50%)
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2
HD3
f = 5 MHz
HD2
HD3
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Common-Mode Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Current
Capacitive Load Drive for 30% Overshoot
DISABLE CHARACTERISTICS
Off Isolation
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off/On
Enabled Leakage Current
Disabled Leakage Current
POWER SUPPLY
Operating Range
Quiescent Current
+Power Supply Rejection Ratio
–Power Supply Rejection Ratio
AD8021AR/AD8021ARM
Min
Typ
Max
Conditions
G = +1, CC = 10 pF, VO = 0.05 V p-p
G = +2, CC = 7 pF, VO = 0.05 V p-p
G = +5, CC = 2 pF, VO = 0.05 V p-p
G = +10, CC = 0 pF, VO = 0.05 V p-p
G = +1, CC = 10 pF
G = +2, CC = 7 pF
G = +5, CC = 2 pF
G = +10, CC = 0 pF
VO = 1 V Step, RL = 500 Ω
0 V to 2.5 V Input Step, G = +2
270
155
135
95
80
110
210
290
Unit
305
190
165
130
110
140
280
390
28
40
MHz
MHz
MHz
MHz
V/µs
V/µs
V/µs
V/µs
ns
ns
VO = 2 V p-p
VO = 2 V p-p
–84
–91
dBc
dBc
VO = 2 V p-p
VO = 2 V p-p
f = 50 kHz
f = 50 kHz
–68
–81
2.1
2.1
dBc
dBc
nV/√Hz
pA/√Hz
2.6
72
0.4
0.8
7.5
10
0.1
76
–84
10
1
0.9 to 4.6
–98
MΩ
pF
V
dB
VO = 50 mV p-p/1 V p-p
1.10 to 3.60
30
50
10/120
V
mA
mA
pF
f = 10 MHz
VO = 0 V to 1 V, 50% Logic to 50% Output
VO = 0 V to 1 V, 50% Logic to 50% Output
VDISABLE – VLOGIC REFERENCE
Logic Ref = 0.4 V
DISABLE = 4.0 V
Logic Ref = 0.4 V
DISABLE = 0.4 V
–40
45
50
1.55/1.70
70
2
30
33
dB
ns
ns
V
µA
µA
µA
µA
TMIN to TMAX
+Input or –Input
1.5 V to 3.5 V
1.25 to 3.38
± 2.25
Output Enabled
Output Disabled
VCC = 4.5 V to 5.5 V, VEE = 0 V
VCC = +5 V, VEE = –0.5 V to +0.5 V
–74
–76
±5
6.7
1.2
–82
–84
1.0
10.3
0.5
mV
µV/°C
µA
nA/°C
±µA
dB
± 12.0 V
7.5
mA
1.5
mA
dB
dB
Specifications subject to change without notice.
–4–
REV. 0
AD8021
ABSOLUTE MAXIMUM RATINGS 1
2.0
MAXIMUM POWER DISSIPATION (mW)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V
Power Dissipation . . . . . . . . Observed Power Derating Curves
Input Voltage (Common-Mode) . . . . . . . . . . . . . . . ± VS ± 1 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ± 0.8 V
Differential Input Current . . . . . . . . . . . . . . . . . . . . . ± 10 mA
Output Short-Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observed Power Derating Curves
Storage Temperature . . . . . . . . . . . . . . . . . . –65∞C to +125∞C
Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C
Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300∞C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
The AD8021 inputs are protected by diodes. Current-limiting resistors are not
used in order to preserve the low noise. If a differential input exceeds ± 0.8 V, the
input current should be limited to ± 10 mA.
1.5
8-LEAD SOIC
1.0
8-LEAD MSOP
0.5
0.01
–55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85
AMBIENT TEMPERATURE (ⴗC)
Figure 2. Maximum Power Dissipation vs. Temperature*
*Specification is for device in free air:
8-Lead SOIC: ␪JA = 125∞C/W
8-Lead MSOP: ␪JA = 145∞C/W
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8021
is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices
is determined by the glass transition temperature of the plastic,
approximately 150∞C. Temporarily exceeding this limit may cause
a shift in parametric performance due to a change in the stresses
exerted on the die by the package. Exceeding a junction temperature of 175∞C for an extended period can result in device failure.
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic
1
2
3
4
5
While the AD8021 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction temperature (150∞C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum power
derating curves.
6
7
8
PIN CONFIGURATION
LOGIC
REFERENCE
1
AD8021
8
DISABLE
–IN
2
7
+VS
+IN
3
6
VOUT
–VS
4
5
CCOMP
Function
LOGIC REFERENCE Reference for Pin 8* Voltage
Level. Connect to logic low
supply.
–IN
Inverting Input
+IN
Noninverting Input
Negative Supply Voltage
–VS
Compensation Capacitor. Tie
CCOMP
to –VS. (See the Applications
section for value.)
Output
VOUT
Positive Supply Voltage
+VS
DISABLE
Disable, Active Low*
*When Pin 8 (DISABLE) is about 2 V or more higher than Pin 1 (LOGIC
REFERENCE), the part is enabled. When Pin 8 is brought down to within about
1.5 V of Pin 1, the part is disabled. (See the Specification tables for exact disable and
enable voltage levels.) If the disable feature is not going to be used, Pin 8 can be tied
to +VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alternatively, if Pin 1 and Pin 8 are not connected, the part will be in an enabled state.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Outline
Branding
AD8021AR
AD8021AR-REEL
AD8021AR-REEL7
AD8021ARM
AD8021ARM-REEL
AD8021ARM-REEL7
AD8021ARZ*
AD8021ARZ-REEL*
AD8021ARZ-REEL7*
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
HNA
HNA
HNA
*Z = Lead Free
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8021 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. D
–5–
AD8021–Typical Performance Characteristics
(TA = 25⬚C, VS = 5 V, RL = 1 k, G = +2, RF = RG = 499 , RS = 49.9 , RO = 976 , RD = 53.6 , CC = 7 pF, CL = 0, CF = 0, VOUT = 2 V p-p,
Freq = 1 MHz, unless otherwise noted.)
24
9
G=2
G = 10, RF = 1k, RG = 110, C C = 0pF
21
18
G = 5, RF = 1k, RG = 249, C C = 2pF
15
6
12
9
G = 2, RF = RG = 499, C C = 7pF
6
3
5
4
12V
3
2
G = 1, RF = 75, C C = 10pF
0
VS = 2.5V
1
–3
0
–6
0.1M
1M
10M
FREQUENCY – Hz
100M
–1
1M
1G
24
3
21
2
G = –1
G = –10, RF = 1k, RG = 100,
RIN = 100, C C = 0pF
18
VS = 2.5V
5V
1
0
15
G = –5, RF = 1k, RG = 200,
RIN = 66.5, C C = 1.5pF
12
GAIN – dB
GAIN – dB
1G
10M
100M
FREQUENCY – Hz
TPC 4. Small Signal Frequency Response vs.
Frequency and Supply, VOUT = 50 mV p-p,
Noninverting. See Test Circuit 1.
TPC 1. Small Signal Frequency Response vs.
Frequency and Gain, VOUT = 50 mV p-p,
Noninverting. See Test Circuit 1.
9
6
G = –2, RF = 499, RG = 249,
RIN = 63.4, C C = 4pF
3
0
–6
0.1M
1M
10M
FREQUENCY – Hz
VS = 12V
–1
–2
–3
–4
–5
G = –1, RF = 499, RG = 499,
RIN = 56.2, C C = 7pF
–3
VS = 2.5V
–6
100M
–7
1M
1G
10M
100M
FREQUENCY – Hz
1G
TPC 5. Small Signal Frequency Response vs.
Frequency and Supply, VOUT = 50 mV p-p,
Inverting. See Test Circuit 3.
TPC 2. Small Signal Frequency Response
vs. Frequency and Gain, VOUT = 50 mV p-p,
Inverting. See Test Circuit 1.
9
9
G=2
CC = 5pF
G=2
8
7
8
7
7pF
GAIN – dB
5
9pF
4
3
5
4
VOUT = 4V p-p
1V p-p
3
2
2
7pF
1
1
9pF
0
0
–1
0.1M
VOUT = 0.1V AND 50mV p-p
6
6
GAIN – dB
5V
7
GAIN – dB
CLOSED-LOOP GAIN – dB
VS = 2.5V
8
1M
10M
FREQUENCY – Hz
100M
–1
1M
1G
10M
100M
FREQUENCY – Hz
1G
TPC 6. Frequency Response vs. Frequency
and VOUT, Noninverting. See Test Circuit 1.
TPC 3. Small Signal Frequency Response vs.
Frequency and Compensation Capacitor,
VOUT = 50 mV p-p. See Test Circuit 1.
–6–
REV. D
AD8021
10
10
G=2
9
8
8
7
7
6
6
GAIN – dB
GAIN – dB
9
5
1k
4
RF = 1k
G=2
RF = RG
RF = 499
RF = 250
5
4
3
RF = 150
3
RL = 100
2
2
1
RF = 75
1
0
0.1M
1M
10M
FREQUENCY – Hz
TPC 7. Large Signal Frequency Response vs.
Frequency and Load, Noninverting. See Test
Circuit 2.
1M
10M
FREQUENCY – Hz
100M
1G
TPC 10. Small Signal Frequency Response vs.
Frequency and RF, Noninverting, VOUT = 50 mV p-p.
See Test Circuit 1.
9
15
+85C
G=2
RF = 1k AND CF = 2.2pF
0
0.1M
1G
100M
G=2
8
12
+25C
7
9
6
–40C
5
+85C
4
VOUT =
50mV p-p
GAIN – dB
VOUT =
2V p-p
3
2
–3
RS = 100
–6
–9
–40C
0
–1
1M
RS = 249
–12
–15
0.1M
1G
10M
100M
FREQUENCY – Hz
TPC 8. Frequency Response vs. Frequency,
Temperature and VOUT, Noninverting.
See Test Circuit 1.
1M
10M
FREQUENCY – Hz
100M
1G
TPC 11. Small Signal Frequency Response vs.
Frequency and RS, Noninverting, VOUT = 50 mV p-p.
See Test Circuit 1.
100
18
G=2
50pF
15
90
30pF
80
12
OPEN-LOOP GAIN – dB
20pF
9
10pF
GAIN – dB
RS = 49.9
0
+25C
1
6
3
0pF
0
70
180
60
135
50
90
40
45
30
0
–6
20
–45
–9
10
–90
–3
–12
1M
10M
100M
FREQUENCY – Hz
0
10k
1G
TPC 9. Small Signal Frequency Response vs.
Frequency and Capacitive Load, Noninverting,
VOUT = 50 mV p-p. See Test Circuit 2 and Figure 16.
REV. D
3
100k
1M
10M
FREQUENCY – Hz
100M
TPC 12. Open-Loop Gain and Phase vs.
Frequency, RG =100 Ω, RF = 1 kΩ, RO = 976 Ω,
RD = 53.6 Ω, CC = 0 pF. See Test Circuit 3.
–7–
–135
1G
PHASE – Degrees
GAIN – dB
6
AD8021
–20
6.4
G=2
–30
6.2
–40
VS = 2.5V
f1
POUT – dBm
GAIN – dB
–50
6.0
5V
5.8
12V
f2
f = 0.2MHz
POUT
–60
976
–70
53.6
50
–80
–90
5.6
–100
–110
5.4
1M
10M
FREQUENCY – Hz
–120
9.5
100M
TPC 13. 0.1 dB Flatness vs. Frequency and
Supply, VOUT = 1 V p-p, RL = 150 Ω, Noninverting.
See Test Circuit 2.
9.7
10.3
10.0
FREQUENCY – MHz
10.5
TPC 16. Intermodulation Distortion vs. Frequency
–20
50
–30
SECOND
–50
DISTORTION – dBc
THIRD-ORDER INTERCEPT – dBm
–40
–60
–70
RL = 100
–80
RL = 1k
–90
–100
–110
–120
45
40
VS = 5V
35
VS = 2.5V
30
25
THIRD
–130
0.1M
1M
FREQUENCY – Hz
10M
20
20M
5
0
TPC 14. Second and Third Harmonic Distortion
vs. Frequency and RL
10
FREQUENCY – MHz
15
20
TPC 17. Third-Order Intercept vs. Frequency and
Supply Voltage
–30
–50
–40
–60
–70
–60
–70
DISTORTION – dBc
DISTORTION – dBc
–50
THIRD
VS = 2.5V
–80
SECOND
–90
–100
SECOND
–120
SECOND
–130
100k
–80
RL = 100
THIRD
–90
SECOND
–100
VS = 5V
–110
SECOND
THIRD
VS = 12V
1M
FREQUENCY – Hz
RL = 1k
–110
THIRD
10M
–120
20M
1
TPC 15. Second and Third Harmonic Distortion
vs. Frequency and VS
2
4
3
VOUT – V p-p
5
6
TPC 18. Second and Third Harmonic Distortion
vs. VOUT and RL
REV. D
–8–
AD8021
–60
3.4
–70
fC = 5MHz
–80
THIRD
–90
SECOND
fC = 1MHz
–100
–3.2
POSITIVE OUTPUT
POSITIVE OUTPUT VOLTAGE – V
SECOND
DISTORTION – dBc
–3.1
3.5
–110
3.3
–3.3
3.2
–3.4
3.1
–3.5
3.0
–3.6
2.9
–120
1
3
4
VOUT – V p-p
2
5
0
1600
120
–40
SHORT-CIRCUIT CURRENT – mA
–50
fC = 5MHz
–60
DISTORTION – dBc
800
1200
LOAD – 400
TPC 22. DC Output Voltage vs. Load. See Test
Circuit 1.
TPC 19. Second and Third Harmonic Distortion
vs. VOUT and Fundamental Frequency (fC), G = +2
SECOND
–70
THIRD
–80
SECOND
–90
fC = 1MHz
THIRD
–100
1
2
3
4
VOUT – V p-p
5
100
VS = 12
80
VS = 5.0
60
VS = 2.5
40
20
0
–50
–110
6
–30
–10
10
30
50
TEMPERATURE – C
70
90
110
TPC 23. Short-Circuit Current to Ground vs.
Temperature
TPC 20. Second and Third Harmonic Distortion
vs. VOUT and Fundamental Frequency (fC), G = +10
50
–70
G=2
fC = 1MHz
40
RL = 1k
RL = 1k, 150
30
–80
20
–90
VOUT – mV
DISTORTION – dBc
–3.8
2000
2.8
6
–3.7
NEGATIVE OUTPUT
THIRD
SECOND
–100
10
–10
–20
THIRD
–30
–110
–40
–50
–120
0
200
400
600
FEEDBACK RESISTANCE – 800
0
1000
TPC 21. Second and Third Harmonic Distortion
vs. Feedback Resistor (RF)
REV. D
40
80
120
TIME – ns
160
200
TPC 24. Small Signal Transient Response vs. RL,
VO = 50 mV p-p. See Test Circuit 2, Noninverting.
–9–
NEGATIVE OUTPUT VOLTAGE – V
–50
AD8021
VO = 4V p-p
G=2
2.0
VO = 2V p-p
G=2
2.0
RL = 1k
1.0
VOUT – V
VOUT – V
1.0
RL = 150
–1.0
VS = 2.5V
–1.0
VS = 5V
–2.0
–2.0
0
40
80
120
TIME – ns
160
0
200
80
120
TIME – ns
160
200
TPC 28. Large Signal Transient Response vs. VS.
See Test Circuit 1.
TPC 25. Large Signal Transient Response vs. RL.
See Test Circuit 2, Noninverting.
5
VIN = 3V
G = +2
VIN = 1V/DIV
VOUT = 2V/DIV
VO = 4V p-p
G = –1
4
40
3
VOUT, RL = 1k
VIN
2
RL = 150
VOLTS
1
–1
VOUT
–2
–3
–4
VIN
–5
0
50
100
150
TIME – ns
200
0
250
CL = 50pF
G=2
200
300
TIME – ns
400
500
TPC 29. Overdrive Recovery vs. RL. See Test Circuit 2.
TPC 26. Large Signal Transient Response.
See Test Circuit 3, Inverting.
2.0
100
VO = 4V p-p
G=2
CL = 10pF, 0pF
VOUT – V
OUTPUT SETTLING
1.0
–1.0
+0.01%
–0.01%
25ns
–2.0
VERT = 0.2mV/DIV
0
40
80
120
TIME – ns
160
HOR = 5ns/DIV
200
TPC 30. 0.01% Settling Time, 2 V Step
TPC 27. Large Signal Transient Response vs. CL.
See Test Circuit 1.
REV. D
–10–
AD8021
100
100
INPUT CURRENT NOISE – pA/ Hz
80
60
SETTLING – V
40
PULSEWIDTH = 120ns
20
0
–20
PULSEWIDTH = 300s
–40
–60
5V
–80
0V
10
t1
–100
0
4
8
12
16
20
24
28
1
10
32
100
TIME – s
TPC 31. Long-Term Settling, 0 V to 5 V, VS = ± 12 V, G = +13
10k
100k
FREQUENCY – Hz
1M
10M
TPC 34. Input Current Noise vs. Frequency
50
0.48
G = 1
40
0.44
VOLTAGE OFFSET – mV
30
20
VOUT – mV
1k
10
–10
–20
–30
0.40
0.36
0.32
0.28
–40
–50
0
40
80
120
TIME – ns
160
0.24
–50
200
TPC 32. Small Signal Transient Response,
VO = 50 mV p-p. G = +1. See Test Circuit 1.
–25
0
25
50
TEMPERATURE – C
75
100
75
100
TPC 35. VOS vs. Temperature
100
8.4
INPUT BIAS CURRENT – A
VOLTAGE NOISE – nV/ Hz
8.0
10
2.1nV/ Hz
7.6
7.2
6.8
6.4
1
10
100
1k
10k
100k
FREQUENCY – Hz
1M
6.0
–50
10M
TPC 33. Input Voltage Noise vs. Frequency
REV. D
–25
25
50
0
TEMPERATURE – C
TPC 36. Input Bias Current vs. Temperature
–11–
AD8021
0
–30
–10
–40
–20
DISABLED ISOLATION – dB
–20
CMRR – dB
–50
–60
–70
–80
–90
–30
–40
–50
–60
–70
–100
–80
–110
–90
–120
10k
100k
1M
FREQUENCY – Hz
10M
–100
0.1M
100M
300
300k
100
100k
30
30k
10
3
1
0.3
0.1
3k
1k
300
100
30
0.01
10
1M
10M
FREQUENCY – Hz
100k
100M
1G
100M
10k
0.03
0.003
10k
10M
FREQUENCY – Hz
TPC 40. Input to Output Isolation, Chip Disabled.
See Test Circuit 7.
OUTPUT IMPEDANCE – OUTPUT IMPEDANCE – TPC 37. CMRR vs. Frequency. See Test Circuit 4.
1M
3
10k
1G
TPC 38. Output Impedance vs. Frequency, Chip
Enabled. See Test Circuit 5.
100k
1M
10M
FREQUENCY – Hz
1G
100M
TPC 41. Output Impedance vs. Frequency, Chip
Disabled. See Test Circuit 8.
0
DISABLE
4V
–10
2V
–20
–PSRR
PSRR – dB
–30
VOUTPUT
2V
tEN = 45ns
1V
–40
–50
VS = 2.5V
+PSRR
VS = 12V
–60
–70
tDIS = 50ns
VS = 5V
–80
–90
0
100
200
300
TIME – ns
400
–100
10k
500
TPC 39. Enable (tEN)/Disable (tDIS) Time vs. VOUT.
See Test Circuit 6.
100k
1M
10M
FREQUENCY – Hz
100M
500M
TPC 42. PSRR vs. Frequency and Supply Voltage.
See Test Circuits 9 and 10.
REV. D
–12–
AD8021
8.5
SUPPLY CURRENT – mA
8.0
7.5
7.0
6.5
6.0
5.5
–50
–25
0
25
50
TEMPERATURE – C
100
75
TPC 43. Quiescent Supply Current vs. Temperature
Test Circuits
HP8753D
NETWORK
ANALYZER
50
50 CABLE
50
AD8021
+VS
RS
50 CABLE
RO
50
+VS
499
499
5
RIN
49.9
CC
5
CC
RD
–VS
49.9
–VS
7pF
RF
RG
499
55.6
499
CF
Test Circuit 1. Noninverting Gain
+VS
50 CABLE
Test Circuit 4. CMRR
FET
PROBE
AD8021
HP8753D
+VS
NETWORK
ANALYZER
RS
50
5
RIN
49.9
100
5
CL
50
CC
RL
–VS
7pF
–VS
CC
RF
RG
RG
499
RF
499
CF
Test Circuit 2. Noninverting Gain with FET Probe
Test Circuit 5. Output Impedance, Chip Enabled
AD8021
+VS
RO
49.9
50
8 DISABLE
RIN
49.9
RG
4V
REV. D
5
CC
49.9
–VS
RF
499
Test Circuit 3. Inverting Gain
976
LOGIC REF
RD
–VS
50 CABLE
1
49.9
1.0V
5
CC
+VS
49.9
50 CABLE
7pF
499
Test Circuit 6. Enable/Disable
–13–
53.6
AD8021
BIAS
BNC
HP8753D
NETWORK
ANALYZER
HP8753D
NETWORK
ANALYZER
50
50
50
50
+VS
50 CABLE
50 CABLE
+VS
49.9
AD8021
1
49.9
LOGIC REF
8 DISABLE
–VS
499
+VS
FET
PROBE
49.9, 5W
976
249
5
5
1k
CC
7pF
–VS
CC
7pF
499
499
499
Test Circuit 7. Input to Output Isolation, Chip Disabled
53.6
Test Circuit 9. Positive PSRR
BIAS
BNC
HP8753D
NETWORK
ANALYZER
50
50
–VS
50 CABLE
+VS
976
249
AD8021
5
HP8753D
1
8
NETWORK
ANALYZER
+VS
100
5
–VS
53.6
CC
7pF
49.9
5W
50
CC
7pF
499
499
–VS
Test Circuit 8. Output Impedance, Chip Disabled
Test Circuit 10. Negative PSRR
REV. D
–14–
AD8021
The typical voltage feedback op amp is frequency stabilized with
a fixed internal capacitor, CINTERNAL, using dominant pole compensation. To a first-order approximation, voltage feedback op amps
have a fixed gain bandwidth product. For example, if its –3 dB
bandwidth for G = +1 is 200 MHz, at a gain of G = +10 its
bandwidth will be only about 20 MHz. The AD8021 is a voltage
feedback op amp with a minimal CINTERNAL of about 1.5 pF. By
adding an external compensation capacitor, CC, the user can
circumvent the fixed gain bandwidth limitation of other voltage
feedback op amps.
bandwidth is degraded to about 20 MHz and the phase margin
increases to 90° (Arrow B). However, by reducing CC to zero,
the bandwidth and phase margin return to about 200 MHz and
60° (Arrow C), respectively. In addition, the slew rate is dramatically increased, as it roughly varies with the inverse of CC.
10
9
COMPENSATION CAPACITANCE – pF
APPLICATIONS
Unlike the typical op amp with fixed compensation, the AD8021
allows the user to
1.
Maximize the amplifier bandwidth for closed-loop gains
between 1 and 10, avoiding the usual loss of bandwidth
and slew rate.
Optimize the trade-off between bandwidth and phase
margin for a particular application.
3.
Match bandwidth in gain blocks with different noise gains,
such as when designing differential amplifiers (as shown in
Figure 10).
110
180
100
135
70
CC = 0pF (B)
(A)
(C)
0
CC = 10pF
50
40
(C)
30
5
4
3
2
1
2
3
5
6
7
NOISE GAIN – V/V
8
9
10
11
Table I and Figure 4 provide recommended values of compensation capacitance at various gains and the corresponding slew rate,
bandwidth, and noise. Note that the value of the compensation
capacitor depends on the circuit noise gain, not the voltage gain.
As shown in Figure 5, the noise gain, GN, of an op amp gain block
is equal to its noninverting voltage gain, regardless of whether
it is actually used for inverting or noninverting gain. Thus,
Noninverting GN = RF / RG + 1
Inverting GN = RF / RG + 1
20
(B)
10
4
Figure 4. Suggested Compensation Capacitance
vs. Gain for Maintaining 1 dB Peaking
45
60
6
0
90
90
86
80
7
1
PHASE – Degrees
OPEN-LOOP GAIN – dB
2.
8
0
(A)
–10
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
1G
10G
1
RS
RG
200
3
–
5
2 –
–VS
Figure 3 is the AD8021 gain and phase plot that has been simplified for instructional purposes. If the desired closed-loop gain
is G = +1 and CC = 10 pF is chosen, Arrow A of the figure
shows that the bandwidth is about 200 MHz and the phase
margin is about 60°. If the gain is changed to G = +10 and CC
is fixed at 10 pF, then (as expected for a typical op amp) the
2
6
AD8021
Figure 3. Simplified Diagram of Open-Loop Gain
and Phase Response
RF
800
+
RF
800
5
3 +
–VS
CCOMP
G = GN = 5
6
AD8021
G = –4
GN = 5
CCOMP
RG
200
NONINVERTING
INVERTING
Figure 5. The Noise Gain of Both Is 5
Table I. Recommended Component Values. See Test Circuit 2. C F = CL = 0, RL = 1 k, RIN = 49.9 Noise Gain
(Noninverting
Gain)
RS
()
RF
()
RG
()
CCOMP
(pF)
Slew
Rate
(V/s)
2
5
10
20
75
49.9
49.9
49.9
49.9
75
499
1k
1k
1k
NA
499
249
110
52.3
10
7
2
0
0
120
150
300
420
200
100
49.9
1k
10
0
34
1
REV. D
–15–
–3 dB
SS BW
(MHz)
Output Noise
(AD8021 Only)
(nV/√Hz)
Output Noise
(AD8021 with Resistors)
(nV/√Hz)
490
205
185
150
42
2.1
4.3
10.7
21.2
42.2
2.8
8.2
15.5
27.9
52.7
6
211.1
264.1
AD8021
With the AD8021, a variety of trade-offs can be made to fine-tune
its dynamic performance. Sometimes more bandwidth or slew
rate is needed at a particular gain. Reducing the compensation
capacitance, as illustrated in TPC 3, will increase the bandwidth
and peaking due to a decrease in phase margin. On the other hand,
if more stability is needed, increasing the compensation cap will
decrease the bandwidth while increasing the phase margin.
this high impedance with a current gain of 5,000, so that the
AD8021 can maintain a high open-loop gain even when driving
heavy loads.
Two internal diode clamps across the inputs (Pins 2 and 3) protect
the input transistors from large voltages that could otherwise cause
emitter-base breakdown, which would result in degradation of
offset voltage and input bias current.
As with all high speed amplifiers, parasitic capacitance and inductance around the amplifier can affect its dynamic response.
Often, the input capacitance (due to the op amp itself, as well
as the PC board) could have a significant effect. The feedback
resistance, together with the input capacitance, may contribute to
a loss of phase margin, thereby affecting the high frequency response,
as shown in TPC 10. Furthermore, a capacitor (CF) in parallel
with the feedback resistor can compensate for this phase loss.
+VS
OUTPUT
+IN
Additionally, any resistance in series with the source will create
a pole with the input capacitance (as well as dampen high frequency resonance due to package and board inductance and
capacitance), the effect of which is shown in TPC 11.
CINTERNAL
1.5pF
–IN
–VS
It must also be noted that increasing resistor values will increase
the overall noise of the amplifier, and that reducing the feedback
resistor value will increase the load on the output stage, thus
increasing distortion (TPC 18).
CCOMP
CC
Figure 6. Simplified Schematic
Using the Disable Feature
When Pin 8 (DISABLE) is approximately 2 V or more higher than
Pin 1 (LOGIC REFERENCE), the part is enabled. When Pin 8
is brought down to within about 1.5 V of Pin 1, the part is disabled. See the Specification tables for exact disable and enable
voltage levels. If the disable feature is not going to be used, Pin 8
can be tied to VS or a logic high source, and Pin 1 can be tied to
ground or logic low. Alternatively, if Pin 1 and Pin 8 are not
connected, the part will be in an enabled state.
THEORY OF OPERATION
The AD8021 is fabricated on the second generation of Analog
Devices’ proprietary High Voltage eXtra-Fast Complementary
Bipolar (XFCB) process, which enables the construction of PNP
and NPN transistors with similar fTs in the 3 GHz region. The
transistors are dielectrically isolated from the substrate (and each
other), eliminating the parasitic and latch-up problems caused
by junction isolation. It also reduces nonlinear capacitance
(a source of distortion) and allows a higher transistor fT for a
given quiescent current. The supply current is trimmed, which
results in less part-to-part variation of bandwidth, slew rate,
distortion, and settling time.
As shown in Figure 6, the AD8021 input stage consists of an NPN
differential pair in which each transistor operates at 0.8 mA collector current. This allows the input devices a high transconductance;
thus, the AD8021 has a low input noise of 2.1 nV/√Hz @ 50 kHz.
The input stage drives a folded cascode that consists of a pair of
PNP transistors. The folded cascode and current mirror provide
a differential to single-ended conversion of signal current. This
current then drives the high impedance node (Pin 5), where the
CC external capacitor is connected. The output stage preserves
PCB LAYOUT CONSIDERATIONS
As with all high speed op amps, achieving optimum performance
from the AD8021 requires careful attention to PC board layout.
Particular care must be exercised to minimize lead lengths
between the ground leads of the bypass capacitors and between
the compensation capacitor and the negative supply. Otherwise,
lead inductance can influence the frequency response and even
cause high frequency oscillations. Use of a multilayer printed
circuit board, with an internal ground plane, will reduce ground
noise and enable a compact component arrangement.
Due to the relatively high impedance of Pin 5 and low values of
the compensation capacitor, a guard ring is recommended. The
guard ring is simply a PC trace that encircles Pin 5 and is
connected to the output, Pin 6, which is at the same potential as
Pin 5. This serves two functions. It shields Pin 5 from any local
circuit noise generated by surrounding circuitry. It also minimizes stray capacitance, which would tend to otherwise reduce
the bandwidth. An example of a guard ring layout may be seen
in Figure 7.
Also shown in Figure 7, the compensation capacitor is located
immediately adjacent to the edge of the AD8021 package, spanning
Pin 4 and Pin 5. This capacitor must be a high quality surfacemount COG or NPO ceramic. The use of leaded capacitors is not
recommended. The high frequency bypass capacitor(s) should
be located immediately adjacent to the supplies, Pins 4 and 7.
To achieve the shortest possible lead length at the inverting
input, the feedback resistor RF is located beneath the board and
just spans the distance from the output, Pin 6, to inverting input
Pin 2. The return node of resistor RG should be situated as
closely as possible to the return node of the negative supply
bypass capacitor connected to Pin 4.
REV. D
–16–
AD8021
Table II. Summary of ADC Driver Performance,
fC = 65 kHz, VOUT = 10 V p-p
(TOP VIEW)
LOGIC REFERENCE
1
8
–IN
2
+VS 7
+IN
3
6
BYPASS
CAPACITOR
DISABLE
VOUT
GROUND
PLANE
–VS
4
5
CCOMP
Parameter
Measurement
Unit
Second Harmonic Distortion
Third Harmonic Distortion
THD
SFDR
–101.3
–109.5
–100.0
100.3
dB
dB
dB
dB
METAL
+12V
50
COMPENSATION
CAPACITOR
GROUND
PLANE
5
–
RG
82.5
DRIVING 16-BIT ADCS
Low noise and adjustable compensation make the AD8021
especially suitable as a buffer/driver for high resolution analogto-digital converters.
Figure 8 shows a typical ADC driver configuration. The AD8021
is in an inverting gain of –7.5, fC is 65 kHz, and its output voltage
is 10 V p-p. The results are listed in Table II.
+12V
65kHz
5
–
570kSPS
ADC
OPTIONAL CF
IN
LO
Table III. Summary of ADC Driver Performance,
fC = 100 kHz, VOUT = 20 V p-p
Parameter
Measurement
Unit
Second Harmonic Distortion
Third Harmonic Distortion
THD
SFDR
–92.6
–86.4
–84.4
5.4
dB
dB
dB
dB
Figure 9 shows another ADC driver connection. The circuit was
tested with a noninverting gain of 10.1 and an output voltage of
approximately 20 V p-p for optimum resolution and noise performance. No filtering was used. An FFT was performed using
Analog Devices’ evaluation software for the AD7665 16-bit
converter. The results are listed in Table III.
DIFFERENTIAL DRIVER
HI
CC
10pF
AD7665
–12V
570kSPS
RF
1.5k
56pF
AD7665
RF
750
IN
16 BITS
2
50
6
AD8021
590
RG
200
5V
+
HI
Figure 9. Noninverting ADC Driver, Gain = 10, fC = 100 kHz
As seen in TPC 15, the harmonic distortion is better than 90 dB at
frequencies between 100 kHz and 1 MHz. This is a real advantage
for complex waveforms that contain high frequency information,
as the phase and gain integrity of the sampled waveform can be
preserved throughout the conversion process. The increase in
loop gain results in improved output regulation and lower noise
when the converter input changes state during a sample. This
advantage is particularly apparent when using 16-bit high resolution ADCs with high sampling rates.
3
IN
CC
–12V
Figure 7. Recommended Location of Critical
Components and Guard Ring
6
AD8021
50
2
IN
LO
Figure 8. Inverting ADC Driver, Gain = –7.5, fC = 65 kHz
REV. D
5V
50 3
+
16 BITS
BYPASS
CAPACITOR
The AD8021 is uniquely suited as a low noise differential driver
for many ADCs, balanced lines, and other applications requiring
differential drive. If pairs of internally compensated op amps are
configured as inverter and follower, the noise gain of the inverter
will be higher than that of the follower section, resulting in an
imbalance in the frequency response (see Figure 11).
A better solution takes advantage of the external compensation
feature of the AD8021. By reducing the CCOMP value of the inverter,
its bandwidth may be increased to match that of the follower,
avoiding compromises in gain bandwidth and phase delay. The
inverting and noninverting bandwidths can be closely matched
using the compensation feature, thus minimizing distortion.
–17–
AD8021
Figure 10 illustrates an inverter-follower driver circuit operating
at a gain of 2, using individually compensated AD8021s. The
values of feedback and load resistors were selected to provide a
total load of less than 1 kΩ, and the equivalent resistances seen
at each op amp’s inputs were matched to minimize offset voltage and drift. Figure 12 is a plot of the resulting ac responses of
driver halves.
VIN
249
G = +2
3 +
6
AD8021
49.9
2
5
–
–VS
Figure 13 shows the schematic of a 2-pole, low-pass active filter,
and Table IV lists typical component values for filters having a
Bessel-type response with gains of 2 and 5. Figure 14 is a network
analyzer plot of this filter’s performance.
VOUT1
1k
232
G = –2
3 +
6
AD8021
2
332
VOUT2
5
C1
1k
–
–VS
The low noise and high gain bandwidth of the AD8021 make it an
excellent choice in active filter circuits. Most active filter literature provides resistor and capacitor values for various filters but
neglects the effect of the op amp’s finite bandwidth on filter
performance; ideal filter response with infinite loop gain is implied.
Unfortunately, real filters do not behave in this manner. Instead,
they exhibit finite limits of attenuation, depending on the gain
bandwidth of the active device. Good low-pass filter performance
requires an op amp with high gain bandwidth for attenuation at
high frequencies, and low noise and high dc gain for low frequency,
pass-band performance.
7pF
499
499
USING THE AD8021 IN ACTIVE FILTERS
+VS
5pF
VIN
664
R1
R2
AD8021
3
6
2
C2
Figure 10. Differential Amplifier
VOUT
5
CC
–VS
12
RF
RG
9
6
Figure 13. Schematic of a Second-Order Low-Pass
Active Filter
3
G = –2
GAIN – dB
0
G = +2
Table IV. Typical Component Values for Second-Order
Low-Pass Filter of Figure 13
–3
–6
–9
–12
–15
–18
100k
1M
10M
100M
Gain R1 () R2 () RF () RS () C1
C2
CC
2
5
10 nF
10 nF
7 pF
2 pF
71.5
44.2
1G
499
365
10 nF
10 nF
40
Figure 11. AC Response of Two Identically
Compensated High Speed Op Amps Configured
for Gains of +2 and –2
30
G=5
GAIN – dB
20
12
9
6
10
0
G=2
–10
–20
3
GAIN – dB
499
90.9
50
FREQUENCY – Hz
G = 2
–30
0
–40
–3
–50
1k
–6
–9
10k
100k
FREQUENCY – Hz
1M
10M
Figure 14. Frequency Response of the Filter Circuit
of Figure 13 for Two Different Gains
–12
–15
–18
100k
215
365
1M
10M
FREQUENCY – Hz
100M
1G
Figure12. AC Response of Two Dissimilarly
Compensated AD8021 Op Amps (Figure 11) Configured
for Gains of +2 and –2. Note the Close Gain Match.
REV. D
–18–
AD8021
Driving Capacitive Loads
20
18
FET
PROBE
5 RSNUB
+VS
16
14
49.9
49.9
GAIN – dB
12
6
–VS
10
499
33pF
CC = 8pF;
RSNUB = 0
CC
499
8
6
4
2
CC = 8pF;
RSNUB = 17.4
0
0.1
1.0
10
FREQUENCY – MHz
100
1000
Figure 15. Peaking vs. RSNUB and CC for CL = 33 pF
REV. D
16
14
12
10
8
6
4
2
0
0
5
10
15
20
25
30
35
CAPACITIVE LOAD – pF
40
45
50
Figure 16. Relationship of RSNUB vs. CL for 2 dB
Peaking at a Gain of +2
CC = 7pF;
RSNUB = 0
RL
1k
18
RSNUB – When the AD8021 drives a capacitive load, the high frequency
response may show excessive peaking before it rolls off. Two
techniques can be used to improve stability at high frequency and
reduce peaking. The first technique is to increase the compensation capacitor, CC, which reduces the peaking while maintaining
gain flatness at low frequencies. The second technique is to add a
resistor, RSNUB, in series between the output pin of the AD8021
and the capacitive load, CL. Figure 15 shows the response of the
AD8021 when both CC and RSNUB are used to reduce peaking.
For a given CL, Figure 16 can be used to determine the value of
RSNUB that maintains 2 dB of peaking in the frequency response.
Note, however, that using RSNUB attenuates the low frequency
output by a factor of RLOAD/(RSNUB + RLOAD).
–19–
AD8021
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
(R-8)
Dimensions shown in millimeters and (inches)
4.00 (0.1574)
3.80 (0.1497)
8
5
1
4
6.20 (0.2440)
5.80 (0.2284)
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
0.50 (0.0196)
45
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
SEATING
0.10
PLANE
C01888–0–10/03(D)
5.00 (0.1968)
4.80 (0.1890)
8
0.25 (0.0098) 0 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4.90
BSC
3.00
BSC
1
4
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.23
0.08
8
0
0.80
0.60
0.40
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Revision History
Location
Page
10/03—Data Sheet changed from REV. C to REV. D.
Edits to SPECIFICATIONS heading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7/03—Data Sheet changed from REV. B to REV. C.
Deleted all references to evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Replaced Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/03—Data Sheet changed from REV. A to REV. B.
Edits to Evaluation Board Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Edits to Figure 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6/02—Data Sheet changed from REV. 0 to REV. A.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
–20–
REV. D