AD ADF7020BCP High performance ism band fsk/ask transceiver ic Datasheet

High Performance ISM Band
FSK/ASK Transceiver IC
ADF7020
Preliminary Technical Data
On-chip VCO and fractional-N PLL
On-chip 7-bit ADC and temperature sensor
±1 ppm RF output frequency accuracy possible from
low cost 100 ppm crystal
Digital RSSI
Leakage current <1 µA in power-down mode
48-lead ultrasmall MLF package (chip scale)
FEATURES
Low power, low IF transceiver
Frequency bands:
433 MHz to 464 MHz
862 MHz to 928 MHz
Data rates supported:
0.3 kbps to 200 kbps, FSK
0.3 kbps to 64 kbps, ASK
2.3 V to 3.6 V power supply
Programmable output power:
−16 dBm to +13 dBm in 0.3 dBm steps
Receiver sensitivity:
−117.5 dBm at 1 kbps, FSK
−110.5 dBm at 9.6 kbps, FSK
−106.5 dBm at 9.6 kbps, ASK
Low power consumption:
19 mA in receive mode
22 mA in transmit mode (10 dBm output)
APPLICATIONS
Low cost wireless data transfer
Remote control/security systems
Wireless metering
Keyless entry
Home automation
Process and building control
Wireless voice
FUNCTIONAL BLOCK DIAGRAM
RLNA
RSET
VREG(1:4)
BIAS
LDO(1:4)
ADCIN
MUXOUT
TEMP
SENSOR
OFFSET
CORRECTION
TEST MUX
LNA
RFIN
MUX
RSSI
IF FILTER
RFINB
7-BIT ADC
FSK/ASK
DEMODULATOR
DATA
SYNCHRONIZER
GAIN
OFFSET
CORRECTION
CE
AGC
CONTROL
FSK MOD
CONTROL
PA OUT
DIVIDERS/
MUXING
Σ-∆
MODULATOR
GAUSSIAN
FILTER
DIV P
RxCLK
Tx/Rx
CONTROL
Tx/Rx DATA
CLKOUT
AFC
CONTROL
INT/LOCK
N/N+1
SLE
VCO
CP
SDATA IN
SDATA OUT
SCLK
PFD
DIV R
RING
OSC
OSC
VCOIN CPOUT
CLK
DIV
CLKOUT
01975-PrG-001
ASK/OOK
MOD CONTROL
GAUSSIAN FILTER
SERIAL
PORT
Figure 1.
Rev. PrH
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADF7020
Preliminary Technical Data
TABLE OF CONTENTS
General Description ......................................................................... 3
Device Programming after Initial Power-Up ......................... 22
Specifications..................................................................................... 4
Serial Interface ................................................................................ 24
Timing Characteristics..................................................................... 7
Readback Format........................................................................ 24
Absolute Maximum Ratings............................................................ 8
Register 0—N Register............................................................... 25
ESD Caution.................................................................................. 8
Register 1—Oscillator/Filter Register...................................... 26
Pin Configuration and Function Descriptions............................. 9
Register 2—Transmit Modulation Register (ASK/OOK
Mode)........................................................................................... 27
Frequency Synthesizer ................................................................... 11
Reference Input Section............................................................. 11
Register 2—Transmit Modulation Register (FSK Mode) ..... 28
Choosing Channels for Best System Performance................. 13
Register 2—Transmit Modulation Register (GFSK/GOOK
Mode)........................................................................................... 29
Transmitter ...................................................................................... 14
Register 3—Receiver Clock Register ....................................... 30
Modulation Schemes.................................................................. 14
Register 4—Demodulator Setup Register ............................... 31
Receiver Section.............................................................................. 16
Register 5—Sync Byte Register................................................. 32
RF Front End............................................................................... 16
Register 6—Correlator/Demodulator Register ...................... 33
RSSI/AGC Section...................................................................... 17
Register 7—Readback Setup Register...................................... 34
FSK Demodulators on the ADF7020 ....................................... 17
Register 8—Power-Down Test Register .................................. 35
FSK Correlator/Demodulator................................................... 17
Register 9—AGC Register......................................................... 36
Linear FSK Demodulator .......................................................... 19
Register 10—AGC 2 Register.................................................... 37
AFC Section ................................................................................ 19
Register 11—AFC Register ....................................................... 37
Automatic Sync Word Recognition.......................................... 20
Register 12—Test Register......................................................... 38
Applications Section....................................................................... 21
Register 13—Offset Removal and Signal Gain Register ....... 39
LNA/PA Matching...................................................................... 21
Outline Dimensions ....................................................................... 40
Transmit Protocol and Coding Considerations ..................... 22
Ordering Guide .......................................................................... 40
Image Rejection Calibration ..................................................... 22
REVISION HISTORY
Revision PrH: Preliminary Version
Rev. PrH | Page 2 of 40
Preliminary Technical Data
ADF7020
GENERAL DESCRIPTION
The ADF7020 is a low power, highly integrated FSK/GFSK/
ASK/OOK/GASK transceiver designed for operation in the
license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. It
is suitable for circuit applications that meet either the European
ETSI-300-220 or the North American FCC (Part 15) regulatory
standards. A complete transceiver can be built using a small
number of external discrete components, making the ADF7020
very suitable for price-sensitive and area-sensitive applications.
The transmit section contains a VCO and low noise
fractional-N PLL with output resolution of <1 ppm. The VCO
operates at twice the fundamental frequency to reduce spurious
emissions and frequency pulling problems.
The transmitter output power is programmable in 0.3 dB steps
from −16 dBm to +13 dBm. The transceiver RF frequency,
channel spacing, and modulation are programmable using a
simple 3-wire interface. The device operates with a power
supply range of 2.3 V to 3.6 V and can be powered down when
not in use.
A low IF architecture is used in the receiver (200 kHz),
minimizing power consumption and the external component
count and avoiding interference problems at low frequencies.
The ADF7020 supports a wide variety of programmable
features including Rx linearity, sensitivity, and IF bandwidth,
allowing the user to trade off receiver sensitivity and selectivity
against current consumption, depending on the application. The
receiver also features a patent-pending automatic frequency
control (AFC) loop, allowing the PLL to track out the frequency
error in the incoming signal.
An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, or the
RSSI signal, which provides savings on an ADC in some
applications. The temperature sensor is accurate to ±5°C over
the full operating temperature range of −40°C to +85°C.
Rev. PrH | Page 3 of 40
ADF7020
Preliminary Technical Data
SPECIFICATIONS
VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted.
Typical specifications are at VDD = 3 V, TA = 25°C.
All measurements are performed using the test circuit in Figure TBD using PN9 data sequence, unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
Frequency Ranges
Frequency Ranges (Divide-by-2 Mode)
Phase Frequency Detector Frequency
TRANSMISSION PARAMETERS
Data Rate FSK/GFSK
Data Rate OOK/ASK
Frequency Shift Keying
GFSK/FSK Frequency Deviation2, 3
Deviation Frequency Resolution
Gaussian Filter BT
Adjacent Channel Power, GFSK
Amplitude Shift Keying
ASK Modulation Depth
OOK –PA Off Feedthrough
Transmit Power4
Transmit Power Variation
Highest Power Setting
Transmit Power Flatness
Programmable Step Size
−20 dBm to +13 dBm
Spurious Emissions during PLL Settling
Integer Boundary
Reference
Harmonics
Second Harmonic
Third Harmonic
All Other Harmonics
VCO Frequency Pulling, OOK mod
Optimum PA Load Impedance5
RECEIVER PARAMETERS
FSK Input Sensitivity6
High Sensitivity Mode
Low Current Mode
Min
Typ
Max
Unit
862
433
RF/256
928
464
20
MHz
MHz
MHz
0.3
0.3
200
641
kbps
kbps
1
4.88
100
110
620
kHz
kHz
Hz
PFD = 3.625 MHz
PFD = 20 MHz
PFD = 3.625 MHz
0.5
TBD
dBc
−50
dBc
Channel spacing = 25 kHz, measured in
adjacent channel ± 8.5 kHz from center;
DR = 4.8 kbps, FDEV = 2.4 kHz,
FRF = 868 MHz
868.95 MHz ± 250 kHz, DR = 38.4 kbps,
FDEV = 19.2 kHz
30
Test Conditions
dB
dBm
dBm
dBm
dBm
FRF = 915 MHz, VDD = 3.0 V, TA = 25°C
FRF = 868 MHz, VDD = 3.0 V, TA = 25°C
FRF = 433 MHz, VDD = 3.0 V, TA = 25°C
TBD
13
TBD
TBD
dBm
dBm
dBm
dB
FRF = 915 MHz, VDD = 3.6 V
FRF = 915 MHz, VDD = 3.0 V
FRF = 915 MHz, VDD = 2.3 V
From 902 MHz to 928 MHz
0.3125
dB
dBm
dBc
dBc
Mute PA until lock enabled (R2_DB5 =1 )
50 kHz loop BW
−50
−20
+13
TBD
TBD
−57
−55
−65
−27
−21
−18
−18
−35
TBD
TBD
TBD
TBD
dBc
dBc
dBc
kHz rms
Ω
Ω
Ω
DR = 9.6 kbps
FRF = 915 MHz
FRF = 868 MHz
FRF = 433 MHz
−117.5
−TBD
dBm
dBm
At BER = 1E − 3, FRF = 915 MHz
DR = 1 kbps, FDEV = 5 kHz
DR = 1 kbps, FDEV = 5 kHz
See notes at end of table.
Rev. PrH | Page 4 of 40
Preliminary Technical Data
Parameter
High Sensitivity Mode
Low Current Mode
High Sensitivity Mode
Low Current Mode
OOK Input Sensitivity
High Sensitivity Mode
Low Current Mode
High Sensitivity Mode
Low Current Mode
LNA and Mixer
Input IP37
Enhanced Linearity Mode
Low Current Mode
High Sensitivity Mode
Rx Spurious Emissions8
ADF7020
−TBD
−TBD
−106.5
−TBD
dBm
dBm
dBm
dBm
Test Conditions
DR = 9.6 kbps, FDEV = 10 kHz
DR = 9.6 kbps, FDEV = 10 kHz
DR = 200 kbps, FDEV = 50 kHz
DR = 200 kbps, FDEV = 50 kHz
At BER = 1E − 3, FRF = 915 MHz
DR = 1 kbps
DR = 1 kbps
DR = 9.6 kbps
DR = 9.6 kbps
6.8
−3.2
−35
−57
−47
dBm
dBm
dBm
dBm
dBm
Pin = −20 dBm, 2 CW interferers
FRF = 915 MHz, f1 = FRF + 3 MHz
F2 = FRF + 6 MHz, maximum gain
<1 GHz at antenna input
>1 GHz at antenna input
kHz
Bits
kHz
IF_BW = 200 kHz
TBD
TBD
27
dB
50
dB
TBD
dB
IF filter BW settings = 100 kHz, 150 kHz,
200 kHz
Desired signal 3 dB above the input
sensitivity level, CW interferer power
level increased until BER = 10−3, image
channel excluded
30
TBD
−3
TBD
dB
dB
dB
dB
12
TBD
TBD
TBD
dBm
Ω
Ω
Ω
−100 to −36
±3
TBD
350
dBm
dB
dB
µs
65
MHz/V
130
MHz/V
Phase Noise (In-Band)
TBD
−92
MHz/V
dBc/Hz
Phase Noise (Out-of-Band)
Residual FM
−110
TBD
dBc/Hz
Hz
AFC
Pull-In Range
Response time
Accuracy
Channel Filtering
Adjacent Channel Rejection
(Offset = ±1 × IF Filter BW Setting)
Second Adjacent Channel Rejection
(Offset = ±2 × IF Filter BW Setting)
Third Adjacent Channel Rejection
(Offset = ±3 × IF Filter BW Setting)
Image Channel Rejection
(Image Channel = FRF − 400 kHz)
Co-channel Rejection
Wide-Band Interference Rejection
Saturation (Maximum Input Level)
Input Impedance
RSSI
Range at Input
Linearity
Absolute Accuracy
Response Time
PHASE LOCKED LOOP
VCO Gain
Min
Typ
−110.5
−104
−99
−TBD
Max
±50
1
See notes at end of table.
Rev. PrH | Page 5 of 40
Unit
dBm
dBm
dBm
dBm
Uncalibrated
Calibrated9
Swept from 100 MHz to 2 GHz, measured
as channel rejection
FSK mode, BER = 10−3
FRF = 915 MHz, RFIN, RFIN to GND
FRF = 868 MHz
FRF = 433 MHz
Maximum input step change, AGC
included, RSSI ready for readback
902 MHz to 928 MHz band.,
VCO adjust = 0
860MHz to 870 MHz band,
VCO Adjust = 0
At 433MHz, VCO Adjust = 0
PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz,
FRF = 915 MHz, VCO BIAS = 4
At 1 MHz offset
From 300 Hz to 5 kHz
ADF7020
Parameter
PLL Settling Time
REFERENCE INPUT
Crystal Reference
External Oscillator
Load capacitance
Input Level
Preliminary Technical Data
Min
3.625
3.625
VOL, Output Low Voltage
CLKOUT Rise/Fall
CLKOUT Load
TEMPERATURE RANGE—TA
POWER SUPPLIES
Voltage Supply
AVDD
DVDD
Transmit Current Consumption
−20 dBm
−10 dBm
0 dBm
10 dBm
Receive Current Consumption
Low Current Mode
High Sensitivity Mode
Power-Down Mode
Low Power Sleep Mode
Max
Unit
µs
24
24
MHz
MHz
pF
CMOS
levels
TBD
TIMING INFORMATION
Chip Enabled to Regulator Ready
Crystal Oscillator Startup time
Tx to Rx Turnaround Time
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
Control Clock Input
LOGIC OUTPUTS
VOH,Output High Voltage
Typ
40
TBD
1
350 µs +
(5 × TBIT)
0.7 × V DD
0.2 × V DD
±1
10
50
µs
ms
Test Conditions
Measured for a 10 MHz frequency step to
within 5 ppm accuracy,
PFD = 20 MHz, LBW = TBD
See the Reference Input Section
CREG = 100 nF
With 19.2 MHz XTAL
Time to synchronized data, includes AGC
settling
V
V
µA
pF
MHz
V
IOH = 500 µA
V
ns
pF
°C
IOL = 500 µA
−40
0.4
5
10
+85
2.3
AVDD
3.6
AVDD
V
DVDD −
0.4
FRF = 915 MHz, VDD = 3.0 V, PA is matched
in to 50 Ω
TBD
12
15
22
mA
mA
mA
mA
19
21
TBD
TBD
mA
mA
0.1
1
µA
1
VCO_BIAS_SETTING = 3
Higher data rates are achievable depending on local regulations.
For definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section.
3
For definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section.
4
Measured as maximum unmodulated power. Output power varies with both supply and temperature.
5
For matching details, see the LNA/PA Matching section.
6
See Table 5 for description of different receiver modes.
7
See Table 5 for description of different receiver modes.
8
Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.
9
See the Image Rejection Calibration section.
2
Rev. PrH | Page 6 of 40
Preliminary Technical Data
ADF7020
TIMING CHARACTERISTICS
VDD = 3 V ± 10%; VGND = 0 V, TA = 25°C, unless otherwise noted.
Guaranteed by design, but not production tested.
Table 2.
Parameter
Limit at TMIN to TMAX
Unit
Test Conditions/Comments
t1
<10
ns
SDATA to SCLK Setup Time
t2
<10
ns
SDATA to SCLK Hold Time
t3
<25
ns
SCLK High Duration
t4
<25
ns
SCLK Low Duration
t5
<10
ns
SCLK to SLE Setup Time
t6
<20
ns
SLE Pulse Width
t7
<TBD
ns
SLE to SCLK Setup Time, Readback
t8
<TBD
ns
SCLK to SREAD Data Valid, Readback
t9
<TBD
ns
SREAD Hold Time after SCLK, Readback
t10
<TBD
ns
SCLK to SLE Disable Time, Readback
t3
t4
SCLK
t1
SDATA
DB31 (MSB)
t2
DB30
DB1
(CONTROL BIT C2)
DB2
DB0 (LSB)
(CONTROL BIT C1)
01975-PrG-002
t6
SLE
t5
Figure 2. Serial Interface Timing Diagram
t1
t2
SCLK
SDATA
REG7 DB0
(CONTROL BIT C1)
SLE
t3
t10
t8
RV16
RV15
RV2
RV1
01975-PrG-003
X
SREAD
t9
Figure 3. Readback Timing Diagram
Rev. PrH | Page 7 of 40
ADF7020
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND1
Analog I/O Voltage to GND
Digital I/O Voltage to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
MLF θJA Thermal Impedance
Lead Temperature Soldering
Vapor Phase (60 s)
Infrared (15 s)
1
Rating
−0.3 V to +5 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−40°C to +85°C
−65°C to +125°C
125°C
TBD°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high-performance RF integrated circuit with an
ESD rating of <2 kV and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
235°C
240°C
GND = CPGND = RFGND = DGND = AGND = 0 V.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrH | Page 8 of 40
Preliminary Technical Data
ADF7020
GND1
GND
VCO GND
GND
VDD
CPOUT
VREG3
VDD3
OSC1
OSC2
MUXOUT
47
46
45
44
43
42
41
40
39
38
37
PIN 1
INDICATOR
VCOIN
1
36
CLKOUT
VREG1
2
35
DATA CLK
VDD1
3
34
DATA I/O
RFOUT
4
33
INT/LOCK
RFGND
5
32
VDD2
RFIN
6
31
VREG2
RFINB
7
30
ADCIN
RLNA
8
29
GND2
VDD4
9
28
SCLK
RSET 10
27
SREAD
VREG4 11
26
SDATA
GND4 12
25
SLE
ADF7020
CE 24
TEST_A 23
GND4 22
FILT_Q 21
FILT_Q 20
GND4 19
FILT_I 18
FILT_I 17
MIX_Q 16
MIX_Q 15
MIX_I 14
MIX_I 13
TOP VIEW
(Not to Scale)
01975-PrG-004
CVCO
48
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
VCOIN
2
VREG1
3
VDD1
4
RFOUT
5
6
RFGND
RFIN
7
8
9
10
11
RFINB
RLNA
VDD4
RSET
VREG4
12
13–18
GND4
MIX/FILT
19, 22
20, 21, 23
GND4
FILT/TEST_A
24
CE
25
SLE
26
SDATA
27
SREAD
28
SCLK
Function
The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO).
The higher the tuning voltage, the higher the output frequency.
Regulator Voltage for PA Block. A 100 nF capacitor should be placed between this pin and ground for
regulator stability and noise rejection.
Voltage Supply for PA Block. Decoupling capacitors (X7R or Tantalum) of 0.1 µF and 0.01 µF should be placed
as close as possible to this pin.
The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The output
should be impedance matched to the desired load using suitable components. See the Transmitter section.
Ground for Output Stage of Transmitter.
LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer. See the LNA/PA Matching section.
Complementary LNA Input. See the LNA/PA Matching section.
External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
Voltage supply for LNA/MIXER block. This pin should be decoupled to ground with a 0.01 µF capacitor.
External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance.
Regulator Voltage for LNA/MIXER block. A 100 nF capacitor should be placed between this pin and GND for
regulator stability and noise rejection.
Ground for LNA/MIXER block.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
Ground for LNA/MIXER block.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when CE
is low, and the part must be reprogrammed once CE is brought high.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches. A latch is selected using the control bits.
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high
impedance CMOS input.
Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The SCLK
input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
Rev. PrH | Page 9 of 40
ADF7020
Pin No.
29
30
Mnemonic
GND2
ADCIN
31
VREG2
32
VDD2
33
INT/LOCK
34
35
DATA I/O
DATA CLK
36
CLKOUT
37
MUXOUT
38
OSC2
39
40
OSC1
VDD3
41
VREG3
42
CPOUT
43
44–47
48
VDD
GND
CVCO
Preliminary Technical Data
Function
Ground for Digital Section.
Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 to
1.9 V. Readback is made using the SREAD pin.
Regulator Voltage for Digital Block. A 100 nF capacitor should be placed between this pin and ground for
regulator stability and noise rejection.
Voltage Supply for Digital Block. A decoupling capacitor (X7R or Tantalum) of 0.01 µF should be placed as
close as possible to this pin.
Bidirectional Pin. In output mode (INTerrupt mode), the ADF7020 asserts the INT/ LOCK pin when it has found
a match for the preamble sequence.
In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold when a valid
preamble has been detected. Once the threshold is locked, NRZ data can be reliably received. In this mode, a
demod lock can be asserted with minimum delay.
Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply.
In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the
center of the received data.
In GFSK transmit mode, the pin outputs an accurate clock to latch the data from the microcontroller into the
transmit section at the exact required data rate. See the Gaussian Frequency Shift Keying (GFSK) section.
A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to
drive several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio.
This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked to the correct
frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface
regulator.
The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by
driving this pin with CMOS levels and disabling the crystal oscillator.
The reference crystal should be connected between this pin and OSC2.
Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a
0.01 µF capacitor.
Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF capacitor should be placed between this pin
and ground for regulator stability and noise rejection.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The
integrated current changes the control voltage on the input to the VCO.
Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 µF capacitor.
Grounds for VCO Block.
A 22 nF capacitor should be placed between this pin and VREG1 to reduce VCO noise.
Rev. PrH | Page 10 of 40
Preliminary Technical Data
ADF7020
FREQUENCY SYNTHESIZER
REFERENCE INPUT SECTION
R Counter
The on-board crystal oscillator circuitry (Figure 5) can use an
inexpensive quartz crystal as the PLL reference. The oscillator
circuit is enabled by setting R1_DB12 high. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected using the automatic frequency
control (see the AFC Section) feature or by adjusting the
fractional-N value (see the N Counter section). A single-ended
reference (TCXO, CXO) can also be used. The CMOS levels
should be applied to OSC2 with R1_DB12 set low.
The 3-bit R counter divides the reference input frequency by an
integer from 1 to 7. The divided-down signal is presented as the
reference clock to the phase frequency detector (PFD). The
divide ratio is set in Register 1. Maximizing the PFD frequency
reduces the N value. This reduces the noise multiplied at a rate
of 20 log(N) to the output, as well as reducing occurrences of
spurious components. The R Register defaults to R = 1 on
power-up:
PFD [Hz] = XTAL/R
MUXOUT and Lock Detect
OSC2
CP2
CP1
The MUXOUT pin allows the user to access various digital
points in the ADF7020. The state of MUXOUT is controlled by
Bits R0_DB(29:31).
01975-PrG-005
OSC1
Figure 5. Oscillator Circuit on the ADF7020
Regulator Ready
Two parallel resonant capacitors are required for oscillation at
the correct frequency; their values are dependent on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds up to the
load capacitance of the crystal, usually 20 pF. Track capacitance
values vary from 2 pF to 5 pF, depending on board layout.
Where possible, choose capacitors that have a very low
temperature coefficient to ensure stable frequency operation
over all conditions.
REGULATOR READY is the default setting on MUXOUT after
the transceiver has been powered up. The power-up time of the
regulator is typically 50 µs. Because the serial interface is
powered from the regulator, the regulator must be at its nominal
voltage before the ADF7020 can be programmed. The status of
the regulator can be monitored at MUXOUT. When the
REGULATOR READY signal on MUXOUT is high,
programming of the ADF7020 can begin.
DVDD
CLKOUT Divider and Buffer
The CLKOUT circuit takes the reference clock signal from the
oscillator section, shown in Figure 5, and supplies a divideddown 50:50 mark-space signal to the CLKOUT pin. An even
divide from 2 to 30 is available. This divide number is set in
R1_DB(8:11). On power-up, the CLKOUT defaults to
divide-by-8.
REGULATOR READY
DIGITAL LOCK DETECT
ANALOG LOCK DETECT
R COUNTER OUTPUT
MUX
MUXOUT
CONTROL
N COUNTER OUTPUT
PLL TEST MODES
CLKOUT
ENABLE BIT
DIVIDER
1 TO 15
÷2
CLKOUT
01975-PrG-006
DGND
OSC1
Figure 7. MUXOUT Circuit
Digital Lock Detect
Figure 6. CLKOUT Stage
To disable CLKOUT, set the divide number to 0. The output
buffer can drive up to a 20 pF load with a 10% rise time at
4.8 MHz. Faster edges can result in some spurious feedthrough
to the output. A small series resistor (50 Ω) can be used to slow
the clock edges to reduce these spurs at FCLK.
Digital lock detect is active high. The lock detect circuit is
located at the PFD. When the phase error on five consecutive
cycles is less than 15 ns, lock detect is set high. Lock detect
remains high until 25 ns phase error is detected at the PFD.
Because no external components are needed for digital lock
detect, it is more widely used than analog lock detect.
Rev. PrH | Page 11 of 40
01975-PrG-007
Σ-∆ TEST MODES
DVDD
ADF7020
Preliminary Technical Data
Analog Lock Detect
This N-channel open-drain lock detect should be operated with
an external pull-up resistor of 10 kΩ nominal. When a lock has
been detected, this output is high with narrow low-going pulses.
For GFSK, it is recommended that an LBW of 2.0 to 2.5 times
the data rate be used to ensure that sufficient samples are taken
of the input data while filtering system noise. The free design
tool ADIsimPLL can be used to design loop filters for the
ADF7020.
Voltage Regulators
N Counter
The ADF7020 contains four regulators to supply stable voltages
to the part. The nominal regulator voltage is 2.3 V. Each
regulator should have a 100 nF capacitor connected between
VREG and GND. When CE is high, the regulators and other
associated circuitry are powered on, drawing a total supply
current of 2 mA. Bringing the chip-enable pin low disables the
regulators, reduces the supply current to less than 1 µA, and
erases all values held in the registers. The serial interface
operates off a regulator supply; therefore, to write to the part,
the user must have CE high and the regulator voltage must be
stabilized. Regulator status (VREG4) can be monitored using
the regulator ready signal from MUXOUT.
The feedback divider in the ADF7020 PLL consists of an 8-bit
integer counter and a 14-bit Σ-∆ fractional-N divider. The
integer counter is the standard pulse-swallow type common in
PLLs. This sets the minimum integer divide value to 31. The
fractional divide value gives very fine resolution at the output,
where the output frequency of the PLL is calculated as
FOUT =
Fractional-N
XTAL
× (Integer-N +
)
R
214
REFERENCE IN
4R
PFD/
CHARGE
PUMP
VCO
Loop Filter
The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. A typical loop filter design is shown in Figure 8.
THIRD-ORDER
Σ-∆ MODULATOR
FRACTIONAL-N
Figure 9. Fractional-N PLL
VCO
01975-PrG-008
CHARGE
PUMP OUT
INTEGER-N
01975-PrG-009
4N
The combination of the integer-N (maximum = 255) and the
fractional-N (maximum = 16383/16384) give a maximum N
divider of 255 + 1. Therefore, the minimum usable PFD is
Figure 8. Typical Loop Filter Configuration
In FSK, the loop should be designed so that the loop bandwidth
(LBW) is approximately five times the data rate. Widening the
LBW excessively reduces the time spent jumping between
frequencies, but can cause insufficient spurious attenuation.
PDFMIN [Hz] = Maximum Required Output Frequency/(255 + 1)
For example, when operating in the European 868 MHz to
870 MHz band, PFDMIN equals 3.4 MHz.
Voltage Controlled Oscillator (VCO)
For ASK systems, a wider LBW is recommended. The sudden
large transition between two power levels might result in VCO
pulling and can cause a wider output spectrum than is desired.
By widening the LBW to more than 10 times the data rate, the
amount of VCO pulling is reduced, because the loop settles
quickly back to the correct frequency. The wider LBW might
restrict the output power and data rate of ASK-based systems
compared with FSK-based systems.
Narrow-loop bandwidths can result in the loop taking long
periods of time to attain lock. Careful design of the loop filter is
critical to obtaining accurate FSK/GFSK modulation.
To minimize spurious emissions, the on-chip VCO operates
from 1732 MHz to 1856 MHz. The VCO signal is then divided
by 2 to give the required frequency for the transmitter and the
required LO frequency for the receiver.
The VCO should be recentered, depending on the required
frequency of operation, by programming the VCO adjust bits
R1_DB(20:21).
The VCO is enabled as part of the PLL by the PLL-enable bit,
R0_DB28.
A further frequency divide-by-2 is included to allow operation
in the lower 433 MHz and 460 MHz bands. To enable operation
in the these bands, R1_DB13 should be set to 1. The VCO needs
an external 22 nF between the VCO and the regulator to reduce
internal noise.
Rev. PrH | Page 12 of 40
Preliminary Technical Data
ADF7020
VCO Bias Current
CHOOSING CHANNELS FOR BEST SYSTEM
PERFORMANCE
VCO bias current can be adjusted using Bits R1_DB19 to
R1_DB16. To ensure VCO oscillation, the minimum bias
current setting under typical conditions is 2.5 mA.
The fractional-N PLL allows the selection of any channel within
868 MHz to 928 MHz (and 433MHz using divide-by-2) to a
resolution of <100 Hz. This also facilitates frequency hopping
systems.
VCO BIAS
R1_DB (16:19)
TO PA AND
N DIVIDER
LOOP FILTER
VCO
÷2
÷2
MUX
VCO SELECT BIT
Figure 10. Voltage Controlled Oscillator (VCO)
01975-PrG-010
220µF
CVCO PIN
Careful selection of the RF transmit channels must be made to
achieve best spurious performance. The architecture of
fractional-N results in some level of the nearest integer channel
moving through the loop to the RF output. These “beat-note”
spurs are not attenuated by the loop, if the desired RF channel
and the nearest integer channel are separated by a frequency of
less than the LBW.
The occurrence of beat-note spurs is rare, because the integer
frequencies are at multiples of the reference, which is typically
>10 MHz.
Beat-note spurs can be significantly reduced in amplitude by
avoiding very small or very large values in the fractional
register, using the frequency doubler. By having a channel
1 MHz away from an integer frequency, a 100 kHz loop filter
can reduce the level to <−45 dBc. When using an external VCO,
the fast lock (bleed) function reduces the spurs to <−60 dBc for
the same conditions.
Rev. PrH | Page 13 of 40
ADF7020
Preliminary Technical Data
TRANSMITTER
RF OUTPUT STAGE
The PA of the ADF7020 is based on a single-ended, controlled
current, open-drain amplifier that has been designed to deliver
up to 13 dBm into a 50 Ω load at a maximum frequency of
928 MHz.
The PA output current and, consequently, the output power are
programmable over a wide range. The PA configurations in
FSK/GFSK and ASK/OOK modulation modes are shown in
Figure 11 and Figure 12, respectively. In FSK/GFSK modulation
mode, the output power is independent of the state of the
DATA_IO pin. In ASK/OOK modulation mode, it is dependent
on the state of the DATA_IO pin and Bit R2_DB29, which
selects the polarity of the TxData input. For each transmission
mode, the output power can be adjusted as follows:
•
FSK/GFSK: The output power is set using bits
R2_DB(9:14).
•
ASK: The output power for the inactive state of the TxData
input is set by Bits R2_DB(15:20). The output power for the
active state of the TxData input is set by Bits R2_DB(9:14).
•
The PA is equipped with overvoltage protection, which makes it
robust in severe mismatch conditions. Depending on the
application, one can design a matching network for the PA to
exhibit optimum efficiency at the desired radiated output power
level for a wide range of different antennas, such as loop or
monopole antennas. See the LNA/PA Matching section for
details.
PA Bias Currents and Mute PA until Lock Bit
Control Bits R2_DB(30:31) facilitate an adjustment of the PA
bias current to further extend the output power control range, if
necessary. If this feature is not required, the default value of
7 µA is recommended. The output stage is powered down by
resetting Bit R2_DB4. To reduce the level of undesired spurious
emissions, the PA can be muted during the PLL lock phase by
setting Bit R2_DB5 (mute PA until lock bit).
MODULATION SCHEMES
OOK: The output power for the active state of the TxData
input is set by Bits R2_DB(9:14). The PA is muted when the
TxData input is inactive.
Frequency Shift Keying (FSK)
Frequency shift keying is implemented by setting the N value
for the center frequency and then toggling this with the TxData
line. The deviation from the center frequency is set using Bits
R2_DB(15:23). The deviation from the center frequency in Hz
is
FSK DEVIATION [Hz] =
R2_DB(30:31)
PFD × Modulation Number
214
2
IDAC
6
where Modulation Number is a number from 1 to 511
(R2_DB(15:23)) .
R2_DB(9:14)
Select FSK using Bits R2_DB(6:8).
RFOUT
R2_DB4
+
DIGITAL
LOCK DETECT
RFGND
FROM VCO
01975-PrG-011
R2_DB5
4R
Figure 11. PA Configuration in FSK/GFSK Mode
PA STAGE
VCO
FSK DEVIATION
FREQUENCY
ASK/OOK MODE
DATA I/O
PFD/
CHARGE
PUMP
÷N
–FDEV
R2_DB(30:31)
6
IDAC
6
+FDEV
R2_DB(9:14)
TxDATA
FRACTIONAL-N
6
Figure 13. FSK Implementation
R2_DB4
R2_DB5
DIGITAL
LOCK DETECT
RFGND
FROM VCO
01975-PrG-012
+
INTEGER-N
R2_DB(15:23)
0
RFOUT
THIRD-ORDER
Σ-∆ MODULATOR
Figure 12. PA Configuration in ASK/OOK Mode
Rev. PrH | Page 14 of 40
01975-PrG-013
R2_DB29
Preliminary Technical Data
ADF7020
Gaussian Frequency Shift Keying (GFSK)
Amplitude Shift Keying (ASK)
Gaussian frequency shift keying reduces the bandwidth
occupied by the transmitted spectrum by digitally prefiltering
the TxData. A TxCLK output line is provided from the
ADF7020 for synchronization of TxData from the microcontroller. The TxCLK line can be connected to the clock input
of a shift register that clocks data to the transmitter at the exact
data rate.
Amplitude shift keying is implemented by switching the output
stage between two discrete power levels. This is accomplished
by toggling the DAC, which controls the output level between
two 6-bit values set up in Register 2. A zero TxData bit sends
Bits R2_DB(15:20) to the DAC. A high TxData bit sends Bits
R2_DB(9:14) to the DAC. A maximum modulation depth of
30 dB is possible.
Setting Up the ADF7020 for GFSK
On-Off Keying (OOK)
To set up the frequency deviation, set the PFD and the mod
control bits:
On-off keying is implemented by switching the output stage to a
certain power level for a high TxData bit and switching the
output stage off for a zero. For OOK, the transmitted power for
a high input is programmed using Bits R2_DB(9:14).
GFSK DEVIATION [Hz] =
PFD × 2 m
212
Gaussian On-Off Keying (G-OOK)
where m is GFSK_MOD_CONTROL set using R2_DB(24:26).
To set up the GFSK data rate:
DR [bps] =
PFD
DIVIDER _ FACTOR × INDEX _ COUNTER
For further information, see the application note, Using GFSK
on the ADF7010, in the EVAL-ADF7010EB1 Technical Note.
Gaussian on-off keying represents a prefiltered form of OOK
modulation. The usually sharp symbol transitions are replaced
with smooth Gaussian filtered transitions, the result being a
reduction in frequency pulling of the VCO. Frequency pulling
of the VCO in OOK mode can lead to a wider than desired BW,
especially if it is not possible to increase the loop filter BW >
300 kHz. The G-OOK sampling clock samples data at the data
rate. (See the Setting Up the ADF7020 for GFSK section.)
Rev. PrH | Page 15 of 40
ADF7020
Preliminary Technical Data
RECEIVER SECTION
RF FRONT END
Based on the specific sensitivity and linearity requirements of
the application, it is recommended to adjust control bits
LNA_mode (R6_DB15) and mixer_linearity (R6_DB18) as
outlined in Table 5.
The ADF7020 is based on a fully integrated, low IF receiver
architecture. The low IF architecture facilitates a very low
external component count and does not suffer from power-lineinduced interference problems.
The gain of the LNA is configured by the LNA_gain field,
R9_DB(20:21), and can be set by either the user or the AGC
logic.
Figure 14 shows the structure of the receiver front end. The
many programming options allow users to trade off sensitivity,
linearity, and current consumption against each other in the
way best suitable for their applications. To achieve a high level
of resilience against spurious reception, the LNA features a
differential input. Switch SW2 shorts the LNA input when
transmit mode is selected (R0_DB27 = 0). This feature
facilitates the design of a combined LNA/PA matching network,
avoiding the need for an external Rx/Tx switch. See the LNA/PA
Matching section for details on the design of the matching
network.
IF Filter Settings/Calibration
Out-of-band interference is rejected by means of a fourth-order
Butterworth polyphase IF filter centered around a frequency of
200 kHz. The bandwidth of the IF filter can be programmed
between 100 kHz and 200 kHz by means of Control Bits
R1_DB(22:23), and should be chosen as a compromise between
interference rejection, attenuation of the desired signal, and the
AFC pull-in range.
To compensate for manufacturing tolerances, the IF filter
should be calibrated once after power-up. The IF filter
calibration logic requires that the IF filter divider in Bits
R6_DB(20:28) be set dependent on the crystal frequency. Once
initiated by setting Bit R6_DB19, the calibration is performed
automatically without any user intervention. The calibration
time is 200 µs, during which the ADF7020 should not be
accessed. It is important not to initiate the calibration cycle
before the crystal oscillator has fully settled. If the AGC loop is
disabled, the gain of IF filter can be set to three levels using the
filter_gain field, R9_DB(20:21). The filter gain is adjusted
automatically, if the AGC loop is enabled.
I (TO FILTER)
RFIN
Tx/Rx SELECT
[R0_DB27]
RFINB
SW2
LNA
LO
Q (TO FILTER)
LNA MODE
[R6_DB15]
MIXER LINEARITY
[R6_DB18]
LNA CURRENT
[R6_DB(16:17)]
01975-PrG-014
LNA GAIN
[R9_DB(20:21)]
LNA/MIXER ENABLE
[R8_DB6]
Figure 14. ADF7020 RF Front End
The signal in the image channel of the low IF mixer, located at a
frequency of 400 kHz below the desired channel, is rejected due
to the image rejection of the polyphase filter. The image
rejection performance of the IF filter is subject to manufacturing tolerances, and, to some extent, temperature drift. To
improve the image rejection, a calibration procedure can be
performed as outlined in the Image Rejection Calibration
section.
The LNA is followed by a quadrature downconversion mixer,
which converts the RF signal to the IF frequency of 200 kHz. It
is important to consider that the output frequency of the
synthesizer must be programmed to a value 200 kHz below the
center frequency of the received channel.
The LNA has two basic operating modes: high gain/low noise
mode and low gain/low power mode. To switch between these
two modes, use the LNA_mode bit, R6_DB15. The mixer is also
configurable between a low current and an enhanced linearity
mode using the mixer_linearity bit, R6_DB18.
Table 5. LNA/Mixer Modes
Receiver Mode
High Sensitivity Mode
(default)
RxMode2
Low Current Mode
Enhanced Linearity Mode
RxMode5
RxMode6
LNA Mode
(R6_DB15)
0
LNA Gain Value
R9_DB(21:20)
30
Mixer Linearity
(R6_DB18)
0
Sensitivity
(DR = 9.6 kbps,
fDEV = 10 kHz)
−110.5
Rx Current
Consumption
(mA)
22
Input IP3 (dBm)
−35
1
1
1
1
0
10
3
3
10
30
0
0
1
1
1
−104
−91
−101
TBD
TBD
20
19
19
TBD
TBD
−15.9
−3.2
6.8
−8.25
−28.8
Rev. PrH | Page 16 of 40
Preliminary Technical Data
ADF7020
RSSI Formula (Converting to dBm)
RSSI/AGC SECTION
The RSSI is implemented as a successive compression log amp
following the base-band channel filtering. The log amp achieves
±3 dB log linearity. It also doubles as a limiter to convert the
signal-to-digital levels for the FSK demodulator. The RSSI itself
is used for amplitude shift keying (ASK) demodulation. In ASK
mode, extra digital filtering is performed on the RSSI value.
Offset correction is achieved using a switched capacitor integrator in feedback around the log amp. This uses the BB offset
clock divide. The RSSI level is converted for user readback and
digitally controlled AGC by an 80-level (7-bit) flash ADC. This
level can be converted to input power in dBm.
OFFSET
CORRECTION
IFWR
LATCH
IFWR
CLK
ADC
RSSI
ASK
DEMOD
R
Gain_Mode_Correction is given by the values in Table 6.
LNA gain and filter gain (LG2/LG1, FG2/FG1) are also obtained
from the readback register.
Table 6. Gain Mode Correction Table
LNA Gain
(LG2, LG1)
H (10)
M (01)
M (01)
M (01)
L (00)
Filter Gain
(FG2, FG1)
H (10)
H (10)
M (01)
L (00)
L (00)
Gain Mode Correction
0
11
19 + 11 = 30
19 + 19 + 11 = 49
19 + 19 + 19 + 11 = 68
An additional factor should be introduced to account for losses
in the front-end matching network/antenna.
Figure 15. RSSI Block Diagram
RSSI Thresholds
When the RSSI is above AGC_HIGH_THRESHOLD, the gain is
reduced. When the RSSI is below AGC_LOW_THRESHOLD,
the gain is increased. A delay (AGC_DELAY) is programmed to
allow for settling of the loop. The user programs the two
threshold values (recommended defaults, 27 and 76) and the
delay (default, 10). The default AGC setup values should be
adequate for most applications. The threshold values must be
chosen to be more than 30 apart for the AGC to operate
correctly.
Offset Correction Clock
In Register 3, the user should set the BB offset clock divide bits
R3_DB(4:5) to give an offset clock between 1 MHz and 2 MHz,
where:
BBOS _CLK [Hz] = XTAL/(BBOS_CLK_DIVIDE)
BBOS_CLK_DIVIDE can be set to 4, 8, or 16.
FSK DEMODULATORS ON THE ADF7020
The two FSK demodulators on the ADF7020 are
•
FSK correlator/demodulator
•
Linear demodulator
Select these using the demod select bits, R4_DB(4:5).
FSK CORRELATOR/DEMODULATOR
The quadrature outputs of the IF filter are first limited and then
fed to a pair of digital frequency correlators that perform bandpass filtering of the binary FSK frequencies at (IF + FDEV) and
(IF − FDEV). Data is recovered by comparing the output levels
from each of the two correlators. The performance of this
frequency discriminator approximates that of a matched filter
detector, which is known to provide optimum detection in the
presence of AWGN.
FREQUENCY CORRELATOR
AGC Information
In Register 9, the user should select automatic gain control by
selecting auto in R9_DB18 and auto in R9_DB19. The user
should then program AGC low threshold R9_DB(4:10) and
AGC high threshold R9_DB(11:17). The recommended/default
values for the low and high thresholds are 30 and 70, respectively. In the AGC2 register the user should program the AGC
delay to be long enough to allow the loop to settle. The
recommended value is 10.
IF
I
LIMITERS
Q
Rev. PrH | Page 17 of 40
IF – FDEV
IF + FDEV
SLICER
0
DB(4:13) DB(14)
DB(8:15)
Figure 16. FSK Correlator/Demodulator Block Diagram
Rx DATA
Rx CLK
01975-PrG-016
IFWR
A
Readback_Code is given by Bits RV7 to RV1 in the readback
register (see Readback Format section).
DATA
SYNCHRONIZER
IFWR
A
where:
POST
DEMOD FILTER
A
01975-PrG-015
1
FSK
DEMOD
Input_Power [dBm] = −110 dBm + (Readback_Code +
Gain_Mode_Correction ) × 0.5
ADF7020
Preliminary Technical Data
Postdemodulator Filter
A second-order, digital low-pass filter removes excess noise
from the demodulated bit stream at the output of the
discriminator. The bandwidth of this postdemodulator filter is
programmable and must be optimized for the user’s data rate. If
the bandwidth is set too narrow, performance is degraded due
to intersymbol interference (ISI). If the bandwidth is set too
wide, excess noise degrades the receiver’s performance.
Typically, the 3 dB bandwidth of this filter is set at
approximately 0.75 times the user’s data rate, using Bits
R4_DB(6:15).
Bit Slicer
The received data is recovered by threshold detecting the output
of the postdemodulator low-pass filter. In the correlator/
demodulator, the binary output signal levels of the frequency
discriminator are always centered on zero. Therefore, the slicer
threshold level can be fixed at zero and the demodulator
performance is independent of the run-length constraints of the
transmit data bit stream. This results in robust data recovery,
which does not suffer from the classic baseline wander
problems that exist in the more traditional FSK demodulators.
Frequency errors are removed by an internal AFC loop that
measures the average IF frequency at the limiter output and
applies a frequency correction value to the fractional-N
synthesizer. This loop should be activated when the frequency
errors are greater than approximately 40% of the transmit
frequency deviation (see the AFC Section).
To optimize the coefficients of the FSK correlator, two
additional bits, R6_DB14 and R6_DB29, must be assigned. The
value of these bits depends on whether K (as defined above) is
odd or even. These bits are assigned according to Table 7 and
Table 8.
Table 7. When K Is Even
K
Even
Even
K
Odd
Odd
The discriminator BW is controlled in Register 6 by
R6_DB(4:13) and is defined as
R6_DB29
0
1
(K + 1)/2
Even
Odd
R6_DB14
1
1
R6_DB29
0
1
Postdemodulator Bandwidth Register Settings
The 3 dB bandwidth of the postdemodulator filter is controlled
by Bits R4_ DB(6:15) and is given by
Post _ Demod _ BWSetting =
210 × 2π × FCUTOFF
DEMOD _ CLK
where FCUTOFF is the target 3 dB bandwidth in Hz of the
postdemodulator filter. This should typically be set to 0.75 times
the data rate (DR).
Some sample settings for the FSK correlator/demodulator are
DEMOD_CLK = 5 MHz
DR = 9.6 kbps
FDEV = 20 kHz
Therefore,
FCUTOFF = 0.75 × 9.6 × 103 Hz
Post_Demod_BW = 211 π 7.2 × 103 Hz/(5 MHz)
Post_Demod_BW = Round(9.26) = 9
FSK Correlator Register Settings
To enable the FSK correlator/demodulator, Bits R4_DB(5:4)
should be set to [01]. To achieve best performance, the
bandwidth of the FSK correlator must be optimized for the
specific deviation frequency that is used by the FSK transmitter.
R6_DB14
0
0
Table 8. When K Is Odd
Data Synchronizer
An oversampled digital PLL is used to resynchronize the
received bit stream to a local clock. The oversampled clock rate
of the PLL (CDR_CLK) must be set at 32 times the data rate.
See the notes for the Register 3—Receiver Clock Register
section for a definition of how to program. The clock recovery
PLL can accommodate frequency errors of up to ±2%.
K/2
Even
Odd
and
K = Round(200 kHz)/20 kHz) = 10
Discriminator_BW = (5 MHz × 10)/(800 × 103) = 62.5 =
63 (rounded to nearest integer)
Table 9.
Discriminator _ BW = (DEMOD _ CLK × K ) /(800 × 10 )
3
where:
DEMOD_CLK is as defined in the Register 3—Receiver Clock
Register section, Note 2.
K = Round(200e3/FSK Deviation)
Setting Name
Post_Demod_BW
Discriminator BW
Dot Product
Rx Data Invert
Rev. PrH | Page 18 of 40
Register Address
R4_DB(6:15)
R6_DB(4:13)
R6_DB14
R6_DB29
Value
0x09
0x3F
0
0
Preliminary Technical Data
ADF7020
The 3 dB bandwidth of this filter is typically set at approximately 0.75 times the user data rate and is assigned by R4
_DB(6:15) as
LINEAR FSK DEMODULATOR
A block diagram of the linear FSK demodulator is shown in
Figure 17.
SLICER
MUX 1
ADC RSSI OUTPUT
LEVEL
Q
FREQUENCY
LINEAR DISCRIMINATOR
DB(6:15)
Figure 17. Block Diagram of Frequency Measurement System and
ASK.OOK/Linear FSK Demodulator
This method of frequency demodulation is useful when very
short preamble length is required and the system protocol
cannot support the overhead of the settling time of the internal
feedback AFC loop settling.
A digital frequency discriminator provides an output signal that
is linearly proportional to the frequency of the limiter outputs.
The discriminator output is then filtered and averaged using a
combined averaging filter and envelope detector. The demodulated FSK data is recovered by threshold-detecting the output of
the averaging filter, as shown in Figure 17. In this mode, the
slicer output shown in Figure 17 is routed to the data synchronizer PLL for clock synchronization. To enable the linear FSK
demodulator, set Bits R4_DB(4:5) to [00].
The 3 dB bandwidth of the postdemodulation filter is set in the
same way as the FSK correlator/demodulator, which is set in
R4_DB(6:15) and is defined as
Post _ Demod _ BW _ Setting =
210 × 2π × FCUTOFF
DEMOD_CLK
where FCUTOFF is the target 3 dB bandwidth in Hz of the
postdemodulator filter.
AFC SECTION
FREQUENCY
READBACK
AND
AFC LOOP
01975-PrG-017
LIMITER
ENVELOPE
DETECTOR
Rx DATA
IF
AVERAGING
FILTER
I
Post_Demod_BW_Setting =
7
210 × 2π × FCUTOFF
DEMOD _ CLK
The ADF7020 supports a real-time AFC loop, which is used to
remove frequency errors that can arise due to mismatches
between the transmit and receive crystals. This uses the
frequency discriminator block, as described in the Linear FSK
Demodulator section (see Figure 17). The discriminator output
is filtered and averaged to remove the FSK frequency
modulation using a combined averaging filter and envelope
detector. In FSK mode, the output of the envelope detector
provides an estimate of the average IF frequency.
Two methods of AFC, external and internal, are supported on
the ADF7020 (in FSK mode only).
External AFC
The user reads back the frequency information through the
ADF7020 serial port and applies a frequency correction value to
the fractional-N synthesizer’s N divider.
The frequency information is obtained by reading the 16-bit
signed AFC_readback, as described in the Readback Format
section, and applying the following formula:
FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215
Note that while the AFC_READBACK value is a signed number,
under normal operating conditions it is positive. In the absence
of frequency errors, the FREQ_RB value is equal to the IF
frequency of 200 kHz.
Internal AFC
where:
FCUTOFF is the target 3 dB bandwidth in Hz of the
postdemodulator filter.
DEMOD_CLK is as defined in the Register 3—Receiver Clock
Register section, Note 2.
The ADF7020 supports a real-time internal automatic
frequency control loop. In this mode, an internal control loop
automatically monitors the frequency error and adjusts the
synthesizer N divider using an internal PI control loop.
The internal AFC control loop parameters are controlled in
Register 11. The internal AFC loop is activated by setting
R11_DB20 to 1. A scaling coefficient must also be entered,
based on the crystal frequency in use. This is set up in
R11_DB(4:19) and should be calculated using
ASK/OOK Operation
ASK/OOK demodulation is activated by setting Bits
R4_DB(4:5) to [10].
Digital filtering and envelope detecting the digitized RSSI input
via MUX 1, as shown in Figure 17, perform ASK/OOK
demodulation. The bandwidth of the digital filter must be
optimized to remove any excess noise without causing ISI in the
received ASK/OOK signal.
AFC_Scaling_Coefficient = (500 × 224)/XTAL
Therefore, using a 10 MHz XTAL yields an AFC scaling
coefficient of 839.
Rev. PrH | Page 19 of 40
ADF7020
Preliminary Technical Data
Maximum AFC Range
The maximum AFC frequency range is ±100 kHz. This is set by
the maximum IF filter bandwidth of 200 kHz. Using the
minimum IF filter bandwidth of 100 kHz, the AFC range is
±50 kHz.
When AFC errors have been removed using either the internal
or external AFC, further improvement in the receiver’s sensitivity can be obtained by reducing the IF filter bandwidth using
Bits R1_DB(22:23).
AUTOMATIC SYNC WORD RECOGNITION
The ADF7020 also supports automatic detection of the sync or
ID fields. To activate this mode, the sync (or ID) word must be
preprogrammed into the ADF7020. In receive mode, this
preprogrammed word is compared to the received bit stream
and, when a valid match is identified, the external pin
INT/LOCK is asserted by the ADF7020.
This feature can be used to alert the microprocessor that a valid
channel has been detected. It relaxes the computational
requirements of the microprocessor and reduces the overall
power consumption. The INT/LOCK is automatically deasserted again after nine data clock cycles.
The automatic sync/ID word detection feature is enabled by
selecting demod mode 2 or 3 in the demodulator setup register.
Do this by setting R4_DB(25:23) = [010] or [011]. Bits
R5_DB(4:5) are used to set the length of the sync/ID word,
which can be either 12, 16, 20, or 24 bits long. The transmitter
must transmit the MSB of the sync byte first and the LSB last to
ensure proper alignment in the receiver sync byte detection
hardware.
For systems using FEC, an error tolerance parameter can also be
programmed that accepts a valid match when up to three bits of
the word are incorrect. The error tolerance value is assigned in
R5_DB(6:7).
Rev. PrH | Page 20 of 40
Preliminary Technical Data
ADF7020
APPLICATIONS SECTION
LNA/PA MATCHING
The ADF7020 exhibits optimum performance in terms of
sensitivity, transmit power, and current consumption only if its
RF input and output ports are properly matched to the antenna
impedance. For cost-sensitive applications, the ADF7020 is
equipped with an internal Rx/Tx switch, which facilitates the
use of a simple combined passive PA/LNA matching network.
Alternatively, an external Rx/Tx switch such as the Analog
Devices ADG919 can be used, which yields a slightly improved
receiver sensitivity and lower transmitter power consumption.
External Rx/Tx Switch
Figure 18 shows a configuration using an external Rx/Tx switch.
This configuration allows an independent optimization of the
matching and filter network in the transmit and receive path,
and is, therefore, more flexible and less difficult to design than
the configuration using the internal Rx/Tx switch. The PA is
biased through inductor L1, while C1 blocks dc current. Both
elements, L1 and C1, also form the matching network, which
transforms the source impedance into the optimum PA load
impedance, ZOPT_PA.
networks in a back-to-back configuration. Due to the
asymmetry of the network with respect to ground, a compromise between the input reflection coefficient and the maximum
differential signal swing at the LNA input must be established.
The use of appropriate CAD software is strongly recommended
for this optimization.
Depending on the antenna configuration, the user might need a
harmonic filter at the PA output to satisfy the spurious emission
requirement of the applicable government regulations. The
harmonic filter can be implemented in various ways, such as a
discrete LC-filter. Dielectric low-pass filter components such as
the LFL18924MTC1A052 (for operation in the 915 MHz band),
or LFL18869MTC2A160 (for operation in the 868 MHz band),
both by Murata Mfg. Co., Ltd., represent an attractive alternative
to discrete designs. The immunity of the ADF7020 to strong
out-of-band interference can be improved by adding a bandpass filter in the Rx path. Apart from discrete designs, SAW or
dielectric filter components such as the
SAFCH869MAM0T00B0S, SAFCH915MAL0N00B0S,
DCFB2869MLEJAA-TT1, or DCFB3915MLDJAA-TT1, all by
Murata Mfg. Co., Ltd., are well suited for this purpose.
VBAT
Internal Rx/Tx Switch
PA_OUT
OPTIONAL
LPF
PA
ANTENNA
ZOPT_PA
ZIN_RFIN
CA
RFIN
LA
ADG919
Rx/Tx – SELECT
LNA
RFINB
ZIN_RFIN
CB
ADF7020
01975-PrG-018
OPTIONAL
BPF
(SAW)
Figure 19 shows the ADF7020 in a configuration where the
internal Rx/Tx switch is used with a combined LNA/PA
matching network. Depending on the application, the slight
performance degradation caused by the internal Rx/Tx switch
might be acceptable, allowing the user to take advantage of the
cost-saving potential of this solution. The design of the
combined matching network must compensate for the
reactance presented by the networks in the Tx and the Rx paths,
taking the state of the Rx/Tx switch into consideration.
VBAT
Figure 18. ADF7020 with External Rx/Tx Switch
ZOPT_PA depends on various factors such as the required output
power, the frequency range, the supply voltage range, and the
temperature range. Selecting an appropriate ZOPT_PA helps to
minimize the Tx current consumption in the application. This
datasheet contains a number of ZOPT_PA values for representative conditions. Under certain conditions, however, it is
recommended to obtain a suitable ZOPT_PA value by means of a
load-pull measurement.
Due to the differential LNA input, the LNA matching network
must be designed to provide both a single-ended to differential
conversion and a complex conjugate impedance match. The
network with the lowest component count that can satisfy these
requirements is the configuration shown in Figure 18, which
consists of two capacitors and one inductor. A first-order
implementation of the matching network can be obtained by
understanding the arrangement as two L-type matching
C1
L1
PA_OUT
PA
ANTENNA
ZOPT_PA
OPTIONAL
BPF OR LPF
ZIN_RFIN
CA
RFIN
LA
LNA
RFINB
ZIN_RFIN
CB
ADF7020
01975-PrG-019
L1
Figure 19. ADF7020 with Internal Rx/Tx Switch
The procedure typically requires several iterations until an
acceptable compromise has been reached. The successful
implementation of a combined LNA/PA matching network for
the ADF7020 is critically dependent on the availability of an
Rev. PrH | Page 21 of 40
ADF7020
Preliminary Technical Data
As with the external Rx/Tx switch, an additional LPF or BPF
might be required to suppress harmonics in the transmit
spectrum or to improve the resilience of the receiver against
out-of-band interferers.
PREAMBLE
SYNC
WORD
ID
FIELD
DATA FIELD
CRC
01975-PrG-042
TRANSMIT PROTOCOL AND CODING
CONSIDERATIONS
Figure 20. Typical Format of a Transmit Protocol
IMAGE REJECTION CALIBRATION
The image channel in this receiver, with an IF at 200 kHz, is at
−200 kHz or +400 kHz below the desired signal. The polyphase
filter rejects this image with an asymmetric frequency response.
The image rejection performance of the receiver is dependent
on how well matched in amplitude the I and Q signals are, and
how perfect the quadrature is between them, that is, how close
to 90° apart they are. The uncalibrated image rejection performance is approximately 30 dB. However, it is possible to improve
on this performance by adjusting the I/Q phase/gain adjust bits
in Register 10, resulting in an image rejection of approximately
45 dB.
Bits R10_DB(24:27) adjust the relative phase of the signal
and Bits R10_DB(16:20) adjust the relative amplitude (see
Figure 20).
A dc-free preamble pattern is recommended for FSK/ASK/
OOK demodulation. The recommended preamble pattern is a
dc-free pattern such as a 10101010… pattern. Preamble patterns
with longer run-length constraints such as 11001100…. can also
be used. However, this results in a longer synchronization time
of the received bit stream in the receiver.
Manchester coding can be used for the entire transmit protocol.
However, the remaining fields that follow the preamble header
do not have to use dc-free coding. For these fields, the ADF7020
can accommodate coding schemes with a run-length of up to
6 bits without any performance degradation.
If longer run-length coding must be supported, the ADF7020
has several other features that can be activated. These involve a
range of programmable options that allow the envelope detector
output to be frozen after preamble acquisition.
LNA
POLYPHASE
FILTER
MIXERS
GAIN
LO I
PHASE
LO Q
01975-PrG-020
accurate electrical model for the PC board. In this context, the
use of a suitable CAD package is strongly recommended. To
avoid this effort, the reference design provided for the ADF7020
RF module can be used.
Figure 20. Phase/Gain Adjustment on ADF7020
DEVICE PROGRAMMING AFTER INITIAL
POWER-UP
Basic mode is the minimum number of write sequences to
power up the device. Enhanced mode uses the additional
features of the ADF7020 to tailor the part to a particular
application such as setting up a sync byte sequence or doing
automatic frequency control.
The sample setting is for the following setup:
FRF = 915 MHz, FSK, DR = 9.868 kbps, ICP = 1.44 mA
FDEV = 50 kHz, XTAL = 10 MHz, Correlator/Demodulator
Rev. PrH | Page 22 of 40
Preliminary Technical Data
ADF7020
EXAMPLE
SETTING
WRITE TO R0
PROGRAM
FREQUENCY
0x72DC 0000
WRITE TO R1
SET UP
OSCILLATOR
AND IF FILTER
0x86 9011
WRITE TO R2
SET UP
MODULATION
PARAMETERS
0x8022 6012
PRIMARY
FUNCTION
EXAMPLE
SETTING
WRITE TO R0
PROGRAM
FREQUENCY
0x0000
WRITE TO R1
SET UP
OSCILLATOR
AND IF FILTER
0x0000
WRITE TO R3
SET UP
Rx CLOCKS
0x0000
WRITE TO R4
SET UP
DEMOD
0x0000
WRITE TO R5
SET UP
SYNC BYTE
SEQUENCE
0x0000
WRITE TO R6
SET UP
Rx MODE
0x0000
WRITE TO R9
SET UP AGC
PARAMETERS AND
LNA/GAIN FILTER
0x0000
WRITE TO R10
SET UP I/Q
GAIN/PHASE
ADJUST
0x0000
WRITE TO R11
SET UP AFC
PARAMETERS
0x0000
REGISTER WRITE
01975-PrG-021
PRIMARY
FUNCTION
Figure 21. Basic Mode—Tx
WRITE TO R0
PROGRAM
FREQUENCY
WRITE TO R1
SET UP
OSCILLATOR
AND IF FILTER
WRITE TO R3
WRITE TO R4
WRITE TO R6
SET UP
Rx CLOCKS
SET UP
DEMOD
SET UP
Rx MODE
EXAMPLE
SETTING
0x7ADB D710
0x86 9011
0x64 2053
0x0194
0x2C82 0326
01975-PrG-023
PRIMARY
FUNCTION
01975-PrG-022
REGISTER WRITE
Figure 23. Enhanced Mode—Rx
Figure 22. Basic Mode—Rx
REGISTER WRITE
WRITE TO R0
PRIMARY
FUNCTION
EXAMPLE
SETTING
CHANGE FREQUENCY
AND CHANGE MODE
TO Rx
0x0000
Figure 24. Change Mode from Tx to Rx
Rev. PrH | Page 23 of 40
01975-PrG-024
REGISTER WRITE
ADF7020
Preliminary Technical Data
SERIAL INTERFACE
RSSI Readback
The serial interface allows the user to program the eleven 32-bit
registers using a 3-wire interface (SCLK, SDATA, and SLE). It
consists of a level shifter, 32-bit shift register and eleven latches.
Signals should be CMOS compatible. The serial interface is
powered by the regulator, and, therefore, is inactive when CE is
low.
The RSSI readback operation yields valid results in Rx mode
with ASK or FSK signals. The format of the readback word is
shown in Figure 25. It is comprised of the RSSI level information (Bits RV1 to RV7), the current filter gain (FG1, FG2), and
the current LNA gain (LG1, LG2) setting. The filter and LNA
gain are coded in accordance with the definitions in Register 9.
With the reception of ASK modulated signals, averaging of the
measured RSSI values improves accuracy. The input power can
be calculated from the RSSI readback value as outlined in the
RSSI/AGC Section.
Data is clocked into the register, MSB first, on the rising edge of
each clock (SCLK). Data is transferred to one of eleven latches
on the rising edge of SLE. The destination latch is determined
by the value of the four control bits (C4 to C1). These are the
bottom four LSBs, DB3 to DB0, as shown in the timing diagram
in Figure 2. Data can also be read back on the SREAD pin.
Battery Voltage ADCIN/Temperature Sensor Readback
The battery voltage is measured at Pin VDD4. The readback
information is contained in Bits RV1 to RV7. This also applies
for the readback of the voltage at the ADCIN pin and the
temperature sensor. From the readback information, the battery
or ADCIN voltage can be determined using
READBACK FORMAT
The readback operation is initiated by writing a valid control
word to the readback register and setting the readback-enable
bit (R7_DB8 = 1). The readback can begin after the control
word has been latched with the SLE signal. SLE must be kept
high while the data is being read out. Each active edge at the
SCLK pin clocks the readback word out successively at the
SREAD pin, as shown in Figure 25, starting with the MSB first.
The data appearing at the first clock cycle following the latch
operation must be ignored.
VBATTERY = (Battery_Voltage_Readback)/21.1
VADCIN = (ADCIN_Voltage_Readback)/42.1
Silicon Revision Readback
The silicon revision readback word is valid without setting any
other registers, especially directly after power-up. The silicon
revision word is coded with four quartets in BCD format. The
product code (PC) is coded with two quartets extending from
Bits RV9 to RV16. The revision code (RV) is coded with two
quartets extending from Bits RV1 to RV8. The product code
should read back as PC = #20h. The current revision code
should read as RC = #30h.
AFC Readback
The AFC readback is valid only during the reception of FSK
signals with either the linear or correlator demodulator active.
The AFC readback value is formatted as a signed 16-bit integer
comprised of Bits RV1 to RV16, and is scaled according to the
following formula:
Filter Calibration Readback
FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215
The filter calibration readback word is contained in Bits RV1 to
RV8, and is for diagnostic purposes only. Using the automatic
filter calibration function, accessible through Register 6, is
recommended.
In the absence of frequency errors, the FREQ_RB value is equal
to the IF frequency of 200 kHz. Note that, for the AFC readback
to yield a valid result, the down-converted input signal must not
fall outside the bandwidth of the analogue IF filter. At low-input
signal levels, the variation in the readback value can be
improved by averaging.
READBACK MODE
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AFC READBACK
RV16
RV15
RV14
RV13
RV12
RV11
RV10
RV9
RV8
RV7
RV6
RV5
RV4
RV3
RV2
RV1
RSSI READBACK
X
X
X
X
X
LG2
LG1
FG2
FG1
RV7
RV6
RV5
RV4
RV3
RV2
RV1
BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK
X
X
X
X
X
X
X
X
X
RV7
RV6
RV5
RV4
RV3
RV2
RV1
SILICON REVISION
RV16
RV15
RV14
RV13
RV12
RV11
RV10
RV9
RV8
RV7
RV6
RV5
RV4
RV3
RV2
RV1
FILTER CAL READBACK
0
0
0
0
0
0
0
0
RV8
RV7
RV6
RV5
RV4
RV3
RV2
RV1
Figure 25. Readback Value Table
Rev. PrH | Page 24 of 40
01975-PrG-025
READBACK VALUE
Preliminary Technical Data
ADF7020
C1 (0) DB0
C2 (0) DB1
C3 (0) DB2
M13
...
M3
M2
M1
FRACTIONAL
DIVIDE RATIO
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
...
...
...
...
...
...
...
...
...
...
1
1
1
.
.
.
1
1
1
1
0
0
1
.
.
.
0
0
1
1
0
1
0
.
.
.
0
1
0
1
4
5
6
.
.
.
32764
32765
32766
32767
N6
N5
N4
N3
N2
N1
N COUNTER
DIVIDE RATIO
0
0
.
.
.
1
0
0
.
.
.
1
0
1
.
.
.
1
1
0
.
.
.
1
1
0
.
.
.
1
1
0
.
.
.
1
1
0
.
.
.
0
1
0
.
.
.
1
31
32
.
.
.
253
1
1
1
1
1
1
1
0
254
1
1
1
1
1
1
1
1
255
Figure 26.
Notes:
1.
The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and also controls the state of the internal Tx/Rx switch.
2.
FOUT =
01975-PrG-026
DB12
M9
C4 (0) DB3
DB13
DB4
DB14
M11
M10
DB5
DB15
M12
M1
M14
N7
Rev. PrH | Page 25 of 40
M2
M15
N8
Fractional-N
XTAL
× (Integer-N +
).
R
215
DB6
DB16
M13
REGULATOR READY (DEFAULT)
R DIVIDER OUTPUT
N DIVIDER OUTPUT
DIGITAL LOCK DETECT
ANALOG LOCK DETECT
THREE-STATE
PLL TEST MODES
Σ-∆ TEST MODES
M3
DB17
M14
MUXOUT
0
1
0
1
0
1
0
1
DB7
DB18
M15
M1
0
0
1
1
0
0
1
1
DB8
DB19
N1
M2
0
0
0
0
1
1
1
1
M4
DB20
N2
M3
M5
DB21
N3
PLL OFF
PLL ON
DB9
DB22
N4
0
1
M6
DB23
N5
PLE1 PLL ENABLE
DB11
DB24
N6
TRANSMIT
RECEIVE
DB10
DB25
N7
0
1
M7
DB26
N8
TRANSMIT/
RECEIVE
M8
Tx/Rx
TR1
ADDRESS
BITS
15-BIT FRACTIONAL-N
DB27
DB29
M1
8-BIT INTEGER-N
TR1
DB30
M2
PLE1 DB28
DB31
M3
MUXOUT
PLL
ENABLE
REGISTER 0—N REGISTER
ADF7020
Preliminary Technical Data
100kHz
150kHz
200kHz
NOT USED
2.
FOUT =
CP2
ICP(MA)
CP1
RSET 3.6kΩ
0
0
1
1
0
1
0
1
0.3
0.9
1.5
2.1
Fractional-N
XTAL
× (Integer-N +
).
R
215
Rev. PrH | Page 26 of 40
DB6
DB5
DB4
R3
R2
R1
CL4
0
0
0
.
.
.
1
C1 (1) DB0
DB7
D1
8mA
C2 (0) DB1
DB8
D1
0
1
R1
1
0
.
.
.
1
C3 (0) DB2
DB9
CL1
866–940
433–470
R2
0
1
.
.
.
1
C4 (0) DB3
XTAL
DOUBLER
XOSC
ENABLE
0
1
Notes:
Set the VCO adjust bits (R1_DB(20:21) to 0 for normal operation.
CL2
DB13
V1
VCO Band
MHz
Figure 27.
1.
DB10
DB14
DD1
VB1
1
0
.
1
VCO BIAS
CURRENT
0.5mA
1mA
V1
R3
0
0
.
.
.
1
RF R COUNTER
DIVIDE RATIO
1
2
.
.
.
7
XTAL
DOUBLER
DISABLE
ENABLED
CL3
0
0
0
.
.
.
1
CL2
0
0
1
.
.
.
1
CL1
0
1
0
.
.
.
1
CLKOUT
DIVIDE RATIO
OFF
2
4
.
.
.
30
01975-PrG-027
0
0
1
1
VB2
0
1
.
1
CL3
DB15
DD2
VB3
0
0
.
1
DB11
DB16
VB1
880–950
870–940
860–930
850–920
CL4
DB17
VB2
0
1
0
1
X1 XTAL OSC
0
OFF
1
ON
ADDRESS
BITS
R COUNTER
DB12
DB18
VB3
0
0
1
1
CLOCKOUT
DIVIDE
X1
DB19
VB4
FREQUENCY
OF OPERATION
FILTER
BANDWIDTH
VCO BAND
DB20
VA1
IR2 IR1
CP
CURRENT
VCO
ADJUST
DB21
VA1
VA2
VB4
0
0
.
1
0
1
0
1
VCO BIAS
VA2
DB22
IR1
DB23
DB24
IR2
DB25
DB26
DB27
DB28
DB29
DB30
DB31
IF FILTER BW
REGISTER 1—OSCILLATOR/FILTER REGISTER
Preliminary Technical Data
ADF7020
X
X
X
X
C1 (0) DB0
C2 (1) DB1
C3 (0) DB2
C4 (0) DB3
DB4
ADDRESS
BITS
PE1
POWER AMPLIFIER
0
1
OFF
ON
MUTE PA UNTIL
MP1 LOCK DETECT HIGH
TxDATA
TxDATA
OFF
ON
0
1
PA2
PA1
PA BIAS
S3
S2
S1
MODULATION SCHEME
0
1
0
1
0
0
1
1
5µA
7µA
9µA
11µA
0
0
1
0
1
0
0
0
1
1
0
1
0
1
1
FSK
GFSK
ASK
OOK
G - OOK
POWER AMPLIFIER OUTPUT LOW LEVEL
D6
.
D5
D2
D1
POWER AMPLIFIER OUTPUT HIGH LEVEL
P6
.
.
P2
P1
X
0
0
0
0
.
.
1
0
0
0
0
.
.
1
X
X
0
0
.
.
.
1
.
.
.
.
.
.
.
1
X
X
0
0
1
.
.
1
X
X
0
1
0
.
.
1
OOK MODE
PA OFF
–16.0dBm
–16 + 0.45dBm
–16 + 0.90dBm
.
.
13dBm
.
.
.
.
.
.
1
.
.
.
.
.
.
1
Figure 28.
Note:
1. See the Transmitter section for a description of how the PA bias affects power amplifier level. Default level is 9 µA.
Rev. PrH | Page 27 of 40
X
0
0
1
.
.
1
X
0
1
0
.
.
1
PA OFF
–16.0dBm
–16 + 0.45dBm
–16 + 0.90dBm
.
.
13dBm
01975-PrG-028
DI1
0
1
PE1
DB12
P4
DB5
DB13
P5
MP1
DB14
P6
DB6
DB15
D1
S1
DB16
D2
DB7
DB17
D3
DB8
DB18
D4
S2
DB19
D5
S3
DB20
D6
DB9
DB21
D7
P1
DB22
D8
DB11
DB23
D9
DB10
DB24
MC1
P2
DB25
MC2
P3
DB26
IC2 IC1 MC3 MC2 MC1
X
MUTE PA
UNTIL LOCK
PA
ENABLE
MODULATION
SCHEME
POWER AMPLIFIER
MC3
DB28
IC2
INDEX
COUNTER
DB29
DI1
MODULATION PARAMETER
DB27
DB30
PA1
GFSK MOD
CONTROL
IC1
DB31
PA2
PA BIAS
TxDATA
INVERT
REGISTER 2—TRANSMIT MODULATION REGISTER (ASK/OOK MODE)
ADF7020
Preliminary Technical Data
0
1
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
D4
D3
D2
D1
P6
P5
P4
P3
P2
P1
S3
S2
TxDATA
TxDATA
PA2
PA1
PA BIAS
0
0
1
1
0
1
0
1
5µA
7µA
9µA
11µA
X
FOR FSK MODE,
D2
....
D3
D9
0
0
0
0
.
1
....
....
....
....
....
....
0
0
0
0
.
1
0
0
1
1
.
1
C1 (0) DB0
DB19
D5
DI1
X
C2 (1) DB1
DB20
D6
X
C3 (0) DB2
DB21
D7
X
MUTE PA
UNTIL LOCK
PA
ENABLE
DB4
DB22
D8
X
PE1
DB23
D9
IC2 IC1 MC3 MC2 MC1
ADDRESS
BITS
C4 (0) DB3
DB24
MC1
DB5
DB25
MC2
DB6
DB26
MC3
S1
DB27
MP1
MODULATION
SCHEME
POWER AMPLIFIER
IC1
MODULATION PARAMETER
DB28
DB29
DI1
GFSK MOD
CONTROL
IC2
DB30
PA1
TxDATA
INVERT
DB31
PA2
PA BIAS
INDEX
COUNTER
REGISTER 2—TRANSMIT MODULATION REGISTER (FSK MODE)
PE1
POWER AMPLIFIER
0
1
OFF
ON
MUTE PA UNTIL
MP1 LOCK DETECT HIGH
D1
F DEVIATION
0
1
0
1
.
1
PLL MODE
1 × FSTEP
2 × FSTEP
3 × FSTEP
.
511 × FSTEP
OFF
ON
0
1
S3
S2
S1
MODULATION SCHEME
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
FSK
GFSK
ASK
OOK
G - OOK
0
0
0
0
.
.
1
Figure 29.
Notes:
1.
2.
FSTEP = PFD / 214
.
PA Bias default = 9 µA.
Rev. PrH | Page 28 of 40
.
.
.
.
.
.
1
.
.
.
.
.
.
1
X
0
0
1
.
.
1
X
0
1
0
.
.
1
PA OFF
–16.0dBm
–16 + 0.45dBm
–16 + 0.90dBm
.
.
13dBm
01975-PrG-029
POWER AMPLIFIER OUTPUT LEVEL
P1
P2
.
.
P6
Preliminary Technical Data
ADF7020
DB9
DB8
DB7
DB6
DB5
P1
S3
S2
S1
MP1
MUTE PA
UNTIL LOCK
PA
ENABLE
DB11
DB10
OFF
ON
MUTE PA UNTIL
MP1 LOCK DETECT HIGH
PA BIAS
0
0
1
1
5µA
7µA
9µA
11µA
0
1
D9
0
0
1
1
IC2
IC1
INDEX_COUNTER
0
0
1
1
0
1
0
1
16
32
64
128
D8
0
1
0
1
GAUSSIAN – OOK
MODE
BLEED/BUFFER OFF
OUTPUT BUFFER ON
BLEED CURRENT ON
BLEED/BUFFER ON
0
1
.
1
0
0
0
0
.
.
1
0
1
.
7
Figure 30.
Notes:
1.
GFSK_DEVIATION = (2GFSK_MOD_CONTROL × PFD)/212.
2.
DR = PFD/(INDEX_COUNTER × DIVIDER_FACTOR).
3.
PA Bias default = 9 µA.
S3
S2
S1
MODULATION SCHEME
0
0
1
0
1
0
0
0
1
1
0
1
0
1
1
FSK
GFSK
ASK
OOK
G - OOK
POWER AMPLIFIER OUTPUT LEVEL
P1
P2
.
.
P6
MC3 MC2 MC1 GFSK_MOD_CONTROL
0
0
.
1
OFF
ON
Rev. PrH | Page 29 of 40
.
.
.
.
.
.
1
.
.
.
.
.
.
1
X
0
0
1
.
.
1
X
0
1
0
.
.
1
PA OFF
–16.0dBm
–16 + 0.45dBm
–16 + 0.90dBm
.
.
13dBm
01975-PrG-030
PA1
0
1
0
1
C1 (0) DB0
POWER AMPLIFIER
0
1
C2 (1) DB1
PE1
INVALID
1
2
3
.
127
C3 (0) DB2
DIVIDER_FACTOR
0
1
0
1
.
1
C4 (0) DB3
D1
0
0
1
1
.
1
DB4
D2
0
0
0
0
.
1
PE1
DB12
P4
P2
DB13
P5
D3
...
...
...
...
...
...
TxDATA
TxDATA
PA2
0
0
.
1
P3
DB14
P6
DB15
DB21
D7
DB16
DB22
D8
...
0
0
0
0
.
1
D1
DB23
D9
D7
D2
DB24
MC1
DB17
DB25
MC2
D3
DB26
MC3
DB18
DB27
IC1
DB19
DB28
IC2
D4
DB29
DI1
0
1
ADDRESS
BITS
D5
DB30
DI1
MODULATION
SCHEME
POWER AMPLIFIER
DB20
DB31
PA1
MODULATION PARAMETER
D6
INDEX
COUNTER
GFSK MOD
CONTROL
PA2
PA BIAS
TxDATA
INVERT
REGISTER 2—TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE)
ADF7020
Preliminary Technical Data
0
0
.
1
1
DB0
DB5
BK2
C1(1)
DB6
OK1
DB1
DB7
OK2
C2(1)
DB8
FS1
DB2
DB9
FS2
DB3
DB10
FS3
C3(0)
DB11
FS4
ADDRESS
BITS
C4(0)
DB12
FS5
BB OFFSET
CLOCK DIVIDE
DB13
FS6
DB4
DB14
FS7
BK1
DB15
FS8
DB16
SK1
DB17
DB18
SK3
SK2
DB19
SK4
...
...
...
...
...
...
CDR CLOCK DIVIDE
SK3
SK2
SK1
SEQ_CLK_DIVIDE
BK2
BK1
BBOS_CLK_DIVIDE
0
0
.
1
1
0
1
.
1
1
1
0
.
0
1
1
2
.
254
255
0
0
1
0
1
x
4
8
16
OK2
OK1
DEMOD_CLK_DIVIDE
0
0
1
1
0
1
0
1
4
1
2
3
FS8
FS7
...
FS3
FS2
FS1
CDR_CLK_DIVIDE
0
0
.
1
1
0
0
.
1
1
...
...
...
...
...
0
0
.
1
1
0
1
.
1
1
1
0
.
0
1
1
2
.
254
255
Figure 31.
Notes:
1.
Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where:
BBOS _ CLK =
2.
XTAL
BBOS _ CLK _ DIVIDE
The demodulator clock (DEMOD_CLK) must be < 12 MHz for FSK and < 6 MHz for ASK, where:
DEMOD _ CLK =
3.
XTAL
DEMOD _ CLK _ DIVIDE
Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where:
CDR _ CLK =
DEMOD _ CLK
CDR _ CLK _ DIVIDE
Note that this might affect your choice of XTAL, depending on the desired data rate.
4.
The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to 40 kHz for ASK:
SEQ _ CLK =
XTAL
SEQ _ CLK _ DIVIDE
Rev. PrH | Page 30 of 40
01975-PrG-031
SK7
0
0
.
1
1
DB20
DB21
DB22
SK7
SK8
SK5
DB23
SK6
DB24
IR1
SK8
DB25
IR2
DB26
DB27
DB28
DB29
DB30
DB31
SEQUENCER CLOCK DIVIDE
DEMOD
CLOCK DIVIDE
REGISTER 3—RECEIVER CLOCK REGISTER
Preliminary Technical Data
ADF7020
0
0
0
0
1
1
0
0
1
1
0
1
DEMOD
SELECT
DEMOD LOCK/
DB24 SYNC WORD MATCH
0
1
0
1
X
DL8
ADDRESS
BITS
DB5
DB4
DB3
DB2
DB1
DB0
C4(0)
C3(1)
C2(0)
C1(0)
DB6
DW1
DS1
DB7
DW2
DS2
DB8
DW3
DB9
DW4
DB16
DL1
–
–
OUTPUT
OUTPUT
INPUT
–
DB11
DB17
DL2
INT/LOCK PIN
SERIAL PORT CONTROL – FREE RUNNING
SERIAL PORT CONTROL – LOCK THRESHOLD
SYNC WORD DETECT – FREE RUNNING
SYNC WORD DETECT – LOCK THRESHOLD
INTERRUPT/LOCK PIN LOCKS THRESHOLD
DEMOD LOCKED AFTER DL8–DL1 BITS
DW5 DB10
DB18
DL3
DEMOD LOCK/SYNC WORD MATCH
DW6
DB19
DL4
DW7 DB12
DB20
DL5
DW8 DB13
DB21
DL6
DW9 DB14
DB22
DL7
DW10 DB15
DB23
POSTDEMODULATOR BW
DL8
DB25
DEMOD MODE LM2 LM1 DL8
0
1
2
3
4
5
DEMODULATOR LOCK SETTING
LM1
LM2
DB26
DB27
DB28
DB29
DB30
DB31
REGISTER 4—DEMODULATOR SETUP REGISTER
DS2
DS1
DEMODULATOR
TYPE
0
0
1
1
0
1
0
1
LINEAR DEMODULATOR
CORRELATOR/DEMODULATOR
ASK/OOK
INVALID
MODE5 ONLY
DL7
...
DL3
DL2
DL1
LOCK_THRESHOLD_TIMEOUT
0
0
0
.
1
1
0
0
0
.
1
1
...
...
...
...
...
...
0
0
0
.
1
1
0
0
1
.
1
1
0
1
0
.
0
1
0
1
2
.
254
255
01975-PrG-032
DL8
Figure 32.
Notes :
1.
The cutoff frequency of the postdemodulator filter should typically be 0.75 times the data rate.
2.
Demodulator modes 1, 3, 4, and 5 are modes that can be activated to allow the ADF7020 to demodulate data-encoding schemes that have run-length constraints
greater than 7.
3.
Post_Demod_BW = 211 π FCUTOFF/DEMOD_CLK.
4.
For Mode 5, the timeout delay to lock threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK, where SEQ_CLK is defined in the Register 3—Receiver Clock Register
section.
Rev. PrH | Page 31 of 40
ADF7020
Preliminary Technical Data
DB4
DB3
DB2
DB1
DB0
C4(0)
C3(1)
C2(0)
C1(1)
CONTROL
BITS
PL1
DB5
DB6
MT1
PL2
DB7
MT2
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
DB18
DB19
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB28
DB29
DB30
DB31
SYNC BYTE SEQUENCE
SYNC BYTE
LENGTH
MATCHING
TOLERANCE
REGISTER 5—SYNC BYTE REGISTER
PL2
PL1
SYNC BYTE
LENGTH
0
0
1
1
0
1
0
1
12 BITS
16 BITS
20 BITS
24 BITS
0
0
1
1
0
1
0
1
0 ERRORS
1 ERROR
2 ERRORS
3 ERRORS
01975-PrG-033
MATCHING
MT2 MT1 TOLERANCE
Figure 33.
Notes:
1.
Sync byte detect is enabled by programming Bits R4_DB(25:23) to [010] or [011].
2.
This register allows a 28-bit sync byte sequence to be stored internally. If the sync byte detect mode is selected, then the INT/LOCK pin goes high when the sync
byte has been detected in Rx mode. Once the sync word detect signal has gone high, it goes low again after nine data bits.
3.
The transmitter must Tx the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware.
Rev. PrH | Page 32 of 40
Preliminary Technical Data
ADF7020
RI1
RxDATA
INVERT
0
1
RxDATA
RxDATA
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
TD7
TD6
TD5
TD4
TD3
TD2
TD1
C4(0)
C3(1)
C2(1)
C1(0)
DB14
DB12
DB15
LG1
DP1
TD8
DB16
LI1
DP1
DOT PRODUCT
0
1
CROSS PRODUCT
DOT PRODUCT
ML1 MIXER LINEARITY
LG1
LNA MODE
0
1
0
1
DEFAULT
REDUCED GAIN
NO CAL
CALIBRATE
0
1
CDR
RESET
TD9
DB17
LI2
CA1 FILTER CAL
DEMOD
RESET
DEFAULT
HIGH
LI2
LI1
LNA BIAS
0
0
800µA (DEFAULT)
.
FC6
FC5
FC4
FC3
FC2
FC1
FILTER CLOCK
DIVIDE RATIO
0
0
.
.
.
.
1
.
.
.
.
.
.
.
0
0
.
.
.
.
1
0
0
.
.
.
.
1
0
0
.
.
.
.
1
0
0
.
.
.
.
1
0
1
.
.
.
.
1
1
0
.
.
.
.
1
1
2
.
.
.
.
511
01975-PrG-034
FC9
ADDRESS
BITS
DISCRIMINATOR BW
TD10 DB13
DB18
ML1
DOT
PRODUCT
DB19
CA1
LNA MODE
DB20
LNA
CURRENT
IF FILTER
CAL
MIXER
LINEARITY
DB21
FC1
DB24
FC5
FC2
DB25
FC6
DB22
DB26
FC7
FC3
DB27
FC8
DB23
DB28
FC9
FC4
DB29
DB30
IF FILTER DIVIDER
RI1
DB31
Rx
RESET
RxDATA
INVERT
REGISTER 6—CORRELATOR/DEMODULATOR REGISTER
Figure 34.
Notes:
1.
See the FSK Correlator/Demodulator section for an example of how to determine register settings.
2.
Nonadherence to correlator programming guidelines results in poorer sensitivity.
3.
The filter clock is used to calibrate the IF filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz. The formula is
XTAL/FILTER_CLOCK_DIVIDE.
4.
The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19 is set high.
5.
Discriminator_BW = (DEMOD_CLK × K)/(800 × 103). See the FSK Correlator/Demodulator section.
Rev. PrH | Page 33 of 40
ADF7020
Preliminary Technical Data
REGISTER 7—READBACK SETUP REGISTER
ADC
MODE
CONTROL
BITS
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
RB3
RB2
RB1
AD2
AD1
C4(0)
C3(1)
C2(1)
C1(1)
RB3 READBACK
AD2 AD1 ADC MODE
0
1
0
0
1
1
DISABLED
ENABLED
RB2 RB1 READBACK MODE
0
0
1
1
0
1
0
1
0
1
0
1
MEASURE RSSI
BATTERY VOLTAGE
TEMP SENSOR
TO EXTERNAL PIN
AFC WORD
ADC OUTPUT
FILTER CAL
SILICON REV
01975-PrG-035
READBACK
SELECT
Figure 35.
Notes:
1.
Readback of the measured RSSI value is valid only in Rx mode. Readback of the battery voltage, the temperature sensor, and the voltage at the external pin is not
available in Rx mode, if the ASK demodulator is active or if AGC is enabled.
2.
Readback of the ADC value is valid in Tx mode only if the log amp/RSSI has not been disabled through the power-down bits R8_DB10. The log amp/RSSI section is
active per default upon enabling Tx mode.
3.
Readback of the AFC word is valid in Rx mode only if either the linear demodulator or the correlator/demodulator is active.
4.
See the Readback Format section for more information.
Rev. PrH | Page 34 of 40
Preliminary Technical Data
ADF7020
PA (Rx MODE)
0
1
PA OFF
PA ON
ADC
ENABLE
FILTER
ENABLE
LNA/MIXER
ENABLE
VCO
ENABLE
SYNTH
ENABLE
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
PD7
SW1
LR2
LR1
PD6
PD5
PD4
PD3
PD2
PD1
C4(1)
C3(0)
C2(0)
C1(0)
PD4
Tx/Rx SWITCH
0
1
DEFAULT (ON)
OFF
LOG AMP/
RSSI
CONTROL
BITS
PLE1
(FROM REG 0)
PD2
PD1
LOOP
CONDITION
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
VCO/PLL OFF
PLL ON
VCO ON
PLL/VCO ON
PLL/VCO ON
LR2
LR1
RSSI MODE
PD3
LNA/MIXER ENABLE
X
X
0
1
RSSI OFF
RSSI ON
0
1
LNA/MIXER OFF
LNA/MIXER ON
PD6
DEMOD ENABLE
PD4
FILTER ENABLE
0
1
DEMOD OFF
DEMOD ON
0
1
FILTER OFF
FILTER ON
PD5
ADC ENABLE
0
1
ADC OFF
ADC ON
Figure 36.
Notes:
1.
For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition.
2.
It is not necessary to write to this register under normal operating conditions.
Rev. PrH | Page 35 of 40
01975-PrG-036
PD9
DEMOD
ENABLE
DB14
INTERNAL Tx/Rx
SWITCH ENABLE
DB15
PA ENABLE
Rx MODE
REGISTER 8—POWER-DOWN TEST REGISTER
ADF7020
Preliminary Technical Data
AUTO AGC
HOLD SETTING
FG2
FG1
FILTER GAIN
GC1 GAIN CONTROL
0
0
1
1
0
1
0
1
8
24
72
INVALID
0
1
AUTO
USER
DB6
DB5
DB4
DB3
DB2
DB1
DB0
GL3
GL2
GL1
C4(1)
C3(0)
C2(0)
C1(1)
DB7
GL4
DB8
DB9
GL6
GL5
DB10
GL7
DB13
GH3
0
1
DB11
DB14
GH4
GS1 AGC SEARCH
LOW
HIGH
DB12
DB15
GH5
FILTER CURRENT
0
1
GH1
DB16
GH6
FI1
ADDRESS
BITS
AGC LOW THRESHOLD
GH2
DB17
DB19
GC1
DB18
DB20
LG1
GS1
DB21
LG2
AGC HIGH THRESHOLD
GH7
DB22
FG1
GAIN
CONTROL
AGC
SEARCH
DB23
FG2
LNA
GAIN
DB24
FILTER
GAIN
FI1
DB25
DB26
DB27
DB28
DB29
DB30
DB31
DIGITAL
TEST IQ
FILTER
CURRENT
REGISTER 9—AGC REGISTER
GL7
GL6
GL5
GL4
GL3
GL2
GL1
AGC LOW
THRESHOLD
0
0
0
0
.
.
.
1
1
1
0
0
0
0
.
.
.
1
1
1
0
0
0
0
.
.
.
1
1
1
0
0
0
0
.
.
.
1
1
1
0
0
0
1
.
.
.
1
1
1
0
1
1
0
.
.
.
0
1
1
1
0
1
0
.
.
.
1
0
1
1
2
3
4
.
.
.
61
62
63
LG2
LG1
LNA GAIN
0
0
1
1
0
1
0
1
3
10
30
INVALID
0
0
0
0
.
.
.
1
1
1
0
0
0
0
.
.
.
0
0
0
0
0
0
0
.
.
.
0
0
1
0
0
0
0
.
.
.
1
1
0
0
0
0
1
.
.
.
1
1
0
0
1
1
0
.
.
.
1
1
0
1
0
1
0
.
.
.
0
1
0
Figure 37.
Notes :
1.
Default AGC_LOW_THRESHOLD = 27, default AGC_HIGH_THRESHOLD = 76. See the RSSI/AGC Section for more details.
2.
AGC high and low settings must be more than 30 apart to ensure correct operation.
3.
LNA gain of 30 is available only if LNA mode, R6_DB15, is set to zero.
Rev. PrH | Page 36 of 40
1
2
3
4
.
.
.
78
79
80
01975-PrG-037
RSSI LEVEL
GH7 GH6 GH5 GH4 GH3 GH2 GH1 CODE
Preliminary Technical Data
ADF7020
DB11
DB10
DB9
DB8
DB7
GL7
GL6
GL5
GL4
PR4
C1 (0) DB0
01975-PrG-038
DB12
DH1
C2 (1) DB1
DB13
DH2
C3 (0) DB2
DB14
DH3
C4 (1) DB3
DB15
DH4
DB4
DB16
GC1
DB5
DB17
GC2
0
1
PHASE TO I CHANNEL
PHASE TO Q CHANNEL
ADDRESS
BITS
PEAK RESPONSE
PR1
DB18
GC3
SIQ2 SELECT IQ
0
1
LEAK FACTOR
PR2
DB19
GC4
SIQ2 SELECT IQ
AGC DELAY
DB6
DB20
GC5
I/Q GAIN ADJUST
PR3
UP/DOWN
DB23
R1
DB21
DB24
PH1
UD1
DB25
PH2
SELECT
I/Q
DB26
PH3
SIQ1 DB22
RESERVED
DB27
I/Q PHASE
ADJUST
PH4
SIQ2 DB28
DB29
DB30
DB31
SELECT
I/Q
REGISTER 10—AGC 2 REGISTER
DEFAULT = 10
GAIN TO I CHANNEL
GAIN TO Q CHANNEL
DEFAULT = 10
DEFAULT = 2
Figure 38.
Note:
1.
This register is not used under normal operating conditions.
DB20 AFC ENABLE
DB19
DB18
DB17
AE1
M16
M15
M14
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
M5
M4
M3
M2
M1
C4(0)
C3(0)
C2(1)
C1(0)
01975-PrG-039
DB9
M6
DB12
M9
DB11
DB13
DB10
DB14
M11
M10
M7
DB15
M12
M8
DB16
INTERNAL
AE1 AFC
0
1
CONTROL
BITS
AFC SCALING COEFFICIENT
M13
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB28
DB29
DB30
DB31
REGISTER 11—AFC REGISTER
OFF
ON
Figure 39.
Notes:
1.
See the Internal AFC section to program AFC scaling coefficient bits.
2.
The AFC scaling coefficient bits can be programmed using the following formula:
AFC_Scaling_Coefficient = Round((500 × 224)/XTAL)
Rev. PrH | Page 37 of 40
ADF7020
Preliminary Technical Data
PRESCALER
0
1
4/5 (DEFAULT)
8/9
CS1
CAL SOURCE
0
1
INTERNAL
SERIAL IF BW CAL
ADDRESS
BITS
DB1
DB0
C1(0)
DB5
T2
C2(0)
DB6
T3
DB2
DB7
T4
C3(1)
DB8
T5
DB3
DB9
T6
DB4
DB10
T7
T1
DB11
C4(1)
DB12
T8
PLL TEST MODES
T9
COUNTER
RESET
DB13
DB18
SF1
DB14
DB19
SF2
DB15
DB20
DB17
DB21
SF3
DB22
SF5
SF4
DB23
SF6
DB16
SOURCE
DB24
CS1
OSC TEST
DB25
DEFAULT = 32. INCREASE
NUMBER TO INCREASE BW
IF USER CAL ON
Σ-∆
TEST MODES
CR1 COUNTER RESET
0
1
DEFAULT
RESET
01975-PrG-043
P
DIGITAL
TEST MODES
IMAGE FILTER ADJUST
QT1
FORCE
LD HIGH
DB26
DB27
DB28
DB29
DB30
ANALOG TEST
MUX
PRE
DB31 PRESCALER
REGISTER 12—TEST REGISTER
Figure 40.
Using the Test DAC on the ADF7020 to Implement
Analog FM DEMOD and Measuring SNR
Programming the test register, Register 12, enables the test DAC.
Both the linear and correlator/demodulator outputs can be
multiplexed into the DAC.
The test DAC allows the output of the postdemodulator filter
for both the linear and correlator/demodulators (Figure 16 and
Figure 17) to be viewed externally. It takes the 16-bit filter
output and converts it to a high frequency, single-bit output
using a second-order error feedback Σ-∆ converter. The output
can be viewed on the XCLKOUT pin. This signal, when IF filtered
appropriately, can then be used to
Setting Up the Test DAC
•
•
Digital test modes = 7: enables the test DAC, with no offset
removal.
•
Digital test modes = 10: enables the test DAC, with offset
removal.
•
Monitor the signals at the FSK/ASK postdemodulator filter
output. This allows the demodulator output SNR to be
measured. Eye diagrams can also be constructed of the
received bit stream to measure the received signal quality.
Provide analog FM demodulation.
While the correlators and filters are clocked by DEMOD_CLK,
CDR_CLK clocks the test DAC. Note that, although the test
DAC functions in a regular user mode, the best performance is
achieved when the CDR_CLK is increased up to or above the
frequency of DEMOD_CLK. The CDR block does not function
when this condition exists.
Register 13 allows a fixed offset term to be removed from the
signal (to remove the IF component in the ddt case). It also has
a signal gain term to allow the usage of the maximum dynamic
range of the DAC.
The output of the active demodulator drives the DAC, that is, if
the FSK correlator/demodulator is selected, the correlator filter
output drives the DAC.
Rev. PrH | Page 38 of 40
Preliminary Technical Data
ADF7020
REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER
01975-PrG-044
DB3
DB2
DB1
DB0
C4(1)
C3(1)
C2(0)
C1(1)
NORMAL PULSE WIDTH
2 × PULSE WIDTH
3 × PULSE WIDTH
.
.
.
16 × PULSE WIDTH
DB4
PULSE EXTENSION
0
1
0
.
.
.
1
DB6
PE1
0
0
1
.
.
.
1
DB7
PE2
0
0
0
.
.
.
1
DB8
DB12
PE1
PE3
0
0
0
.
.
.
1
CONTROL
BITS
KP
DB9
DB13
PE2
DB11
DB14
PE3
PE4
DB10
DB15
PE4
DB16
DB17
DB19
DB18
DB20
DB21
DB22
DB23
DB24
DB25
KI
DB5
PULSE
EXTENSION
TEST DAC OFFSET REMOVAL
DB26
DB27
DB28
DB29
DB30
DB31
TEST DAC GAIN
Figure 41.
Note:
1.
Because the linear demodulator’s output is proportional to frequency, it usually consists of an offset combined with a relatively low signal. The offset can be
removed, up to a maximum of 1.0 and gained to use the full dynamic range of the DAC:
DAC_input = (2^ Test_DAC_Gain) × (Signal − Test_DAC_Offset_Removal/4096)
Rev. PrH | Page 39 of 40
ADF7020
Preliminary Technical Data
OUTLINE DIMENSIONS
0.25 MIN
0.25
MIN
PIN 1
INDICATOR
TOP
VIEW
7.00
BSC SQ
37
36
0.50
BSC
0.55
0.50
0.45
48
1
5.25
4.70 SQ
2.25
BOTTOM
VIEW
25
24
12
13
5.50 BSC
1.50
1.45
1.40
0.05 MAX
0.02 NOM
SEATING
PLANE
0.35
0.20
0.25
COPLANARITY
0.05
Figure 42. 48-Lead Micro Lead Frame Chip Scale Package [MLFCSP]
(CP-48M)
7 mm × 7 mm Body
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADF7020BCP
Temperature Range
−40°C to +85°C
Package Description
48-Lead Micro Lead Frame Chip Scale Package [MLFCSP]
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR01975–0–6/04(PrH)
Rev. PrH | Page 40 of 40
Package Option
CP-48M
Similar pages