HI-8425, HI-8426 November 2015 8-Channel, Ground /Open, or Supply / Open Sensor 4-channel 200 mA Ground / Open Driver GENERAL DESCRIPTION · Airbus ABD0100H compliant sense inputs The HI-8425 is a combined 8-channel discrete-to-digital sensor and quad low side driver fabricated with Silicon-onInsulator (SOI) technology for robust latch-up free operation. Sense detection can either be GND/Open or Supply/Open as configured by the SNSE_SEL pin. Supply/Open sensing is also referred to as 28V/Open sensing. The sensing circuit window comparator thresholds can be fixed at the internal programmed values or can be set externally at the HI_SET and LO_SET pins, as selected by the THS_SEL pin. The digital SENSE outputs can be tristated by taking the OE pin high. · 4 Low-Side 200 mA drivers The HI-8426 puts all of the features of the HI-8425 except the individual Fault Detection Outputs, Tri-state pin selection and fixed internal thresholds into a 32-pin Chip Scale Package (QFN) which measures only 5mm x 5mm. · Diode Clamps for Discharging Inductive Loads APPLICATIONS · Avionics Discrete to Digital Sensing · Relay Driver · Lamp driver · Discrete Signaling PIN CONFIGURATIONS VWET - 1 SENSE0 - 2 SENSE1 - 3 SENSE2 - 4 SENSE3 - 5 SENSE4 - 6 SENSE5 - 7 SENSE6 - 8 SENSE7 - 9 OE - 10 HI-8425PCI HI-8425PCT HI-8425PCM 30 29 - FAULT_0 28 - DRV_0 27 - DRV_1 26 - FAULT_1 25 - GND 24 - FAULT_2 23 - DRV_2 22 - DRV_3 21 - FAULT_3 40 Pin Plastic 6mm x 6mm Chip-scale package (QFN) 32 - VWET 31 - VLOGIC 30 - HI_SET 29 - LO_SET 28 - SNSE_SEL 27 - DSEL_0 26 - DSEL_1 25 - DSEL_2 Interface to the digital subsystem is simple CMOS logic inputs and outputs. The logic pins are compatible with 5V or 3.3V logic allowing direct connection to a wide range of microcontrollers or FPGAs. · Max Power Dissipation Automatically Limited by Fault Protection 40 - VLOGIC 39 - THS_SEL 38 - HI_SET 37 - LO_SET 36 - SNSE_SEL 35 - FAULT_OR 34 - DSEL_0 33 - DSEL_1 32 - DSEL_2 31 - DSEL_3 The HI-8425 also offers four low side switches each capable of sinking 200 mA of current. Each switch transistor is controlled by its own digital input pin and is fully fault protected. Over-current conditions, such as a short circuit, are detected and inhibited while signaling the fault condition at the corresponding logic output. These four FAULT outputs are also available in a combined OR output. The outputs are fully protected from transients when driving relays. · Over-Current Fault Detection Signaled by Logic Output SO_0 - 11 SO_1 - 12 SO_2 - 13 SO_3 - 14 SO_4 - 15 SO_5 - 16 SO_6 - 17 SO_7 - 18 GND - 19 - 20 All sense inputs are internally lightning protected to DO160G, Section 22, Cat AZ, BZ and ZZ without external components. · 4.5 Ohm On Resistance · Robust CMOS Silicon-on-Insulator (SOI) technology · Sense Detection Range 3V to 22V · Logic Operation from 3.0V to 5.5V · Lightning Protected Sense Inputs (DS8425 Rev. F) SO_0 SO_1 SO_2 SO_3 SO_4 SO_5 SO_6 SO_7 · Selectable Thresholds and Hysteresis - · 8-channel Selectable Sense Operation, GND/Open or Supply/Open HI-8426PCI HI-8426PCT HI-8426PCM 24 - DSEL_3 23 - DRV0 22 - DRV1 21 - GND 20 - DRV_2 19 - DRV_3 18 - FAULT_OR 17 - GND 9 10 11 12 13 14 15 16 FEATURES SENSE0 - 1 SENSE1 - 2 SENSE2 - 3 SENSE3 - 4 SENSE4 - 5 SENSE5 - 6 SENSE6 - 7 SENSE7 - 8 32 Pin Plastic 5mm x 5mm Chip-scale package (QFN) (See page 15 for leaded QFP package options) HOLT INTEGRATED CIRCUITS www.holtic.com 11/15 HI-8425, HI-8426 BLOCK DIAGRAM VLOGIC VWET VLOGIC THS_SEL VREF_HI VOLTAGE REFERENCE VREF_LO VTHI/10 SNSE_SEL VTLO/10 HI_SET LO_SET VWET VLOGIC SNSE_SEL + 23.8k SENSE_0 SENSE_1 SENSE_2 SENSE_3 SENSE_4 SENSE_5 SENSE_6 SENSE_7 - 3.3k LIGHTNING PROTECTION 29k + - 360k SNSE_SEL 40k SO_0 SO_1 SO_2 SO_3 SO_4 SO_5 SO_6 SO_7 OE DSEL_0 DSEL_1 DSEL_2 DSEL_3 DRV_0 DRV_1 DRV_2 DRV_3 Drive Control Current Sense GND FAULT_0 FAULT_1 FAULT_2 FAULT_3 FAULT_OR GND Figure 2 HOLT INTEGRATED CIRCUITS 2 HI-8425, HI-8426 PIN DESCRIPTIONS SYMBOL FUNCTION DESCRIPTION Optional input to supply relay wetting current to sense lines in GND/Open operation VWET Supply SENSE0 Discrete Input Discrete input 0. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open SENSE1 Discrete Input Discrete input 1. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open SENSE2 Discrete Input Discrete input 2. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open SENSE3 Discrete Input Discrete input 3. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open SENSE4 Discrete Input Discrete input 4. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open SENSE5 Discrete Input Discrete input 5. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open SENSE6 Discrete Input Discrete input 6. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open SENSE7 Discrete Input Discrete input 7. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open OE Digital Input If High, SO_n and fault outputs are high-impedance. OE has internal 30kΩ pull-down resistor SO_0 Digital output High if SNSE_SEL=0 and SENSE0 < VLO, or Low if SNSE_SEL=1 and SENSE0 > VHI SO_1 Digital output High if SNSE_SEL=0 and SENSE1 < VLO, or Low if SNSE_SEL=1 and SENSE1 > VHI SO_2 Digital output High if SNSE_SEL=0 and SENSE2 < VLO, or Low if SNSE_SEL=1 and SENSE2 > VHI SO_3 Digital output High if SNSE_SEL=0 and SENSE3 < VLO, or Low if SNSE_SEL=1 and SENSE3 > VHI SO_4 Digital output High if SNSE_SEL=0 and SENSE4 < VLO, or Low if SNSE_SEL=1 and SENSE4 > VHI SO_5 Digital output High if SNSE_SEL=0 and SENSE5 < VLO, or Low if SNSE_SEL=1 and SENSE5 > VHI SO_6 Digital output High if SNSE_SEL=0 and SENSE6 < VLO, or Low if SNSE_SEL=1 and SENSE6 > VHI SO_7 Digital output High if SNSE_SEL=0 and SENSE7 < VLO, or Low if SNSE_SEL=1 and SENSE7 > VHI FAULT_3 Digital output High if Driver 3 is attempting to sink excess current DRV_3 Switch Output Drain node of Ground switch driver 3 GND Supply DRV_2 Switch Output Drain node of Ground switch driver 2 FAULT_2 Digital output High if Driver 2 is attempting to sink excess current 50kΩ to GND Ground for logic and Analog Ground return for DRV0-3. GND pin and the isolated backside pad should be grounded for optimum performance and power dissipation. FAULT_1 Digital output High if Driver 1 is attempting to sink excess current DRV_1 Switch Output Drain node of Ground switch driver 1 DRV_0 Switch Output Drain node of Ground switch driver 0 FAULT_0 Digital output High if Driver 0 is attempting to sink excess current DSEL_3 Digital Input When high, turns on Driver 3. DSEL_3 has an internal 30kΩ pull-down resistor DSEL_2 Digital Input When high, turns on Driver 2. DSEL_2 has an internal 30kΩ pull-down resistor DSEL_1 Digital Input When high, turns on Driver 1. DSEL_1 has an internal 30kΩ pull-down resistor DSEL_0 Digital Input When high, turns on Driver 0. DSEL_0 has an internal 30kΩ pull-down resistor FAULT_OR Digital Output High if any Driver is attempting to sink excess current SNSE_SEL Digital Input If Low, SENSE pins are sensing Open/Gnd. If High, SENSE pins sense SUPPLY/Open LO_SET Analog input If THS_SEL is High, this pin sets the lower window comparator threshold HI_SET Analog input If THS_SEL is High, this pin sets the upper window comparator threshold THS_SEL Digital Input If THS_SEL is Low, comparator thresholds are set internally. THS_SEL has an internal 30kΩ pull-up VLOGIC Supply Logic supply. (3.0V - 5.5V) HOLT INTEGRATED CIRCUITS 3 HI-8425, HI-8426 FUNCTIONAL DESCRIPTION SENSING WETTING CURRENT The 8 Sense Channels can be configured to meet the requirements of a variety of conditions and applications. Table 1 summarizes basic function selection and Table 2 gives more details on possible threshold values. For GND/Open applications with VWET open, the wetting current with the input voltage at GND is simply (VLOGIC 0.75)/3.3k. When applying a higher voltage at the VWET pin the wetting current is (VLOGIC - 0.75)/3.3k + (VWET 4.2)/127k. Additional wetting current can be achieved by placing an external resistor and a diode between VWET and the individual sense inputs. GND/OPEN SENSING For GND/Open sensing, the SNS_SEL pin is connected to GND. Referring to the Block Diagram, Figure 2, this selection will connect a 3.3kΩ pull-up resistor through a diode to VLOGIC and a 23.8kΩ resistor through 3 diodes to VWET. These resistors give extra noise immunity for detecting the open state while providing relay wetting current. Configuring THS_SEL, HI_SET/LO_SEL and VWET as described below sets the window comparator thresholds, VTHI and VTLO, the open input voltage when open, and the input current. HI-8425 (40 pin version) - THRESHOLD SELECT The HI-8425 offers a choice between internally fixed thresholds or external thresholds provided by the user. With THS_SEL set to GND, the window comparator thresholds are fixed based on an internal reference. The high threshold, VTHI, and the low threshold, VTHLO levels may be found in Table 2. When the internal references are used the HI_SET and LO_SET pins should be connected to GND. For applications with either large GND offsets or thresholds higher than VLOGIC - 0.75V, THS_SEL is set high and the thresholds are set externally, for example by a simple resistor divider off the VLOGIC supply. In this case VTHI is equal to 10X the voltage on the HI_SET pin. VTLO is equal to 10X the voltage on the LO_SET pin. This mode allows the user complete flexibility to define the thresholds and hysteresis levels. HI-8426 (32 pin version) THRESHOLD SELECT For applications that can take advantage of the very small 32 pin chip scale package of the HI-8426, THS_SEL is not available and an internal pull-up makes it mandatory to supply HI_SET and LO_SET externally. OPEN INPUT VOLTAGE For correct operation, the VSENSE_n when open, must be higher than VTHI so SO_n will be low. This condition requires VWET to be set greater than (VTHI/0.9 + 2.25V). Various ARINC standards such as ARINC 763 define the standard “Open” signal as characterized by a resistance of 100kΩ or more with respect to signal common. The user should consider this 100kΩ to ground case when setting the thresholds. SUPPLY/OPEN SENSING The 8 Sense Channels can be configured to sense Supply/Open by connecting the SNSE_SEL pin to VLOGIC. Refering to Figure 2, a 32kΩ resistor is switched in series to provide a pull down in addition to the 400kΩ of the comparator input divider to GND. Similar to the GND/Open case configuring THS_SEL, HI_SET/LO_SEL and VWET as described below sets the window comparator thresholds, the open input voltage when open and the wetting current. THRESHOLD SELECT The threshold selections are handled in the same way as stated above for the GND/OPEN case. For THS_SEL set low, the internal reference nominally sets the window comparator. See table 2 for the VTHI and VTHLO threshold levels. For THS_SEL set high, the final thresholds are 10X the voltage set on the HI_SET and LO_SET pins. The VWET pin must be left open in the Supply/Open sensing case. WETTING CURRENT For the Supply/Open case the wetting current into the sense input is the current sunk by the effective 28kΩ to GND. For VSENSE_n = 28V, IWET is 1ma. See Figure 12. Table 1. Function Table SENSE_n SNSE_SEL OE SO_n Open or > VTHI L (GND/OPEN) L L < VTLO L (GND/OPEN) L H X L (GND/OPEN) H Z Open or < VTLO H (V+/OPEN) L H > VTHI H (V+/OPEN) L L X H (V+/OPEN) H Z H = VLOGIC, L = GND, Z = Hi-Z, X = Don’t Care, V+ = VSUPPLY See Table 2 for values of VTHI/VTLO HOLT INTEGRATED CIRCUITS 4 HI-8425, HI-8426 FUNCTIONAL DESCRIPTION Table 2. Configuration options and allowed threshold values -55C to 125C. Operation Threshold Selected Maximum HI_SET (VTHI = HI_SETx10) Minimum LO_SET (VTLO = LO_SETx10) Guaranteed High Threshold Guaranteed Low Threshold L GND/OPEN Internal - - 2.5V 1.0V L L GND/OPEN Internal - - 2.7V 1.0V 28V L L GND/OPEN Internal - - 2.55V 1.0V 3.0V 7V L H GND/OPEN External 0.4V (4.0V) 0.3V (3.0V) VTHI + 0.5V VTLO - 0.5V 3.6V 7V L H GND/OPEN External 0.4V (4.0V) 0.3V (3.0V) VTHI + 0.5V VTLO - 0.5V 3.0V to 3.6V 28V L H GND/OPEN External 2.2V (22V) 0.3V (3.0V) VTHI + 0.5V VTLO - 0.5V 3.0V to 3.6V OPEN H L V+/OPEN Internal - - 15.5V 11.0V 3.0V to 3.6V OPEN H H V+/OPEN Exernal 2.2V (22V) 0.3V (3.0V) VTHI + 0.5V VTLO - 0.5V 4.5V OPEN L L GND/OPEN Internal - - 3.25V 1.0V 5.5V OPEN L L GND/OPEN Internal - - 3.75V 1.0V 5.0V 28V L L GND/OPEN Internal - - 3.5V 1.0V 4.5V 7V L H GND/OPEN External 0.4V (4.0V) 0.3V (3.0V) VTHI + 0.5V VTLO - 0.5V 5.5V 7V L H GND/OPEN External 0.4V (4.0V) 0.3V (3.0V) VTHI + 0.5V VTLO - 0.5V 4.5V to 5.5V 28V L H GND/OPEN External 2.2V (22V) 0.3V (3.0V) VTHI + 0.5V VTLO - 0.5V 4.5V to 5.5V OPEN H L V+/OPEN Internal - - 15.5V 11.0V 4.5V to 5.5V OPEN H H V+/OPEN External 2.2V (22V) 0.3V (3.0V) VTHI + 0.5V VTLO - 0.5V SNSE_ THS_ SEL SEL VLOGIC VWET Pin 3.0V OPEN L 3.6V OPEN 3.3V NOTE: VTHI = Sense pin high threshold (HI_SET x 10), VTLO = Sense pin low threshold (LO_SET x 10) OUTPUT ENABLE OVER-CURRENT SHUTDOWN The output enable pin, OE, available on the HI-8425, tristates all Sense Outputs and Low Side Driver Fault Outputs to allow connecting the tri-state outputs in parallel with other tri-stated chips. The OE pin has a pull-down and when left open will cause these digital outputs to be driven to their logic levels. If the OE pin is High, these digital outputs are high impedance. Maximum DC power dissipation per driver is approximately 0.5W at room temperature. Conditions that would cause the power to exceed this amount will result in a shut down of the driver. Over-current shutdown is initiated when the driver pin voltage is more than approximately 1.5V from GND. However there is a delay of approximately 11μsec before the shutdown actually occurs giving the driver an opportunity to charge capacitive loads and thereby avoid shutdown. Similarly, if the driver is on and a high load is suddenly switched on, the over-current shutdown will be delayed in activation. Note that even when the over-current fault condition is present, the driver pin is still sourcing a few milliamps. This low current condition continues until the input is taken low or the load is removed. OUTPUT DRIVERS LOW SIDE DRIVERS Both product versions offer four Low Side Drivers. Each driver (NMOS switch) is capable of sinking a minimum of 200mA while exhibiting a Ron of 4.5Ω typical. Each output has diode clamps for protection during inductive kick-back for relay applications. Off-state leakage is typically less than 10nA at room temperature. The inputs, DSEL0 through DSEL3, have internal pull-downs which hold off the drivers until logic highs are presented. FAULT CONDITIONS Each driver has a converter that translates an over-current detection into a logic high output at its FAULT output. The FAULT_OR output goes high if one or more FAULT outputs are high. These outputs can be tri-stated by setting OE high. HOLT INTEGRATED CIRCUITS 5 HI-8425, HI-8426 FUNCTIONAL DESCRIPTION LIGHTNING PROTECTION All SENSE_n inputs are protected to RTCA/DO-160G, Section 22, Categories AZ and BZ, Waveforms 3, 4, 5A, with no external components. In addition, all inputs are also protected to ZZ, Waveforms 3 and 5B, to provide more robustness in composite airframe applications. Table 3 and Figure 3 give values and waveforms. See Application Note AN-305 for recommendations on lightning protection of Holt’s family of Discrete-to-Digital devices. Waveforms 3/3 4/1 5A/5A 5B/5B Voc (V) / Isc (A) Voc (V) / Isc (A) Voc (V) / Isc (A) Voc (V) / Isc (A) 2 250/10 125/25 125/125 125/125 Z 500/20 300/60 300/300 300/300 3 600/24 300/60 300/300 300/300 Level Table 3. Waveform Peak Amplitudes Voltage/Current Waveform 3 V/I (%) Peak 1.0 V (%) 1.0 50% 0.5 0.5 -0.5 0.3 I/V (%) 1.0 t Peak 1us/div. Current/Voltage Waveform 5A 0.0 50% T1 I/V (%) 1.0 0.8 Peak T1 = 6.4µs +/-20% T2 = 69µs +/-20% T2 t Current/Voltage Waveform 5B 0.8 50% 0.5 50% 0.5 0.3 0.0 Voltage Waveform 4 0.8 0.0 -1.0 Peak 0.3 T1 t T2 T1 = 40µs +/-20% T2 = 120µs +/-20% 0.0 T1 Figure 3. Lightning Waveforms HOLT INTEGRATED CIRCUITS 6 t T2 T1 = 50µs +/-20% T2 = 500µs +/-20% HI-8425, HI-8426 APPLICATION EXAMPLES VWET OPEN VLOGIC VLOGIC = 3.3V HI_SET For GND/Open SNSE_SEL = GND Low to High Threshold = 2.7V High to Low Threshold = 1.0V LO_SET GND SNSE_SEL For 28V/Open SNSE_SEL = VLOGIC Low to High Threshold = 15.5V High to Low Threshold = 11.0V GND SENSE0 SENSE1 SENSE2 SENSE3 SENSE4 SENSE5 SENSE6 SENSE7 From SENSORS THS_SEL HI-8425 SO_0 SO_1 SO_2 SO_3 SO_4 SO_5 SO_6 SO_7 OE Figure 4 Input Sensing with Internal Thresholds VWET VLOGIC OPEN VLOGIC = 3.3V 10μF 10V 0.1μF 10V 68k HI_SET = 1.12V GND 15k 3.3μF 10V LO_SET = 0.64V Low to High Threshold = 11.2V High to Low Threshold = 6.4V LO_SET 20k GND VLOGIC = 3.3V VLOGIC = 3.3V From SENSORS HI_SET SENSE0 SENSE1 SENSE2 SENSE3 SENSE4 SENSE5 SENSE6 SENSE7 3.3μF 10V SNSE_SEL THS_SEL HI-8425 SO_0 SO_1 SO_2 SO_3 SO_4 SO_5 SO_6 SO_7 OE Figure 5 Input Sensing, 28V/OPEN, Typical ABD0100H Thresholds HOLT INTEGRATED CIRCUITS 7 HI-8425, HI-8426 APPLICATION EXAMPLES VWET VLOGIC 28V VLOGIC = 3.3V 10μF 10V 0.1μF 10V 75k HI_SET = 0.97V GND HI_SET 3.3μF 10V 13k LO_SET = 0.56V LO_SET 18k Low to High Threshold = 9.7V High to Low Threshold = 5.6V 3.3μF 10V GND GND VLOGIC = 3.3V From SENSORS SENSE0 SENSE1 SENSE2 SENSE3 SENSE4 SENSE5 SENSE6 SENSE7 SNSE_SEL THS_SEL SO_0 SO_1 SO_2 SO_3 SO_4 SO_5 SO_6 SO_7 HI-8425 OE Figure 6 Input Sensing, GND/OPEN Typical ABD0100H Thresholds, 1ma wetting current V+ V+ DRV_n DRV_n HI-8425 HI-8425 DSEL_n LOAD Drive Control DSEL_n Drive Control Current Sense Current Sense GND GND FAULT_n FAULT_n Figure 7 Lowside Output Driving Relay Figure 8 Lowside Output Driving LED V+ V+ DRV_n DRV_n HI-8425 HI-8425 DSEL_n DSEL_n Drive Control Drive Control Current Sense Current Sense GND GND FAULT_n FAULT_n Figure 9 Lowside Output Driving Lamp Figure 10 Lowside Output Driving Resistive Load HOLT INTEGRATED CIRCUITS 8 HI-8425, HI-8426 APPLICATION EXAMPLES V+ DRV_n HI-8425 DSEL_n SENSE_n SENSE_n SENSE_n Drive Control Current Sense GND HI-8425 HI-8430 FAULT_n Figure 11 Lowside Output Used for Discrete Signaling with three separate users Figure 12 Input Current Vs. Input Voltage HOLT INTEGRATED CIRCUITS 9 HI-8425 HI-8425, HI-8426 RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS Voltages referenced to Ground Supply Voltage (VLOGIC) ......................... DRV_n ...................... 55V VWET ......................... -0.3V to +55V DC Driver Current per pin ......................... Logic Input Voltage Range ................ -0.3V to VLOGIC+0.3V Discrete Input Voltage Range Supply Voltage -0.3V to +7V ................................. 3.0V to 5.5V VWET ................................. 7.0V to 36V Operating Temperature Range Industrial Screening ............. -40°C to +85°C Hi-Temp Screening ............. -55°C to +125°C 300mA .................. VLOGIC -80V to +80V Continuous Power Dissipation (TA=+70°C) QFN (derate 21.3mW/°C above +70°C) ........ QFP (derate 10.0mW/°C above +70°C) ........ 1.7W 1.5W Solder Temperature (reflow) 260°C ........................... Junction Temperature ............................. 175°C Storage Temperature ............................ -65°C to -150°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. D.C. ELECTRICAL CHARACTERISTICS VDD = 3.3V or 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS DISCRETE INPUTS SENSE V+/OPEN Resistance to Ground SEN_SEL = High, VWET floating RIN Case 1: THS_SEL = GND Internal Threshold Mode Open State Input Voltage VOS Input voltage to give High output V+ State Input Voltage VV+ Input voltage to give Low output Input Current at 28V IIN28 VIN = 28V Hysteresis kΩ 30 VHY Case 2: THS_SEL = Open or VLOGIC 11.0 15.5 V V 0.95 mA 1.5 V HI_SET/LO_SET pin set Thresholds HI_SET Threshold Range VTHI HI Threshold is set to HI_SET X 10 0.4 2.2 V LO_SET Threshold Range VTLO LO Threshold is set to LO_SET X 10 0.3 2.1 V Min Threshold Window VTHW HI_SET > LO_SET 0.1 Sense Threshold Accuracy Voltage referred to the sense input, see table 2 HOLT INTEGRATED CIRCUITS 10 VTLO - 25% V VTHI + 25% V HI-8425, HI-8426 D.C. ELECTRICAL CHARACTERISTICS (cont) VDD = 3.3V or 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS DISCRETE INPUTS SENSE GND/OPEN Resistance in series with diode to VLOGIC RIN 3.3 kΩ Resistance in series with diode to VWET RW 23.8 kΩ Case 1: THS_SEL = GND Internal Threshold Mode Ground State Input Voltage VGS Input voltage to give High output Open State Input Voltage VOS Input voltage to give Low output VDD = 5.5V VDD = 3.0V Input Current at 0V IIN28 Hysteresis VHY 1.0 3.75 2.5 V -0.65 -1.65 VIN = 0V, VDD = 3.0V VIN = 0V, VDD = 5.5V V mA mA 0.15 V HI_SET/LO_SET pins set Thresholds Case 2: THS_SEL = Open or VLOGIC HI_SET Threshold Range VTHI HI Threshold is set to HI_SET X 10 0.4 2.2 V LO_SET Threshold Range VTLO LO Threshold is set to LO_SET X 10 0.3 2.1 V Min Threshold Window VTHW HI_SET > LO_SET Voltage referred to the sense input, see table 2 Sense Threshold Accuracy 0.1 V VTHI + 25% VTLO - 25% V LOGIC INPUTS Input Voltage Input Current, OE, DSEL_n VIH Input Voltage HI VIL Input Votage LO ISINK ISOURCE Input Current, THS_SEL ISINK ISOURCE Input Current, SNSE_SEL ISINK ISOURCE 80% VLOGIC 20% VIN = VLOGIC, 30kΩ pull down 125 VIN = VLOGIC μA 0.1 VIN = GND 0.1 VIN = GND , 30kΩ pull up VLOGIC μA μA 125 μA VIN = VLOGIC 0.1 μA VIN = GND, 0.1 μA HOLT INTEGRATED CIRCUITS 11 HI-8425, HI-8426 D.C. ELECTRICAL CHARACTERISTICS (cont) VDD = 3.3V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). LOGIC OUTPUTS Output Voltage Output Current VOH IOH = -100μA VOL IOL = 100μA IOL VOUT= 0.4V IOH VOUT = VLOGIC - 0.4V Tri-State Leakage Current ITSL Output Capacitance CO PARAMETER SYMBOL 90% VLOGIC 10% 1.6 VLOGIC > Vout > GND VLOGIC mA -1.0 -1.0 mA 1.0 μA 15 CONDITION MIN TYP pF MAX UNITS 1.0 μA 8 Ω ANALOG INPUTS HI_SET/LO_SET Leakage Current IL Max leakage for VLOGIC > Vinput > GND -0.1 LOW SIDE DRIVERS On Resistance Over Current Threshold Over Current Delay RON VDCMAX ISOURCE = 200mA See Figure 16 Maximum VDS before current limiting. See Figure 17 4.5 1.5 5 V TOC Period that Driver sinks max current. See Figure 17 11 μs IDD1 All Sense Pins Open 10 mA All Sense Inputs = 0V, VWET = 28V 20 mA SUPPLY CURRENT VLOGIC Current VWET Current IVWET HOLT INTEGRATED CIRCUITS 12 HI-8425, HI-8426 AC ELECTRICAL CHARACTERISTICS VDD = 3.3V or 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS SENSE V+/OPEN Delay, Output going High tH1 See Figure 13, THS_SEL = GND, 25°C 1.0 μs Delay, Output going Low tL1 See Figure 13, THS_SEL = GND, 25°C 1.0 μs Delay, Output going High tH2 See Figure 14, THS_SEL = GND, 25°C 1.0 μs Delay, Output going Low tL2 See Figure 14, THS_SEL = GND, 25°C 1.0 μs Tri-state Delay, On tTSON See Figure 15, THS_SEL = GND, 25°C 40 ns Tri-state Delay, Off tTSOFF See Figure 15, THS_SEL = GND, 25°C 40 ns SENSE GND/OPEN TRI-STATE DELAY HIGH SIDE DRIVERS Turn On Delay, DSEL_N tSON See Figure 16, VLOGIC = 3.3V, 25°C Turn Off Delay, DSEL_N tSOFF See Figure 16, VLOGIC = 3.3V, 25°C 900 ns Fault Output Delay, On tFON See Figure 17, VLOGIC = 3.3V, 25°C 15 μs Fault Output Delay, Off tFOFF See Figure 17, VLOGIC = 3.3V, 25°C 15 μs HOLT INTEGRATED CIRCUITS 13 400 ns HI-8425, HI-8426 TEST CIRCUIT AND TIMING DIAGRAMS 28V SENSE_n 12V tR = tF = 1μs SENSE_n GND SO_n tH1 tL1 15pf 3.3V HI-8425 SO_n Figure 13 28V/Open Output Delay VLOGIC SO_n 5k 15pf SO_n 5k 2.5V SENSE_n tR = tF = 1μs 3.3V OE 1.8V 50% tR = tF = 10ns GND tH2 tL2 3.3V 3.3V tTSON tTSOFF 90% SO_n SO_n Figure 14 GND/Open Output Delay Figure 15 Sense Enable Output Delay 28V 28V 100pf 134Ω 1.65V 10% Short to V+ DRV_n DRV_n 3.3V DSEL_n tR = tF = 10ns 3.3V DSEL_n tR = tF = 10ns 50% 50% 28V tTSON DRV_n tTSOFF 90% tFON FAULT_n 10% Figure 16 Low Side Driver Output Delay 3.3V tFOFF 50% Figure 17 Low Side Driver Fault Delay HOLT INTEGRATED CIRCUITS 14 HI-8425, HI-8426 ORDERING INFORMATION HI - 842xxx x x LEAD FINISH PART NUMBER Blank Tin / Lead (Sn /Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) F TEMPERATURE RANGE PART NUMBER FLOW BURN IN I -40°C TO +85°C I NO T -55°C TO +125°C T NO M -55°C TO +125°C M YES PART NUMBER PACKAGE DESCRIPTION 40 PIN PLASTIC CHIP SCALE (40PCS) 8425PQ 44 PIN PLASTIC QUAD FLAT PACK (44PMQS) 8426PC 32 PIN PLASTIC CHIP SCALE (32PCS) 8426PQ 32 PIN PLASTIC QUAD FLAT PACK (32PQS) 32 31 30 29 28 27 26 25 44 43 42 41 40 39 38 37 36 35 34 - VWET - VLOGIC - HI_SET - LO_SET - SNSE_SEL - DSEL_0 - DSEL_1 - DSEL_2 - N/C - VLOGIC - THS_SEL - HI_SET - LO_SET - SNSE_SEL - FAULT_OR - DSEL_0 - DSEL_1 - DSEL_2 - DSEL_3 8425PC -1 -2 -3 -4 -5 -6 -7 -8 HI-8426PQI HI-8426PQT HI-8426PQM 24 - DSEL_3 23 - DRV0 22 - DRV1 21 - GND 20 - DRV_2 19 - DRV_3 18 - FAULT_OR 17 - GND N/C - 1 VWET - 2 SENSE0 - 3 SENSE1 - 4 SENSE2 - 5 SENSE3 - 6 SENSE4 - 7 SENSE5 - 8 SENSE6 - 9 SENSE7-10 N/C -11 HI-8425PQI HI-8425PQT HI-8425PQM 33 - NC 32 - FAULT_0 31 - DRV_0 30 - DRV_1 29 - FAULT_1 28 - GND 27 - FAULT_2 26 - DRV_2 25 - DRV_3 24 - FAULT_3 23 - N/C OE - 12 SO_0 - 13 SO_1 - 14 SO_2 - 15 SO_3 - 16 SO_4 - 17 SO_5 - 18 SO_6 - 19 SO_7 - 20 GND - 21 N/C - 22 SO_0 - 9 SO_1 - 10 SO_2 - 11 SO_3 - 12 SO_4 - 13 SO_5 - 14 SO_6 - 15 SO_7 - 16 SENSE0 SENSE1 SENSE2 SENSE3 SENSE4 SENSE5 SENSE6 SENSE7 32 - Pin Plastic Quad Flat Pack (PTQFP) 7mm x 7mm body 44 - Pin Plastic Quad Flat Pack (PQFP) 10mm x 10mm body HOLT INTEGRATED CIRCUITS 15 HI-8425, HI-8426 REVISION HISTORY P/N Rev DS8425 NEW A Date 12/03/12 03/11/13 B 03/25/13 C D 08/20/13 10/23/13 E 02/25/15 F 11/03/15 Description of Change Initial Release Correct reference to pull-up resistor on inputs from 3.5k to 3.3k. Update VWET estimation formulas. Clarify VWET value for GND/Open and V+/Open sense options in DC Characteristics table. Update Figure 12 Input Current vs. Input Voltage charts. Delete Sensing Application Table. Add more detailed Table 2 instead. Updated Electrical Characteristics Corrected typos in internal threshold limits for V+/Open with VWET open. Was 11.5V. Should be 11.0V. Updated Discrete Input Voltage Range from +/-60V to +/-80V. Add “M-Grade” to PQFP and QFN package options. Reference AN-305 for lightning protection. Clarify ABD0100H compliance of sense inputs. Update QFN-32, QFP-44 and QFP-32 package drawings. Clarify voltage range for VWET. Clarify Sense Threshold Accuracy parameter. HOLT INTEGRATED CIRCUITS 16 PACKAGE DIMENSIONS millimeters 40-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) 6.00 ± .10 Electrically isolated pad on bottom of package. Connect to any ground or power plane for optimum thermal dissipation. Package Type: 40PCS 4.1 ± .05 0.50 BSC 6.00 ± .10 4.1 ± .05 0.25 typ. 0.40 ± .05 See Detail A 0.90 ± .10 0.2 typ 0.90 ± .10 0.02 typ. BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) Detail A 32-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) 5.000 BSC (0.197) Electrically isolated heat sink pad on bottom of package. Connect to any ground or power plane for optimum thermal dissipation. millimeters (inches) Package Type: 32PCS 3.400 ± 0.050 (0.134 ± 0.002) 0.50 BSC (0.0197) 5.000 BSC (0.197) 3.400 ± 0.050 (0.134 ± 0.002) Top View 1.00 max (0.039) 0.200 typ (0.008) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 17 Bottom View 0.25 (0.010) typ 0.400 ± 0.050 (0.016 ± 0.002) PACKAGE DIMENSIONS millimeters (inches) 44-PIN PLASTIC QUAD FLAT PACK (PQFP) Package Type: 44PMQS 0.230 MAX. (0.009) 0.80 BSC (0.031) 10.000 BSC (0.394) SQ. 13.200 BSC (0.520) SQ. 0.370 ± 0.080 (0.015 ± 0.003) 0.880 ± 0.150 (0.035 ± 0.006) 1.60 typ (0.063) 0.20 min (0.008) See Detail A 2.70 MAX. (0.106) 0.30 R MAX. (0.012) 2.00 ± 0.20 (0.079 ± 0.008) 0.13 R MIN. Detail A (0.005) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 0° £ Q £ 7° millimeters (inches) 32 PIN PLASTIC QUAD FLAT PACK (PQFP) Package Type: 32PQS 0.145 ± 0.055 (0.006 ± 0.002) 9.00 BSC sq. (0.354) 0.80 BSC (0.031) 7.00 BSC sq. (0.276) 0.375 ± 0.075 (0.015 ± 0.003) 0.60 ± 0.150 (0.024 ± 0.006) 1.00 ± 0.05 (0.039 ± 0.002) 0.20 R (0.008) max See Detail A 0° £ Q £ 7° 1.20 max (0.047) 0.004 ± 0.002 (0.10 ± 0.05) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 0.08 R (0.003) min Detail A HOLT INTEGRATED CIRCUITS 18