Holtek HT45R35 C/r to f type 8-bit otp mcu Datasheet

HT45R35
C/R to F Type 8-Bit OTP MCU
Features
· Operating voltage:
· Power Down and Wake-up function reduce power
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
consumption
· Up to 0.5ms instruction cycle with 8MHz system clock
· 16 bidirectional I/O lines
at VDD=5V
· Two external interrupt inputs shared with I/O lines
· All instructions executed in one or two machine
· 8-bit programmable timer/event counter with
cycles
· 14-bit table read instruction
overflow interrupt and 7-stage prescaler
· External RC oscillation converter
· Four-level subroutine nesting
· On-chip crystal and RC oscillator
· Bit manipulation instruction
· Watchdog Timer
· 63 powerful instructions
· 12 capacitor/resistor sensor input
· Low voltage reset function
· 2048´14 program memory
· 16-pin DIP/NSOP, 20-pin DIP/SOP,
24/28-pin SKDIP/SOP, 28-pin SSOP and
32-pin QFN packages
· 120´8 data memory RAM
General Description
The HT45R35 is an 8-bit high performance, RISC architecture microcontroller device specifically designed for
cost-effective multiple I/O control product applications.
wake-up functions, Watchdog Timer, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer
products, subsystem controllers, etc.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, Power Down and
Rev. 1.20
1
January 29, 2010
HT45R35
Block Diagram
P A 0 /IN T 0 /R C 1
P A 1 /IN T 1 /R C 2
S T A C K 0
P ro g ra m
R O M
In te rru p t
C ir c u it
S T A C K 1
P ro g ra m
C o u n te r
T M R C
IN T C
M
T M R
U
P r e s c a le r
X
W D T S
In s tr u c tio n
R e g is te r
M
M P
U
X
D a ta
M e m o ry
P A C
P A 0
P A 1
P A 2
P A 3
P A 5
P A 7
P O R T A
P A
M U X
In s tr u c tio n
D e c o d e r
A L U
P B C
P O R T B
S ta tu s
T im e r B
O S C 2
O S
R E
V D
V S
C 1
S
S
A C C
A n a lo g
S w itc h
D
R C
O s c illa tio n
Rev. 1.20
M
T im e r A
2
R C
C lo c k
/IN
/IN
/T
/R
/R
/R
T 0 /R
T 1 /R
M R /R
C 4 , P
C 1 0 ,
C 1 2
U
S y s te m
C lo c k /4
X
C 1
C 2
R C
O S C
C 3
A 4 /R C 9
P A 6 /R C 1 1
P B 0 ~ P B 7
P B
S h ifte r
T im in g
G e n e ra to r
M
W D T
W D T P r e s c a le r
S y s te m
P A 2 /T M R /R C 3
U
S y s te m
S y s te m
X
C lo c k
C lo c k /4
O s c illa tio n O u tp u t
R C 1 ~ R C 1 2
R C O U T
IN
R R E F
C R E F
January 29, 2010
HT45R35
Pin Assignment
P B 3
1
2 4
P B 4
P B 2
2
2 3
P B 5
P A 3 /P B 3 /T M R 1 /R C 4
1
2 0
P A 4 /P B 4 /R C 9
P B 1
3
2 2
P B 6
P A 2 /P B 2 /T M R 0 /R C 3
2
1 9
P A 5 /P B 5 /R C 1 0
P B 0
4
2 1
P B 7
V S S
1
1 6
O S C 2
P B 1
3
1 8
P B 6
V S S
5
2 0
O S C 2
C R E F
2
1 5
O S C 1
P B 0
4
1 7
P B 7
C R E F
6
1 9
O S C 1
R R E F
3
1 4
V D D
V S S
5
1 6
O S C 2
R R E F
7
1 8
V D D
R C O U T /IN
4
1 3
R E S
C R E F
6
1 5
O S C 1
R C O U T /IN
8
1 7
R E S
P A 0 /IN T 0 /R C 1
5
1 2
P A 7 /R C 1 2
R R E F
7
1 4
V D D
P A 0 /IN T 0 /R C 1
9
1 6
P A 7 /R C 1 2
P A 1 /IN T 1 /R C 2
6
1 1
P A 6 /R C 1 1
R C O U T /IN
8
1 3
R E S
P A 1 /IN T 1 /R C 2
1 0
1 5
P A 6 /R C 1 1
P A 2 /T M R 0 /R C 3
7
1 0
P A 5 /R C 1 0
P A 0 /IN T 0 /R C 1
9
1 2
P A 7 /R C 1 2
P A 2 /T M R 0 /R C 3
1 1
1 4
P A 5 /R C 1 0
P A 3 /T M R 1 /R C 4
8
9
P A 4 /R C 9
P A 1 /IN T 1 /R C 2
1 0
1 1
P A 6 /R C 1 1
P A 3 /T M R 1 /R C 4
1 2
1 3
P A 4 /R C 9
H T 4 5 R 3 5
1 6 D IP -A /N S O P -A
H T 4 5 R 3 5
2 0 D IP -B /S O P -B
H T 4 5 R 3 5
2 4 S K D IP -B /S O P -B
1
2 8
P B 4
P B 2
2
2 7
P B 5
P B 1
3
2 6
P B 6
P B 0
4
2 5
P B 7
V S S
5
2 4
O S C 2
C R E F
6
2 3
O S C 1
R R E F
7
2 2
V D D
R C O U T /IN
8
2 1
R E S
P A 0 /IN T 0 /R C 1
9
2 0
P A 7 /R C 1 2
P A 1 /IN T 1 /R C 2
1 0
1 9
P A 6 /R C 1 1
P A 2 /T M R 0 /R C 3
1 1
1 8
P A 5 /R C 1 0
9 1 0 1 1 1 2 1 3 1 4 1 5 1 6
P A 3 /T M R 1 /R C 4
1 2
1 7
P A 4 /R C 9
R C 5
1 3
1 6
R C 8
P A 5
P A 4
R C 8
R C 7
R C 6
R C 5
P A 3
P A 2
R C 6
1 4
1 5
R C 7
O S C 2
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
P B 1
P B 3
C
R
R C O U
P A 0 /IN T 0
P A 1 /IN T 1
P B 0
N C
V S S
R E F
R E F
T /IN
/R C 1
/R C 2
3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5
1
2
2 4
N C
2 2
N C
2 3
3
H T 4 5 R 3 5
3 2 Q F N -A
4
5
6
2 1
2 0
1 9
1 8
7
8
O S
V D
R E
P A
P A
D
C 1
S
7 /R C 1 2
6 /R C 1 1
/R C 1 0
/R C 9
/T M R 1 /R C 4
/T M R 0 /R C 3
H T 4 5 R 3 5
2 8 S K D IP -A /S O P -A /S S O P -A
1 7
N C
Pin Description
Pin Name
I/O
Options
Description
PA0/INT0/RC1
PA1/INT1/RC2
PA2/TMR/RC3
PA3/RC4
PA4/RC9
PA5/RC10
PA6/RC11
PA7/RC12
I/O
Pull-high*
Wake-up
Bidirectional 8-bit I/O port. Each pin can be configured as a wake-up input
via configuration options. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Pull-high resistors can be added to
the each pin via a configuration option.
Pins PA0 and PA1 are pin-shared with external interrupt input pins INT0
and INT1, respectively. Configuration options determine the interrupt enable/disable and the interrupt low/high trigger type. Pins PA2 is
pin-shared with the external timer input pins TMR.
Each Pin of PA0~PA3 and PA4~PA7 are pin-shared with RC1~RC4 and
RC9~RC12 respectively via configuration options.
RC1~RC4 and RC9~RC12 are capacitor or resistor connection pins.
PB0~PB7
I/O
Pull-high*
Bidirectional 8-bit I/O port. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Pull-high resistors can be added to
the each pin via a configuration option.
RC5~RC8
I
¾
Capacitor or resistor connection pins
RCOUT
I
¾
Capacitor or resistor connection pin to RC OSC
IN
I
¾
Oscillation input pin
RREF
O
¾
Reference resistor connection pin
CREF
O
¾
Reference capacitor connection pin
Rev. 1.20
3
January 29, 2010
HT45R35
Pin Name
I/O
Options
Description
RES
I
¾
Schmitt trigger reset input. Active low
VSS
¾
¾
Negative power supply, ground
VDD
¾
¾
Positive power supply
OSC1
OSC2
I
O
Crystal or RC
OSC1, OSC2 are connected to an RC network or Crystal determined by a
configuration option, for the internal system clock. In the case of the RC
oscillator, OSC2 can be used to monitor the system clock. Its frequency is
1/4 system clock.
Note: *All pull-high resistors are controlled by an option bit.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
IOL Total ..............................................................150mA
IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
VDD
IDD1
Parameter
Operating Voltage
Operating Current
(Crystal OSC, RC OSC)
Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
fSYS=4MHz
2.2
¾
5.5
V
fSYS=8MHz
3.3
¾
5.5
V
¾
1
2
mA
¾
3
5
mA
¾
4
8
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
VDD
¾
3V
Conditions
No load, fSYS=4MHz
5V
IDD2
Operating Current
(Crystal OSC, RC OSC)
ISTB1
Standby Current
(WDT Enabled)
3V
Standby Current
(WDT Disabled)
3V
VIL1
Input Low Voltage for I/O Ports,
TMR, INT0 and INT1
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR, INT0 and INT1
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
LVR enabled
2.7
3.0
3.3
V
IOL
4
8
¾
mA
I/O, RREF and CREF Sink Current
10
20
¾
mA
ISTB2
5V
No load, fSYS=8MHz
No load, system HALT
5V
No load, system HALT
5V
3V
VOL=0.1VDD
5V
Rev. 1.20
4
January 29, 2010
HT45R35
Symbol
IOH
RPH
RPL
Parameter
I/O, RREF and CREF Source
Current
Test Conditions
VDD
3V
Conditions
VOH=0.9VDD
5V
Min.
Typ.
Max.
Unit
-2
-4
¾
mA
-5
-10
¾
mA
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
Pull-high Resistance
RC1~RC12 Pull-low Resistance
A.C. Characteristics
Symbol
fSYS
fTIMER
Parameter
System Clock
(Crystal OSC, RC OSC)
Timer I/P Frequency
tWDTOSC Watchdog Oscillator Period
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
11
23
46
ms
8
17
33
ms
tWDT1
Watchdog Time-out Period
(WDT RC OSC)
3V
tWDT2
Watchdog Time-out Period
(System Clock/4)
¾
Without WDT prescaler
¾
1024
¾
tSYS
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Reset Time
¾
¾
0.25
1
2
ms
Without WDT prescaler
5V
Wake-up from HALT
Note: *tSYS=1/fSYS
Rev. 1.20
5
January 29, 2010
HT45R35
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, a conditional skip
execution, loading the PCL register, a subroutine call,
an initial reset, an internal interrupt, an external interrupt
or return from a subroutine, the PC manipulates the program transfer by loading the address corresponding to
each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter - PC
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise the program will proceed with the next instruction.
The program counter, PC controls the sequence in
which the instructions stored in program ROM are executed and its contents specify full range of program
memory.
The lower byte of the program counter, PCL is a readable and writable register. Moving data into the PCL performs a short jump. The destination must be within the
current Program Memory Page.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
When a control transfer takes place, an additional
dummy cycle is required.
S y s te m
C lo c k
O S C 2 (R C
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
External Interrupt 0
0
0
0
0
0
0
0
0
1
0
0
External Interrupt 1
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
0
1
1
0
0
External RC Oscillation Converter Interrupt
0
0
0
0
0
0
1
0
0
0
0
Skip
Program Counter+2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *10~*0: Program Counter bits
S10~S0: Stack register bits
#10~#0: Instruction code bits
Rev. 1.20
@7~@0: PCL bits
6
January 29, 2010
HT45R35
· Location 010H
Program Memory
This location is reserved for the external RC oscillation converter interrupt service program. If an interrupt
results from an external RC oscillation converter, and
if the interrupt is enabled and the stack is not full, the
program begins execution at this location.
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
2048´14 bits, addressed by the program counter and table pointer.
· Table location
Certain locations in the program memory are reserved
for special usage:
Any location in the program memory can be used as a
look-up table. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
transfer the contents of the lower-order byte to the
specified data memory, and the higher-order byte to
TBLH. Only the destination of the lower-order byte in
the table is well-defined, the other bits of the table
word are transferred to the lower portion of TBLH, and
the remaining 2 bits are read as ²0². The Table
Higher-order byte register, TBLH, is read only. The table pointer, TBLP, is a read/write register, which indicates the table location. Before accessing the table,
the location must be placed in TBLP. The TBLH register is read only and cannot be restored. If the main
routine and the ISR (Interrupt Service Routine) both
employ the table read instruction, the contents of the
TBLH in the main routine are likely to be changed by
the table read instruction used in the ISR and errors
may occur. Therefore, using the table read instruction
in the main routine and also in the ISR should be
avoided. However, if the table read instruction has to
be used in both the main routine and in the ISR, the interrupt should be disabled prior to the table read instruction execution. The interrupt should not be
re-enabled until TBLH has been backed up. All table
related instructions require two cycles to complete the
operation. These areas may function as normal program memory depending upon the requirements.
· Location 000H
This area is reserved for program initialisation. After a
device reset, the program always begins execution at
location 000H.
· Location 004H
This location is reserved for the external interrupt 0
service program. If the INT0 input pin is activated, the
interrupt is enabled and the stack is not full, the program begins execution at this location.
· Location 008H
This location is reserved for the external interrupt 1
service program. If the INT1 input pin is activated, the
interrupt is enabled and the stack is not full, the program begins execution at this location.
· Location 00CH
This location is reserved for the Timer/Event Counter
interrupt service program. If a Timer interrupt results
from a Timer/Event Counter overflow, and the interrupt is enabled and the stack is not full, the program
begins execution at this location.
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
E x te rn a l In te rru p t 0
0 0 8 H
E x te rn a l In te rru p t 1
0 0 C H
T im e r /E v e n t C o u n te r O v e r flo w
0 1 0 H
E x te r n a l R C O s c illa tio n
C o n v e rte r In te rru p t
n 0 0 H
n F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
7 0 0 H
7 F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
P ro g ra m
M e m o ry
Stack Register - STACK
This is a special part of the memory which is used to save
the contents of the program counter only. The stack is
organised into 4-levels and is neither part of the data nor
part of the program space, and is neither readable nor
writable. The activated level is indexed by the stack
pointer, SP and is neither readable nor writeable. At a
subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled
1 4 - B its
N o te : n ra n g e s fro m 0 to 7
Program Memory
Instruction
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *10~*0: Table location bits
P10~P8: Current program counter bits
@7~@0: Table pointer bits
Rev. 1.20
7
January 29, 2010
HT45R35
by a return instruction, RET or RETI, the program counter
is restored to its previous value from the stack. After a device reset, the stack pointer will point to the top of the
stack.
0 0 H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost as only the most recent 4 return addresses are stored.
0 4 H
B P
0 5 H
A C C
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
0 D H
T M R
0 E H
T M R C
Data Memory - RAM
0 F H
The data memory has a capacity of 146´8 bits. The data
memory is divided into two functional groups: special function registers and general purpose data memory (120´8).
Most are read/write, but some are read only. The general
purpose data memory, addressed from 28H to 7FH at
Bank 0 and from 40H to 5FH at Bank 1, is used for data
and control information under instruction commands.
1 1 H
1 0 H
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
S p e c ia l P u r p o s e
D a ta M e m o ry
1 6 H
1 7 H
1 8 H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by the ²SET [m].i²
and ²CLR [m].i² bit manipulation instructions. They are
also indirectly accessible through the memory pointer
registers (MP0;01H, MP1;02H).
1 9 H
1 A H
A S C R 0
1 B H
A S C R 1
1 C H
A S C R 2
1 D H
1 E H
IN T C 1
1 F H
Bank 1 must be addressed indirectly using the memory
pointer MP1 and the indirect addressing register IAR1.
Any direct addressing or any indirect addressing using
MP0 and IAR0 will always result in data from Bank 0 being accessed.
2 0 H
2 1 H
T M R A H
2 2 H
R C O C C R
2 3 H
T M R B H
T M R A L
2 4 H
T M R B L
2 5 H
R C O C R
Indirect Addressing Register
2 6 H
The method of indirect addressing allows data manipulation using memory pointers instead of the usual direct
memory addressing method where the actual memory
address is defined. Any action on the indirect addressing registers will result in corresponding read/write operations to the memory location specified by the
corresponding memory pointers. This device contains
two indirect addressing registers known as IAR0 and
IAR1 and two memory pointers MP0 and MP1. Note that
these indirect addressing registers are not physically
implemented and that reading the indirect addressing
registers indirectly will return a result of ²00H² and writing to the registers indirectly will result in no operation.
2 7 H
2 8 H
7 F H
4 0 H
5 F H
G e n e ra l P u rp o s e D a ta M e m o ry
(8 8 B y te s )
R A M
M a p p in g B a n k 0
: U n u s e d
R e a d a s "0 0 "
G e n e ra l P u rp o s e D a ta M e m o ry
(3 2 B y te s )
R A M
M a p p in g B a n k 1
RAM Mapping
registers is carried out, the actual address that the
microcontroller is directed to is the address specified by
the related memory pointer.
The two memory pointers, MP0 and MP1, are physically
implemented in the data memory and can be manipulated in the same way as normal registers providing a
convenient way with which to address and track data.
When any operation to the relevant indirect addressing
Rev. 1.20
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
Bit 7 of the memory pointers are not implemented. However, it must be noted that when the memory pointers in
this device is read, a value of ²1² will be read.
8
January 29, 2010
HT45R35
· Rotation - RL, RR, RLC, RRC
Bank Pointer - BP
· Increment and Decrement - INC, DEC
When using instructions to access the general purpose
data memory in Bank 0 or Bank 1, it is necessary to ensure that the correct area is selected. The general purpose data memory is sub-divided into two banks, Bank 0
and Bank 1 for this device. Selecting the correct data
memory area is achieved by using the bank pointer. If
data in Bank 0 or Bank 1 is to be accessed, the BP must
be set to the values ²00H² or ²01H² respectively, however, it must be noted that data in Bank 1 can only be addressed indirectly using the MP1 memory pointer and
the IAR1 indirect addressing register.
· Branch decision - SZ, SNZ, SIZ, SDZ ....
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO). It
also records the status information and controls the operation sequence.
Any direct addressing or any indirect addressing using
MP0 and IAR0 will always result in data from Bank 0 being accessed. The data memory is initialized to Bank 0
after a reset, except for the WDT time-out reset in the
Power Down Mode, in which case, the data memory
bank remains unchanged.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected
only by a system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² instruction.
It should be noted that the special function data memory
is not affected by the bank selection, which means that
the special function registers can be accessed from
within either Bank 0 or Bank 1.
The PDF flag can be affected only by executing a
²HALT² or ²CLR WDT² instruction or a system
power-up.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location ²05H² of the data memory
and can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
· Arithmetic operations - ADD, ADC, SUB, SBC, DAA
· Logic operations - AND, OR, XOR, CPL
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
Rev. 1.20
9
January 29, 2010
HT45R35
Interrupt
External interrupts are triggered by an edge transition
on pins INT0 or INT1. A configuration option enables
these pins as interrupts and selects if they are active on
high to low or low to high transitions. If active their related interrupt request flag, EIF0; bit 4 in INTC0, and
EIF1; bit 5 in INTC0, will be set. After the interrupt is enabled, the stack is not full, and the external interrupt is
active, a subroutine call to location ²04H² or ²08H² will
occur. The interrupt request flags, EIF0 or EIF1, and the
EMI bit will all be cleared to disable other interrupts.
The devices provides two external interrupts, one internal 8-bit timer/event counter interrupt and one external
RC oscillation converter interrupt. The interrupt control
register 0, INTC0, and interrupt control register 1,
INTC1, both contain the interrupt control bits that are
used to set the enable/disable and interrupt request
flags.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. However this scheme may prevent further
interrupt nesting. Other interrupt requests may happen
during this interval but only the interrupt request flag is
recorded. If a certain interrupt requires servicing within
the service routine, the EMI bit and the corresponding
bit of the INTC0 and INTC1 registers may be set to allow
interrupt nesting.
The internal Timer/Event Counter interrupt is initialised
by setting the Timer/Event Counter interrupt request
flag, TF; bit 6 in INTC0. A timer interrupt will be generated when the timer overflows. After the interrupt is enabled, and the stack is not full, and the TF bit is set, a
subroutine call to location ²0CH² will occur. The related
interrupt request flag, TF, is reset, and the EMI bit is
cleared to disable other interrupts.
If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate
service is desired, the stack must be prevented from becoming full.
The external RC oscillation converter interrupt is initialized by setting the external RC oscillation converter interrupt request flag, RCOCF; bit 4 of INTC1. This is caused
by a Timer A or Timer B overflow. When the interrupt is
enabled, and the stack is not full and the RCOCF bit is
set, a subroutine call to location ²10H² will occur. The related interrupt request flag, RCOCF, will be reset and the
EMI bit cleared to disable further interrupts.
All interrupts have a wake-up capability. As an interrupt
is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a
subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack.
If the contents of the accumulator or status register are
altered by the interrupt service program, this may corrupt the desired control sequence, therefore their contents should be saved in advance.
Bit No.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1, if the stack is not full. To
return from the interrupt subroutine, a ²RET² or ²RETI²
instruction may be invoked. RETI will set the EMI bit to
enable an interrupt service, but RET will not.
Label
Function
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EEI0
Controls the external interrupt 0 (1= enabled; 0= disabled)
2
EEI1
Controls the external interrupt 1 (1= enabled; 0= disabled)
3
ETI
Controls the Timer/Event Counter interrupt (1= enabled; 0= disabled)
4
EIF0
External interrupt 0 request flag (1= active; 0= inactive)
5
EIF1
External interrupt 1 request flag (1= active; 0= inactive)
6
TF
Internal Timer/Event Counter request flag (1= active; 0= inactive)
7
¾
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
0
1~3, 5~7
4
Label
Function
ERCOCI Controls the external RC oscillation converter interrupt (1= enabled; 0= disabled)
¾
Unused bit, read as ²0²
RCOCF External RC oscillation converter request flag (1= active; 0= inactive)
INTC1 (1EH) Register
Rev. 1.20
10
January 29, 2010
HT45R35
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
External Interrupt 0
1
04H
External Interrupt 1
2
08H
Timer/Event Counter Overflow
3
0CH
External RC Oscillation
Converter Interrupt
4
10H
C 1
In te r n a l
O s c illa to r
C ir c u it
O S C 1
R p
R f
C a
C b
T o in te r n a l
c ir c u its
O S C 2
C 2
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator
resonator types, to ensure oscillation and accurate frequency generation, it may be necessary to add two
small value external capacitors, C1 and C2. The exact
values of C1 and C2 should be selected in consultation
with the crystal or resonator manufacturer¢s specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to
assist with oscillation start up.
Interrupt Priority
The EMI, EEI0, EEI1, ETI and ERCOCI bits are all used
to control the enable/disable status of interrupts. These
bits prevent the requested interrupt from being serviced.
Once the interrupt request flags, TF, RCOCF, EIF1 and
EIF0, are all set, they remain in the INTC1 or INTC0 registers respectively until the interrupts are serviced or
cleared by a software instruction.
Internal Ca, Cb, Rf Typical Values @ 5V, 25°C
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well controlled, the original control sequence may be damaged
once the ²CALL² is executed in the interrupt subroutine.
Ca
Cb
Rf
TBD
TBD
TBD
Oscillator Internal Component Values
Crystal Oscillator C1 and C2 Values
C1
C2
CL
12MHz
TBD
TBD
TBD
Oscillator Configuration
8MHz
TBD
TBD
TBD
Various oscillator options offer the user a wide range of
functions according to their various application requirements. Two types of system clocks can be selected
while various clock source options for the Watchdog
Timer are provided for maximum flexibility. All oscillator
options are selected through the configuration options.
4MHz
TBD
TBD
TBD
1MHz
TBD
TBD
TBD
Crystal Frequency
Note:
The two methods of generating the system clock are:
1. C1 and C2 values are for guidance only.
2. CL is the crystal manufacturer specified
load capacitor value.
Crystal Recommended Capacitor Values
· External crystal/resonator oscillator
· External RC oscillator
Resonator C1 and C2 Values
One of these two methods must be selected using the
configuration options.
Resonator Frequency
More information regarding the oscillator is located in
Application Note HA0075E on the Holtek website.
External Crystal/Resonator Oscillator
C2
3.58MHz
TBD
TBD
1MHz
TBD
TBD
455kHz
TBD
TBD
Note:
The simple connection of a crystal across OSC1 and
OSC2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. However, for some crystals and most
Rev. 1.20
C1
C1 and C2 values are for guidance only.
Resonator Recommended Capacitor Values
11
January 29, 2010
HT45R35
External RC Oscillator
Watchdog Timer - WDT
Using the external system RC oscillator requires that a
resistor, with a value between 24kW and 1.5MW, is connected between OSC1 and VDD, and a capacitor is connected to ground. The generated system clock divided
by 4 will be provided on OSC2 as an output which can
be used for external synchronization purposes. Note
that as the OSC2 output is an NMOS open-drain type, a
pull high resistor should be connected if it to be used to
monitor the internal frequency. Although this is a cost effective oscillator configuration, the oscillation frequency
can vary with VDD, temperature and process variations
and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies
are required.For the value of the external resistor ROSC
refer to the Holtek website for typical RC Oscillator vs.
Temperature and VDD characteristics graphics. Note
that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. The external capacitor shown
on the diagram does not influence the frequency of oscillation.
The WDT clock can be sourced from its own dedicated
internal oscillator (WDT oscillator), or from the or instruction clock, which is the system clock divided by 4.
The choice is determined via a configuration option. The
WDT timer is designed to prevent a software malfunction or sequence from jumping to an unknown location
with unpredictable results. The Watchdog Timer can be
disabled by a configuration option. If the Watchdog
Timer is disabled, any executions related to the WDT result in no operation.
V
R
The WDT clock source is first divided by 256. If the internal WDT oscillator is used ,this gives a nominal time-out
period of approximately 17ms at 5V. This time-out period may vary with temperatures, VDD and process variations. By using the WDT prescaler, longer time-out
periods can be realised. Writing data to the WS2, WS1,
WS0 bits in the WDTS register, can give different
time-out periods. If WS2, WS1 and WS0 are all equal to
1, the division ratio will be 1:128, and the maximum
time-out period will be 2.1s at 5V. If the internal WDT oscillator is disabled, the WDT clock may still come from
the instruction clock and operate in the same manner
except that in the Power Down state the WDT will stop
counting and lose its protecting purpose. The high nibble and bit 3 of the WDTS can be used for user defined
flags.
D D
O S C
O S C 1
4 7 0 p F
fS
Y S
/4 N M O S O p e n D r a in
If the device operates in a noisy environment, using the
internal WDT oscillator is the recommended choice,
since the HALT instruction will stop the system clock.
O S C 2
External RC Oscillator
Watchdog Timer Oscillator
The WDT oscillator is a fully self-contained free running
on-chip RC oscillator with a typical period of 65ms at 5V
requiring no external components. When the device enters the Power Down Mode, the system clock will stop
running but the WDT oscillator continues to free-run and
to keep the watchdog active. However, to preserve
power in certain applications the WDT oscillator can be
disabled via a configuration option.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS (09H) Register
S y s te m
C lo c k /4
W D T P r e s c a le r
O p tio n
S e le c t
8 - b it C o u n te r
W D T
O S C
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.20
12
January 29, 2010
HT45R35
set causes a device initialisation and the WDT overflow
performs a ²warm reset². After the TO and PDF flags
are examined, the reason for the device reset can be determined. The PDF flag is cleared by a system power-up
or executing the ²CLR WDT² instruction and is set when
a ²HALT² instruction is executed. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the program counter and stack pointer; the other
registers maintain their their original status.
The WDT overflow under normal operation will generate
a ²chip reset² and set the status bit ²TO². But in the
Power Down mode, the overflow will generate a ²warm
reset², where only the Program Counter and Stack
Pointer are reset to zero. To clear the contents of the
WDT, including the WDT prescaler, three methods can
be used; an external reset (a low level to RES), a software instruction and a ²HALT² instruction. The software
instruction includes ²CLR WDT² instruction and the instruction pair - ²CLR WDT1² and ²CLR WDT2². Of
these two types of instruction, only one can be active depending on the configuration option - ²CLR WDT times
selection option². If the ²CLR WDT² is selected, i.e.
CLRWDT times equal one, any execution of the ²CLR
WDT² instruction will clear the WDT. In the case that
²CLR WDT1² and ²CLR WDT2² are chosen, i.e.
CLRWDT times equal two, these two instructions must
be executed to clear the WDT; otherwise, the WDT may
reset the chip as a result of a time-out.
The port A and interrupt methods of wake-up can be
considered as a continuation of normal execution. Each
bit in port A can be independently selected by configuration options to wake-up the device. When awakened
from an I/O port stimulus, the program will resume execution at the next instruction. If it is awakened due to an
interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the
stack is full, the program will resume execution at the
next instruction. If the interrupt is enabled and the stack
is not full, the regular interrupt response takes place. If
an interrupt request flag is set to ²1² before entering the
Power Down Mode, the wake-up function of the related
interrupt will be disabled. Once a wake-up event occurs,
it takes 1024 tSYS (system clock periods) to resume normal operation. A dummy period is therefore inserted after wake-up. If the wake-up results from an interrupt
acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If the
wake-up results in the next instruction execution, this
will be executed immediately after the dummy period is
finished.
Power Down Operation
The Power Down mode is initialized by the ²HALT² instruction and results in the following...
· The system oscillator will be turned off but the WDT
oscillator keeps running, if the internal WDT oscillator
has been selected as the WDT source clock.
· The contents of the on chip RAM and registers remain
unchanged.
· The WDT and WDT prescaler will be cleared and will
resume counting, if the internal WDT oscillator has
been selected as the WDT source clock
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Power Down
mode.
· AlloftheI/Oportswillmaintaintheiroriginalstatus.
· The PDF flag is set and the TO flag is cleared.
The system can leave the Power Down mode by means
of an external reset, an interrupt, an external falling
edge signal on port Aor a WDT overflow. An external re-
Rev. 1.20
13
January 29, 2010
HT45R35
Reset
The functional unit device reset status are shown below.
There are three ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
A WDT time-out, when the device is in the Power Down
mode, is different from other device reset conditions, in
that it can perform a ²warm reset² that resets only the
Program Counter and the Stack Poiner, leaving the
other circuits in their original state. Some registers remain unchanged during other reset conditions. Most
registers are reset to their ²initial condition² when the reset conditions are met. By examining the PDF and TO
flags, the program can distinguish between the different
device reset types.
TO
PDF
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter
Off
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
H A L T
W a rm
R e s e t
W D T
RESET Conditions
R E S
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
O S C 1
S y s te m
R e s e t
Reset Configuration
Note: ²u² means ²unchanged²
To guarantee that the system oscillator is started and
stabilised, the SST or System Start-up Timer, provides
an extra-delay of 1024 system clock pulses when the
system is reset (power-up, WDT time-out or RES reset)
or when the system awakens from a Power Down state.
V
V
D D
D D
0 .0 1 m F
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up the Power Down
mode will enable the SST delay.
1 0 0 k W
1 0 0 k W
R E S
0 .1 m F
An extra option load time delay is added during a system
reset (power-up, WDT time-out during normal mode or a
RES reset).
B a s ic
R e s e t
C ir c u it
R E S
1 0 k W
0 .1 m F
H i-n o is e
R e s e t
C ir c u it
Reset Circuit
V D D
Note:
R E S
tS
S T
S S T T im e - o u t
C h ip
Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the
Hi-noise Reset Circuit.
R e s e t
Reset Timing Chart
Rev. 1.20
14
January 29, 2010
HT45R35
The states of the registers is summarized in the table.
Reset
(Power-on)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
MP1
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
BP
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
ASCR0
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
ASCR1
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
ASCR2
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
Register
Program
Counter
INTC1
---0 ---0
---0 ---0
---0 ---0
---0 ---0
---u ---u
TMRAH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRAL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCCR
0000 1---
0000 1---
0000 1---
0000 1---
uuuu u---
TMRBH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRBL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCR
1xxx --00
1xxx --00
1xxx --00
1xxx --00
uuuu --uu
Note:
²*² means ²warm reset²
²u² means ²unchanged²
²x² means ²unknown²
²-² stands for unimplemented
If the configuration options select PA0~PA7 to be RC inputs, then the corresponding bits in the PA data register
and PA control register will be unimplemented and will be read as zero.
If the configuration options select PA0~PA7 to be normal I/O pins, then bit 0~bit3 in the ASCR0 and ASCR1
registers will be unimplemented and will be read as zero.
Rev. 1.20
15
January 29, 2010
HT45R35
Timer/Event Counter
means the clock source comes from an external TMR
pin. The timer mode functions as a normal timer with the
clock source coming from the fINT clock. The pulse width
measurement mode can be used to measure the high or
low level duration of an external signal on the TMR pin.
The counting is based on the fINT clock source. In the
event counting or timer mode, once the timer/event counter starts counting, it will count from the current contents
in the Timer/Event Counter to FFH. Once overflow occurs, the counter is reloaded from the Timer/Event Counter preload register and an interrupt request flag TF; bit 5
of INTC0, is generated at the same time.
An 8-bit timer/event counter, known as Timer/Event
Counter, is implemented in the microcontroller. The
Timer/Event Counter contains an 8-bit programmable
count-up counter whose clock may come from an external source or from the system clock. Using the external
clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. Using the internal clock allows the user to
generate an accurate time base.
There are 2 registers related to the Timer/Event Counter, TMR and TMRC. Two physical registers are mapped
to the TMR location; writing to TMR places the start
value of the Timer/Event Counter in a preload register
while reading TMR retrieves the contents of the
Timer/Event Counter. The TMRC is a timer/event counter control register, which defines the timer operating
conditions.
In the pulse width measurement mode, with the TON
and TE bits equal to one, once the TMR pin has received a transient from low to high, or high to low if the
TE bit is 0, it will start counting until the TMR pin returns
to its original level and resets the TON bit. The measured result will remain in the Timer/Event Counter even
if the activated transient occurs again. Therefore, only a
single shot measurement can be made. The TON bit
must be set again by software for further measurements
The TM0, TM1 bits define the operating mode. The event
count mode is used to count external events, which
S y s te m
C lo c k
7 - S ta g e P r e s c a le r
f IN
8 -1 M U X
T P S C 2 ~ T P S C 0
D a ta B u s
T
T M 1
T M 0
T M R
8 - B it T im e r /E v e n t C o u n te r R e lo a d
P r e lo a d R e g is te r
T E
T M 1
T M 0
T O N
8 - B it T im e r /E v e n t
C o u n te r (T M R )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
Timer/Event Counter
Bit No.
Label
Function
0~2
TPSC0~TPSC2
To define the prescaler stages, TPSC2, TPSC1, TPSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
3
TE
To define the TMR active edge of the timer/event counter
(0=active on low to high; 1=active on high to low)
4
TON
5
¾
6
7
TM0
TM1
To enable or disable timer counting (0=disabled; 1=enabled)
Unused bit, read as ²0²
To define the operating mode, TM1, TM0=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC (0EH) Register
Rev. 1.20
16
January 29, 2010
HT45R35
External RC Oscillation Converter
to be made. Note that, in this operating mode, the
Timer/Event Counter starts counting not according to
the logic level but according to the transient edges. In
the case of a counter overflow, the counter is reloaded
from the Timer/Event Counter preload register and issues an interrupt request just like the other two modes.
An external RC oscillation mode is implemented in the
device. The RC oscillation converter contains two 16-bit
programmable count-up counters.
The RC oscillation converter is comprised of the
TMRAL, TMRAH, TMRBL, TMRBH registers when the
RCO bit, bit 1 of RCOCR register, is ²1². The RC oscillation converter Timer B clock source may come from an
external RC oscillator. The Timer A clock source comes
from the system clock or from the system clock/4, determined by the RCOCCR register.
To enable a counting operation, the Timer ON bit, TON; bit
4 of TMRC, should be set to ²1². In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other
two modes, the TON can only be reset by instructions. The
Timer/Event Counter overflow is one of the wake-up
sources. No matter what the operation mode is, writing a 0
to ETI can disable the interrupt service.
There are six registers related to the RC oscillation converter, i.e., TMRAH, TMRAL, RCOCCR, TMRBH,
TMRBL and RCOCR. The internal timer clock is the input to TMRAH and TMRAL, the external RC oscillation
is the input to TMRBH and TMRBL. The OVB bit, bit 0 of
the RCOCR register, decides whether Timer A overflows or Timer B overflows, then the RCOCF bit is set
and an external RC oscillation converter interrupt occurs. When the RC oscillation converter mode Timer A
or Timer B overflows, the RCOCON bit is reset to ²0²
and stops counting. Writing to TMRAH/TMRBH places
the start value in Timer A/Timer B while reading
TMRAH/TMRBH obtains the contents of Timer A/Timer
B. Writing to TMRAL/TMRBL only writes the data into a
low byte buffer. However writing to TMRAH/TMRBH will
write the data and the contents of the low byte buffer into
If the Timer/Event Counter is switched off, then writing
data to the Timer/Event Counter preload register will
also directly reload that data to the Timer/Event Counter. But if the Timer/Event Counter is already running,
data written to it will only be loaded into the Timer/Event
Counter preload register. The Timer/Event Counter will
continue to operate until an overflow occurs. When the
Timer/Event Counter is read, the clock will be blocked to
avoid errors. As clock blocking may results in a counting
error, this must be taken into consideration by the programmer. Bit0~Bit2 of the TMRC register can be used to
define the pre-scaling stages of the internal clock source
of the Timer/Event Counter.
Bit No.
Label
0~2
¾
Unused bit, read as ²0²
¾
Undefined bit, this bit can read/write
3
4
5
6
7
Function
RCOCON Enable or disable external RC oscillation converter counting (0=disabled; 1=enabled)
Define the Timer A clock source, RCOM2, RCOM1, RCOM0=
000=System clock
001=System clock/4
RCOM0 010=Unused
RCOM1 011=Unused
RCOM2 100=Unused
101=Unused
110=Unused
111=Unused
RCOCCR (22H) Register
Bit No.
Label
Function
0
OVB
In the RC oscillation converter mode, this bit is used to define the timer/event counter interrupt,
which comes from Timer A overflow or Timer B overflow.
(0=Timer A overflow; 1=Timer B overflow)
1
RCO
Define RC oscillation converter mode.
(0=Disable RC oscillation converter mode; 1=Enable RC oscillation converter mode)
2~3
¾
4~7
RW
Unused bit, read as ²0²
4-bit read/write registers for user defined.
RCOCR (25H) Register
Rev. 1.20
17
January 29, 2010
HT45R35
S y s te m
S y s te m
C lo c k
C lo c k /4
S 1
O V B = 0
S 2
T im e r A
E x te rn a l R C
O s c illa tio n C o n v e r te r In te r r u p t
R C O C O N
O V B = 1
T im e r B
R C
O S C
R e s e t R C O C O N
O u tp u t
External RC Oscillation Converter
and RCOM2 bits of RCOCCR define the clock source of
Timer A. It is recommended that the clock source of
Timer A uses the system clock or the instruction clock.
the Timer A/Timer B (16-bit) simultaneously. Timer
A/Timer B is changed by writing to TMRAH/TMRBH but
writing to TMRAL/TMRBL will keep the Timer A/Timer B
unchanged.
If the RCOCON bit, bit 4 of RCOCCR, is set to ²1², Timer
A and Timer B will start counting until Timer A or Timer B
overflows, the timer/event counter will then generate an
interrupt request flag which is RCOCF; bit 4 of INTC1.
The Timer A and Timer B will stop counting and will reset
the RCOCON bit to ²0² at the same time. If the
RCOCON bit is ²1², TMRAH, TMRAL, TMRBH and
TMRBL cannot be read or written.
R e a d in g TM R A H / TM R B H w i l l al s o l at ch t h e
TMRAL/TMRBL into the low byte buffer to avoid false
timing problem. Reading TMRAL/TMRBL returns the
contents of the low byte buffer. Therefore, the low byte
of Timer A/Timer B can not be read directly. It must read
TMRAH/TMRBH first to ensure that the low byte contents of Timer A/Timer B are latched into the buffer.
The resistor and capacitor form an oscillation circuit and
input to TMRBH and TMRBL. The RCOM0, RCOM1
External RC oscillation converter mode example program - Timer A overflow:
clr RCOCCR
mov a, 00000010b
mov RCOCR,a
clr intc1.4
mov a, low (65536-1000)
mov tmral, a
mov a, high (65536-1000)
mov tmrah, a
mov a, 00h
mov tmrbl, a
mov a, 00h
mov tmrbh, a
mov a, 00110000b
mov RCOCCR, a
p10:
clr wdt
snz intc1.4
jmp p10
clr intc1.4
Rev. 1.20
; Enable External RC oscillation mode and set Timer A overflow
; Clear External RC Oscillation Converter interrupt request flag
; Give timer A initial value
; Timer A count 1000 time and then overflow
; Give timer B initial value
; Timer A clock source=fSYS/4 and timer on
; Polling External RC Oscillation Converter interrupt request flag
; Clear External RC Oscillation Converter interrupt request flag
; Program continue
18
January 29, 2010
HT45R35
Analog Switch
There are 12 analog switch lines in the device for RC1~RC12, and three corresponding Analog Switch Control registers, which are ASCR0, ASCR1 and ASCR2.
If the configuration options select PA0~PA3 to be normal I/O pins, then the corresponding bit 0~bit3 bits in the ASCR0
register will be unimplemented and will be read as zero.
Bit No.
Label
Function
0
AS1ON
Defines RC1 analog switch is on or off. AS1ON=
0=Analog switch 1 on, and RC1 is disconnected to pull-low
1=Analog switch 1 off, and RC1 is connected to pull-low or not according ASPLON0 register
1
AS2ON
Defines RC2 analog switch is on or off. AS2ON=
0=Analog switch 2 on, and RC2 is disconnected to pull-low
1=Analog switch 2 off, and RC2 is connected to pull-low or not according ASPLON0 register
2
AS3ON
Defines RC3 analog switch is on or off. AS3ON=
0=Analog switch 3 on, and RC3 is disconnected to pull-low
1=Analog switch 3 off, and RC3 is connected to pull-low or not according ASPLON1 register
3
AS4ON
Defines RC4 analog switch is on or off. AS4ON=
0=Analog switch 4 on, and RC4 is disconnected to pull-low
1=Analog switch 4 off, and RC4 is connected to pull-low or not according ASPLON1 register
4
AS5ON
Defines RC5 analog switch is on or off. AS5ON=
0=Analog switch 5 on, and RC5 is disconnected to pull-low
1=Analog switch 5 off, and RC5 is connected to pull-low or not according ASPLON2 register
5
AS6ON
Defines RC6 analog switch is on or off. AS6ON=
0=Analog switch 6 on, and RC6 is disconnected to pull-low
1=Analog switch 6 off, and RC6 is connected to pull-low or not according ASPLON2 register
6
AS7ON
Defines RC7 analog switch is on or off. AS7ON=
0=Analog switch 7 on, and RC7 is disconnected to pull-low
1=Analog switch 7 off, and RC7 is connected to pull-low or not according ASPLON3 register
7
AS8ON
Defines RC8 analog switch is on or off. AS8ON=
0=Analog switch 8 on, and RC8 is disconnected to pull-low
1=Analog switch 8 off, and RC8 is connected to pull-low or not according ASPLON3 register
ASCR0 (1AH) Register
If the configuration options select PA4~PA7 to be normal I/O pins, then the corresponding bit 0~bit3 bits in the ASCR1
register will be unimplemented and will be read as zero.
Bit No.
Label
Function
0
AS9ON
Defines RC9 analog switch is on or off. AS9ON=
0=Analog switch 9 on, and RC9 is disconnected to pull-low
1=Analog switch 9 off, and RC9 is connected to pull-low or not according ASPLON4 register
1
Defines RC10 analog switch is on or off. AS10ON=
AS10ON 0=Analog switch 10 on, and RC10 is disconnected to pull-low
1=Analog switch 10 off, and RC10 is connected to pull-low or not according ASPLON4 register
2
Defines RC11 analog switch is on or off. AS11ON=
AS11ON 0=Analog switch 11 on, and RC11 is disconnected to pull-low
1=Analog switch 11 off, and RC11 is connected to pull-low or not according ASPLON5 register
3
Defines RC12 analog switch is on or off. AS12ON=
AS12ON 0=Analog switch 12 on, and RC12 is disconnected to pull-low
1=Analog switch 12 off, and RC12 is connected to pull-low or not according ASPLON5 register
4~7
¾
Unused bit, read as ²0²
ASCR1 (1BH) Register
Rev. 1.20
19
January 29, 2010
HT45R35
If the configuration options select PA0~PA7 to be normal I/O pins, then the corresponding bits in the ASCR2 register, bit
0, bit1, bit4 and bit5, must be set to ²0² to disable the RC1/RC2, RC3/RC4, RC9/RC10 or RC11/RC12 pull-low resistors. These bits are set to ²0² or ²1² by software.
Bit No.
Label
Function
0
Defines RC1 pull-low and RC2 pull-low is non-pull-low. ASPLON0=
0=RC1 and RC2 are non-pull-low
ASPLON0 1=RC1 and RC2 are pull-low or not according RC1, RC2 analog is on or off.
RC1/RC2 is connected to pull-low when ASPLON0=1 and AS1ON/AS2ON analog switch is
off.
1
Defines RC3 pull-low and RC4 pull-low is non-pull-low. ASPLON1=
0=RC3 and RC4 are non-pull-low
ASPLON1 1=RC3 and RC4 are pull-low or not according RC3, RC4 analog is on or off.
RC3/RC4 is connected to pull-low when ASPLON1=1 and AS3ON/AS4ON analog switch is
off.
2
Defines RC5 pull-low and RC6 pull-low is non-pull-low. ASPLON2=
0=RC5 and RC6 are non-pull-low
ASPLON2 1=RC5 and RC6 are pull-low or not according RC5, RC6 analog is on or off.
RC5/RC6 is connected to pull-low when ASPLON2=1 and AS5ON/AS6ON analog switch is
off.
3
Defines RC7 pull-low and RC8 pull-low is non-pull-low. ASPLON3=
0=RC7 and RC8 are non-pull-low
ASPLON3 1=RC7 and RC8 are pull-low or not according RC7, RC8 analog is on or off.
RC7/RC8 is connected to pull-low when ASPLON3=1 and AS7ON/AS8ON analog switch is
off.
4
Defines RC9 pull-low and RC10 pull-low is non-pull-low. ASPLON4=
0=RC9 and RC10 are non-pull-low
ASPLON4 1=RC9 and RC10 are pull-low or not according RC9, RC10 analog is on or off.
RC9/RC10 is connected to pull-low when ASPLON4=1 and AS9ON/AS10ON analog switch is
off.
5
Defines RC11 pull-low and RC12 pull-low is non-pull-low. ASPLON5=
0=RC11 and RC12 are non-pull-low
ASPLON5 1=RC11 and RC12 are pull-low or not according RC11, RC12 analog is on or off.
RC11/RC12 is connected to pull-low when ASPLON5=1 and AS11ON/AS12ON analog switch
is off.
6~7
¾
Unused bit, read as ²0²
ASCR2 (1CH) Register
A S C R 0
A S C R 1
A S C R 2
T .G .1 ~ T .G .1 2
R C 1 ~ R C 1 2
R C 1 ~ R C 1 2
P u ll- lo w
R C 1
T .G .1
R C 2
T .G .2
R C 3
T .G .3
R C 4
T .G .4
R C 5
T .G .5
R C 6
T .G .6
R C 7
T .G .7
R C 8
T .G .8
R C 9
T .G .9
R C 1 0
T .G .1 0
R C 1 1
T .G .1 1
R C 1 2
T .G .1 2
R C O U T
IN
R R E F
C R E F
T im e r B
Analog Switch
Rev. 1.20
20
January 29, 2010
HT45R35
Each line of port A has the capability of waking-up the
device.
Input/Output Ports
There are 16 bidirectional input/output lines in the
microcontroller, all located within port PA and PB. All of
these I/O ports can be used for input and output operations. For input operation, these ports are non-latching,
that is, the inputs must be ready at the T2 rising edge of
the ²MOV A,[m]² instruction. For output operation, all the
data is latched and remains unchanged until the output
latch is rewritten.
Each line of port A and port B has a pull-high option.
Once the pull-high option is selected, the I/O line will
have a pull-high resistor connected. Otherwise, the
pull-high resistors are absent. It should be noted that a
non-pull-high I/O line operating in an input mode will be
in a floating state.
The PA0, PA1 and PA2 are pin-shared with INT0, INT1
and TMR pins, respectively. Pins PA0~PA3 and
PA4~PA7 are pin-shared with RC1~RC4 and
RC9~RC12, respectively. If configuration options select
PA0~PA7 to be RC input pins, then the corresponding
bits in the PA data register and PA control register will be
unimplemented.
Each I/O line has its own control register, known as PAC
and PBC, to control the input/output configuration. With
this control register, the pin status is either a CMOS output or a Schmitt trigger input, but can be reconfigured
dynamically, under software control. To function as an
input, the corresponding bit in the control register must
be written with a ²1². The input source also depends on
the control register. If the control register bit is ²1², the input
will read the pad state. If the control register bit is ²0², the
contents of the latches will move to the internal bus. The
latter is possible in the read-modify-write instruction.
It is recommended that unused or not bonded out I/O
lines should be set as output pins using software instruction to avoid consuming power under input floating
state.
Low Voltage Reset - LVR
When setup as an output the output types are CMOS.
The microcontroller provides a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as when changing a battery, the LVR
will automatically reset the device internally.
After a device reset, the I/O ports will be initially all setup
as inputs, and will therefore be in a high state if the
configuration options have selected pull-high resistors,
otherwise they will be in a floating condition. Each bit of
these input/output latches can be set or cleared by the
²SET [m].i² and ²CLR [m].i² instructions.
The LVR includes the following specifications:
· The low voltage (0.9V~VLVR) has to remain in its origi-
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
nal state for longer than tLVR. If the low voltage state
does not exceed tLVR, the LVR will ignore it and will not
perform a reset function.
· The LVR uses an ²OR² function with the external RES
signal to perform a chip reset.
V
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
P u ll- h ig h
Q
D
D D
Q
C K
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P A 0 ~ P A 7
P B 0 ~ P B 7
D a ta B it
Q
D
C K
S
Q
M
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly )
U
X
O P 0 ~ O P 7
IN T 0 fo r P A 0 o n ly
IN T 1 fo r P A 1 o n ly
T M R fo r P A 2 o n ly
Input/Output Ports
Rev. 1.20
21
January 29, 2010
HT45R35
The relationship between VDD and VLVR is shown below.
V D D
5 .5 V
V
O P R
5 .5 V
V
L V R
3 .0 V
2 .2 V
0 .9 V
Note:
VOPR is the voltage range for proper chip operation at 4MHz system clock.
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
R e s e t
N o r m a l O p e r a tio n
R e s e t
*1
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before starting the normal operation.
*2: Since low voltage has to be maintained its original state for longer than tLVR, therefore a tLVR delay enters
the reset mode.
Options
The following table shows the various options within the microcontroller. All of the options must be defined to ensure
proper system functioning.
No.
Function
Description
1
Wake up PA0~PA7 (bit option)
None wake-up or wake-up
2
Pull high PA0~PA7 and PB0~PB7 (bit option)
None pull-high or pull-high
3
WDT clock source
WDTOSC or fSYS/4
4
WDT
Enable or disable
5
CLRWDT
1 or 2 instructions
6
LVR
Enable or disable
7
OSC
X¢tal mode or RC mode
8
INT0 trigger edge
Disable, rising edge, falling edge or double edge
9
INT1 trigger edge
Disable, rising edge, falling edge or double edge
10
I/O or RC connection pins
PA0 or RC1, PA1 or RC2, PA2 or RC3, PA3 or RC4,
PA4 or RC9, PA5 or RC10, PA6 or RC11, PA7 or RC12
Rev. 1.20
22
January 29, 2010
HT45R35
Application Circuits
R to F Application Circuit
V
D D
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
P B 0 ~ P B 7
s e n s o r
1
R
s e n s o r
2
R C 2
0 .1 m F
R
s e n s o r
R C 1 2
V S S
O S C
C ir c u it
R
R C 1
R E S
1 2
*R
R R E F
R C O U T
IN
O S C 1
*C
C R E F
O S C 2
S e e O s c illa to r
S e c tio n
H T 4 5 R 3 5
C to F Application Circuit 1
V
D D
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
P B 0 ~ P B 7
R C 1
R E S
R C 2
0 .1 m F
V S S
O S C
C ir c u it
R C 1 2
O S C 1
C R E F
R C O U T
IN
O S C 2
R R E F
C
C
s e n s o r
1
C
s e n s o r
2
s e n s o r
1 2
*C
*R
S e e O s c illa to r
S e c tio n
H T 4 5 R 3 5
Rev. 1.20
23
January 29, 2010
HT45R35
C to F Application Circuit 2
V
D D
P B 0 ~ P B 7
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
R E S
R C 2
0 .1 m F
V S S
O S C
C ir c u it
R C 1 2
R C O U T
IN
R R E F
O S C 1
O S C 2
C
s e n s o r
1
C
s e n s o r
2
R C 1
C
s e n s o r
1 2
*R
C R E F
S e e O s c illa to r
S e c tio n
*C
H T 4 5 R 3 5
Note: 1. The ²*R² resistance and ²*C² capacitance should be consideration for the frequency of RC OSC.
2. Rsensor1~Rsensor12 are the resistance sensors.
3. Csensor1~Csensor12 are the capacitance sensors.
Rev. 1.20
24
January 29, 2010
HT45R35
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
Rev. 1.20
25
January 29, 2010
HT45R35
Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.20
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
26
January 29, 2010
HT45R35
Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Rev. 1.20
27
January 29, 2010
HT45R35
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
Rev. 1.20
28
January 29, 2010
HT45R35
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 1.20
29
January 29, 2010
HT45R35
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.20
30
January 29, 2010
HT45R35
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.20
31
January 29, 2010
HT45R35
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.20
32
January 29, 2010
HT45R35
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.20
33
January 29, 2010
HT45R35
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.20
34
January 29, 2010
HT45R35
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.20
35
January 29, 2010
HT45R35
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.20
36
January 29, 2010
HT45R35
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.20
37
January 29, 2010
HT45R35
Package Information
16-pin DIP (300mil) Outline Dimensions
A
B
A
1 6
9
1
8
B
1 6
9
1
8
H
H
C
C
D
D
G
E
G
E
I
F
I
F
Fig1. Full Lead Packages
Fig2. 1/2 Lead Packages
· MS-001d (see fig1)
Symbol
Dimensions in mil
Min.
Nom.
Max.
A
780
¾
880
B
240
¾
280
C
115
¾
195
D
115
¾
150
E
14
¾
22
F
45
¾
70
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
· MS-001d (see fig2)
Symbol
Rev. 1.20
Dimensions in mil
Min.
Nom.
Max.
A
735
¾
775
B
240
¾
280
C
115
¾
195
D
115
¾
150
E
14
¾
22
F
45
¾
70
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
38
January 29, 2010
HT45R35
· MO-095a (see fig2)
Symbol
A
Rev. 1.20
Dimensions in mil
Min.
Nom.
Max.
745
¾
785
B
275
¾
295
C
120
¾
150
D
110
¾
150
E
14
¾
22
F
45
¾
60
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
39
January 29, 2010
HT45R35
16-pin NSOP (150mil) Outline Dimensions
1 6
A
9
B
8
1
C
C '
G
H
D
E
a
F
· MS-012
Symbol
Rev. 1.20
Dimensions in mil
Min.
Nom.
Max.
A
228
¾
244
B
150
¾
157
C
12
¾
20
C¢
386
¾
394
D
¾
¾
69
E
¾
50
¾
F
4
¾
10
G
16
¾
50
H
7
¾
10
a
0°
¾
8°
40
January 29, 2010
HT45R35
20-pin DIP (300mil) Outline Dimensions
A
B
A
2 0
1 1
1
1 0
B
2 0
1 1
1 0
1
H
H
C
C
D
D
E
F
I
G
E
F
Fig1. Full Lead Packages
I
G
Fig2. 1/2 Lead Packages
· MS-001d (see fig1)
Symbol
Dimensions in mil
Min.
Nom.
Max.
A
980
¾
1060
B
240
¾
280
C
115
¾
195
D
115
¾
150
E
14
¾
22
F
45
¾
70
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
· MO-095a (see fig2)
Symbol
Rev. 1.20
Dimensions in mil
Min.
Nom.
Max.
A
945
¾
985
B
275
¾
295
C
120
¾
150
D
110
¾
150
E
14
¾
22
F
45
¾
60
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
41
January 29, 2010
HT45R35
20-pin SOP (300mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
a
F
· MS-013
Symbol
Rev. 1.20
Dimensions in mil
Min.
Nom.
Max.
A
393
¾
419
B
256
¾
300
C
12
¾
20
C¢
496
¾
512
D
¾
¾
104
E
¾
50
¾
F
4
¾
12
G
16
¾
50
H
8
¾
13
a
0°
¾
8°
42
January 29, 2010
HT45R35
24-pin SKDIP (300mil) Outline Dimensions
A
A
1 3
2 4
B
1 3
2 4
B
1 2
1
1 2
1
H
H
C
C
D
D
E
F
I
G
E
F
I
G
Fig2. 1/2 Lead Packages
Fig1. Full Lead Packages
· MS-001d (see fig1)
Symbol
A
Dimensions in mil
Min.
Nom.
Max.
1230
¾
1280
B
240
¾
280
C
115
¾
195
D
115
¾
150
E
14
¾
22
F
45
¾
70
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
· MS-001d (see fig2)
Symbol
Rev. 1.20
Dimensions in mil
Min.
Nom.
Max.
A
1160
¾
1195
B
240
¾
280
C
115
¾
195
D
115
¾
150
E
14
¾
22
F
45
¾
70
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
43
January 29, 2010
HT45R35
· MO-095a (see fig2)
Symbol
A
Rev. 1.20
Dimensions in mil
Min.
Nom.
Max.
1145
¾
1185
B
275
¾
295
C
120
¾
150
D
110
¾
150
E
14
¾
22
F
45
¾
60
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
44
January 29, 2010
HT45R35
24-pin SOP (300mil) Outline Dimensions
1 3
2 4
A
B
1 2
1
C
C '
G
H
D
E
a
F
· MS-013
Symbol
Rev. 1.20
Dimensions in mil
Min.
Nom.
Max.
A
393
¾
419
B
256
¾
300
C
12
¾
20
C¢
598
¾
613
D
¾
¾
104
E
¾
50
¾
F
4
¾
12
G
16
¾
50
H
8
¾
13
a
0°
¾
8°
45
January 29, 2010
HT45R35
28-pin SKDIP (300mil) Outline Dimensions
A
B
2 8
1 5
1
1 4
H
C
D
E
Symbol
A
Rev. 1.20
F
I
G
Dimensions in mil
Min.
Nom.
Max.
1375
¾
1395
B
278
¾
298
C
125
¾
135
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
295
¾
315
I
¾
¾
375
46
January 29, 2010
HT45R35
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
a
F
· MS-013
Symbol
Rev. 1.20
Dimensions in mil
Min.
Nom.
Max.
A
393
¾
419
B
256
¾
300
C
12
¾
20
C¢
697
¾
713
D
¾
¾
104
E
¾
50
¾
F
4
¾
12
G
16
¾
50
H
8
¾
13
a
0°
¾
8°
47
January 29, 2010
HT45R35
28-pin SSOP (150mil) Outline Dimensions
1 5
2 8
A
B
1 4
1
C
C '
G
H
D
E
Symbol
Dimensions in mm
Min.
Nom.
Max.
5.79
¾
6.20
B
3.81
¾
3.99
C
0.20
¾
0.30
C¢
9.80
¾
10.01
D
1.37
¾
1.52
E
¾
0.64
¾
F
0.10
¾
0.25
G
0.56
¾
0.71
H
0.18
¾
0.25
a
0°
¾
8°
A
Rev. 1.20
a
F
48
January 29, 2010
HT45R35
SAW Type 32-pin (5mm´5mm) QFN Outline Dimensions
D
D 2
2 5
3 2
2 4
b
1
E
E 2
e
1 7
8
1 6
A 1
A 3
L
9
K
A
Symbol
Rev. 1.20
Dimensions in mm.
Min.
Nom.
A
0.7
¾
0.8
A1
0.00
¾
0.05
A3
¾
0.2
¾
b
0.18
¾
0.30
D
¾
5.0
¾
E
¾
5.0
¾
e
¾
0.5
¾
D2
1.25
¾
3.25
E2
1.25
¾
3.25
L
0.30
¾
0.50
K
¾
¾
¾
49
Max.
January 29, 2010
HT45R35
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 20W, SOP 24W, SOP 28W (300mil)
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Dimensions in mm
330.0±1.0
62.0±1.5
13.0
+0.5/-0.2
2.0±0.5
24.8
+0.3/-0.2
30.2±0.2
SSOP 28S (150mil)
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Dimensions in mm
330.0±1.0
100.0±1.5
13.0
+0.5/-0.2
2.0±0.5
16.8
+0.3/-0.2
22.2±0.2
SAW QFN 32 (5mm´5mm)
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.20
Dimensions in mm
330.0±1.0
100.0±0.1
13.0
+0.5/-0.2
2.0±0.5
12.5
+0.3/-0.2
¾
50
January 29, 2010
HT45R35
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
B 0
C
D 1
P
K 0
A 0
R e e l H o le
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 20W
Symbol
Description
Dimensions in mm
24.0
+0.3/-0.1
W
Carrier Tape Width
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5
D1
Cavity Hole Diameter
1.50
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.8±0.1
B0
Cavity Width
13.3±0.1
K0
Cavity Depth
3.2±0.1
+0.1/-0.0
+0.25/-0.00
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
21.3±0.1
Rev. 1.20
51
January 29, 2010
HT45R35
SOP 24W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.55
+0.10/-0.00
D1
Cavity Hole Diameter
1.50
+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.9±0.1
B0
Cavity Width
15.9±0.1
K0
Cavity Depth
3.1±0.1
t
Carrier Tape Thickness
0.35±0.05
C
Cover Tape Width
21.3±0.1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5
D1
Cavity Hole Diameter
1.50
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.85±0.10
B0
Cavity Width
18.34±0.10
K0
Cavity Depth
2.97±0.10
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
21.3±0.1
Rev. 1.20
52
+0.1/-0.0
+0.25/-0.00
January 29, 2010
HT45R35
SSOP 28S (150mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
16.0±0.3
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.55
+0.10/-0.00
D1
Cavity Hole Diameter
1.50
+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
10.3±0.1
K0
Cavity Depth
2.1±0.1
7.5±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
SAW Type 32-pin (5mm´5mm) QFN
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
12.0±0.3
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
5.50±0.05
D
Perforation Diameter
1.5
D1
Cavity Hole Diameter
1.50
P0
Perforation Pitch
P1
Cavity to Perforation (Length Direction)
2.00±0.05
A0
Cavity Length
5.25±0.10
B0
Cavity Width
5.25±0.10
K0
Cavity Depth
1.1±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 1.20
+0.1/-0.0
+0.25/-0.00
4.0±0.1
0.30±0.05
9.3±0.1
53
January 29, 2010
HT45R35
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
54
January 29, 2010