MX29F022/022NT/B
2M-BIT[256K x 8]CMOS FLASH MEMORY
FEATURES
• 262,144x 8 only
• Fast access time: 55/70/90/120ns
• Low power consumption
•
•
•
•
• Status Reply
- 30mA maximum active current
- 1uA typical standby current@5MHz
Programming and erasing voltage 5V±10%
Command register architecture
- Byte Programming (7us typical)
- Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte
x1, and 64K-Byte x 3)
Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors or
the whole chip with Erase Suspend capability.
- Automatically programs and verifies data at specified address
Erase Suspend/Erase Resume
- Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation.
•
•
•
•
•
•
•
•
- Data polling & Toggle bit for detection of program
and erase cycle completion.
Chip protect/unprotect for 5V only system or 5V/12V
system
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1 to VCC+1V
Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
Hardware RESET pin
- Resets internal state machine to read mode
Low VCC write inhibit is equal to or less than 3.2V
Package type:
- 32-pin PDIP
- 32-pin PLCC
- 32-pin TSOP (Type 1)
20 years data retention
GENERAL DESCRIPTION
The MX29F022T/B is a 2-mega bit Flash memory
organized as 256K bytes of 8 bits only. MXIC's Flash
memories offer the most cost-effective and reliable read/
write non-volatile random access memory. The
MX29F022T/B is packaged in 32-pin PDIP, PLCC and
32-pin TSOP(I). It is designed to be reprogrammed and
erased in-system or in-standard EPROM programmers.
MXIC's Flash technology reliably stores memory
contents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The MX29F022T/
B uses a 5.0V ± 10% VCC supply to perform the High
Reliability Erase and auto Program/Erase algorithms.
The standard MX29F022T/B offers access time as fast
as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention,
the MX29F022T/B has separate chip enable (CE) and
output enable (OE) controls.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F022T/B uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining
maximum EPROM compatibility.
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MX29F022/022NT/B
32 TSOP (TYPE 1)
PIN CONFIGURATIONS
32 PDIP
NC on MX29F022NT/B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX29F022T/B
RESET
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
(NC on
MX29F022NT/B)
A11
A9
A8
A13
A14
A17
WE
VCC
RESET
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX29F022T/B
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
(NORMAL TYPE)
32 PLCC
A7
32
SECTOR STRUCTURE
A17
1
WE
VCC
A16
4
RESET
5
A15
A12
NC on MX29F022NT/B
30
29
A6
A13
A5
A8
A4
A9
A3
MX29F022T/B
9
25
A2
A17~A0
3FFFFH
A14
3BFFFH
OE
A1
A10
A0
CE
2FFFFH
Q5
Q4
Q3
VSS
Q7
K-BYTE
8
K-BYTE
32
K-BYTE
64
K-BYTE
64
K-BYTE
64
K-BYTE
1FFFFH
Q6
21
20
17
Q2
Q1
13
14
8
39FFFH
A11
37FFFH
Q0
16 K-BYTE
(BOOT SECTOR)
0FFFFH
00000H
MX29F022T Sector Architecture
PIN DESCRIPTION:
A17~A0
SYMBOL
PIN NAME
A0~A17
Address Input
Q0~Q7
Data Input/Output
3FFFFH
K-BYTE
64
K-BYTE
64
K-BYTE
32
K-BYTE
8
K-BYTE
8
K-BYTE
1FFFFH
CE
Chip Enable Input
WE
Write Enable Input
0FFFFH
RESET
Hardware Reset Pin/Sector Protect Unlock
07FFFH
OE
Output Enable Input
05FFFH
VCC
Power Supply Pin (+5V)
GND
64
2FFFFH
03FFFH
Ground Pin
00000H
16 K-BYTE
(BOOT SECTOR)
MX29F022B Sector Architecture
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MX29F022/022NT/B
BLOCK DIAGRAM
WRITE
CONTROL
CE
OE
WE
RESET
STATE
INPUT
HIGH VOLTAGE
LOGIC
MACHINE
(WSM)
LATCH
BUFFER
STATE
MX29F022T/B
REGISTER
FLASH
ARRAY
Y-DECODER
AND
X-DECODER
ADDRESS
A0-A17
PROGRAM/ERASE
ARRAY
SOURCE
HV
Y-PASS GATE
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
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MX29F022/022NT/B
AUTOMATIC PROGRAMMING
AUTOMATIC ERASE ALGORITHM
The MX29F022T/B is byte programmable using the
Automatic Programming algorithm. The Automatic
Programming algorithm does not require the system to
time out or verify the data programmed. The typical chip
programming time of the MX29F022T/B at room temperature is less than 2 seconds.
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
verifies the erase, and counts the number of sequences.
A status bit similar to DATA polling and status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming
operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10ms erase pulses
according to MXIC's High Reliability Chip Erase
algorithm. Typical erasure at room temperature is
accomplished in less than two second. The device is
erased using the Automatic Erase algorithm. The
Automatic Erase algorithm automatically programs the
entire array prior to electrical erase. The timing and
verification of electrical erase are internally controlled
within the device.
Commands are written to the command register using
standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which
controls the erase and programming circuitry. During
write cycles, the command register internally latches
address and data needed for the programming and erase
operations. During a system write cycle addresses are
latched on the falling edge, and data are latched on the
rising edge of WE .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29F022T/B electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed one
byte at a time using the EPROM programming mechanism of hot electron injection.
AUTOMATIC SECTOR ERASE
The MX29F022T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are internally controlled by the device.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command register to respond to its full command set.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write a program set-up commands (include
2 unlock write cycle and A0H) include 2 unlock write
cycle and A0H and a program command (program data
and address). The device automatically times the programming pulse width, verifies the program verification,
and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provides feedback to the user as
to the status of the programming operation.
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MX29F022/022NT/B
TABLE 1. SOFTWARE COMMAND DEFINITIONS
Command
First Bus
Second Bus Third Bus
Fourth Bus
Fifth Bus
Sixth Bus
Bus
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Addr
Data Addr
Cycle
Data
Addr
Data Addr
Data Addr
Reset
1
XXXH F0H
Read
1
RA
RD
Read Silicon ID
4
555H
AAH 2AAH 55H
555H 90H
ADI
DDI
Chip Protect Verify
4
555H
AAH 2AAH 55H
555H 90H
(SA)
00H
Data Addr Data
X02H 01H
Program
4
555H
AAH 2AAH 55H
555H A0H PA
PD
Chip Erase
6
555H
AAH 2AAH 55H
555H 80H
555H
AAH 2AAH 55H 555H 10H
Sector Erase
6
555H
AAH 2AAH 55H
555H 80H
555H
AAH 2AAH 55H SA
Sector Erase Suspend
1
XXXH B0H
Sector Erase Resume
1
XXXH 30H
Unlock for chip
6
555H
555H 80H
555H
AAH 2AAH 55H 555H 20H
AAH 2AAH 55H
30H
protect/unprotect
Note:
1. ADI = Address of Device identifier; A1=0,A0 =0 for manufacture code,A1=0, A0 =1 for device code (Refer to Table
3).
DDI = Data of Device identifier : C2H for manufacture code, 36H/37H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.
Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A17 in either state.
4. For Chip Protect Verify operation: If read out data is 01H, it means the chip has been protected. If read out data is
00H, it means the chip is still not being protected.
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MX29F022/022NT/B
TABLE 2. MX29F022T/B BUS OPERATION
Pins
CE
OE
WE
A0
A1
A6
A9
Q0~Q7
L
L
H
L
L
X
VID(2)
C2H
L
L
H
H
L
X
VID(2)
36H/37H
Read
L
L
H
A0
A1
A6
A9
DOUT
Standby
H
X
X
X
X
X
X
HIGH Z
Output Disable
L
H
H
X
X
X
X
Write
L
H
L
A0
A1
A6
A9
HIGH Z
DIN(3)
Chip Protect with 12V
L
VID(2)
L
X
X
L
VID(2)
X
L
VID(2)
L
X
X
H
VID(2)
X
L
L
H
X
H
X
VID(2)
Code (5)
L
H
L
X
X
L
H
X
L
H
L
X
X
H
H
X
L
L
H
X
H
X
H
Code(5)
X
X
X
X
X
X
X
HIGH Z
Mode
Read Silicon ID
Manufacturer Code(1)
Read Silicon ID
Device Code(1)
system (6)
Chip Unprotect with 12V
system (6)
Verify chip Protect
with 12V system
Chip Protect without 12V
system (6)
Chip Unprotect without 12V
system (6)
Verify Chip Protect/Unprotect
without 12V system (7)
Reset
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H means unprotected.
Code=01H means protected.
6. Refer to chip protect/unprotect algorithm and waveform.
Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system"
command.
7. The "verify chip protect/unprotect without 12V system" is only following "chip protect/unprotect without 12V system"
command.
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MX29F022/022NT/B
READ/RESET COMMAND
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
The read or reset operation is initiated by writing the
read/reset command sequence into the command register. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verification begin. The
erase and verification operations are completed when
the data on Q7 is "1" at which time the device returns to
the Read mode. The system is not required to provide
any control or timing during these operations.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid command must then be written to place the device in the
desired state.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the
device resides in the target system. PROM programmers typically access signature codes by raising A9 to
a high voltage. However, multiplexing high voltage onto
address lines is not generally desired system design practice.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verify command is required).
If the Erase operation was unsuccessful, the data on Q5
is "1" (see Table 4), indicating the erase operation of exceed internal timing limit.
The MX29F022T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read
silicon ID command sequence into the command register. Following the command write, a read cycle with
A1=VIL, A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of 36H for MX29F022T, 37H for MX29F022B.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.
TABLE 3. EXPANDED SILICON ID CODE
Pins
Manufacture code
Device code
for MX29F022T
Device code
for MX29F022B
Chip Protection Verification
A0
VIL
VIH
A1
VIL
VIL
Q7
1
0
Q6
1
0
Q5
0
1
Q4
0
1
Q3
0
0
Q2
0
1
Q1
1
1
Q0
0
0
Code(Hex)
C2H
36H
VIH
VIL
0
0
1
1
0
1
1
1
37H
X
X
VIH
VIH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
01H (Protected)
00H (Unprotected)
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MX29F022/022NT/B
eration. After this command has been executed, the
command register will initiate erase suspend mode. The
state machine will return to read mode automatically after suspend is ready. At this time, state machine only
allows the command register to respond to the Read
Memory Array, Erase Resume and Program commands.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspended
program operation is complete, the system can once
again read array data within non-suspended sectors.
SET-UP AUTOMATIC SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Set-up Sector Erase command and Automatic
Sector Erase command. Upon executing the Automatic
Sector Erase command, the device will automatically
program and verify the sector(s) memory for an all-zero
data pattern. The system does not require to provide
any control or timing during these operations.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verification begin. The erase and verification operations are
complete when the data on Q7 is "1" and the data on Q6
stops toggling for two consecutive read cycles, at which
time the device returns to the Read mode. The system
does not required to provide any control or timing
during these operations.
When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
set-up command-80H. Two more "unlock" write cycles
are then followed by the sector erase command-30H.
The sector address is latched on the falling edge of WE,
while the command(data) is latched on the rising edge
of WE. Sector addresses selected are loaded into
internal register on the sixth falling edge of WE. Each
successive sector load cycle started by the falling edge
of WE must begin within 30us from the rising edge of
the preceding WE. Otherwise, the loading period ends
and internal auto sector erase cycle starts. (Monitor Q3
to determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command
other than Sector Erase (30H) or Erase Suspend (B0H)
during the time-out period resets the device to read mode.
ERASE SUSPEND
This command is only valid while the state machine is
executing Automatic Sector Erase operation, and
therefore will only be responded during Automatic/Sector Erase operation. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase op-
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MX29F022/022NT/B
TABLE 4. WRITE OPERATION STATUS
Status
Q7
Q6
Note1
Byte Program in Auto Program Algorithm
Auto Erase Algorithm
Erase Suspend Read
In Progress
Erase Suspend Read
Q3
Q2
Note2
Q7
Toggle
0
N/A
No Toggle
0
Toggle
0
1
Toggle
1
No
0
N/A
Toggle
(Erase Suspended Sector)
Erase Suspended Mode
Q5
Toggle
Data
Data
Data
Data
Data
Q7
Toggle
0
N/A
N/A
Q7
Toggle
1
N/A
No Toggle
0
Toggle
1
1
Toggle
Q7
Toggle
1
N/A
N/A
(Non-Erase Suspended Sector)
Erase Suspend Program
Byte Program in Auto Program Algorithm
Exceeded
Auto Erase Algorithm
Time Limits Erase Suspend Program
Note:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5 : Exceeded Timing Limits" for more information.
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MX29F022/022NT/B
rising edge of the second WE pulse of the two write pulse
sequences.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all other
conditions. Another Erase Suspend command can be
written after the chip has resumed erasing.
While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is compete. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data Polling feature is valid after the rising
edge of the second WE pulse of two write pulse sequences.
The Data Polling feature is active during Automatic Program/Erase algorithm or sector erase time-out. (see section Q3 Sector Erase Timer)
SET-UP AUTOMATIC PROGRAM COMMANDS
To initiate Automatic Program mode, A three-cycle command sequence is required. There are two "unlock" write
cycles. These are followed by writing the Automatic Program command A0H.
Q6 : Toggle BIT I
Once the Automatic Program command is initiated, the
next WE pulse causes a transition to an active programming operation. Addresses are latched on the falling edge,
and data are internally latched on the rising edge of the
WE pulse. The rising edge of WE also begins the programming operation. The system does not require to provide further controls or timings. The device will automatically provide an adequate internally generated program
pulse and verify margin.
The MX29F022T/B features a "Toggle Bit" as a method
to indicate to the host system that the Auto Program/
Erase algorithms are either in progress or complete.
If the program operation was unsuccessful, the data on
Q5 is "1", indicating the program operation of internally
exceed timing limit. The automatic programming operation is complete when the data read on Q6 stops toggling for two consecutive read cycles and the data on
Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read mode(no
program verify command is required).
After an erase command sequence is written, if the chip
is protected, Q6 toggles and returns to reading array data.
During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6
to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6
stops toggling.
WRITE OPERATION STATUS DATA POLLINGQ7
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended.
When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When
the device enters the Erase Suspend mode, Q6 stops
toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended.
Alternatively, the system can use Q7(see the subsection on Q7 : Data Polling).
The MX29F022T/B also features Data Polling as a
method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress
or completed.
If a program address falls within a protected sector, Q6
toggles for approximately 2us after the program command sequence is written, then returns to reading array
data.
While the Automatic Programming algorithm is in
operation, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an
attempt to read the device will produce the true data last
written to Q7. The Data Polling feature is valid after the
Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on Q6. Refer to the toggle bit algorithm.
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MX29F022/022NT/B
status as described in the previous paragraph.
Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of the toggle bit algorithm
flow chart).
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether
that sector is erase-suspended. Toggle Bit I is valid after
the rising edge of the final WE pulse in the command
sequence.
Q5
Exceeded Timing Limits
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sectors and mode information. Refer to
Table 4 to compare outputs for Q2 and Q6.
Q5 will indicate if the program or erase time has
exceeded the specified limits (internal pulse count). Under
these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not
successfully completed. Data Polling and Toggle Bit are
the only operating functions not of the device under this
condition.
If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other
sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the
other active sectors in the device.
Reading Toggle Bits Q6/ Q2
Refer to the toggle bit algorithm for the following
discussion. Whenever the system initially begins
reading toggle bit status, it must read Q7-Q0 at least
twice in a row to determine whether a toggle bit is
toggling. Typically, the system would note and store the
value of the toggle bit after the first read. After the
second read, the system would compare the new value
of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase
operation. The system can read array data on Q7-Q0 on
the following read cycle.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.
If this time-out condition occurs during the byte
programming operation, it specifies that the entire
sector containing that byte is bad and this sector may
not be reused, (other sectors are still functional and can
be reused).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase operation. If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the
Automatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops
toggling. Once the Device has exceeded timing limits,
the Q5 bit will indicate a "1". Please note that this is not
a device failure condition since the device was
incorrectly used.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the
P/N:PM0556
REV. 1.3, NOV. 11, 2002
11
MX29F022/022NT/B
POWER SUPPLY DECOUPLING
Q3
Sector Erase Timer
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected between its VCC and GND.
After the completion of the initial sector erase command
sequence the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase command sequence.
CHIP PROTECTION WITH 12V SYSTEM
The MX29F022T/B features hardware chip protection,
which will disable both program and erase operations. To
activate this mode, the programming equipment must
force VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL.(see Table 2)
Programming of the protection circuitry begins on the
falling edge of the WE pulse and is terminated on the
rising edge. Please refer to chip protect algorithm and
waveform.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the
command has been accepted, the system software
should check the status of Q3 prior to and following each
subsequent sector erase command. If Q3 were high on
the second status check, the command may not have
been accepted.
To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 ( with CE and OE at VIL and WE at VIH. When A1=1,
it will produce a logical "1" code at device output Q0 for
the protected status. Otherwise the device will produce
00H for the unprotected status. In this mode, the addresses, except for A1, are in "don't care" state. Address locations with A1 = VIL are reserved to read manufacturer and device codes.(Read Silicon ID)
DATA PROTECTION
The MX29F022T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets
the state machine in the Read mode. In addition, with its
control register architecture, alteration of the memory
contents only occurs after successful completion of specific command sequences. The device also incorporates
several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or
system noise.
It is also possible to determine if the chip is protected in
the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected status.
CHIP UNPROTECT WITH 12V SYSTEM
The MX29F022T/B also features the chip unprotect mode,
so that all sectors are unprotected after chip unprotect is
completed to incorporate any changes in the code.
WRITE PULSE "GLITCH" PROTECTION
To activate this mode, the programming equipment must
force VID on control pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.(see
Table 2) Refer to chip unprotect algorithm and waveform
for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE pulse and is
terminated on the rising edge.
Noise pulses of less than 5ns (typical) on CE or WE will
not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
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REV. 1.3, NOV. 11, 2002
12
MX29F022/022NT/B
Performing a read operation with A1=VIH, it will produce
00H at data outputs (Q0-Q7) for an unprotected chip. It
is noted that all sectors are unprotected after the chip
unprotect algorithm is complete.
ABSOLUTE MAXIMUM RATINGS
RATING
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
A9
CHIP PROTECTION WITHOUT 12V SYSTEM
The MX29F022T/B also feature a hardware chip
protection method in a system without 12V power supply. The programming equipment do not need to supply
12 volts to protect all sectors. The details are shown in
chip protect algorithm and waveform.
VALUE
0oC to 70oC
-65oC to 125oC
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 13.5V
NOTICE:
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may
affect reliability.
CHIP UNPROTECT WITHOUT 12V SYSTEM
The MX29F022T/B also feature a hardware chip
unprotection method in a system without 12V power supply. The programming equipment do not need to supply
12 volts to unprotect all sectors. The details are shown
in chip unprotect algorithm and waveform.
NOTICE:
Specifications contained within the following tables are subject to change.
POWER-UP SEQUENCE
The MX29F022T/B powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of a two-step command sequence.
Vpp and Vcc power up sequence is not required.
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REV. 1.3, NOV. 11, 2002
13
MX29F022/022NT/B
TEMPORARY SECTOR UNPROTECT OPERATION (only for 29F022T/B)
Start
RESET = VID (Note 1)
Perform Erase or Program Operation
Operation Completed
RESET = VIH
Temporary Sector Unprotect Completed(Note 2)
Note : 1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V
2. All previously protected sectors are protected again.
P/N:PM0556
REV. 1.3, NOV. 11, 2002
14
MX29F022/022NT/B
TEMPORARY SECTOR UNPROTECT
Parameter Std. Description
Test Setup All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tRSP
RESET Setup Time for Temporary Sector Unprotect
Min
4
us
Note:
Not 100% tested
TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM (only for 29F022T/B)
12V
RESET
0 or 5V
0 or 5V
Program or Erase Command Sequence
tVIDR
tVIDR
CE
WE
tRSP
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REV. 1.3, NOV. 11, 2002
15
MX29F022/022NT/B
AC CHARACTERISTICS
Parameter Std
Description
Test Setup All Speed Options Unit
tREADY
RESET PIN Low (Not During Automatic Algorithms)
MAX
500
ns
to Read or Write (See Note)
tRP1
RESET Pulse Width (During Automatic Algorithms)
MIN
10
us
tRP2
RESET Pulse Width (NOT During Automatic Algorithms)
MIN
500
ns
tRH
RESET High Time Before Read(See Note)
MIN
0
ns
Note:
Not 100% tested
RESET TIMING WAVEFORM (only for 29F002T/B)
CE, OE
tRH
RESET
tRP2
tReady
Reset Timing NOT during Automatic Algorithms
RESET
tRP1
Reset Timing during Automatic Algorithms
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REV. 1.3, NOV. 11, 2002
16
MX29F022/022NT/B
CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL
CIN1
CIN2
COUT
PARAMETER
MIN.
Input Capacitance
Control Pin Capacitance
Output Capacitance
TYP
MAX.
8
12
12
UNIT
pF
pF
pF
CONDITIONS
VIN = 0V
VIN = 0V
VOUT = 0V
READ OPERATION
DC CHARACTERISTICS TA = 0oC TO 70oC, VCC = 5V ± 10% (VCC=5V ± 5% for 29F022/022N-55)
SYMBOL
ILI
ILO
ISB1
ISB2
ICC1
ICC2
VIL
VIH
VOL
VOH1
VOH2
PARAMETER
Input Leakage Current
Output Leakage Current
Standby VCC current
MIN.
TYP
1
Operating VCC current
Input Low Voltage
-0.3(NOTE1)
Input High Voltage
2.0
Output Low Voltage
Output High Voltage(TTL)
2.4
Output High Voltage(CMOS)VCC-0.4
MAX.
1
10
1
5
30
50
0.8
VCC + 0.3
0.45
UNIT
mA
mA
mA
uA
mA
mA
V
V
V
V
V
CONDITIONS
VIN = GND to VCC
VOUT = GND to VCC
CE = VIH
CE = VCC + 0.3V
IOUT = 0mA, f=5MHz
IOUT = 0mA, f=10MHz
IOL = 2.1mA
IOH =-2mA
IOH =-100uA,VCC=VCC
MIN
NOTES:
1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.
2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
P/N:PM0556
REV. 1.3, NOV. 11, 2002
17
MX29F022/022NT/B
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ± 10%(VCC = 5V ± 5% for 29F022T/B-55)
SYMBOL
tACC
tCE
tOE
tDF
tOH
PARAMETER
Address to Output Delay
CE to Output Delay
OE to Output Delay
OE High to Output Float (Note1)
Address to Output hold
SYMBOL PARAMETER
tACC
tCE
tOE
tDF
tOH
Address to Output Delay
CE to Output Delay
OE to Output Delay
OE High to Output Float (Note1)
Address to Output hold
29F022T/B-55
MIN. MAX.
55
55
25
0
20
0
29F022T/B-70
MIN.
MAX.
70
70
30
0
20
0
UNIT
ns
ns
ns
ns
ns
29F022T/B-90
MIN. MAX.
29F022T/B-120
MIN.
MAX.
UNIT CONDITIONS
0
0
90
90
40
30
0
0
120
120
50
30
ns
ns
ns
ns
ns
CONDITIONS
CE=OE=VIL
OE=VIL
CE=VIL
CE=VIL
CE=OE=VIL
CE=OE=VIL
OE=VIL
CE=VIL
CE=VIL
CE=OE=VIL
TEST CONDITIONS:
• Input pulse levels: 0.45V/2.4V for 70ns max.
: 0V/3V for 55ns speed grade.
• Input rise and fall times: < 10ns for 70ns max.
: < 5ns for 55ns speed grade.
• Output load: 1 TTL gate + 100pF(Including scope and jig) for 70ns max.
: 1 TTL gate + 50pF(Including scope and jig) for 55ns speed grade.
• Reference levels for measuring timing : 0.8V/2.0V or 70ns max.
:1.5V/1.5V for 55ns speed grade.
NOTE:
1.tDF is defined as the time at which the output achieves the
open circuit condition and data is no longer driven.
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REV. 1.3, NOV. 11, 2002
18
MX29F022/022NT/B
READ TIMING WAVEFORMS
VIH
ADD Valid
A0~17
VIL
tCE
VIH
CE
VIL
WE
VIH
OE
VIH
tACC
VIL
DATA
Q0~7
tDF
tOE
VIL
VOH
HIGH Z
tOH
DATA Valid
HIGH Z
VOL
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REV. 1.3, NOV. 11, 2002
19
MX29F022/022NT/B
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ± 10%(VCC = 5V ± 5% for 29F022/022N-55)
SYMBOL
PARAMETER
ICC1 (Read)
Operating VCC Current
MIN.
TYP MAX. UNIT CONDITIONS
30
mA
IOUT=0mA, f=5MHz
ICC2
50
mA
IOUT=0mA, F=10MHz
ICC3 (Program)
50
mA
In Programming
ICC4 (Erase)
50
mA
In Erase
mA
CE=VIH, Erase Suspended
ICCES
VCC Erase Suspend Current
2
NOTES:
1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.
2. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is
the sum of ICCES and ICC1 or ICC2.
4. All current are in RMS unless otherwise noted.
P/N:PM0556
REV. 1.3, NOV. 11, 2002
20
MX29F022/022NT/B
±5% for 29F022T/B-55)
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ± 10%(VCC=5V±
29F022T/B-55(Note2) 29F022T/B-70 29F022T/B-90
MAX.
MIN.
MAX.
MIN.
29F022T/B-12
SYMBOL
PARAMETER
MIN.
tOES
OE setup time
0
0
0
MAX. MIN.
0
MAX. UNIT
ns
tCWC
Command programming cycle
70
70
90
120
ns
tCEP
WE programming pulse width
45
45
45
50
ns
tCEPH1
WE programming pulse width High
20
20
20
20
ns
tCEPH2
WE programming pulse width High
20
20
20
20
ns
tAS
Address setup time
0
0
0
0
ns
tAH
Address hold time
45
45
45
50
ns
tDS
Data setup time
20
30
45
50
ns
tDH
Data hold time
0
0
0
0
ns
tCESC
CE setup time before command write
0
0
0
0
ns
tDF
Output disable time (Note 1)
20
30
40
40
ns
tAETC
Total erase time in auto chip erase
3(TYP.) 24
3(TYP.) 24
3(TYP.) 24
3(TYP.) 24
s
tAETB
Total erase time in auto sector erase
1(TYP.) 8
1(TYP.) 8
1(TYP.) 8
1(TYP.) 8
s
tAVT
Total programming time in auto verify
7(TYP.) 210
7(TYP.) 210
7(TYP.) 210
7(TYP.) 210
us
(Byte Program time)
tBAL
Sector address load time
100
100
100
100
us
tCH
CE Hold Time
0
0
0
0
us
tCS
CE setup to WE going low
0
0
0
0
us
tVLHT
Voltage Transition Time
4
4
4
4
us
tOESP
OE Setup Time to WE Active
4
4
4
4
us
tWPP1
Write pulse width for chip protect
10
10
10
10
us
tWPP2
Write pulse width for chip unprotect
12
12
12
12
ms
NOTES:
1.tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
2.Under condition of VCC=5V±5%,CL=50pF, VIH/VIL=3.0V/0V, VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=-2mA.
P/N:PM0556
REV. 1.3, NOV. 11, 2002
21
MX29F022/022NT/B
SWITCHING TEST CIRCUITS
1.6K ohm
DEVICE UNDER
TEST
CL
1.2K ohm
+5V
DIODES=IN3064
OR EQUIVALENT
CL=100pF Including jig capacitance for 29F022/022N-70,
29F022/022N-90,29F022/022N-12
CL=50pF Including jig capacitance for 29F022/022N-55
SWITCHING TEST WAVEFORMS(I) for MX29F022/022N-70/90/120
2.4V
2.0V
2.0V
TEST POINTS
0.8V
0.8V
0.45V
INPUT
OUTPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are <20ns.
SWITCHING TEST WAVEFORMS(I) for MX29F022/022N-55
3.0V
1.5V
TEST POINTS
1.5V
0V
INPUT
OUTPUT
AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".
Input pulse rise and fall times are < 5ns.
P/N:PM0556
REV. 1.3, NOV. 11, 2002
22
MX29F022/022NT/B
COMMAND WRITE TIMING WAVEFORM
VCC
5V
ADD
A0~17
VIH
WE
VIH
ADD Valid
VIL
tAH
tAS
VIL
tOES
tCEPH1
tCEP
tCWC
CE
VIH
VIL
tCS
OE
VIL
DATA
Q0-7
tCH
VIH
tDS
tDH
VIH
DIN
VIL
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REV. 1.3, NOV. 11, 2002
23
MX29F022/022NT/B
AUTOMATIC PROGRAMMING TIMING WAVEFORM
polling and toggle bit checking after automatic
verification star ts. Device outputs DATA during
programming and DATA after programming on Q7.(Q6 is
for toggle bit; see toggle bit, DATA polling, timing
waveform)
One byte data is programmed. Verifying in fast
algorithm and additional programming by external
control are not required because these operations are
executed automatically by internal control circuit.
Programming completion can be verified by DATA
AUTOMATIC PROGRAMMING TIMING WAVEFORM
Vcc 5V
A11~A17
A0~A10
ADD Valid
2AAH
555H
tAS
WE
ADD Valid
555H
tCWC
tAH
tCEPH1
tCESC
tAVT
CE
tCEP
OE
tDS
Q0~Q1
tDH
Command In
tDF
Command In
Command In
DATA
Data In
DATA polling
,Q4(Note 1)
Q7
Command In
Command #AAH
Command In
Command In
Command #55H
Command #A0H
DATA
Data In
(Q0~Q7)
DATA
tOE
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2:Toggle bit
P/N:PM0556
REV. 1.3, NOV. 11, 2002
24
MX29F022/022NT/B
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Toggle Bit Checking
Q6 not Toggled
NO
YES
Invalid
Command
NO
Verify Byte Ok
YES
NO
.
Q5 = 1
Auto Program Completed
YES
Reset
Auto Program Exceed
Timing Limit
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REV. 1.3, NOV. 11, 2002
25
MX29F022/022NT/B
TOGGLE BIT ALGORITHM
START
Read Q7~Q0
(Note 1)
Read Q7~Q0
NO
Toggle Bit Q6
=Toggle?
YES
NO
Q5=1?
YES
(Note 1,2)
Read Q7~Q0 Twice
Toggle Bit Q6
=Toggle?
YES
Program/Erase Operation Not
Complete, Write Reset Command
Program/Erase Operation Complete
Notes:
1.Read toggle bit Q6 twice to determine whether or not it is toggle. See text.
2.Recheck toggle bit Q6 because it may stop toggling as Q5 changes to "1". See text.
P/N:PM0556
REV. 1.3, NOV. 11, 2002
26
MX29F022/022NT/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is
not required because data is erased automatically by
internal control circuit. Erasure completion can be
verified by DATA polling and toggle bit checking after
automatic erase starts. Device outputs "0" during
erasure and 1 after erasure on Q7.(Q6 is for toggle bit;
see toggle bit, DATA polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM
Vcc 5V
A11~A17
A0~A10
2AAH
555H
555H
555H
tAS
WE
2AAH
555H
tCWC
tAH
tCEPH1
tAETC
CE
tCEP
OE
tDS tDH
Q0,Q1,
Command In
Command In
Command In
Command In
Command In
Command In
Q4(Note 1)
Q7
DATA polling
Command In
Command In
Command In
Command In
Command In
Command In
Command #AAH
Command #55H
Command #80H
Command #AAH
Command #55H
Command #10H
(Q0~Q7)
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
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REV. 1.3, NOV. 11, 2002
27
MX29F022/022NT/B
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Toggle Bit Checking
Q6 not Toggled
NO
YES
Invalid
Command
NO
DATA Polling
Q7 = 1
YES
NO
Q5 = 1
Auto Chip Erase Completed
YES
Reset
.
Auto Chip Erase Exceed
Timing-Limit
P/N:PM0556
REV. 1.3, NOV. 11, 2002
28
MX29F022/022NT/B
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
checking after automatic erase starts. Device outputs 0
during erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, DATA polling, timing waveform)
Sector data indicated by A13 to A17 are erased. External erase verification is not required because data are
erased automatically by internal control circuit. Erasure
completion can be verified by DATA polling and toggle bit
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Vcc 5V
Sector
Address0
A13~A17
A0~A10
555H
2AAH
555H
555H
Sector
Address1
Sector
Addressn
2AAH
tAS
tCWC
tAH
WE
tCEPH1
tBAL
tAETB
CE
tCEP
OE
tDS tDH
Q0,Q1,
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Q4(Note 1)
Q7
DATA polling
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H
(Q0~Q7)
Command
In
Command #30H
Command
In
Command #30H
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N:PM0556
REV. 1.3, NOV. 11, 2002
29
MX29F022/022NT/B
AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
Toggle Bit Checking
Q6 Toggled ?
NO
Invalid Command
YES
Load Other Sector Addrss If Necessary
(Load Other Sector Address)
NO
Last Sector
to Erase
YES
Time-out Bit
Checking Q3=1 ?
NO
YES
Toggle Bit Checking
Q6 not Toggled
NO
YES
NO
Q5 = 1
DATA Polling
Q7 = 1
YES
Reset
Auto Sector Erase Completed
Auto Sector Erase Exceed
Timing Limit
P/N:PM0556
REV. 1.3, NOV. 11, 2002
30
MX29F022/022NT/B
ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data B0H
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
Programming End
NO
YES
Write Data 30H
Continue Erase
Another
Erase Suspend ?
NO
YES
P/N:PM0556
REV. 1.3, NOV. 11, 2002
31
MX29F022/022NT/B
TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITH 12V
A1
A6
12V
5V
A9
tVLHT
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 1
WE
tOESP
CE
Data
01H
tOE
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V
A1
12V
5V
A9
tVLHT
A6
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 2
WE
tOESP
CE
Data
00H
tOE
P/N:PM0556
REV. 1.3, NOV. 11, 2002
32
MX29F022/022NT/B
CHIP PROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
PLSCNT=1
OE=VID,A9=VID,CE=VIL
A6=VIL
Activate WE Pulse
Time Out 10us
Device Failed
Set WE=VIH, CE=OE=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1
No
PLSCNT=32?
No
Data=01H?
Yes
Yes
Remove VID from A9
Write Reset Command
Device Failed
Chip Protection
Complete
P/N:PM0556
REV. 1.3, NOV. 11, 2002
33
MX29F022/022NT/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
PLSCNT=1
Set OE=A9=VID
CE=VIL,A6=1
Activate WE Pulse
Time Out 12ms
Increment
PLSCNT
Set OE=CE=VIL
A9=VID,A1=1
Read Data from Device
No
Data=00H?
No
PLSCNT=1000?
Yes
Yes
Remove VID from A9
Write Reset Command
Device Failed
Chip Unprotect
Complete
P/N:PM0556
REV. 1.3, NOV. 11, 2002
34
MX29F022/022NT/B
TIMING WAVEFORM FOR CHIP PROTECTION/UNPROTECTION FOR SYSTEM WITHOUT 12V
6th command
cycle : 555H
7th command
cycle
A6,A9 & sector address are don't care
during toggle bit polling period, or just
be kept valid value in read window.
Protected Verify
Reset to Read Mode
'1'
A1
X
tACC
'1'
A6
X
A9
X
X
X=Don't care
'0'
'0'
X
(Note 2)
'0'
X
X
X
X
OE
tAS tAH
tOE
WE
A6,A9 and Sector Addr. should be latched on the falling e
dge of WE or CE , ehich occurs last, for WSM reference
CE
Toggle Bit Polling
tCEP
(Q0-Q7)
20H
X(2)
Dout
Dout
tCE
Dout
Dout
F0H
Note1: Don't care except F0H.
Note2: Protection:7th command cycle A6 goes low.
Unprotection: 7th command cycle A6 goes high.
Note3: Protection verify:01H
Un-protection verify:00H
Note4: Must issue "unlock for chip protection/unprotection" command before chip protection/un-protection for a
system without 12V provided.
P/N:PM0556
REV. 1.3, NOV. 11, 2002
35
MX29F022/022NT/B
CHIP PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "Unlock for chip protect/unprotect"
Command
OE=VID,A9=VID
CE=VIL,A6=VIL
Activate WE Pulse to start
Data don't care
Toggle bit checking
Q6 not Toggle
No
.
Yes
Set CE=OE=VIL
A9=VIH
Increment PLSCNT
Read from Sector
Addr. =SA,A1=1
No
PLSCENT=32?
No
Data=01H?
Yes
Device Failed
Yes
Write Reset Command
Chip Protection
Complete
P/N:PM0556
REV. 1.3, NOV. 11, 2002
36
MX29F022/022NT/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "unlock for chip protect/unprotect"
Command (Table 1)
Set OE=A9=VIH
CE=VIL,A6=1
Activate WE Pulse to start
Data don't care
No
Toggle bit checking
Q6 not Toggled
Increment
PLSCNT
Yes
Set OE=CE=VIL
A9=VIH,A1=1
Read Data from Device
No
Data=00H?
No
Yes
PLSCNT=1000?
Yes
Write Reset Command
Device Failed
Chip Unprotect
Complete
P/N:PM0556
REV. 1.3, NOV. 11, 2002
37
MX29F022/022NT/B
ID CODE READ TIMING WAVEFORM MODE
VCC
5V
VID
VIH
VIL
ADD
A9
tACC
tACC
A1
VIH
VIL
ADD
A2-A8
A10-A17
CE
VIH
VIL
VIH
VIL
WE
VIH
tCE
VIL
OE
VIH
tOE
VIL
tDF
tOH
tOH
VIH
DATA
Q0-Q7
DATA OUT
DATA OUT
VIL
36H/37H
C2H
P/N:PM0556
REV. 1.3, NOV. 11, 2002
38
MX29F022/022NT/B
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO.
ACCESS TIME
OPERATING CURRENT
STANDBY CURRENT
PACKAGE
(ns)
MAX.(mA)
MAX.(uA)
MX29F022TPC-55
55
30
5
32 Pin PDIP
MX29F022TPC-70
70
30
5
32 Pin PDIP
MX29F022TPC-90
90
30
5
32 Pin PDIP
MX29F022TPC-12
120
30
5
32 Pin PDIP
MX29F022TTC-55
55
30
5
32 Pin TSOP
(Normal Type)
MX29F022TTC-70
70
30
5
32 Pin TSOP
(Normal Type)
MX29F022TTC-90
90
30
5
32 Pin TSOP
(Normal Type)
MX29F022TTC-12
120
30
5
32 Pin TSOP
(Normal Type)
MX29F022TQC-55
55
30
5
32 Pin PLCC
MX29F022TQC-70
70
30
5
32 Pin PLCC
MX29F022TQC-90
90
30
5
32 Pin PLCC
MX29F022TQC-12
120
30
5
32 Pin PLCC
MX29F022BPC-55
55
30
5
32 Pin PDIP
MX29F022BPC-70
70
30
5
32 Pin PDIP
MX29F022BPC-90
90
30
5
32 Pin PDIP
MX29F022BPC-12
120
30
5
32 Pin PDIP
MX29F022BTC-55
55
30
5
32 Pin TSOP
(Normal Type)
MX29F022BTC-70
70
30
5
32 Pin TSOP
(Normal Type)
MX29F022BTC-90
90
30
5
32 Pin TSOP
(Normal Type)
MX29F022BTC-12
120
30
5
32 Pin TSOP
(Normal Type)
MX29F022BQC-70
70
30
5
32 Pin PLCC
MX29F022BQC-90
90
30
5
32 Pin PLCC
MX29F022BQC-12
120
30
5
32 Pin PLCC
MX29F022NTPC-55
55
30
5
32 Pin PDIP
MX29F022NTPC-70
70
30
5
32 Pin PDIP
MX29F022NTPC-90
90
30
5
32 Pin PDIP
MX29F022NTPC-12
120
30
5
32 Pin PDIP
P/N:PM0556
REV. 1.3, NOV. 11, 2002
39
MX29F022/022NT/B
PART NO.
ACCESS TIME
OPERATING CURRENT
STANDBY CURRENT
(ns)
MAX.(mA)
MAX.(uA)
MX29F022NTTC-55
55
30
5
MX29F022NTTC-70
70
30
5
PACKAGE
32 Pin TSOP
(Normal Type)
32 Pin TSOP
(Normal Type)
MX29F022NTTC-90
90
30
5
MX29F022NTTC-12
120
30
5
32 Pin TSOP
(Normal Type)
32 Pin TSOP
(Normal Type)
MX29F022NTQC-55
55
30
5
32 Pin PLCC
MX29F022NTQC-70
70
30
5
32 Pin PLCC
MX29F022NTQC-90
90
30
5
32 Pin PLCC
MX29F022NTQC-12
120
30
5
32 Pin PLCC
MX29F022NBPC-55
55
30
5
32 Pin PDIP
MX29F022NBPC-70
70
30
5
32 Pin PDIP
MX29F022NBPC-90
90
30
5
32 Pin PDIP
MX29F022NBPC-12
120
30
5
32 Pin PDIP
MX29F022NBTC-55
55
30
5
32 Pin TSOP
MX29F022NBTC-70
70
30
5
(Normal Type)
32 Pin TSOP
(Normal Type)
MX29F022NBTC-90
90
30
5
MX29F022NBTC-12
120
30
5
32 Pin TSOP
(Normal Type)
32 Pin TSOP
(Normal Type)
MX29F022NBQC-70
70
30
5
32 Pin PLCC
MX29F022NBQC-90
90
30
5
32 Pin PLCC
MX29F022NBQC-12
120
30
5
32 Pin PLCC
P/N:PM0556
REV. 1.3, NOV. 11, 2002
40
MX29F022/022NT/B
ERASE AND PROGRAMMING PERFORMANCE (1)
LIMITS
TYP.(2)
MAX.(3)
UNITS
Sector Erase Time
1
8
s
Chip Erase Time
3
24
s
Byte Programming Time
7
210
us
Chip Programming Time
3.5
10.5
sec
PARAMETER
Erase/Program Cycles
Note:
MIN.
100,000
Cycles
1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25° C,5V.
3.Maximum value measured at 25° C,4.5V.
LATCH-UP CHARACTERISTICS
MIN.
MAX.
Input Voltage with respect to GND on all pins except I/O pins
-1.0V
13.5V
Input Voltage with respect to GND on all I/O pins
-1.0V
Vcc + 1.0V
-100mA
+100mA
MIN.
UNIT
20
Years
Current
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
DATA RETENTION
PARAMETER
Data Retention Time
P/N:PM0556
REV. 1.3, NOV. 11, 2002
41
MX29F022/022NT/B
PACKAGE INFORMATION
P/N:PM0556
REV. 1.3, NOV. 11, 2002
42
MX29F022/022NT/B
P/N:PM0556
REV. 1.3, NOV. 11, 2002
43
MX29F022/022NT/B
P/N:PM0556
REV. 1.3, NOV. 11, 2002
44
MX29F022/022NT/B
REVISION HISTORY
Revision
Description
Page
Date
1.0
1.To remove "Advanced Information" data sheet marking and
contain information on products in full production
2.The modification summary of Revision 0.9.4 to Revision 1.0:
2-1.Program/erase cycle times:10K cycles-->100K cycles
2-2.To add data retention 20 years
2-3.To remove A9 from the timing waveform of protection/
unprotection without 12V
2-4.Multi-sector erase time-out:30ms-->30us,
2-5.tBAL:80us-->100us
To modify "Package Information"
1. To correct typing error
1. To change part no. from MX29F022/022N to MX29F022/022NT/B
P1
DEC/21/1999
1.1
1.2
1.3
P/N:PM0556
P1,41
P1,41
P35
P8
P21
P42~44
All
All
JUN/14/2001
JUN/11/2002
NOV/11/2002
REV. 1.3, NOV. 11, 2002
45
MX29F022/022NT/B
MACRONIX INTERNATIONAL CO., LTD.
Headquarters:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
Europe Office :
TEL:+32-2-456-8020
FAX:+32-2-456-8021
Hong Kong Office :
TEL:+86-755-834-335-79
FAX:+86-755-834-380-78
Japan Office :
Kawasaki Office :
TEL:+81-44-246-9100
FAX:+81-44-246-9105
Osaka Office :
TEL:+81-6-4807-5460
FAX:+81-6-4807-5461
Singapore Office :
TEL:+65-6346-5505
FAX:+65-6348-8096
Taipei Office :
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-262-8887
FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.