AD ADL5906SCPZN-R2 10 mhz to 10 ghz 67 db trupwr detector Datasheet

10 MHz to 10 GHz
67 dB TruPwr Detector
ADL5906
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VPOS2
3
10
TEMPERATURE
SENSOR
ADL5906
RFIN+ 14
VTEMP
7
VSET
6
VRMS
5
CRMS
LINEAR-IN-dB VGA
(NEGATIVE SLOPE)
X2
ITGT
NIC 2
G=5
NIC 16
BIAS AND POWER
DOWN CONTROL
VREF
2.3V
EPAD
Power amplifier linearization/control loops
Transmitter signal strength indication (TSSI)
RF instrumentation
8
ISQR
X2
RFIN– 15
NIC 13
APPLICATIONS
VPOS1
26pF
1
11
TADJ/
PWDN
VREF
12
VTGT GND2
9
4
GND1
11287-001
Accurate rms-to-dc conversion from 10 MHz to 10 GHz
Single-ended ±1.0 dB dynamic range: 67 dB at 2.14 GHz
No balun or external input matching required
Response independent of waveform types, such as
GSM-EDGE/CDMA/W-CDMA/TD-SCDMA/WiMAX/LTE
Logarithmic slope: 55 mV/dB
Temperature stability: <±1 dB from −40°C to +125°C
Operating temperature: −55°C to +125°C
Supply voltage: 4.75 V to 5.25 V
Sleep current: 250 µA
Pin compatible with ADL5902 and AD8363
Figure 1.
GENERAL DESCRIPTION
The ADL5906 is a true rms responding power detector that has a
67 dB measurement range when driven with a single-ended 50 Ω
source. The easy to use input makes the ADL5906 frequency
versatile by eliminating the need for a balun or any other form
of external input tuning for operation up to 10 GHz.
The ADL5906 provides a solution in a variety of high frequency
systems requiring an accurate rms measurement of signal power.
The ADL5906 can operate from 10 MHz to 10 GHz and can
accept inputs from −65 dBm to +8 dBm with varying crest factors
and bandwidths, such as GSM-EDGE, CDMA, W-CDMA,
TD-SCDMA, WiMAX, and OFDM-based LTE carriers. In
addition, its temperature stability over the broad temperature
range of −55°C to +125°C makes it ideally suited for a wide array
of communications, military, industrial, and instrumentation
applications.
Rev. 0
Used as a power measurement device, VRMS is connected to
VSET. The output is then proportional to the logarithm of the
rms value of the input. In other words, the reading is presented
directly in decibels and is scaled 1.1 V per decade, or 55 mV/dB;
other slopes are easily arranged. In controller mode, the voltage
applied to VSET determines the power level required at the
input to null the deviation from the setpoint. The output buffer
can provide high load currents.
Requiring only a single supply of 5 V and a few capacitors, it is
easy to use and capable of being driven single-ended or with a
balun for differential input drive. The ADL5906 has a low 250 µA
sleep current when powered down by a logic high applied to the
PWDN pin. It powers up within approximately 1.4 µs to its
nominal operating current of 68 mA at 25°C.
The ADL5906 is supplied in a 4 mm × 4 mm, 16-lead LFCSP, and
it is pin compatible with the ADL5902 and the AD8363 TruPwr™
rms detectors. This feature allows the designer to create one circuit
layout for projects requiring different dynamic ranges. A fully
populated RoHS-compliant evaluation board is available.
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ADL5906
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
VSET Interface ............................................................................ 19
Applications ....................................................................................... 1
Output Interface ......................................................................... 19
Functional Block Diagram .............................................................. 1
VTGT Interface .......................................................................... 19
General Description ......................................................................... 1
Basis for Error Calculations ...................................................... 20
Revision History ............................................................................... 2
Measurement Mode Basic Connections.................................. 20
Specifications..................................................................................... 3
Setting VTADJ ................................................................................ 20
Absolute Maximum Ratings ............................................................ 7
Setting VTGT ................................................................................. 21
ESD Caution .................................................................................. 7
Choosing a Value for CRMS......................................................... 21
Pin Configuration and Function Descriptions ............................. 8
Output Voltage Scaling .............................................................. 22
Typical Performance Characteristics ............................................. 9
System Calibration and Error Calculation.............................. 24
Theory of Operation ...................................................................... 16
Using VTEMP to Improve Intercept Temperature Drift ........... 25
Square Law Detector and Amplitude Target .............................. 16
Description of Characterization ............................................... 27
RF Input Interface ...................................................................... 17
Evaluation Board ............................................................................ 28
Temperature Sensor Interface ................................................... 17
Evaluation Board Assembly Drawings .................................... 29
VREF Interface ........................................................................... 17
Outline Dimensions ....................................................................... 30
Temperature Compensation Interface ..................................... 18
Ordering Guide .......................................................................... 30
Power-Down Interface ............................................................... 19
REVISION HISTORY
3/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
Data Sheet
ADL5906
SPECIFICATIONS
VPOS1 = VPOS2 = 5 V, TA = 25°C, single-ended input drive, RT = 60.4 Ω, VRMS connected to VSET, VTGT = 0.8 V, CRMS = 0.1 µF. Negative
current values imply that the ADL5906 is sourcing current out of the indicated pin.
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range
RF INPUT INTERFACE
Input Impedance
Common-Mode Voltage
100 MHz
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
700 MHz
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
900 MHz
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
Deviation from CW Response
(−45 dBm to −5 dBm)
Test Conditions/Comments
Min
Typ
Max
Unit
10 to 10,000
MHz
2500
2.5
Ω
V
Continuous wave (CW) input, TA = 25°C
Calibration at −55 dBm, −40 dBm, and 0 dBm
Calibration at −55 dBm, −40 dBm, and 0 dBm
Deviation from output at 25°C, VTADJ = 0.35 V
−40°C < TA < +85°C; PIN = 0 dBm
−40°C < TA < +85°C; PIN = −45 dBm
−55°C < TA < +125°C; PIN = 0 dBm
−55°C < TA < +125°C; PIN = −45 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
62
2
−60
dB
dBm
dBm
−0.8/+0.2
−0.8/+0.4
−1.3/+0.2
−1.2/+0.6
59
−64
dB
dB
dB
dB
mV/dB
dBm
CW input, TA = 25°C
Calibration at −55 dBm, −40 dBm, and 0 dBm
Calibration at −55 dBm, −40 dBm, and 0 dBm
Deviation from output at 25°C, VTADJ = 0.35 V
−40°C < TA < +85°C; PIN = 0 dBm
−40°C < TA < +85°C; PIN = −45 dBm
−55°C < TA < +125°C; PIN = 0 dBm
−55°C < TA < +125°C; PIN = −45 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm, and 0 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
62
2
−60
dB
dBm
dBm
−0.9/+0.3
−0.9/+0.4
−1.5/+0.3
−1.3/+0.7
59
−65
dB
dB
dB
dB
mV/dB
dBm
63
3
−60
dB
dBm
dBm
−0.8/+0.3
−0.9/+0.4
−1.4/+0.3
−1.4/+0.8
59
−65
−0.1
dB
dB
dB
dB
mV/dB
dBm
dB
−0.2
dB
0.05
−0.1
dB
dB
RFIN+, Pin RFIN− (Pin 14, Pin 15), ac-coupled
Single-ended drive, 50 MHz
CW input, TA = 25°C
Calibration at −55 dBm, −40 dBm, and 0 dBm
Calibration at −55 dBm, −40 dBm, and 0 dBm
Deviation from output at 25°C, VTADJ = 0.35 V
−40°C < TA < +85°C; PIN = 0 dBm
−40°C < TA < +85°C; PIN = −45 dBm
−55°C < TA < +125°C; PIN = 0 dBm
−55°C < TA < +125°C; PIN = −45 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
12.16 dB peak-to-rms ratio (four-carrier W-CDMA)
11.58 dB peak-to-rms ratio (LTE TM1, one-carrier, 20 MHz
bandwidth)
10.56 dB peak-to-rms ratio (W-CDMA)
7.4 dB peak-to-rms ratio (64 QAM)
Rev. 0 | Page 3 of 32
ADL5906
Parameter
1900 MHz
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
2140 MHz
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
Deviation from CW Response
(−45 dBm to −5 dBm)
2600 MHz
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
3500 MHz
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
Data Sheet
Test Conditions/Comments
Min
Typ
Max
Unit
CW input, TA = 25°C
Calibration at −55 dBm, −40 dBm, and 0 dBm
Calibration at −55 dBm, −40 dBm, and 0 dBm
Deviation from output at 25°C, VTADJ = 0.35 V
−40°C < TA < +85°C; PIN = 0 dBm
−40°C < TA < +85°C; PIN = −45 dBm
−55°C < TA < +125°C; PIN = 0 dBm
−55°C < TA < +125°C; PIN = −45 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
66
6
−60
dB
dBm
dBm
−0.8/+0.2
−0.8/+0.5
−1.4/+0.2
−1.2/+0.9
57
−65
dB
dB
dB
dB
mV/dB
dBm
CW input, TA = 25°C
Calibration at −55 dBm, −40 dBm, and 0 dBm
Calibration at −55 dBm, −40 dBm, and 0 dBm
Deviation from output at 25°C, VTADJ = 0.35 V
−40°C < TA < +85°C; PIN = 0 dBm
−40°C < TA < +85°C; PIN = −45 dBm
−55°C < TA < +125°C; PIN = 0 dBm
−55°C < TA < +125°C; PIN = −45 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
12.16 dB peak-to-rms ratio (four-carrier W-CDMA)
67
7
−60
dB
dBm
dBm
−0.8/+0.3
−0.8/+0.6
−1.3/+0.3
−1.2/+0.9
56
−65
−0.1
dB
dB
dB
dB
mV/dB
dBm
dB
11.58 dB peak-to-rms ratio (LTE TM1, one-carrier, 20 MHz
bandwidth)
10.56 dB peak-to-rms ratio (one-carrier W-CDMA)
7.4 dB peak-to-rms ratio (64 QAM)
0.1
dB
0.1
−0.1
dB
dB
68
8
−60
dB
dBm
dBm
−0.9/+0.3
−1/+0.5
−1.4/+0.3
−1.4/+0.8
55
−65
dB
dB
dB
dB
mV/dB
dBm
65
5
−60
dB
dBm
dBm
−1.5/0
−1/+0.3
−1.5/0
−1.4/+0.4
52
−64
dB
dB
dB
dB
mV/dB
dBm
CW input, TA = 25°C
Calibration at −55 dBm, −40 dBm, and 0 dBm
Calibration at −55 dBm, −40 dBm, and 0 dBm
Deviation from output at 25°C, VTADJ = 0.4 V
−40°C < TA < +85°C; PIN = 0 dBm
−40°C < TA < +85°C; PIN = −45 dBm
−55°C < TA < +125°C; PIN = 0 dBm
−55°C < TA < +125°C; PIN = −45 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
CW input, TA = 25°C
Calibration at −55 dBm, −40 dBm, and 0 dBm
Calibration at −55 dBm, −40 dBm, and 0 dBm
Deviation from output at 25°C, VTADJ = 0.45 V
−40°C < TA < +85°C; PIN = 0 dBm
−40°C < TA < +85°C; PIN = −45 dBm
−55°C < TA < +125°C; PIN = 0 dBm
−55°C < TA < +125°C; PIN = −45 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
Rev. 0 | Page 4 of 32
Data Sheet
Parameter
5800 MHz
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
OUTPUT INTERFACE
Output Swing, Controller Mode
Current Source/Sink Capability
Rise Time
Fall Time
SETPOINT INPUT
Voltage Range
Input Resistance
Logarithmic Scale Factor
Logarithmic Intercept
TEMPERATURE COMPENSATION
Input Voltage Range
Input Bias Current
Input Resistance
VOLTAGE REFERENCE
Output Voltage
Temperature Sensitivity
Short-Circuit Current Source/
Sink Capability
Voltage Regulation
TEMPERATURE REFERENCE
Output Voltage
Temperature Coefficient
Short-Circuit Current Source/
Sink Capability
Voltage Regulation
RMS TARGET INTERFACE
Input Voltage Range
Input Bias Current
Input Resistance
POWER-DOWN INTERFACE
Voltage Level to Enable
Voltage Level to Disable
Input Bias Current
Enable Time
Disable Time
ADL5906
Test Conditions/Comments
Min
CW input, TA = 25°C
Calibration at −50 dBm, −40 dBm, and 0 dBm
Calibration at −50 dBm, −40 dBm, and 0 dBm
Deviation from output at 25°C, VTADJ = 1 V
−40°C < TA < +85°C; PIN = 0 dBm
−40°C < TA < +85°C; PIN = −45 dBm
−55°C < TA < +125°C; PIN = 0 dBm
−55°C < TA < +125°C; PIN = −45 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
−65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm
VRMS (Pin 6)
Swing range minimum, RL ≥ 500 Ω to ground
Swing range maximum, RL ≥ 500 Ω to ground
Typ
Max
57
3
−54
dB
dBm
dBm
−2.4/+0
−1.4/-0.2
−3.6/+0
−2.1/-0.2
42
−60
dB
dB
dB
dB
mV/dB
dBm
0.05
3.92
0.1
14.6
V
V
mA
µs
µs
3.92
0.4
72
56
−65
V
V
kΩ
mV/dB
dBm
10/10
PIN = off to −10 dBm, 10% to 90%, CRMS = 1 nF
PIN = −10 dBm to off, 90% to 10%, CRMS = 1 nF
VSET (Pin 7)
Log conformance error ≤ 1 dB, minimum 2.14 GHz
Log conformance error ≤ 1 dB, maximum 2.14 GHz
f = 2.14 GHz
f = 2.14 GHz
TADJ/PWDN (Pin 1)
0
VTADJ = 0.35 V
VTADJ = 0.35 V
VREF (Pin 11)
PIN = −55 dBm
25°C ≤ TA ≤ 125°C
−55°C ≤ TA ≤ +25°C
25°C ≤ TA ≤ 125°C
−55°C ≤ TA ≤ +25°C
TA = 25°C, ILOAD = 2 mA
VTEMP (Pin 8)
TA = 25°C, RL ≥ 10 kΩ
−40°C ≤ TA ≤ +125°C, RL ≥ 10 kΩ
25°C ≤ TA ≤ 125°C
−55°C ≤ TA ≤ +25°C
TA = 25°C, ILOAD = 1 mA
VTGT (Pin 12)
5
70
VPOS
V
µA
kΩ
2.3
−0.12
0.07
4/0.05
V
mV/°C
mV/°C
mA
3/0.05
−0.4
mA
%
1.4
4.8
4/0.05
V
mV/°C
mA
3/0.05
−2.8
mA
%
0.2
VTGT = 0.8 V
2.5
V
µA
kΩ
1.3
V
V
µA
µA
µs
µs
8
100
VTADJ/PWDN (Pin 1)
VPWDN decreasing
VPWDN increasing
VPWDN = 5 V
VPWDN = 0 V
VPWDN low to VRMS, 10% to 90%, CRMS = 1 nF, PIN = 0 dBm
VPWDN high to VRMS, 90% to 10%, CRMS = 1 nF, PIN = 0 dBm
Rev. 0 | Page 5 of 32
Unit
1.4
72
0.1
1.4
1.0
ADL5906
Parameter
POWER SUPPLY INTERFACE
Supply Voltage
Quiescent Current
Power-Down Current
Data Sheet
Test Conditions/Comments
VPOS1, VPOS2 (Pin 3, Pin 10)
TA = 25°C, PIN < −60 dBm
TA = 125°C, PIN < −60 dBm
VPWDN > 1.4 V
Rev. 0 | Page 6 of 32
Min
Typ
Max
Unit
4.75
5
68
86
250
5.25
V
mA
mA
µA
Data Sheet
ADL5906
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage, VPOS1, VPOS2
Input Average RF Power1
Equivalent Voltage, Sine Wave Input
Internal Power Dissipation
θJC2
θJB2
θJA2
ΨJT2
ΨJB2
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
1
2
Rating
5.25 V
21 dBm
2.51 V p-p
550 mW
10.6°C/W
35.3°C/W
57.2°C/W
1.0°C/W
34°C/W
150°C
−55°C to +125°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
This is for long durations. Excursions above this level, with durations much
less than 1 second, are possible without damage.
No airflow with the exposed pad soldered to a 4-layer JEDEC board.
Rev. 0 | Page 7 of 32
ADL5906
Data Sheet
12 VTGT
11 VREF
10 VPOS2
9 GND2
14 RFIN+
NOTES
1. NIC = NO INTERNAL CONNECTION. DO NOT
CONNECT TO THIS PIN.
2. THE EXPOSED PAD REQUIRES A GOOD THERMAL
AND ELECTRICAL CONNECTION TO THE GROUND
OF THE PRINTED CIRCUIT BOARD (PCB).
11287-002
VTEMP 8
VSET 7
CRMS 5
GND1 4
ADL5906
TOP VIEW
(Not to Scale)
VRMS 6
VPOS1 3
13 NIC
PIN 1
INDICATOR
TADJ/PWDN 1
NIC 2
15 RFIN–
16 NIC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
TADJ/PWDN
2, 13, 16
3, 10
NIC
VPOS1,
VPOS2
4, 9
5
GND1, GND2
CRMS
6
VRMS
7
VSET
8
11
VTEMP
VREF
12
VTGT
14, 15
RFIN+, RFIN−
EPAD
Description
Temperature Compensation/Shutdown. This is a dual function pin used for controlling temperature slope
compensation at voltages <1.0 V and/or for shutting down the device at voltages >1.4 V. The temperature
compensation voltage is generally set by connecting this pin to VREF through a resistive voltage divider (see
the Setting VTADJ section for additional information). See Figure 46 for an equivalent circuit.
No Internal Connection. Do not connect to these pins. These pins are not internally connected.
Power Supply. Because these pins are internally shorted, they must be connected to the same 5 V power
supply. The power supply to each pin must also be decoupled using 100 pF and 100 nF capacitors located as
close as possible to the pins.
Ground. Connect both GND1 and GND2 to system ground using a low impedance path.
RMS Averaging Capacitor. Connect an rms averaging capacitor between CRMS and ground. See the Choosing
a Value for CRMS section for more information. See Figure 48 for an equivalent circuit.
RMS Output. In measurement mode, this pin is connected to VSET either directly or through a resistor divider
(when the slope is being increased). In controller mode, this pin is used to drive the gain control input of a
voltage variable attenuator (VVA) or variable gain amplifier (VGA). See Figure 48 for an equivalent circuit.
Setpoint Input. In measurement mode, this pin is connected to VRMS either directly or through a resistor
divider. In controller mode, the voltage applied to this pin sets the decibel value of the required RF input level to
balance the automatic power control loop. See Figure 47 for an equivalent circuit.
Temperature Sensor Output of 1.4 V at 25°C with a Coefficient of 4.8 mV/°C. See Figure 43 for an equivalent circuit.
Reference Voltage Output. This voltage reference has a nominal value of 2.3 V. This reference output voltage
can be used to set the voltage to the TADJ/PWDN and VTGT pins. See Figure 44 for an equivalent circuit.
RMS Target Voltage. The voltage applied to this pin sets the target RF input at the output of the VGA that is also the
rms squaring circuit. The recommended voltage for VTGT is 0.8 V. Increasing VTGT above 0.8 V degrades the rms
accuracy of the ADL5906. Reducing VTGT below 0.8 V can improve the rms accuracy for signals with very high crest
factors; however, it reduces the detection range of the ADL5906. See Figure 49 for an equivalent circuit.
RF Inputs. The RF inputs are normally applied single-ended with the RF input signal ac-coupled to RFIN+ and
RFIN− ac-coupled to ground. See Figure 42 for an equivalent circuit.
The exposed pad on the underside of the device (EPAD) is also internally connected to ground and requires a
good thermal and electrical connection to the ground of the printed circuit board (PCB).
Rev. 0 | Page 8 of 32
Data Sheet
ADL5906
TYPICAL PERFORMANCE CHARACTERISTICS
VPOS1 = VPOS2 = 5 V, single-ended input drive, VRMS connected to VSET, VTGT = 0.8 V, CRMS = 0.1 µF, TA = +25°C (green),
−55°C (light blue), −40°C (blue), +85°C (red), +105°C (orange), and +125°C (black), where appropriate. Error referred to slope
and intercept at indicated calibration points. Input RF signal is a sine wave (CW), unless otherwise indicated.
4.0
4.0
100MHz TO 1GHz
0dBm
3.5
3.5
–10dBm
1.0
10
PIN (dBm)
0
0.01
1
10
FREQUENCY (GHz)
Figure 3. Typical VRMS vs. Input Power (dBm) vs. Frequency
(10 MHz to 10 GHz) at 25°C
6.0
0.1
Figure 6. Typical VRMS vs. Frequency for Six RF Input Levels
6.0
5
5.5
4
5.0
4.5
3
4.5
3
4.0
2
4.0
2
3.5
1
3.5
1
3.0
0
3.0
0
2.5
–1
2.5
–1
2.0
–2
2
–2
1.5
–3
1.5
–3
1.0
–4
1.0
–4
0.5
–5
0.5
–5
0
–65
ERROR (dB)
–6
–55
–45
–35
–25
–15
–5
0
–65
11287-104
5.0
CW
QPSK PEP = 3.8dB
16 QAM PEP = 6.3dB
64 QAM PEP = 7.4dB
OUTPUT VOLTAGE (V)
6
5.5
5
PIN (dBm)
5
4
–6
–55
–45
–35
–25
–15
–5
5
PIN (dBm)
Figure 4. Error from CW Linear Reference vs. Signal Modulation
(QPSK, 16 QAM, 64 QAM), Frequency = 900 MHz, CRMS = 0.1 µF,
Three Point Calibration at 0 dBm, −40 dBm, and −55 dBm
6.0
6
CW
QPSK PEP = 3.8dB
16 QAM PEP = 6.3dB
64 QAM PEP = 7.4dB
Figure 7. Error from CW Linear Reference vs. Signal Modulation
(QPSK, 16 QAM, 64 QAM), Frequency = 2.14 GHz, CRMS = 0.1 µF,
Three Point Calibration at 0 dBm, −40 dBm, and −55 dBm
6.0
5
5.5
4
5.0
4
4.5
3
4.5
3
4.0
2
4.0
2
3.5
1
3.5
1
3.0
0
3.0
0
2.5
–1
2.5
–1
2.0
–2
2
–2
1.5
–3
1.5
–3
1.0
–4
1.0
–4
0.5
–5
0.5
–5
0
–65
–6
–55
–45
–35
–25
PIN (dBm)
–15
–5
5
ERROR (dB)
11287-005
5.0
CW
CDMA 2000 PEP = 11.02dB
1C W-CDMA PEP = 10.56dB
4C W-CDMA PEP = 12.08dB
OUTPUT VOLTAGE (V)
6
5.5
ERROR (dB)
5
11287-003
0
11287-006
0.5
20MHz
10MHz
0
–65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
OUTPUT VOLTAGE (V)
–50dBm
1.0
0.5
OUTPUT VOLTAGE (V)
–40dBm
1.5
11287-007
1.5
–30dBm
2.0
Figure 5. Error from CW Linear Reference vs. Signal Modulation (CDMA 2000,
One-Carrier W-CDMA, Four-Carrier W-CDMA), Frequency = 2.14 GHz,
CRMS = 0.1 µF, Three Point Calibration at 0 dBm, −40 dBm, and −55 dBm
Rev. 0 | Page 9 of 32
0
–65
6
CW
LTE TM1 1CR 20MHz PEP = 11.58dB
5
ERROR (dB)
2.0
–20dBm
2.5
–6
–55
–45
–35
–25
–15
–5
5
PIN (dBm)
Figure 8. Error from CW Linear Reference vs. Signal Modulation
(LTE TM1 One-Carrier, 20 MHz), Frequency = 2.14 GHz, CRMS = 0.1 µF,
Three Point Calibration at 0 dBm, −40 dBm, and −55 dBm
11287-008
2.5
3.0
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
8GHz
9GHz
10GHz
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.0
ADL5906
Data Sheet
6.0
5
5.5
5.0
4
5.0
4
4.5
3
4.5
3
4.0
2
4.0
2
3.5
1
3.5
1
3.0
0
3.0
0
2.5
–1
2.5
–1
2.0
–2
2.0
–2
1.5
–3
1.5
–3
1.0
–4
1.0
–4
0.5
–5
0.5
–5
–15
–5
5
PIN (dBm)
Figure 9. VRMS and Log Conformance Error vs. Input Level and Temperature at
100 MHz
–35
–25
–15
–5
5
PIN (dBm)
5.0
4
5.0
4
4.5
3
4.5
3
4.0
2
4.0
2
3.5
1
3.5
1
3.0
0
3.0
0
2.5
–1
2.5
–1
2.0
–2
2.0
–2
1.5
–3
1.5
–3
1.0
–4
1.0
–4
0.5
–5
0.5
–5
–55
–45
–35
–25
–15
–5
5
PIN (dBm)
Figure 10. VRMS and Log Conformance Error vs. Input Level and Temperature
at 700 MHz
6.0
0
–65
11287-010
–6
OUTPUT VOLTAGE (V)
5.5
ERROR (dB)
6.0
0
–65
6
VTADJ = 0.35V
–55
–45
–35
–25
–15
–5
5
5
–6
PIN (dBm)
Figure 13. Distribution of Log Conformance Error with Respect to VRMS at
25°C vs. Input Level and Temperature at 700 MHz
5.5
5.0
4
5.0
4
4.5
3
4.5
3
4.0
2
4.0
2
3.5
1
3.5
1
3.0
0
3.0
0
2.5
–1
2.5
–1
2.0
–2
2.0
–2
1.5
–3
1.5
–3
1.0
–4
1.0
–4
0.5
–5
0.5
–6
–55
–45
–35
–25
PIN (dBm)
–15
–5
5
0
–65
11287-011
0
–65
OUTPUT VOLTAGE (V)
6.0
5
ERROR (dB)
6
VTADJ = 0.35V
CALIBRATION AT 0dBm, –40dBm, AND –55dBm
5.5
Figure 11. VRMS and Log Conformance Error vs. Input Level and Temperature
at 900 MHz
ERROR (dB)
Figure 12. Distribution of Log Conformance Error with Respect to VRMS at
25°C vs. Input Level and Temperature at 100 MHz
5
VTADJ = 0.35V
CALIBRATION AT 0dBm, –40dBm, AND –55dBm
5.5
OUTPUT VOLTAGE (V)
–45
6
6.0
OUTPUT VOLTAGE (V)
–6
–55
ERROR (dB)
–25
11287-013
–35
VTADJ = 0.35V
6
5
ERROR (dB)
–45
5
–5
–55
–45
–35
–25
PIN (dBm)
–15
–5
5
–6
11287-014
–55
0
–65
6
VTADJ = 0.35V
11287-012
–6
11287-009
OUTPUT VOLTAGE (V)
0
–65
ERROR (dB)
VTADJ = 0.35V
CALIBRATION AT 0dBm, –40dBm, AND –55dBm
5.5
OUTPUT VOLTAGE (V)
6
6.0
Figure 14. Distribution of Log Conformance Error with Respect to VRMS at
25°C vs. Input Level and Temperature at 900 MHz
Rev. 0 | Page 10 of 32
Data Sheet
6
VTADJ = 0.35V
CALIBRATION AT 0dBm, –40dBm, AND –55dBm 5
6.0
5.5
5.0
4
5.0
4
4.5
3
4.5
3
4.0
2
4.0
2
3.5
1
3.5
1
3.0
0
3.0
0
2.5
–1
2.5
–1
2.0
–2
2.0
–2
1.5
–3
1.5
–3
1.0
–4
1.0
–4
0.5
–5
0.5
–5
–25
–15
–5
5
PIN (dBm)
–35
–25
–15
–5
Figure 18. Distribution of Log Conformance Error with Respect to VRMS at
25°C vs. Input Level and Temperature at 1.9 GHz
6
6
VTADJ = 0.35V
CALIBRATION AT 0dBm, –40dBm, AND –55dBm 5
6.0
5.0
4
5.0
4
4.5
3
4.5
3
4.0
2
4.0
2
3.5
1
3.5
1
3.0
0
3.0
0
2.5
–1
2.5
–1
2.0
–2
2.0
–2
1.5
–3
1.5
–3
1.0
–4
1.0
–4
0.5
–5
0.5
–5
0
–65
–45
–35
–25
–15
–5
5
PIN (dBm)
OUTPUT VOLTAGE (V)
ERROR (dB)
Figure 16. VRMS and Log Conformance Error vs. Input Level and Temperature
at 2.14 GHz
6.0
VTADJ = 0.35V
5.5
–6
–55
0
–65
5
–6
–55
–45
–35
–25
–15
5
–5
PIN (dBm)
Figure 19. Distribution of Log Conformance Error with Respect to VRMS at
25°C vs. Input Level and Temperature at 2.14 GHz
6
5.5
5
5.0
4
5.0
4
4.5
3
4.5
3
4.0
2
4.0
2
3.5
1
3.5
1
3.0
0
3.0
0
2.5
–1
2.5
–1
2.0
–2
2.0
–2
1.5
–3
1.5
–3
1.0
–4
1.0
–4
0.5
–5
0.5
–5
–6
–55
–45
–35
–25
PIN (dBm)
–15
–5
5
0
–65
11287-017
0
–65
OUTPUT VOLTAGE (V)
6.0
5
ERROR (dB)
6
VTADJ = 0.4V
CALIBRATION AT 0dBm, –40dBm, AND –55dBm
5.5
Figure 17. VRMS and Log Conformance Error vs. Input Level and Temperature
at 2.6 GHz
ERROR (dB)
–6
5
PIN (dBm)
11287-016
OUTPUT VOLTAGE (V)
–45
5.5
6.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
ERROR (dB)
Figure 15. VRMS and Log Conformance Error vs. Input Level and Temperature
at 1.9 GHz
–55
11287-018
–35
ERROR (dB)
–45
11287-019
–55
0
–65
VTADJ = 0.4V
–6
–55
–45
–35
–25
PIN (dBm)
–15
–5
5
ERROR (dB)
–6
5
11287-020
0
–65
6
VTADJ = 0.35V
5.5
11287-015
OUTPUT VOLTAGE (V)
6.0
ADL5906
Figure 20. Distribution of Log Conformance Error with Respect to VRMS at
25°C vs. Input Level and Temperature at 2.6 GHz
Rev. 0 | Page 11 of 32
Data Sheet
5.0
4
5.0
4
4.5
3
4.5
3
4.0
2
4.0
2
3.5
1
3.5
1
3.0
0
3.0
0
2.5
–1
2.5
–1
2.0
–2
2.0
–2
1.5
–3
1.5
–3
1.0
–4
1.0
–4
0.5
–5
0.5
–5
–35
–25
–5
–15
5
PIN (dBm)
–35
–25
–15
5
–5
PIN (dBm)
Figure 24. Distribution of Log Conformance Error with Respect to VRMS at
25°C vs. Input Level and Temperature at 3.5 GHz
6
6.0
5
5.5
2.50
4
5.0
4
2.25
3
4.5
3
2.00
2
4.0
2
3.5
1
3.0
0
VTADJ = 1V
CALIBRATION AT 0dBm, –40dBm, AND –50dBm
1.75
1
1.50
0
1.25
–1
1.00
–2
0.75
0.50
0.25
–45
–35
–25
–5
–15
5
–1
2.0
–2
–3
1.5
–3
–4
1.0
–4
–5
0.5
–5
0
–60
–6
–55
VTADJ = 1V
2.5
11287-022
0
–65
ERROR (dB)
2.75
OUTPUT VOLTAGE (V)
6
3.00
5
PIN (dBm)
Figure 22. VRMS and Log Conformance Error vs. Input Level and Temperature
at 5.8 GHz
–50
–40
–30
–20
0
–10
–6
10
PIN (dBm)
Figure 25. Distribution of Log Conformance Error with Respect to VRMS at
25°C vs. Input Level and Temperature at 5.8 GHz
6
3.00
5
2.75
2.50
4
2.50
4
2.25
3
2.25
3
2.00
2
2.00
2
1.75
1
1.75
1
1.50
0
1.50
0
1.25
–1
1.25
–1
1.00
–2
1.00
–2
0.75
–3
0.75
–3
0.50
–4
0.50
–4
0.25
–5
0.25
–5
0
–45
0
–35
–6
–35
–25
–15
PIN (dBm)
–5
5
11287-023
2.75
VTADJ = 1V
CALIBRATION AT 0dBm, –20dBm, AND –35dBm
ERROR (dB)
6
3.00
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
–45
Figure 23. VRMS and Log Conformance Error vs. Input Level and Temperature
at 8 GHz
ERROR (dB)
OUTPUT VOLTAGE (V)
ERROR (dB)
Figure 21. VRMS and Log Conformance Error vs. Input Level and Temperature
at 3.5 GHz
–6
–55
ERROR (dB)
–45
11287-025
–55
0
–65
5
VTADJ = 1V
CALIBRATION AT 0dBm, –10dBm, AND –20dBm
5
–6
–25
–15
PIN (dBm)
–5
5
ERROR (dB)
–6
VTADJ = 0.45V
5.5
11287-026
0
–65
OUTPUT VOLTAGE (V)
6
6
VTADJ = 0.45V
CALIBRATION AT 0dBm, –40dBm, AND –55dBm 5
6.0
5.5
11287-021
OUTPUT VOLTAGE (V)
6.0
11287-024
ADL5906
Figure 26. VRMS and Log Conformance Error vs. Input Level and Temperature
at 10 GHz
Rev. 0 | Page 12 of 32
Data Sheet
ADL5906
6.0
1000
REPRESENTS 4500 PARTS
5.5
RF BURST PULSE
5.0
800
4.5
OUTPUT (V)
4.0
COUNT
600
400
0dBm
3.5
–10dBm
3.0
–20dBm
2.5
–30dBm
2.0
–40dBm
1.5
200
1.0
3.1
3.0
3.2
3.4
3.3
3.5
VRMS (V)
0
11287-027
2.9
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TIME (ms)
11287-030
0.5
0
2.8
Figure 30. Output Response to RF Burst Input, Carrier Frequency = 2.14 GHz,
CRMS = 0.1 µF
Figure 27. Distribution of VRMS, PIN = −10 dBm, 900 MHz
1000
6.0
REPRESENTS 4500 PARTS
5.5 TADJ/PWDN
PULSE
5.0
800
OUTPUT VOLTAGE (V)
COUNTS
4.5
600
400
4.0
0dBm
3.5
–10dBm
3.0
–20dBm
2.5
–30dBm
2.0
–40dBm
1.5
200
1.0
1.0
1.1
1.2
1.3
1.4
1.5
VRMS (V)
0
11287-028
0.9
Figure 28. Distribution of VRMS, PIN = −45 dBm, 900 MHz
4
6
8
10
12
14
16
18
20
22
Figure 31. Output Response Using Power-Down Mode for Various RF Input
Levels, Carrier Frequency = 2.14 GHz, CRMS = 1 nF
6.0
5.5
5.5 TADJ/PWDN
PULSE
5.0
RF BURST PULSE
5.0
4.5
3.5
–10dBm
3.0
–20dBm
2.5
–30dBm
2.0
–40dBm
1.5
4.0
0dBm
3.5
–10dBm
3.0
–20dBm
2.5
–30dBm
2.0
–40dBm
1.5
1.0
1.0
0.5
0.5
0
5
10
15
20
25
TIME (µs)
30
35
40
45
50
0
0
0.5
1.0
1.5
TIME (ms)
Figure 29. Output Response to RF Burst Input, Carrier Frequency = 2.14 GHz,
CRMS = 1 nF
2.0
2.5
11287-032
0dBm
OUTPUT VOLTAGE (V)
4.5
4.0
11287-029
OUTPUT VOLTAGE (V)
2
TIME (µs)
6.0
0
0
11287-031
0.5
0
0.8
Figure 32. Output Response Using Power-Down Mode for Various RF Input
Levels, Carrier Frequency = 2.14 GHz, CRMS = 0.1 µF
Rev. 0 | Page 13 of 32
ADL5906
Data Sheet
240
40
NOISE SPECTRAL DENSITY (nV/√Hz)
220
30
200
20
CHANGE IN VREF (mV)
180
160
140
120
100
10
0
–10
80
–20
60
40
–30
1k
100k
10k
10M
1M
–40
–55
11287-033
0
100
FREQUENCY (Hz)
5
2.3
4
2.1
3
1.9
2
1.7
1
1.5
0
1.3
–1
1.1
–2
0.9
–3
0.7
–4
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 33. Noise Spectral Density of VRMS, PIN = −10 dBm, −35 dBm, and
−60 dBm (No Change in NSD vs. PIN), CRMS = 0.1 µF
2.5
5
–15
–35
11287-036
20
Figure 36. Change in VREF vs. Temperature with Respect to 25°C,
PIN = −40 dBm
1000
–15
5
25
45
65
85
105
COUNT
ERROR (°C)
400
200
–5
125
0
2.25
TEMPERATURE (°C)
2.26
2.27
2.28
2.29
2.30
2.31
2.32
11287-037
–35
600
1.45
11287-038
0.5
–55
800
11287-034
VTEMP (V)
REPRESENTS 4500 PARTS
VREF BIAS VOLTAGE (V)
Figure 34. VTEMP and Linearity Error with Respect to Straight Line vs.
Temperature for Typical Device
Figure 37. Distribution of VREF at 25°C, No RF Input
1000
100
REPRESENTS 4500 PARTS
SUPPLY CURRENT (mA)
800
COUNT
600
400
10
VPWDN
DECREASING
VPWDN
INCREASING
1
200
1.34
1.36
1.38
1.40
VTEMP VOLTAGE (V)
1.42
1.44
0.1
1.20
11287-035
0
1.32
1.25
1.30
1.35
1.40
VPWDN (V)
Figure 35. Distribution of VTEMP at 25°C, No RF Input
Figure 38. Supply Current vs. VPWDN
Rev. 0 | Page 14 of 32
Data Sheet
ADL5906
10
90
0
RETURN LOSS (dB)
80
75
70
65
–10
–20
55
50
–55
–30
START 10MHz
–35
–15
5
25
45
65
85
TEMPERATURE (°C)
105
125
1GHz/DIV
STOP 10GHz
Figure 39. Supply Current vs. Temperature
Figure 40. Return Loss at RF Input Port, 10 MHz to 10 GHz
Rev. 0 | Page 15 of 32
11287-040
60
11287-004
SUPPLY CURRENT (mA)
85
ADL5906
Data Sheet
THEORY OF OPERATION
The VGA output is
The ADL5906 is functionally nearly identical to the ADL5902
but has a broader frequency range (10 MHz to 10 GHz). It is a
true rms responding detector with a 67 dB measurement range
at 2.14 GHz and a greater than 57 dB measurement range at
frequencies up to 5.8 GHz. It is pin compatible with the ADL5902
and AD8363. Transfer function peak-to-peak ripple is <±0.3 dB
over the entire dynamic range. Temperature stability of the rms
output measurements provides <±1 dB error typical over the
temperature range of −40°C to +125°C up to 3.5 GHz. The device
accurately measures waveforms that have a high peak-to-rms
ratio (crest factor).
VSIG = GSET × RFIN = GO × RFIN e − (VSET / VGNS )
where RFIN is the ac voltage applied to the input terminals of the
ADL5906.
The output of the VGA, VSIG, is applied to a wideband square law
detector. The detector provides the true rms response of the RF
input signal, independent of waveform. The detector output, ISQR, is
a fluctuating current with a positive mean value. The difference
between ISQR and an internally generated current, ITGT, is integrated
by the parallel combination of CF and the external capacitor
attached to the CRMS pin at the summing node. CF is an on-chip
26 pF filter capacitor, and CRMS, the external capacitance connected
to the CRMS pin, can be used to arbitrarily increase the averaging
time while trading off with the response time. When the AGC
loop is at equilibrium
The ADL5906 consists of a high performance automatic gain
control (AGC) loop. As shown in Figure 41, the AGC loop
comprises a wide bandwidth variable gain amplifier (VGA), square
law detectors, an amplitude target circuit, and an output driver.
The nomenclature used in this data sheet to distinguish between a
pin name and the signal on that pin is as follows:
•
Mean(ISQR) = ITGT
This equilibrium occurs only when
The pin name is all uppercase, for example, CRMS, VSET,
and VRMS.
The signal name or a value associated with that pin is the
pin mnemonic with a partial subscript, for example, CRMS,
VSET, and VRMS.
Mean(VSIG2) = VTGT2
(4)
where VTGT is the voltage presented at the VTGT pin. This pin
can conveniently be connected to the VREF pin through a voltage
divider to establish a target rms voltage, VATG, of ~40 mV rms when
VTGT = 0.8 V.
SQUARE LAW DETECTOR AND AMPLITUDE TARGET
Because the square law detectors are electrically identical and
well matched, process and temperature dependent variations
are effectively cancelled.
The VGA gain has the form
GSET = GO e − (VSET / VGNS )
(3)
(1)
where:
GO is the basic fixed gain.
VGNS is a scaling voltage that defines the gain slope (the decibel
change per voltage). The gain decreases with increasing VSET.
VPOS1/VPOS2
CH
(INTERNAL)
RFIN+
VGA
VSIG
X2
SUMMING
NODE
ISQR
ITGT
VATG =
VTGT
20
X2
VTGT
RFIN–
GSET
CRMS
VSET
CRMS
(EXTERNAL)
CF
(INTERNAL)
VRMS
GND1/GND2
TEMPERATURE COMPENSATION
AND BIAS
TADJ/PWDN
TEMPERATURE
SENSOR
VTEMP (1.4V)
BAND GAP
REFERENCE
Figure 41. Simplified Architecture Details
Rev. 0 | Page 16 of 32
VREF (2.3V)
11287-041
•
(2)
Data Sheet
ADL5906
When forcing the previous identity by varying the VGA setpoint, it
is apparent that
RMS(VSIG) = √(Mean(VSIG2)) = √(VATG2) = VATG
VBIAS
VPOS
ESD
(5)
2.5kΩ
Substituting the value of VSIG from Equation 2 results in
RMS(G0 × RFIN e − (VSET / VGNS ) ) = VATG
ESD
(6)
2.5kΩ
RFIN+
RFIN–
LOAD
When connected as a measurement device, VSET = VRMS. Solving
for VRMS as a function of RFIN,
(7)
When RMS(RFIN) = VZ, this implies that VRMS = 0 V because
log10(1) = 0. This makes the intercept the input that forces VRMS =
0 V if the ADL5906 had no sensitivity limit.
In most applications, the AGC loop is closed through the setpoint
interface and the VSET pin. In measurement mode, VRMS is
directly connected to VSET (see the Measurement Mode Basic
Connections section for more information). In controller mode,
a control voltage is applied to VSET, and the VRMS pin typically
drives the control input of an amplification or attenuation system.
In this case, the voltage at the VSET pin forces a signal amplitude
at the RF inputs of the ADL5906 that balances the system through
feedback.
fHIGHPASS = 1/(2 × π × 50 × C)
(8)
ESD
ESD
ESD
ESD
ESD
ESD
ESD
Figure 42. RF Inputs
Extensive ESD protection is employed on the RF inputs, and this
protection limits the maximum possible input to the ADL5906.
TEMPERATURE SENSOR INTERFACE
The ADL5906 provides a temperature sensor output with a scaling
factor of the output voltage of approximately 4.8 mV/°C. The
output is capable of sourcing 4 mA and sinking 50 µA maximum
at 25°C. An external resistor can be connected from VTEMP to
GND to provide additional current sink capability. The typical
output voltage at 25°C is approximately 1.4 V.
VPOS
INTERNAL
VPAT
RF INPUT INTERFACE
Figure 42 shows the RF input connections within the ADL5906.
Two internal 2.5 kΩ resistors connected between RFIN+ and RFIN−
primarily set the input impedance. A dc level of approximately
half the supply voltage on each pin is established internally at
the center point of the bias resistors. Either the RFIN+ or the
RFIN− pin can be used as the single-ended RF input pin. Connect
signal coupling capacitors from the input signal to the RFIN+
and RFIN− pins. A single external 60.4 Ω resistor to ground
from the desired input creates an equivalent 50 Ω impedance
over a broad section of the operating frequency range. RF ac-couple
the other input pin to common (ground). The input signal highpass corner formed by the internal and external resistances of
the input coupling capacitor is
ESD
VTEMP
12kΩ
4kΩ
GND
Figure 43. TEMP Interface Simplified Schematic
VREF INTERFACE
The VREF pin provides an internally generated voltage reference
for the user. The VREF voltage is a temperature stable 2.3 V
reference that is capable of sourcing 4 mA and sinking 50 µA
maximum. An external resistor can be connected from VREF
to GND to provide additional current sink capability. The
voltage on this pin can be used to drive the TADJ/PWDN and
VTGT pins.
VPOS
where C is the capacitance in farads, and fHIGHPASS is in hertz.
The input coupling capacitors must be large enough in value to
pass the input signal frequency of interest and determine the low
end of the frequency response. RFIN+ and RFIN− can also be
driven differentially using a balun.
INTERNAL
VOLTAGE
VREF
16kΩ
GND
Figure 44. VREF Interface Simplified Schematic
Rev. 0 | Page 17 of 32
11287-141
ESD
GND
ESD
11287-042
where:
VSLOPE = 1.12 V/decade (or 56 mV/dB) at 2.14 GHz.
VZ is the intercept voltage.
ESD
11287-143
VRMS = VSLOPE × log10(RMS(RFIN)/VZ)
ADL5906
Data Sheet
TEMPERATURE COMPENSATION INTERFACE
3.70
The ADL5906 has a TADJ pin that provides the ability to optimize
temperature performance using proprietary techniques as in
the ADL5902. Just like the ADL5902, the ADL5906 has dual
functionality on Pin 1, TADJ/PWDN; however, the PWDN
function was redesigned to be driven by CMOS logic as low
as 1.8 V. For more detail on the power-down interface, see the
Power-Down Interface section.
3.65
There is a trade-off in setting values, and optimizing for one
area of the dynamic range may mean less than optimal drift
performance at other input amplitudes. In addition, different
voltages applied to the VTGT pin impact drift; all TADJ voltages
shown in the performance curves were determined with a
VTGT of 0.8 V. For VTGT values that do not deviate too far
from the nominal 0.8 V, and for frequencies up to approximately
5 GHz, it is expected that the TADJ voltages are a good starting
point for the best temperature drift compensation.
Compensating the device for temperature drift using VTADJ allows
for great flexibility. If the user requires minimum temperature drift
at a given input power, a subset of the dynamic range, or even
over a different temperature range than shown in this data
sheet, the VTADJ can be swept while monitoring VRMS over the
temperature at the frequency and amplitude of interest. The
optimal VTADJ to achieve minimum temperature drift at a given
power and frequency is the value of VTADJ where the output has
minimum movement.
3.55
3.50
3.45
3.40
3.35
3.30
3.25
3.20
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VTADJ VOLTAGE (V)
11287-043
One difference in the temperature compensation of the ADL5906
compared to the ADL5902 is that VTADJ adjusts the slope of the
detector, and with the ADL5902, the intercept was adjusted.
Adjusting the slope was found beneficial to locking in temperature
drift and thereby producing parallel error curves over most
frequencies. Any remaining intercept temperature drift can
then be reduced in the digital domain after sampling VRMS
because the intercept drift is quite repeatable at frequencies
up to approximately 5.8 GHz (see the Using VTEMP to
Improve Intercept Temperature Drift section).
OUTPUT VOLTAGE (V)
For optimal performance, the output temperature drift must
be compensated using the TADJ pin. The absolute value of
compensation varies with frequency and VTGT. For recommended
VTADJ values at popular frequencies, see the Setting VTADJ section.
3.60
Figure 45. Effect of VTADJ at Various Temperatures, 2.14 GHz, 0 dBm
Varying VTADJ has only a very slight effect on VRMS at device
temperatures near 25°C; however, the compensation circuit has
increasing effect as the temperature departs farther from 25°C.
It is important to note that the slope is adjusted vs. temperature.
The pivot point of this is at low input power levels and thereby
moves the VRMS output more at larger input signal levels; that
is, near maximum input power, the temperature drift can be
minimized the most. This is advantageous in most power
measurement cases because errors at larger powers tend to have
more of a negative effect.
The TADJ/PWDN pin has a nominal input resistance of 70 kΩ and
can be conveniently driven from an external source or from an
attenuated value of VREF using a resistor divider. The resistors are
shown in the evaluation board schematic (see Figure 63). The
voltage range for VTADJ is from 0 V to approximately 1.0 V because
approximately 1.3 V is the logic threshold for power down of
the device.
Rev. 0 | Page 18 of 32
Data Sheet
ADL5906
POWER-DOWN INTERFACE
OUTPUT INTERFACE
Figure 46 shows a simplified schematic representation of the
TADJ/PWDN interface.
The ADL5906 incorporates rail-to-rail output drivers with pull-up
and pull-down capabilities. The level shift circuitry and the output
amplifier are very fast compared to the typical rms response
required by a complex waveform. In essence, the output stage from
the CRMS pin to the VRMS output is only a dc signal because
by definition VRMS is supposed to be a single rms value. The
VRMS pin can source and sink up to 10 mA.
VPOS
MAXIMUM
TEMPERATURE
OPERATING
VOLTAGE = 1V COMPENSATION
CIRCUIT
ESD
TADJ 1kΩ
TADJ/
PWDN
ESD
ESD
5
PWD = PWDN ×
7
50kΩ
1kΩ
LOGIC
THRESHOLD
~1V ± 0.1V
SHUTDOWN
CIRCUIT
GND
Figure 46. TADJ/PWDN Interface Simplified Schematic
VSET INTERFACE
The VSET interface has a high input impedance of 72 kΩ. The
voltage at VSET is converted to an internal current used to set the
internal VGA gain. The VGA attenuation control is approximately
18 dB/V.
ISQR
CRMS
LEVEL
SHIFT
CIRCUITRY
ESD
ITGT
CRMS
EXTERNAL
VRMS
2kΩ
ESD
26pF
500Ω
GND
Figure 48. VRMS Interface Simplified Schematic
VTGT INTERFACE
The target voltage can be set with an external source or by
connecting the VREF pin (nominally 2.3 V) to the VTGT pin
through a resistive voltage divider. With 0.8 V on the VTGT pin,
the rms voltage that must be provided by the VGA to balance
the AGC feedback loop is 0.8 V × 0.05 = 40 mV rms. Most of
the characterization information in this data sheet was collected
at VTGT = 0.8 V. Voltages higher and lower than this can be used;
however, doing so increases or decreases the gain at the internal
squaring cell, which results in a corresponding increase or decrease
in intercept. This, in turn, affects the sensitivity and the usable
measurement range, in addition to the sensitivity to different
carrier modulation schemes. As VTGT decreases, the squaring
circuits produce more noise; this becomes noticeable in the output
response at low input signal amplitudes. As VTGT increases,
measurement error due to modulation increases, and temperature
drift tends to decrease. The chosen VTGT value of 0.8 V represents a
compromise between these characteristics.
GAIN ADJUST
VSET
~2.1V DC BIAS
VPOS
63kΩ
ESD
g × X2
VTGT
9kΩ
1kΩ
ESD
50kΩ
11287-045
GND
ITGT
50kΩ
ESD
20kΩ
Figure 47. VSET Interface Simplified Schematic
GND
Figure 49. VTGT Interface
Rev. 0 | Page 19 of 32
11287-047
LOGIC
THRESHOLD
~1.3V ± 0.1V
20kΩ
11287-044
70kΩ
VPOS
ESD
11287-046
The quiescent and power-down currents for the ADL5906 at
25°C are approximately 68 mA and 250 µA, respectively. The
dual function TADJ/PWDN pin is connected to the temperature
compensation circuit as well as the power-down circuit. The
temperature compensation circuit responds only to voltages
between 0 V and 1 V. When the voltage on this pin is greater than
~1.4 V, the device is fully powered down. Figure 38 shows this
characteristic as a function of VPWDN. The TADJ/PWDN pin with
an internal 70 kΩ resistor to ground sinks approximately 26 µA
at 1.8 V, 47 µA at 3.3 V, and 72 µA at 5 V. The source used to disable
the ADL5906 must have a sufficiently high current capability for
this reason. Figure 31 shows the typical response times for various
RF input levels. The output reaches within 1 dB of its steady state
value in approximately 12 µs for CRMS = 1 nF; however, the reference
voltage is available to full accuracy in a much shorter time. This
wake-up response varies depending on the input coupling and
the value of CRMS.
ADL5906
Data Sheet
BASIS FOR ERROR CALCULATIONS
MEASUREMENT MODE BASIC CONNECTIONS
The slope and intercept used in the error plots are calculated using
the coefficients of a linear regression performed on data collected
in its central operating range. The error plots in the Typical
Performance Characteristics section are shown in two formats:
error from the ideal line and error with respect to the 25°C output
voltage. The error from the ideal line is the decibel difference in
VRMS from the ideal straight-line fit of VRMS calculated by the linear
regression fit over the linear range of the detector, typically at
25°C. The error in decibels is calculated by
The basic connections circuit for ADL5906 is shown in Figure 51.
The ADL5906 requires a single supply of nominally 5 V. The
supply is connected to the VPOS1 and VPOS2 supply pins.
Decouple each of these pins using two capacitors with values equal
or similar to those shown in Figure 51. Place these capacitors as
close as possible to the VPOS pins. The three no connect pins
(NIC) are not internally connected. Leave these pins unconnected.
Error (dB) = (VRMS − Slope × (PIN − PZ))/Slope
(9)
where PZ is the x-axis intercept expressed in decibels relative to
1 mW (the input amplitude that produces a 0 V output if such an
output were possible).
The error from the ideal line is not a measure of absolute accuracy
because it is calculated using the slope and intercept of each device.
However, it verifies the linearity and the effect of temperature
and modulation on the response of the device. An example of
this type of plot is Figure 9. The slope and intercept that form
the ideal line are those at 25°C with CW modulation. Figure 4,
Figure 5, Figure 7, and Figure 8 show the error with various
popular forms of modulation with respect to the ideal CW
line. This method for calculating error is accurate, assuming
that each device is calibrated at room temperature.
In the second plot format, the VRMS voltage at a given input
amplitude and temperature is subtracted from the corresponding
VRMS at 25°C and then divided by the 25°C slope to obtain an error
in decibels. This type of plot does not provide any information
on the linear-in-dB performance of the device; it merely shows
the decibel equivalent of the deviation of VRMS over temperature,
given a calibration at 25°C. When calculating error from any
one particular calibration point, this error format is accurate. It
is accurate over the full range shown on the plot assuming that
enough calibration points are used. Figure 12 shows this plot type.
The error calculations for Figure 34 are similar to those for the
VRMS plots. The slope and intercept of the VTEMP function vs.
temperature are determined and applied as follows:
(10)
Error (°C) = (VTEMP − Slope × (Temp − TZ))/Slope
where:
VTEMP is the voltage at the TEMP pin at that temperature.
Slope is, typically, 4.8 mV/°C.
Temp is the ambient temperature of the ADL5906 in degrees
Celsius.
TZ is the x-axis intercept expressed in degrees Celsius (the
temperature that would result in a VTEMP of 0 V if this were
possible).
An external 60.4 Ω resistor combines with the relatively high RF
input impedance of the ADL5906 to provide a broadband 50 Ω
match. Place an ac coupling capacitor between this resistor and
RFIN+. AC-couple the RFIN− input to ground using the same
value capacitor. To operate down to 10 MHz, the coupling
capacitors must be at least 100 pF.
The ADL5906 is placed in measurement mode by connecting
the VRMS pin to the VSET pin. In measurement mode, the output
voltage is proportional to the log of the rms input signal level.
SETTING VTADJ
As described in the Theory of Operation section, the output
temperature drift can be compensated by applying a voltage to
the TADJ pin. The compensating voltage varies with frequency.
The voltage for the TADJ pin can be easily derived from a resistor
divider connected to the VREF pin. Table 4 shows the recommended
VTADJ voltages for operation from −55°C to +125°C, along with
resistor divider values. Resistor values are chosen so that they
neither pull too much current from the VREF pin (IOUTMAX = 4 mA)
nor are so large that the maximum bias current at a VTADJ = 1 V
(14 µA) affects the resulting voltage.
The VTADJ function provides temperature compensation of
the output slope of the ADL5906. The Using VTEMP to Improve
Intercept Temperature Drift section describes how the
temperature stability of the ADL5906 can be further improved.
Table 4. Recommended VTADJ Voltages
Frequency
10 MHz to 2.14 GHz
2.6 GHz
3.5 GHz
5.8 GHz
8 GHz
10 GHz
Rev. 0 | Page 20 of 32
VTADJ (V)
0.35
0.4
0.45
1.0
1.0
1.0
R9 (Ω)
1500
1500
1500
1540
1540
1540
R12 (Ω)
270
316
365
1200
1200
1200
Data Sheet
ADL5906
SETTING VTGT
Figure 50 shows how output noise varies with CRMS when the
ADL5906 is driven by a single-carrier W-CDMA signal (Test
Model TM1-64, peak envelope power = 10.56 dB, bandwidth =
3.84 MHz).
350
OUTPUT NOISE (mV p-p)
300
250
10000
200
1000
150
100
100
10
50
1
CHOOSING A VALUE FOR CRMS
CRMS provides the averaging function for the internal rms
computation. Using the minimum value for CRMS allows the
quickest response time to a pulsed waveform but leaves significant
output noise on the output voltage signal. By the same token, a
large filter capacitor reduces output noise but at the expense of
response time.
0
1
+5V
C3
0.1µF
C7
0.1µF
C4
100pF
C5
100pF
VPOS2
10
3
TEMPERATURE
SENSOR
ADL5906
14
X2
ISQR
VSET
15
C12
10nF
VTEMP
8
7
LINEAR-IN-dB VGA
(NEGATIVE SLOPE)
X2
ITGT
VRMS
NIC 2
VRMS
6
G=5
NIC 16
NIC 13
BIAS AND POWER
DOWN CONTROL
VREF
2.3V
CRMS
5
EPAD
26pF
R12
12
11
1
TADJ/
PWDN
VREF
R9
(SEE TEXT)
(AND TABLE)
VTGT
R10
3.74kΩ
9
GND2
4
GND1
R11
2kΩ
Figure 51. Basic Connections for Operation in Measurement Mode
Rev. 0 | Page 21 of 32
C9
0.1µF
(SEE TEXT)
(AND TABLE)
11287-148
R3
60.4Ω
RFIN–
0.1
10000
Figure 50 also shows how the response time is affected by the
value of CRMS. To measure this, an RF burst at 2.14 GHz at 0 dBm
was applied to the ADL5906. The 10% to 90% rise time and
90% to 10% fall time were then measured.
VPOS1
RFIN+
1000
CRMS (nF)
+5V
RFIN
100
Figure 50. Output Noise, Rise and Fall Times vs. CRMS Capacitance,
Single-Carrier W-CDMA (TM1-64) at 2.14 GHz with PIN = 0 dBm
In applications where response time is not critical, a relatively large
capacitor can be placed on the CRMS pin. In Figure 51, a value
of 0.1 µF is used. For most signal modulation schemes, this value
ensures excellent rms measurement compliance and low residual
output noise. There is no maximum capacitance limit for CRMS.
C10
10nF
10
RISE TIME/FALL TIME (µs)
1000000
OUTPUT NOISE (V p-p)
RISE TIME (µs)
FALL TIME (µs)
100000
11287-049
As described in the Theory of Operation section, setting the
voltage on VTGT to 0.8 V represents a compromise between
achieving excellent rms accuracy and maximizing dynamic range.
The voltage on VTGT can be derived from the VREF pin using
a resistor divider, as shown Figure 51. Like the resistors chosen
to set the VTADJ voltage, the resistors setting VTGT must have
reasonable values that do not pull too much current from VREF
or cause bias current errors. In addition, note the combined current
that VREF must deliver to generate the VTADJ and VTGT voltages.
The values shown in Figure 51 and Table 4 result in a maximum
VREF current of 1.7 mA. This current is well below the
maximum specified VREF current of 4 mA.
ADL5906
Data Sheet
Table 5. Recommended Minimum CRMS Values for Various Modulation Schemes
QPSK, 5 MSPS (SQR COS Filter, α = 0.35)
QPSK ,15 MSPS (SQR COS Filter, α = 0.35)
64 QAM, 1 MSPS (SQR COS Filter, α = 0.35)
64 QAM, 5 MSPS (SQR COS Filter, α = 0.35)
64 QAM, 13 MSPS (SQR COS Filter, α = 0.35)
W-CDMA, One-Carrier, TM1-64
W-CDMA Four-Carrier, TM1-64, TM1-32, TM1-16, TM1-8
LTE, TM1, One-Carrier, 20 MHz (2048 QPSK Subcarriers)
Peak Envelope
Power Ratio (dB)
3.8
3.8
7.4
7.4
7.4
10.56
12.08
11.58
Table 5 shows the recommended minimum values of CRMS for
popular modulation schemes. Using lower capacitor values results
in rms measurement errors. Output response time is also shown.
If the output noise shown in Table 5 is unacceptably high, it can
be reduced by
•
•
Increasing CRMS
Implementing an averaging algorithm after the output voltage
of the ADL5906 has been sampled by an analog-to-digital
converter (ADC)
Carrier
Bandwidth (MHz)
5
15
1
5
13
3.84
18.84
20
OUTPUT VOLTAGE SCALING
The linear output voltage range of the ADL5906 is nominally
0.3 V to 3.7 V. VRMS is clamped to a maximum voltage of ~3.9 V;
this helps improve falling edge settling speeds because the VRMS
output stays closer to the nominal linear-in-dB output range of
0.3 V to 3.7 V. Within the 0 V to 3.9 V maximum output range,
the slope can be adjusted as needed via extra resistors, as shown
in Figure 52.
Output Noise
(mV p-p)
84
42
265
380
205
820
640
140
Rise/Fall
Time (µs)
0.2/10
0.2/10
3/85
0.2/10
0.2/10
0.2/10
0.2/10
0.2/10
If only a part of the RF input power range of the ADL5906 is
being used (for example, −10 dBm to −60 dBm), increase the
scaling so that this reduced input range fits into the available
output swing (0 V to 3.9 V) of the ADL5906.
The output swing is reduced by simply adding a voltage divider on
the output pin, as shown in the A side of Figure 52. Reducing the
output scaling can be used when interfacing the ADL5906 to an
ADC with a 0 V to 2.5 V input range.
The values in Table 5 were experimentally determined to be the
minimum capacitance that ensures good rms accuracy for that
particular signal type. This test was carried out by starting out
with a large capacitance value on the CRMS pin (for example,
10 µF). The value of VRMS was noted for a fixed input power level
(for example, −10 dBm). The value of CRMS was then progressively
reduced (this can be done with press-down capacitors) until
the value of VRMS started to deviate from its original value (this
indicates that the accuracy of the rms computation is degrading
and that CRMS is becoming too small).
In general, the minimum required rms averaging capacitance
increases as the peak-to-average ratio of the carrier increases. The
minimum required CRMS also tends to increase as the bandwidth
of the carrier decreases. With narrow-band carriers, the noise
spectrum of the VRMS output tends to have a correspondingly
narrow profile. The relatively narrow spectral profile demands
a larger value of CRMS that reduces the low-pass corner frequency
of the averaging function and ensures a valid rms computation.
CRMSMIN (nF)
1
1
10
1
1
1
1
1
R2
7
VSET
7
VSET
R6
6
VRMS
R1
6
VRMS
R15
A
B
11287-149
Modulation/Standard
Figure 52. Decreasing and Increasing Slope
The output voltage swing can be increased using a technique that is
analogous to setting the gain of an op amp in noninverting mode
(see the B side of Figure 52) with the VSET pin being the equivalent
of the inverting input of the op amp.
With VRMS connected to VSET, the nominal transfer function
of the ADL5906 is given by
VRMS = Slope × (PIN − Intercept)
For example at 3.5 GHz, with PIN equal to 0 dBm, the nominal
output voltage is equal to 0.052 V/dB × (0 dBm − (−64 dBm) =
3.328 V.
To scale this voltage downward using a resistor divider, choose a
value for R15 and calculate R1 using the following equation:
Rev. 0 | Page 22 of 32

V
− 1
R1 = R15 ×  RMS
'
V
 RMS

(11)
Data Sheet
ADL5906
To scale this voltage upward, choose a value for R2 and calculate
R6 using the following equation:
 V'

R6 = (R2 || R IN ) RMS − 1
 VRMS

(12)
where:
RIN is the input resistance of VSET (72 kΩ).
V'RMS is the desired maximum output voltage.
VRMS is the nominal maximum output voltage before scaling
(see Figure 9 through Figure 26).
When choosing R1, R2, R6, and R15, notice the current drive
capability of the VRMS pin and the input resistance of the VSET
pin. The choice of resistors must not be too small because this
results in excessive current drawn out of the VRMS pin (the VRMS
pin can source a maximum current of 10 mA). However, choosing
an R2 that is too large is also problematic. If the value of R2 chosen
is compatible with the input resistance of the VSET pin (72 kΩ),
this input resistance, which varies slightly from part to part,
contributes to the resulting slope and output voltage. In general,
ensure that the value of R2 is at least 10 times smaller than the
input resistance of VSET. Therefore, the values for R6 and R2
must be in the 1 kΩ to 5 kΩ range. Similar values must be used
for R1 and R15.
It is also important to take into account part-to-part and frequency
variation in output swing along with the maximum output voltage
(3.9 V) of the output stage of the ADL5906. The VRMS part-topart distribution is well characterized at major frequency bands
in the Typical Performance Characteristics section (see Figure 12
through Figure 14, Figure 18 through Figure 20, Figure 24, and
Figure 25). The resistor values in Table 6, which were calculated
based on 3.5 GHz operation, have been conservatively chosen so
that there is no chance that the desired output voltage swings
exceed the output swing of the ADL5906 (when scaling upward)
or the input range of a 0 V to 2.5 V ADC (when scaling downward). In each case, the nominal maximum voltage that results is
100 mV below the desired maximum to account for part-to-part
variation and resistor tolerances.
Table 6. Output Voltage Range Scaling Examples at 3.5 GHz
Desired Input Range (dBm)
0 to −60
−10 to −50
0 to −60
−10 to −50
Slope Increase
R6 (Ω) R2 (Ω)
274
2000
681
2000
Slope Decrease
R1 (Ω) R15(Ω)
787
348
2000
2000
New Slope (mV/dB)
59
70
37
44
Rev. 0 | Page 23 of 32
Nominal Maximum Output Voltage (V)
3.8
3.8
2.4
2.4
ADL5906
Data Sheet
1
3.0
0
4.5
2.5
–1
2.0
–2
1.5
–3
1.0
–4
–5
0.5
0
–65
–6
–55
–45
–35
–25
–15
–5
5
PIN (dBm)
11287-051
OUTPUT VOLTAGE (V)
5.0
Figure 53. 2.14 GHz VRMS and Log Conformance Error at +25°C, −40°C, and
+85°C Using Two-Point Calibration at 0 dBm and −40 dBm
Because slope and intercept vary from device to device, board
level calibration must be performed to achieve high accuracy.
The equation for the idealized output voltage can be written as
VRMS(IDEAL) = Slope × (PIN − Intercept)
In general, calibration is performed during equipment manufacture
by applying two or more known signal levels to the input of the
ADL5906 and measuring the corresponding output voltages.
The calibration points must be within the linear operating range
of the device.
With a two-point calibration, the slope and intercept are calculated
as follows:
Slope = (VRMS1 − VRMS2)/(PIN1 − PIN2)
(14)
Intercept = PIN1 − (VRMS1/Slope)
(15)
After the slope and intercept are calculated and stored in nonvolatile
memory during equipment calibration, an equation can be used
to calculate an unknown input power based on the output
voltage of the detector.
PIN (Unknown) = (VRMS(MEASURED)/Slope) + Intercept
Figure 53 includes a plot of this error at +25°C, −40°C, and +85°C
when using a two-point calibration (calibration points are 0 dBm
and −40 dBm). The error at the calibration points at 25°C (in
this case, −40 dBm and 0 dBm) is equal to 0 dB by definition.
The residual nonlinearity of the transfer function that is apparent
in the two-point calibration error plot can be reduced by
increasing the number of calibration points. Figure 54 shows
the post-calibration error plots for a three-point calibration. With
a multipoint calibration, the transfer function is segmented, with
each segment having its own slope and intercept. Multiple known
power levels (three levels in this case) are applied, and multiple
voltages are measured. When the equipment is in operation, the
measured voltage from the detector is first used to determine
which of the stored slope and intercept calibration coefficients
are to be used. Then, the unknown power level is calculated
by inserting the appropriate slope and intercept values into
Equation 16.
When choosing calibration points, there is no requirement for,
or value in, equal spacing between the points. There is also no
limit to the number of calibration points used. However, when
more calibration points are used, calibration time increases.
6.0
(13)
where:
Slope is the change in output voltage divided by the change in
input power (dB).
Intercept is the calculated input power level at which the output
voltage is equal to 0 V (note that Intercept is an extrapolated
theoretical value and not a measured value).
(17)
4.0
6
OUTPUT VOLTAGE –40°C
OUTPUT VOLTAGE +25°C 5
OUTPUT VOLTAGE +85°C
4
ERROR –40°C
ERROR +25°C
3
ERROR +85°C
2
3.5
1
3.0
0
2.5
–1
2.0
–2
1.5
–3
1.0
–4
0.5
–5
5.5
VTADJ = 0.35V
5.0
4.5
0
–65
–6
–55
–45
–35
–25
PIN (dBm)
–15
–5
5
ERROR (dB)
3.5
5.5
Error (dB) = (VRMS(MEASURED) − VRMS(IDEAL))/Slope
OUTPUT VOLTAGE (V)
4.0
6
OUTPUT VOLTAGE –40°C
OUTPUT VOLTAGE +25°C 5
OUTPUT VOLTAGE +85°C
4
ERROR –40°C
ERROR +25°C
3
ERROR +85°C
2
6.0
ERROR (dB)
The measured transfer function of the ADL5906 at 2.14 GHz is
shown in Figure 53, which contains plots of both output voltage
vs. input level and linearity error vs. input level. As the input level
varies from −65 dBm to +5 dBm, the output voltage varies from
~0.25 V to ~3.9 V.
The log conformance error is the difference between this straight
line and the actual performance of the detector.
11287-152
SYSTEM CALIBRATION AND ERROR CALCULATION
Figure 54. 2.14 GHz VRMS and Log Conformance Error at +25°C, −40°C, and
+85°C Using Three-Point Calibration at 0 dBm, −40 dBm, and −55 dBm
The −40°C and +85°C error plots in Figure 54 are generated using
the +25°C slope and intercept values. This is consistent with
equipment calibration in a mass production environment where
calibration of multiple temperatures is not practical.
(16)
Rev. 0 | Page 24 of 32
Data Sheet
ADL5906
VRMS' (V)
4.5
For example, at 2.14 GHz, TCVRMS for hot drift can be calculated as
6
5
4
3
4.0
2
3.5
1
3.0
0
2.5
–1
2.0
–2
1.5
–3
1.0
–4
0.5
–5
0
–65
TCVRMS = (0.3 dB/60°C) × 56 mV/dB = 0.28 mV/°C
–55
–45
–35
–25
–15
–5
5
–6
PIN (dBm)
Table 7 also lists the typical temperature coefficient of the VTEMP
temperature sensor output. To calculate the appropriate amount of
compensation required at a particular frequency, a VTEMP weighting
factor is calculated. This is simply the ratio of the temperature
coefficients of VTEMP and VRMS. These weighting factors are
also shown in Table 7.
Figure 55. VRMS’ and Log Conformance Error vs. Input Level and Temperature
at 100 MHz Using VTEMP Intercept Compensation
6.0
5.5
VRMS' –40°C
VRMS' +25°C
VRMS' +85°C
ERROR –40°C
ERROR +25°C
ERROR +85°C
4.5
Using the data shown in Table 7, an adjusted value for VRMS (VRMS‘)
can be calculated using the following equation:
(19)
where:
VTEMP25 is equal to the voltage measured on VTEMP during system
calibration at ambient temperature.
VTEMP is equal to the voltage on VTEMP during normal operation.
6
VTADJ = 0.35V
5.0
VRMS' (V)
The value for slope that is used can also be the slope that is
calculated during device calibration. This gives results that are
slightly more accurate because there is slight variation in slope
from device to device.
 V
− VTEMP25 
VRMS' = VRMS −  TEMP
 Weighting Factor 


VRMS' –40°C
VRMS' +25°C
VRMS' +85°C
ERROR –40°C
ERROR +25°C
ERROR +85°C
5.0
(18)
where:
DRIFTVRMS is the specified drift of VRMS (scaled in dB) from
ambient to either −40°C or +85°C at an input power level of
0 dBm (see Table 1).
∆TEMP is equal to either +65°C for cold drift (that is, +25°C −
(−40°C)) or +60°C for hot drift (that is, +85°C − +25°C).
Slope is the specified slope of VRMS (see Table 1).
VTADJ = 0.35V
5
4
3
4.0
2
3.5
1
3.0
0
2.5
–1
2.0
–2
1.5
–3
1.0
–4
0.5
–5
0
–65
–6
–55
–45
–35
–25
PIN (dBm)
–15
–5
5
ERROR (dB)
TCVRMS = (DRIFTVRMS/ΔTEMP) × Slope
6.0
5.5
ERROR (dB)
As shown in Figure 54, whereas the slope is stable vs. the
temperature at 2140 MHz, the intercept of the ADL5906 does
vary slightly vs. temperature (approximately +0.3 dB at +85°C
and −0.8 dB at −40°C). This variation in intercept is constant vs.
input power level at most frequencies. Table 7 lists the average
temperature coefficient of VRMS in mV/°C at frequencies from
100 MHz to 5.8 GHz. This temperature coefficient is given by
the following equation:
From a system calibration and operation perspective, the only
additional measurements that are required to implement this
algorithm are measurement and storage of VTEMP during calibration
(that is, at ambient temperature) and measurement of VTEMP
during operation. All other information required to implement
this algorithm (that is, nominal temperature drift of VRMS and
temperature coefficient of VTEMP) is based on typical data sheet
specifications.
11287-153
In applications where VTEMP and VRMS are both being digitized
by an ADC, the VTEMP voltage can be used to further improve
the temperature drift of the ADL5906.
Figure 55 to Figure 62 show typical plots of VRMS’ vs. input level
and temperature at frequencies from 100 MHz to 5.8 GHz when
this temperature compensation algorithm is applied.
11287-054
USING VTEMP TO IMPROVE INTERCEPT
TEMPERATURE DRIFT
Figure 56. VRMS’ and Log Conformance Error vs. Input Level and Temperature
at 700 MHz Using VTEMP Intercept Compensation
Rev. 0 | Page 25 of 32
ADL5906
Data Sheet
6.0
5
5.5
4
5.0
3
4.5
4.0
2
4.0
2
3.5
1
3.5
1
3.0
0
3.0
0
2.5
–1
2.5
–1
2.0
–2
2.0
–2
1.5
–3
1.5
–3
1.0
–4
1.0
–4
0.5
–5
0.5
–5
–35
–25
–15
–5
5
PIN (dBm)
Figure 57. VRMS’ and Log Conformance Error vs. Input Level and Temperature
at 900 MHz Using VTEMP Intercept Compensation
6.0
–35
–25
–15
–5
5
PIN (dBm)
Figure 60. VRMS’ and Log Conformance Error vs. Input Level and Temperature
at 2600 MHz Using VTEMP Intercept Compensation
5.5
4
5.0
3
4.5
4.0
2
4.0
2
3.5
1
3.5
1
3.0
0
3.0
0
2.5
–1
2.5
–1
2.0
–2
2.0
–2
1.5
–3
1.5
–3
1.0
–4
1.0
–4
0.5
–5
0.5
–5
–55
–45
–35
–25
–15
–5
5
–6
PIN (dBm)
VRMS' (V)
Figure 58. VRMS’ and Log Conformance Error vs. Input Level and Temperature
at 1900 MHz Using VTEMP Intercept Compensation
6.0
6
VTADJ = 0.45V
0
–65
11287-156
0
–65
ERROR (dB)
6.0
4.5
–55
VRMS' –40°C
VRMS' +25°C
VRMS' +85°C
ERROR –40°C
ERROR +25°C
ERROR +85°C
–45
–35
–25
–15
–5
5
5
4
3
–6
PIN (dBm)
Figure 61. VRMS’ and Log Conformance Error vs. Input Level and Temperature
at 3500 MHz Using VTEMP Intercept Compensation
6.0
5
5.5
4
5.0
3
4.5
4.0
2
4.0
2
3.5
1
3.5
1
3.0
0
3.0
0
2.5
–1
2.5
–1
2.0
–2
2.0
–2
1.5
–3
1.5
–3
1.0
–4
1.0
–4
0.5
–5
0.5
–5
5.0
4.5
0
–65
–55
–45
–35
–25
PIN (dBm)
–15
–5
5
–6
VRMS' (V)
VRMS' –40°C
VRMS' +25°C
VRMS' +85°C
ERROR –40°C
ERROR +25°C
ERROR +85°C
0
–65
11287-057
VTADJ = 0.35V
ERROR (dB)
6
5.5
Figure 59. VRMS’ and Log Conformance Error vs. Input Level and Temperature
at 2140 MHz using VTEMP Intercept Compensation
ERROR (dB)
–6
5
VRMS' –40°C
VRMS' +25°C
VRMS' +85°C
ERROR –40°C
ERROR +25°C
ERROR +85°C
VTADJ = 0.35V
5.0
VRMS' (V)
–45
6
5.5
VRMS' (V)
–55
3
11287-058
–45
–55
0
–65
4
ERROR (dB)
–6
5
11287-059
0
–65
VRMS' –40°C
VRMS' +25°C
VRMS' +85°C
ERROR –40°C
ERROR +25°C
ERROR +85°C
VTADJ = 1V
–55
VRMS' –40°C
VRMS' +25°C
VRMS' +85°C
ERROR –40°C
ERROR +25°C
ERROR +85°C
–45
–35
–25
PIN (dBm)
–15
–5
5
6
5
4
3
–6
ERROR (dB)
VRMS' (V)
4.5
6
VTADJ = 0.4V
11287-060
5.0
VRMS' (V)
VRMS' –40°C
VRMS' +25°C
VRMS' +85°C
ERROR –40°C
ERROR +25°C
ERROR +85°C
11287-155
VTADJ = 0.35V
5.5
ERROR (dB)
6
6.0
Figure 62. VRMS’ and Log Conformance Error vs. Input Level and Temperature
at 5800 MHz Using VTEMP Intercept Compensation
Rev. 0 | Page 26 of 32
Data Sheet
ADL5906
Table 7. Scaling Factors for Intercept Temperature Drift Compensation Using VTEMP
Frequency
(MHz)
100
700
900
1900
2140
2600
3500
5800
TCVRMS, −40°C to +25°C,
PIN = 0 dBm (mV/°C)
0.72615
0.81692
0.72615
0.70154
0.68923
0.76154
1.2
1.23931
TCVRMS, 25°C to 85°C,
PIN = 0 dBm (mV/°C)
0.19667
0.295
0.295
0.19
0.28
0.275
0
0.08041
TCVTEMP
(mV/°C)
4.8
4.8
4.8
4.8
4.8
4.8
4.8
4.8
VTEMP Weighting Factor,
−40°C to +25°C
(TCVTEMP/TCVRMS)
6.61017
5.87571
6.61017
6.84211
6.96429
6.30303
4
5.99417
TCVRMS based on temperature drift at PIN = −10 dBm.
1
DESCRIPTION OF CHARACTERIZATION
For a description on how characterization was completed, see the ADL5902 data sheet.
Rev. 0 | Page 27 of 32
VTEMP Weighting Factor,
+25°C to +85°C
(TCVTEMP/TCVRMS)
24.40678
16.27119
16.27119
25.26316
17.14286
17.45455
∞
85.287
ADL5906
Data Sheet
EVALUATION BOARD
signal is applied to the SMA connector (RFIN). The output
voltage is available on the SMA connector (VOUT1) or on the
test loop (VOUT). Configuration options for the evaluation
board are listed in Table 8.
The ADL5906-EVALZ is a fully populated, 4-layer, FR4based evaluation board. For normal operation, it requires a
5 V/100 mA power supply. The 5 V power supply must be
connected to the VPOS and GND test loops. The RF input
VPOS
C3
0.1µF
C7
0.1µF
C4
100pF
C5
100pF
VPOS1
VPOS2
10
3
TEMPERATURE
SENSOR
ADL5906
R3
60.4Ω
RFIN+
RFIN–
VTEMP
R2
(OPEN)
IDET
14
X2
VSET
15
VSET
7
LINEAR-IN-dB VGA
(NEGATIVE SLOPE)
C12
10nF
X2
ITGT
NIC 2
G=5
6
VRMS
R6
0Ω
R1
0Ω
VOUT
R15
(OPEN)
NIC 16
NIC 13
VREF
2.3V
BIAS AND POWER
DOWN CONTROL
5
EPAD
26pF
11
1
TADJ/
PWDN
VOUT1
12
VREF
VTGT
9
GND2
CRMS
C9
0.1µF
4
GND1
GND
R12
270Ω
R9
1.5kΩ
TC2
R10
3.74kΩ
VREF
R11
2kΩ
VTGT
11287-150
C10
10nF
RFIN
8
Figure 63. Evaluation Board Schematic
Table 8. Evaluation Board Configuration Options
Component
RFIN, R3, C10,
C12
VTGT, R10,
R11
VPOS, GND,
C3, C4, C5,C7
Function/Notes
RF input. The evaluation board is configured for single-ended drive on the RFIN+ pin (Pin 14).
Capacitors C10 and C12 have been set large enough so that the full frequency range of the
device is covered. If operation down to 10 MHz is not required, the value of these capacitors
can be reduced.
VTGT interface. R10 and R11 are set up to provide 0.8 V to VTGT derived from VREF. If R10 and
R11 are removed, an external voltage can be applied on the VTGT test point.
Power supply interface and decoupling. Apply the power supply for the evaluation board to
the VPOS and GND test loops. The nominal supply decoupling consists of a 100 pF capacitor and a
0.1 µF capacitor on each power supply pin, with the 100pF capacitor placed closer to the pin.
Rev. 0 | Page 28 of 32
Default Value
RFIN = SMA connector,
C10 = C12 = 10 nF,
R3 = 60.4 Ω
VTGT = black test loop,
R10 = 3.74 kΩ,
R11 = 2 kΩ,
VTGT = 0.8 V
VPOS = red test loop,
GND = black test loop,
C3 = C7 = 0.1 µF,
C4 = C5 = 100 pF
Data Sheet
Component
VOUT, VOUT1,
VSET, R1, R2,
R6, R15
C9
TC2, R9, R12
ADL5906
Function/Notes
Output interface. In measurement mode, a portion of the voltage at the VRMS pin is fed back
to the VSET pin via R6 (R6 is normally set to 0 Ω). Using the voltage divider created by R2 and
R6, the magnitude of the slope of VRMS is increased by reducing the portion of VRMS that is fed
back to VSET. Resistors R1 and R15 can be used to reduce the output slope.
In controller mode, R6 must be open. In this mode, the ADL5906 can control the gain of a variable
gain amplifier (VGA) or voltage variable attenuator (VVA). A setpoint voltage is applied to the
VSET test loop, and the VRMS test loop or SMA connector drives the gain control input of the
VGA/VVA.
RMS averaging capacitor. The value of the rms averaging capacitor should be set based on the
peak-to-average ratio of the input signal and based on the desired output response time and
residual output noise.
TADJ/PWDN interface. The TADJ/PWDN pin controls the slope temperature compensation
and/or shuts down the device. The evaluation board is configured with VTADJ connected to
VREF through a resistor divider (R9, R12). This voltage divider can be removed (or simply
overdriven) allowing for the external application of a voltage to the VTADJ pin by applying a
voltage to the TC2 test point.
Default Value
VOUT = black test loop,
VOUT1 = SMA connector,
VSET = black test loop,
R1 = R6 = 0 Ω,
R15 = R2 = open
C9 = 0.1 µF
TC2 = black test loop,
R9 = 1.5 kΩ, R12 = 270 Ω,
VTADJ = 0.35 V
11287-056
11287-055
EVALUATION BOARD ASSEMBLY DRAWINGS
Figure 65. ADL5906 Evaluation Board Layout, Bottom Side
Figure 64. ADL5906 Evaluation Board Layout, Top Side
Rev. 0 | Page 29 of 32
ADL5906
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.35
0.30
0.25
0.65
BSC
PIN 1
INDICATOR
16
13
1
12
EXPOSED
PAD
2.25
2.10 SQ
1.95
9
TOP VIEW
0.80
0.75
0.70
0.70
0.60
0.50
4
8
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
111908-A
4.10
4.00 SQ
3.90
Figure 66. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-23)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADL5906ACPZN-R2
ADL5906ACPZN-R7
ADL5906SCPZN-R2
ADL5906SCPZN-R7
ADL5906-EVALZ
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−55°C to +125°C
−55°C to +125°C
Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 30 of 32
Package Option
CP-16-23
CP-16-23
CP-16-23
CP-16-23
Ordering Quantity
250
1,500
250
1,500
Data Sheet
ADL5906
NOTES
Rev. 0 | Page 31 of 32
ADL5906
Data Sheet
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11287-0-3/13(0)
Rev. 0 | Page 32 of 32