IRF AUIRFN8459 Dual n-channel mosfet Datasheet

AUTOMOTIVE GRADE
Features
 Advanced Process Technology
 Dual N-Channel MOSFET
 Ultra Low On-Resistance
 175°C Operating Temperature
 Fast Switching
 Repetitive Avalanche Allowed up to Tjmax
 Lead-Free, RoHS Compliant
 Automotive Qualified *
AUIRFN8459
VDSS
40V
RDS(on) typ.
4.8m
5.9m
max
70A
ID (Silicon Limited)
50A
ID (Package Limited)
Description
Specifically designed for Automotive applications, this HEXFET®
Power MOSFET utilizes the latest processing techniques to
achieve extremely low on-resistance per silicon area. Additional
features of this design are a 175°C junction operating temperature,
fast swithcing speed and improved repetitive avalanche rating.
These features combine to make this product an extremely
efficient and reliable device for use in Automotive and wide variety
of other applications.
Applications
 12V Automotive Systems
 Brushed DC Motor
 Braking
 Transmission
Base Part Number
Package Type
AUIRFN8459
Dual PQFN 5mm x 6mm
DUAL PQFN 5X6 mm
G
D
S
Gate
Drain
Source
Standard Pack
Form
Quantity
Tape and Reel
4000
Orderable Part Number
AUIRFN8459TR
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; and
functional operation of the device at these or any other condition beyond those indicated in the specifications is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. The thermal resistance and power dissipation ratings are measured under
board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise specified.
ID @ TC (Bottom) = 25°C
ID @ TC (Bottom) = 100°C
ID @ TC (Bottom) = 25°C
IDM
Parameter
Continuous Drain Current, VGS @ 10V 
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current 
PD @TC (Bottom) = 25°C
Power Dissipation
VGS
EAS
EAS (Tested)
IAR
EAR
TJ
TSTG
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy (Thermally Limited) 
Single Pulse Avalanche Energy 
Avalanche Current 
Repetitive Avalanche Energy 
Operating Junction and
Storage Temperature Range
Max.
70
50
50
320
Units
50
W
0.33
± 20
66
110
See Fig. 14, 15, 22a, 22b
W/°C
V
mJ
-55 to + 175
A
A
°C
HEXFET® is a registered trademark of International Rectifier.
*Qualification standards can be found at http://www.irf.com/
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Thermal Resistance
Symbol
Parameter
RJC (Bottom)
Junction-to-Case 
Typ.
–––
Max.
3.0
RJC (Top)
Junction-to-Case 
–––
45
RJA
Junction-to-Ambient 
–––
105
RJA (<10s)
Junction-to-Ambient 
–––
80
Units
°C/W
Static Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
40
–––
–––
V VGS = 0V, ID = 250µA
––– 0.037 ––– V/°C Reference to 25°C, ID = 1.0mA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient
–––
4.8
5.9
RDS(on)
Static Drain-to-Source On-Resistance
m VGS = 10V, ID = 40A 
VGS(th)
Gate Threshold Voltage
2.2
3.0
3.9
V VDS = VGS, ID = 50µA
gfs
Forward Transconductance
66
–––
–––
S VDS = 10V, ID = 40A
RG
Internal Gate Resistance
–––
1.9
–––

–––
–––
1.0
VDS = 40V, VGS = 0V
Drain-to-Source Leakage Current
µA
IDSS
–––
–––
150
VDS = 40V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
–––
–––
100
VGS = 20V
nA
Gate-to-Source Reverse Leakage
–––
––– -100
VGS = -20V
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
Qg
Total Gate Charge
–––
40
60
ID = 40A
VDS = 20V
Qgs
Gate-to-Source Charge
–––
13
–––
nC
VGS = 10V
Qgd
Gate-to-Drain ("Miller") Charge
–––
14
–––
Qsync
Total Gate Charge Sync. (Qg - Qgd)
–––
26
–––
ID = 40A, VDS =0V, VGS = 10V
td(on)
Turn-On Delay Time
–––
10
–––
VDD = 26V
ID = 40A
tr
Rise Time
–––
55
–––
ns
td(off)
Turn-Off Delay Time
–––
25
–––
RG = 2.7
VGS = 10V
Fall Time
–––
42
–––
tf
Ciss
Input Capacitance
––– 2250 –––
VGS = 0V
VDS = 25V
Coss
Output Capacitance
–––
340
–––
Crss
Reverse Transfer Capacitance
–––
215
–––
pF ƒ = 1.0 MHz
Coss eff. (ER) Effective Output Capacitance (Energy Related)
–––
400
–––
VGS = 0V, VDS = 0V to 32V 
Coss eff. (TR) Effective Output Capacitance (Time Related)
–––
490
–––
VGS = 0V, VDS = 0V to 32V 
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
Continuous Source Current
–––
––– 70
MOSFET symbol
IS
A
(Body Diode)
showing the
integral reverse
Pulsed Source Current
–––
–––
320
ISM
A
(Body Diode) 
p-n junction diode.
VSD
Diode Forward Voltage
–––
–––
1.3
V TJ = 25°C, IS = 40A, VGS = 0V 
dv/dt
Peak Diode Recovery 
–––
7.0
––– V/ns TJ = 175°C, IS= 40A, VDS = 40V
–––
22
–––
TJ = 25°C
trr
Reverse Recovery Time
ns
VR = 34V,
–––
23
–––
TJ = 125°C
IF = 40A
–––
17
–––
TJ = 25°C
di/dt = 100A/µs
Qrr
Reverse Recovery Charge
nC
–––
17
–––
TJ = 125°C
IRRM
Reverse Recovery Current
–––
1.0
–––
A TJ = 25°C
2
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1000
1000
100
BOTTOM
10
1
4.3V
 60µs PULSE WIDTH
Tj = 25°C
100
BOTTOM
10
4.3V
 60µs PULSE WIDTH
Tj = 175°C
1
0.1
0.1
1
10
0.1
100
Fig. 1 Typical Output Characteristics
100
1.8
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
Fig. 2 Typical Output Characteristics
1000
100
T J = 175°C
10
T J = 25°C
1
VDS = 10V
 60µs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
6.0
7.0
8.0
ID = 40A
VGS = 10V
1.6
1.4
1.2
1.0
0.8
0.6
9.0
-60 -40 -20
VGS, Gate-to-Source Voltage (V)
10000
0
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig. 4 Normalized On-Resistance vs. Temperature
Fig. 3 Typical Transfer Characteristics
14
VGS, Gate-to-Source Voltage (V)
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = C gd
Coss = Cds + Cgd
C, Capacitance (pF)
1
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Ciss
1000
Coss
Crss
ID= 40A
12
VDS= 32V
VDS= 20V
VDS= 8.0V
10
8
6
4
2
0
100
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
3
VGS
15V
10V
8.0V
7.0V
6.0V
5.0V
4.5V
4.3V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.0V
4.5V
4.3V
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0
10
20
30
40
50
60
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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AUIRFN8459
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
100
T J = 175°C
10
T J = 25°C
1
100µsec
100
1msec
Limited by
10
Package
OPERATION IN THIS AREA
LIMITED BY RDS(on)
1
Tc = 25°C
Tj = 150°C
Single Pulse
VGS = 0V
0.1
0.5
1.0
1.5
2.0
2.5
3.0
0.1
VSD, Source-to-Drain Voltage (V)
Limited By Package
ID, Drain Current (A)
50
40
30
20
10
0
25
50
75
100
125
150
175
Id = 1.0mA
48
46
44
42
40
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Case Temperature
0.25
0.20
Energy (µJ)
Fig 10. Drain-to–Source Breakdown Voltage
RDS (on), Drain-to -Source On Resistance (m )
0.30
0.15
0.10
0.05
0.00
20
30
100
50
TC , Case Temperature (°C)
10
10
Fig 8. Maximum Safe Operating Area
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
70
60
1
VDS, Drain-toSource Voltage (V)
Fig. 7 Typical Source-to-Drain Diode
40
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical Coss Stored Energy
4
DC
0.1
0.0
0
10msec
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20.0
VGS = 5.5V
VGS = 6.0V
16.0
VGS = 7.0V
VGS = 8.0V
VGS = 10V
12.0
8.0
4.0
0
50
100
150
200
ID, Drain Current (A)
Fig 12. Typical On-Resistance vs. Drain Current
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AUIRFN8459
Thermal Response ( ZthJC ) °C/W
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Avalanche Current (A)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming  Tj = 150°C and
Tstart =25°C (Single Pulse)
10
1
0.1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 125°C.
0.01
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Avalanche Current vs. Pulse Width Current
70
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 40A
EAR , Avalanche Energy (mJ)
60
50
40
30
20
10
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1.Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for every
part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
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4.5
25
ID = 40A
VGS(th) Gate threshold Voltage (V)
RDS(on), Drain-to -Source On Resistance ( m )
AUIRFN8459
20
15
T J = 125°C
10
T J = 25°C
5
4.0
3.5
3.0
2.5
8
12
16
= 50µA
= 250µA
= 1.0mA
= 1.0A
2.0
0
4
ID
ID
ID
ID
1.5
20
-75
-50
-25
VGS, Gate-to-Source Voltage (V)
75
100
125
150
5
IF = 26A
V R = 34V
4
IF = 40A
V R = 34V
4
TJ = 25°C
TJ = 125°C
3
IRRM (A)
IRRM (A)
50
Fig 17. Threshold Voltage vs. Temperature
5
2
TJ = 25°C
TJ = 125°C
3
2
1
1
0
0
0
100
200
300
400
500
0
600
100
200
300
400
500
600
diF /dt (A/µs)
diF /dt (A/µs)
Fig 19. Typical Stored Charge vs. dif/dt
Fig 18. Typical Recovery Current vs. dif/dt
90
90
IF = 26A
V R = 34V
80
70
70
IF = 40A
V R = 34V
TJ = 25°C
60
TJ = 125°C
80
TJ = 25°C
TJ = 125°C
QRR (nC)
60
QRR (nC)
25
T J , Temperature ( °C )
Fig 16. Typical On-Resistance vs. Gate Voltage
50
40
50
40
30
30
20
20
10
10
0
0
0
100
200
300
400
500
600
diF /dt (A/µs)
Fig 20. Typical Recovery Current vs. dif/dt
6
0
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0
100
200
300
400
500
600
diF /dt (A/µs)
Fig 21. Typical Stored Charge vs. dif/dt
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Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
Fig 22a. Unclamped Inductive Test Circuit
Fig 23a. Switching Time Test Circuit
Fig 22b. Unclamped Inductive Waveforms
Fig 23b. Switching Time Waveforms
VDD
Fig 24a. Gate Charge Test Circuit
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Fig 24b. Gate Charge Waveform
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AUIRFN8459
Dual PQFN 5x6 Package Details
For more information on board mounting, including footprint and stencil recommendation, please refer to application
note AN-1136: http://www.irf.com/technical-info/appnotes/an-1136.pdf
For more information on package inspection techniques, please refer to application note AN-1154:
http://www.irf.com/technical-info/appnotes/an-1154.pdf
Dual PQFN 5x6 Part Marking
INTERNATIONAL
RECTIFIER LOGO
DATE CODE
ASSEMBLY
SITE CODE
(Per SCOP 200-002)
PIN 1
IDENTIFIER
XXXX
XYWWX
XXXXX
PART NUMBER
(“4 or 5 digits”)
MARKING CODE
(Per Marking Spec)
LOT CODE
(Eng Mode - Min last 4 digits of EATI#)
(Prod Mode - 4 digits of SPN code)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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Qualification Information†
Qualification Level
Moisture Sensitivity Level
Human Body Model
Automotive
(per AEC-Q101)
Comments: This part number(s) passed Automotive qualification. IR’s Industrial and Consumer qualification level is granted by extension of the higher Automotive level.
Dual PQFN 5mm x 6mm
MSL1
Class H1B(+/- 1000V)
††
AEC-Q101-001
ESD
Charged Device Model
Class C5 (+/- 1000V)††
AEC-Q101-005
RoHS Compliant
†
Yes
Qualification standards can be found at International Rectifier’s web site: http//www.irf.com/
†† Highest passing voltage.
Notes:
 Repetitive rating; pulse width limited by max. junction temperature.
 Limited by TJmax, starting TJ = 25°C, L =75µH, RG = 50, IAS = 40A, VGS = 10V.
ISD  50A, di/dt  650A/µs, VDD  V(BR)DSS, TJ  175°C.
 Pulse width  400µs; duty cycle 2%.
 Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
 Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
 When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques
refer to application note #AN-994: http://www.irf.com/technical-info/appnotes/an-994.pdf
 R is measured at TJ of approximately 90°C.
 This value determined from sample failure population, starting TJ = 25°C, L= 75µH, RG = 50, IAS = 40A, VGS =10V.
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 50A.
Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements
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IMPORTANT NOTICE
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the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services
at any time and to discontinue any product or services without notice. Part numbers designated with the “AU” prefix follow
automotive industry and / or customer specific requirements with regards to product discontinuance and process change
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IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with IR’s
standard warranty. Testing and other quality control techniques are used to the extent IR deems necessary to support this
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Tel: (310) 252-7105
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