Allegro A1162 Programmable precision hall-effect switch with advanced diagnostic Datasheet

A1162
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
FEATURES AND BENEFITS
DESCRIPTION
• User-programmable unipolar switchpoints
• Integrated diagnostics for enhanced system safety and
reliability
□□ Enabled on demand
□□ Integrated electromagnetic coils test the entire sensor
signal path
□□ Designed for ISO 26262 / ASIL systems (QM)
• Chopper stabilized
□□ Resistant to physical stress
□□ Superior temperature stability
• Internal regulator for wide operating voltage range
□□ 3.8 to 24 V
• Automotive-grade ruggedness
□□ Solid-state reliability
□□ Reverse-battery protection
2
□□ Output short-circuit protection
□□ AEC-Q100 qualified
• Small surface-mount package
The A1162 is a unipolar Hall-effect switch with an externally
enabled diagnostic function and user-programmable
switchpoints. On-chip electromagnetic coils are used to
implement self-test of the sensor’s entire magnetic and electrical
signal chain. It is designed for systems where precise magnet
switchpoints and safety, reliability, or both, are critical, such
as those designed to meet the requirements of ISO 26262.
-
PACKAGE:
8-Pin eTSSOP (Suffix LE)
Continued on next page...
VREG
VREG
Trim Control
To all subcircuits
Dynamic Offset
Cancellation
Regulator
When the diagnostic feature is enabled, the output of the A1162
provides a square wave output which confirms the device
is properly sensing the internally generated magnetic field.
Therefore, use of the A1162 either eliminates the need for
redundant sensors in safety-critical applications or increases
robustness in safety-critical applications that might otherwise
require redundant sensors (drive-by-wire systems, etc.).
This monolithic IC integrates a voltage regulator, Hall voltage
generator, small-signal amplifier, chopper stabilization, Schmitt
trigger, and short-circuit-protected open-collector output able
to sink up to 25 mA. The on-board regulator permits operation
Not to scale
VCC
In normal operating mode, the A1162 functions as a standard
unipolar Hall-effect switch. The device output transistor turns
on (output signal switches low) in the presence of sufficient
magnetic field (>BOP max). The output transistor of the A1162
switches off (output signal switches high) when the magnetic
field is removed (<BRP min).
Switchpoint
Programming
AMP
Signal
Recovery
Threshold
NORM
DAIG
DIAG
VOUT
Control
Current
Limit
System Diagnostics
GND
Functional Block Diagram
A1162-DS
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
DESCRIPTION (CONTINUED)
with supply voltages of 3.8 to 24 V. It is temperature-stable and
stress-resistant, making it especially suited for operation over
temperature ranges up to 150ºC (L temperature range). Superior
high-temperature performance is made possible through advanced
dynamic offset cancellation techniques, which reduce the residual
offset voltage normally caused by device overmolding, temperature
dependencies, and thermal stress.
The A1162 is a Quality Managed (QM) product that has been
developed according to the automotive quality requirements of
TS 16949 and contains features targeted for automotive safety
applications. This product can be qualified for use in accordance
with ISO 26262 in compliant safety systems by ensuring a robust
integration of the component into the system design. Safety
documentation will be provided to support and guide the integration
process.
SPECIFICATIONS
Selection Guide
Part Number
Packing
Package
A1162LLETR-00-T
4000 pieces / reel
8-pin TSSOP
Temperature Range,
TA (ºC)
–40 to 150
Output in South
Polarity Field
Low
Magnetic Operate
Point, BOP (G)
Programmable
RoHS
COMPLIANT
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Unit
Forward Supply Voltage
VCC
30
V
Reverse Supply Voltage
VRCC
–18
V
Forward Diagnostic Enable Voltage
VDIAG
6.5
V
Reverse Diagnostic Enable Voltage
VRDIAG
–0.5
V
Output Off Voltage
VOUT
30
V
Continuous Output Current
IOUT
25
mA
Reverse Output Current
IOUTR
50
mA
–40 to 150
°C
TJ(max)
165
°C
Tstg
–65 to 170
°C
Operating Ambient Temperature
TA
Maximum Junction Temperature
Storage Temperature
Range L
NC/GND
1
8
NC/GND
VOUT
2
7
GND
3
6
GND
4
5
Package LE, 8-Pin eTSSOP Pinouts
Terminal List Table
Pin #
Symbol
Description
NC/GND
1
NC/GND
DIAG
2
VOUT
Output from circuit
VCC
3
GND
Ground
4
GND
Ground
Connected to ground internally. May be left
floating or connected to ground.
5
VCC
Connects power supply to chip
6
DIAG
Diagnostic Enable
7
NC/GND
Connected to ground internally. May be left
floating or connected to ground.
8
NC/GND
Connected to ground internally. May be left
floating or connected to ground.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
OPERATING CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges, unless otherwise
specified
Characteristics
Symbol
Test Conditions
Min.
Typ.1
Max.
Unit
Electrical Characteristics
Supply Voltage
Output Leakage Current
Output Saturation Voltage
VCC
Operating, TJ < 165°C
3.8
–
24
V
IOUTOFF
VOUT = 24 V, B < BRP
–
–
10
µA
VOUT(SAT)
IOUT = 20 mA, B > BOP
–
185
400
mV
Output Current Limit
IOM
B > BOP
30
–
60
mA
Power-On Time 2
tON
VCC > 3.8 V, B < BRPmin – 10 G,
B > BOPmax + 10 G
–
–
25
µs
Chopping Frequency
fC
–
400
–
kHz
Output Rise Time 2,3
tr
RLOAD = 820 Ω, CL = 20 pF
–
0.2
2
µs
Output Fall Time 2,3
tf
RLOAD = 820 Ω, CL = 20 pF
–
0.1
2
µs
Supply Current
Reverse-Battery Current
ICC(ON)
B > BOP
–
–
5
mA
ICC(OFF)
B < BRP
–
–
5
mA
ICC(DIAG)
DIAG = 1, TJ < TJ(MAX)
–
16
25
mA
VRCC = –18 V
–
–
–10
mA
IRCC
Supply Zener Clamp Voltage
VZSUP
ICC = 8 mA, TA = 25°C
30
–
–
V
Output Zener Voltage
VZOUT
IOUT = 3 mA, TA = 25°C
28
–
–
V
PWM Carrier Frequency
fPWMout
With diagnostic mode enabled
–
3
–
kHz
DCFAIL
DIAG = 1, Device Malfunction
–
0
40
%
Duty Cycle (Diagnostic Mode) 4
DCFAIL
DIAG = 1, Device Malfunction
60
100
–
%
DCPASS
DIAG = 1, Device Normal
40
50
60
%
DIAG pin pulled low
–
1
–
MΩ
–
–
0.6
V
1.5
–
5
V
Diagnostic Characteristics
DIAG Pin Input Resistance
RDIAG
DIAG Pin Input Low Voltage
Threshold
VIL
Device in Normal Mode
DIAG Pin Input High Voltage
Threshold
VIH
Device in Diagnostic Mode
Diagnostic Time
tD
The diagnostics feature should be enabled
for at least tD in order to obtain an accurate
PWM signal.
1
–
–
ms
tDIS
Time from when DIAG pin is released (High
to Low transition) to valid device output
–
–
25
µs
Diagnostic Disable Time
Continued on next page...
1 Typical
data is at TA = 25ºC and VCC = 12 V and it is for design information only.
time, Rise time and Fall time are guaranteed through device characterization and not final test.
L = oscilloscope probe capacitance.
4 When the DUT passes the diagnostic tests, the output will be a 50% duty cycle signal. Any other output indicates the DUT failed the test. Please see the application notes for
more information.
2 Power-on
3C
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
OPERATING CHARACTERISTICS (continued): Valid over full operating voltage and ambient temperature ranges, unless
otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.1
Max.
Unit
Magnetic Characteristics 5
Magnetic Step Size
BOP programming step size
–
5
–
G
–
250
G
Operate Point
BOP
Programmable
BRPmin +
BHYS
Release Point
BRP
Programmable
–5
–
BOPmax –
BHYS
G
BHYS00
BHYS register = 00
5
–
30
G
BHYS01
BHYS register = 01
7
–
40
G
BHYS10
BHYS register = 10
10
–
60
G
BHYS11
BHYS register = 11
15
–
65
G
800
10,000
–
G
Hysteresis (BOP – BRP)
Maximum External Field in
Diagnostic Mode 6
BEXT(DIAG)
Drift Detection Threshold
Operate Point Drift
BOP(DRIFT)
Programmable
0.25 × BOP
–
1.75 × BOP
G
Release Point Drift
BRP(DRIFT)
Programmable
0.25 × BRP
–
1.75 × BRP
G
1 Typical
data is at TA = 25ºC and VCC = 12 and it is for design information only
5 Magnetic flux density (B) is indicated as a negative value for north-polarity magnetic fields, and is a positive value for south-polarity magnetic fields.
6 800 G is the maximum test capability due to practical equipment limitations. Design simulations show that a 10,000 G external field will not adversely affect the sensor in
diagnostic mode.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
Package Thermal Resistance
Test Conditions*
RθJA
On 4-layer PCB based on JEDEC standard JESD51-7
Value
Unit
145
ºC/W
*Additional thermal information available on the Allegro website
Maximum
Power
Dissipation
vs. Ambient
Temperature
Power
Dissipation
versus
Ambient Temperature
1000
900
800
Power Dissipation, PD (mW)
700
600
(R
J
A
500
=
14
5
ºC
/W
)
400
300
200
100
0
20
40
60
80
100
120
140
Temperature, TA (°C)
160
180
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
CHARACTERISTIC PERFORMANCE
ICC(OFF) vs. VCC
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
VCC
3.8 V
12 V
24 V
-50
0
50
100
Supply Current, ICC(OFF) (mA)
Supply Current, ICC(OFF) (mA)
ICC(OFF) vs. TA
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
TA
-40ºC
25ºC
150ºC
150
0
5
Ambient Temperature, TA (°C)
3.8 V
12 V
24 V
100
Supply Current, ICC(ON) (mA)
Supply Current, ICC(ON) (mA)
VCC
50
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-40ºC
25ºC
150ºC
150
0
5
VCC
3.8 V
12 V
24 V
100
Ambient Temperature, TA (°C)
150
Supply Current, ICC(DIAG) (mA)
Supply Current, ICC(DIAG) (mA)
15
20
25
ICC(DIAG) vs. VCC
26
24
22
20
18
16
14
12
10
8
50
10
Supply Voltage, VCC (V)
ICC(DIAG) vs. TA
0
25
TA
Ambient Temperature, TA (°C)
-50
20
ICC(ON) vs. VCC
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
15
Supply Voltage, VCC (V)
ICC(ON) vs. TA
-50
10
26
24
22
20
18
16
14
12
10
8
TA
-40ºC
25ºC
150ºC
0
5
10
15
20
25
Supply Voltage, VCC (V)
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Output Saturation Voltage, VOUT(SAT) (mV)
VOUT(SAT) vs. TA
400
350
300
250
200
150
VCC
3.8 V
12 V
24 V
100
50
0
-50
0
50
100
150
Ambient Temperature, TA (°C)
Output Saturation Voltage, VOUT(SAT) (mV)
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
VOUT(SAT) vs. VCC
400
350
300
250
200
150
TA
100
-40ºC
25ºC
150ºC
50
0
0
5
PWM Carrier Frequency, fPWMout (kHz)
100
150
25ºC
0
5
10
15
Supply Voltage, VCC (V)
fPWMout vs. TA
fPWMout vs. VCC
5
4
3
VCC
2
3.8 V
12 V
24 V
1
0
0
50
25
TA
Ambient Temperature, TA (°C)
6
-50
Duty Cycle, DCPASS (%)
3.8 V
60
58
56
54
52
50
48
46
44
42
40
100
Ambient Temperature, TA (°C)
150
PWM Carrier Frequency, fPWMout (kHz)
Duty Cycle, DCPASS (%)
VCC
50
20
DCPASS vs. VCC
60
58
56
54
52
50
48
46
44
42
40
0
15
Supply Voltage, VCC (V)
DCPASS vs. TA
-50
10
20
25
6
5
4
3
TA
2
-40ºC
1
25ºC
150ºC
0
0
5
10
15
20
25
Supply Voltage, VCC (V)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
BOP(init) vs. VCC
10
5
0
-5
VCC
3.8 V
12 V
24 V
-10
-15
-50
0
50
100
150
Magnetic Operate Point, BOP(init) (G)
Magnetic Operate Point, BOP(init) (G)
BOP(init) vs. TA
10
5
0
-5
TA
-40ºC
25ºC
150ºC
-10
-15
0
5
0
-5
-10
-15
VCC
3.8 V
12 V
24 V
-20
-25
0
50
100
150
-10
-15
TA
-40ºC
25ºC
150ºC
-20
-25
0
5
VCC
25
20
3.8 V
12 V
24 V
15
10
5
0
100
Ambient Temperature, TA (°C)
150
Magnetic Release Point, BHYS(init) (G)
Magnetic Hysteresis, BHYS(init) (G)
10
15
20
25
Supply Voltage, VCC (V)
BHYS(init) vs. VCC
30
50
25
-5
BHYS(init) vs. TA
0
20
0
Ambient Temperature, TA (°C)
-50
15
BRP(init) vs. VCC
Magnetic Release Point, BRP(init) (G)
Magnetic Release Point, BRP(init) (G)
BRP(init) vs. TA
-50
10
Supply Voltage, VCC (V)
Ambient Temperature, TA (°C)
30
TA
25
-40ºC
25ºC
150ºC
20
15
10
5
0
0
5
10
15
20
25
Supply Voltage, VCC (V)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
BHYS vs. TA
10
9
8
7
6
5
4
3
2
1
0
65
Hysteresis, BHYS (G)
Magnetic Step Size (G)
BOP Programming Step Size vs. TA
BHYS00
BHYS01
BHYS10
BHYS11
55
45
35
25
15
5
-50
0
50
100
150
-50
Bit 5
Bit 4
BOP(init)
Bit 3
Bit 2
Bit 1
Bit 0
0
4
8
12
16
20
Code
50
100
150
BOP Bit Weight vs. TA
24
28
32
36
Magnetic Operate Point, BOP (G)
Magnetic Operate Point, BOP(avg) (G)
BOP(avg) vs. Code
180
160
140
120
100
80
60
40
20
0
-20
0
Ambient Temperature, TA (°C)
Ambient Temperature, TA (°C)
160
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
140
120
100
80
60
40
20
0
-50
0
50
100
150
Ambient Temperature, TA (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
FUNCTIONAL DESCRIPTION
Operation
Power-On Sequence and Timing
The output of these devices switches low (turns on) when a magnetic field perpendicular to the Hall sensor exceeds the operate
point threshold, BOP (see Figure 1). After turn-on, the output is
capable of sinking 25 mA and the output voltage is VOUT(SAT).
When the magnetic field is reduced below the release point (BRP)
the device output goes high (turns off). The difference in the
magnetic operate and release points is the hysteresis (BHYS) of
the device. This built-in hysteresis allows clean switching of the
output, even in the presence of external mechanical vibration and
electrical noise.
The output states are only valid when the supply voltage is within
the specified operating range (VCC(MIN) ≤ VCC ≤ VCC(MAX)) and
the power-on time has elapsed (t > tON). Refer to Figure 2 for an
illustration of the power-on sequence.
Powering-on the device in the hysteresis range, less than BOP and
higher than BRP, results in a HIGH output state. The correct state
is attained after the first excursion beyond BOP or BRP. The output
will not switch until there is a valid transition beyond BOP or BRP.
VOUT(OFF)
Output Undefined for
VCC < VCC(MIN)
Switch to High
VCC
0
BRP
Output Responds According
to Magnetic Field Input
B > BOP or B < BRP
t > tON(MAX)
time
V
VCC(MIN)
VOUT(SAT)
BOP
0
0
V
VOUT(ON)
Switch to Low
VOUT
V+
Once the supply voltage is within the operational range, the
output will be in the low state (power-on state), irrespective of
the magnetic field. The output will remain low until the sensor is
fully powered on (t > tON), at which point, the output will respond
to the corresponding magnetic field presented to the sensor.
B+
BHYS
Figure 1: Switching Behavior of Unipolar Switches
VCC
0
t ON
time
Figure 2: Power-On Sequence and Timing
On the horizontal axis, the B+ direction indicates increasing south
polarity magnetic field strength.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
Diagnostic Mode of Operation
The diagnostic mode is accessed by applying a voltage higher
than VIH on the diagnostic enable pin. The diagnostic mode uses
an internally generated magnetic signal to exercise the signal
path. This signal is compared to two reference signals in the
Schmitt Trigger block (refer to Figure 3).
If the diagnostic signal is between the two reference signals, the
part is considered to be working within specifications and a 50%
DIAG
PWM signal is set at the output pin, as shown in Figure 3. If the
diagnostic signal is above the upper reference or below the lower
reference, the output is set at a fixed value (High/Low).
The diagnostic mode of operation not only detects catastrophic
failures but also drifts in the magnetic switchpoints. If BOP or
BRP drift to values below or above the values stated in the Drift
Detection Threshold table, the output is set at a fixed value when
in the diagnostic mode of operation.
DIAG
VOUT
Device OK
Duty Cycle = 50%
Device Failure
Duty Cycle ≠ 50%
Figure 3: Diagnostic Functional Diagram
When the device passes, there will be a 50% duty-cycle signal sent out. In the event of a failure, the output will typically be forced either high
or low. Diagnostic mode is only active when DIAG is pulled high.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
Applications
Extensive applications information on magnets and Hall-effect
sensors is available in:
It is strongly recommended that an external capacitor be connected (in close proximity to the Hall sensor) between the supply
and ground of the device to reduce both external noise and noise
generated by the chopper stabilization technique. As shown in
Figure 4, a 0.1 µF capacitor is typical.
Note that pins 3 and 4 are the primary ground return for all sensor
functions. These pins should be connected together close to the
IC. Pins 1, 7, and 8 are connected to ground internally, but these
pins may be connected to ground or left floating. They must not
be connected to VCC or any other signal.
•
Hall-Effect IC Applications Guide, AN27701
•
Soldering Methods for Allegro’s Products – SMT and
Through-Hole, AN26009
•
Guideline for Designing Subassemblies Using Hall-Effect
Devices, AN27703.1
•
ASEK-02 Allegro Sensor Evaluation Kit Technical Guide
All are provided on the Allegro website:
www.allegromicro.com
V+
CBYPASS
0.1 µF
RL
VCC
From
Controller
DIAG
A1162
VOUT
Output
CL
Optional
GND
GND
Figure 4: Typical Application Circuit
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
PROGRAMMING GUIDELINES
Overview
Programming is accomplished by sending a series of input voltage pulses serially through the VCC (supply) pin of the device.
A unique combination of different voltage level pulses controls
the internal programming logic of the device to select a desired
programmable parameter and change its value. There are three
voltage levels that must be taken into account when programming. These levels are referred to as high (VPH), mid (VPM), and
low (VPL).
The A1162 features three programmable modes, Try mode, Blow
mode, and Read mode:
The ASEK-02 kit is intended for use as a benchtop engineering
tool, for learning about, evaluating, and characterizing Allegro
sensors, for programming/calibrating devices in small volumes,
and for developing code and procedures for use in production.
Note that this kit is not recommended for production purposes.
See the Allegro Sensor Evaluation Kit Technical Guide (ASEK-02)
available at http://www.allegromicro.com/en/Sample-And-Buy/
Demo-Boards/ASEK-02-Demo-Board.aspx for more details. Contact your local Allegro FAE regarding availability or purchase the
kit from Digi-Key (Part Number 620-1625-ND).
• In Try mode, programmable parameter values are set and
measured simultaneously. A parameter value is stored
temporarily, and is reset after cycling the supply voltage.
• In Blow mode, the value of a programmable parameter may
be permanently set by blowing solid-state fuses internal to the
device. Device-locking is also accomplished in this mode.
tACTIVE
• In Read mode, each bit may be verified as blown or not blown.
Supply Voltage, VCC
The programming sequence is designed to help prevent the device
from being programmed accidentally—for example, as a result of
noise on the supply line. Note that, for all programming modes, no
parameter programming registers are accessible after the devicelevel LOCK bit is set. The only function that remains accessible is
the overall Fuse Checking feature.
Although any programmable variable power supply can be used
to generate the pulse waveforms, for design evaluations, Allegro
highly recommends using the ASEK-02 Allegro Sensor IC Evaluation Kit. The ASEK-02 kit provides a graphical user interface
(GUI) for programming various Allegro field-programmable
Hall-effect devices. In addition, a low-voltage interface board
(ASEK-02-WB-T) is required—contact your local FAE regarding
availability.
tPr
VPH
tBLOW
tPf
VPM
VPL
(Supply
cycled)
tLOW
tLOW
GND
Programming
pulses
Blow
pulse
Figure 5: Programming Pulse Definitions (see Table 1)
Table 1: Programming Pulse Requirements, Protocol at TA = 25°C
Characteristics
Symbol
Notes
Min.
Typ.
Max.
Unit
4.5
5
5.5
V
12.5
–
14
V
21
–
27
V
VCC = 5 → 26 V, CBLOW = 0.1 µF (min); minimum supply current required to
ensure proper fuse blowing.
175
–
–
mA
VPL
Programming Voltage
VPM
Measured at the VCC pin
VPH
Programming Current
IPP
tLOW
Pulse Width
Duration of VPL separating pulses at VPM or VPH
20
–
–
µs
tACTIVE
Duration of pulses at VPM or VPH for key/code selection
20
–
–
µs
tBLOW
Duration of pulse at VPH for fuse blowing
90
100
–
µs
Pulse Rise Time
tPr
VPL to VPM or VPL to VPH
5
–
100
µs
Pulse Fall Time
tPf
VPM to VPL or VPH to VPL
5
–
100
µs
0.375
–
–
V/µs
Blow Pulse Slew Rate
SRBLOW
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Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
Code The number used to identify the combination of fuses
activated in a bit field, expressed as the decimal equivalent of the
binary value. The LSB of a bit field is denoted as code 1, or bit 0.
Addressing Increasing the bit field code of a selected register
by serially applying a pulse train through the VCC pin of the
device. Each parameter can be measured during the addressing
process, but the internal fuses must be blown before the programming code (and parameter value) becomes permanent.
Fuse Blowing Applying a high-voltage pulse of sufficient
duration to permanently set an addressed bit by blowing a fuse
internal to the device. Once a bit (fuse) has been blown, it cannot
be reset.
Blow Pulse A high-voltage pulse of sufficient duration to blow
the addressed fuse.
Cycling the Supply Powering-down, and then powering-up the
supply voltage. Cycling the supply is used to clear the programming settings in Try mode.
Programming Procedure
Programming involves selection of a register and mode, and then
setting values for parameters in the register for evaluation or fuse
blowing. Figure 10 provides an overview state diagram.
REGISTER SELECTION
Each programmable parameter can be accessed through a specific
register. To select a register, from the Initial state, a sequence of
voltage pulses consisting of one VPH pulse, one VPM pulse, and
then a unique combination of VPH and VPM pulses, is applied
serially to the VCC pin (with no VCC supply interruptions). This
MODE SELECTION
The same physical registers are used for all programming modes.
To distinguish Blow mode and Read mode, when selecting the
registers, an additional pulse sequence consisting of eleven VPM
pulses followed by one VPH pulse is added to the key. The combined register and mode keys are shown in Table 3.
TRY MODE
In Try mode, the bit field addressing is accomplished by applying a series of VPM pulses to the VCC pin of the device, as shown
in Figure 7. Each pulse increases the total bit field value of the
selected parameter, increasing by one on the falling edge of each
additional VPM pulse. When addressing a bit field in Try mode,
the number of VPM pulses is represented by a decimal number
called a code. Addressing activates the corresponding fuse locations in the given bit field by increasing the binary value of an
internal DAC, up to the maximum possible code. As the value
of the bit field code increases, the value of the programmable
parameter changes. Measurements can be taken after each VPM
pulse to determine if the desired result for the programmable
parameter has been reached. Cycling the supply voltage resets
all the locations in the bit field that have un-blown fuses to their
initial states. This should also be done before selection of a different register in Try mode.
When addressing a parameter in Try mode, the bit field address
(code) defaults to the value 1, on the falling edge of the final register selection key VPH pulse (see Figure 5). A complete example
is shown in Figure 8. Note that, in the four BOP selection virtual
registers, after the maximum code is entered, the next VPM pulse
wraps back to the beginning of the register, and selects code 0.
VPH
VPM
VPL
GND
Figure 6: Example of Try Mode Register Selection
Pulses, for the BOP Negative Trim, Up-Counting
Register.
VCC
VCC
VPH
VPM
Code 2n –1
Key A series of voltage pulses used to select a register or mode
Code 2n –2
Bit Field The internal fuses unique to each register, represented
as a binary number. Changing the bit field settings of a particular
register causes its programmable parameter to change, based on
the internal programming logic.
To simplify Try mode, the A1162 provides a set of virtual registers for each combination of: BOP selection (BOPSEL), BHYS
selection, and a facility for transiting BOP magnitude values in
an increasing or decreasing sequence. These registers also allow
wrapping back to the beginning of the register after transiting the
register.
Code 3
Register The section of the programming logic that controls the
choice of programmable modes and parameters.
sequence of pulses is called the key, and uniquely identifies each
register. An example register selection key is shown in Figure 6.
Code 2
Definition of Terms
Code 1
A1162
VPL
GND
Figure 7: Try Mode Bit Field Addressing Pulses.
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Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
Bit Field
Address Codes
Register (and Mode)
Selection Key
6
7
8
9
GND
Code 2
VPL
10 11
Code 12
5
Code 11
4
Code 10
3
Code 9
2
Code 8
1
Code 7
4
Code 6
3
Code 5
2
Code 4
1
Code 3
VPM
Code 1
VCC
VPH
Figure 8: Example of Try Mode Programming Pulses Applied to the VCC Pin
In this example, BOP Trim, Down-Counting register is addressed to code 12 by the eleven VPM pulses (code 1 is selected automatically at the
falling edge of the register-mode selection key).
The BOP selecting virtual register allows the programmer to
adjust the BOP parameter from low to high, or from high to low.
Figure 9 shows the relationship between the BOP parameter and
the different Try mode registers.
BLOW MODE
After the required code is determined for a given parameter, its
value can be set permanently by blowing individual fuses in the
appropriate register bit field. Blowing is accomplished by selecting the register and mode selection key, followed by the appropriate bit field address, and ending the sequence with a Blow
pulse. The Blow mode selection key is a sequence of eleven VPM
pulses followed by one VPH pulse. The Blow pulse consists of a
VPH pulse of sufficient duration (tBLOW ) to permanently set an
addressed bit by blowing a fuse internal to the device. The device
power must be cycled after each individual fuse is blown.
Due to power requirements, a 0.1 μF blowing capacitor (CBLOW )
must be mounted between the VCC pin and the GND pin during programming, to ensure enough current is available to blow
fuses. If programming in the application, CBYPASS (see Figure 1)
can serve the same purpose.
The fuse for each bit in the bit field must be blown individually.
The A1162 built-in circuitry allows only one fuse at a time to be
blown. During Blow mode, the bit field can be considered a “onehot” shift register. Table 2 illustrates how to relate the number of
VPM pulses to the binary and decimal value for Blow mode bit
field addressing. It should be noted that the simple relationship
between the number of VPM pulses and the required code is:
2n = Code,
where n is the number of VPM pulses, and the bit field has an initial state of decimal code 1 (binary 00000001). To correctly blow
the required fuses, the code representing the required parameter
value must be translated to a binary number. For example, as
shown in Figure 9, decimal code 5 is equivalent to the binary
number 101. Therefore bit 2 must be addressed and blown, the
device power supply cycled, and then bit 0 must be addressed
and blown. The order of blowing bits, however, is not important. Blowing bit 0 first, and then bit 2 is acceptable. A complete
example is shown in Figure 10.
Table 2: Blow Mode Bit Field Addressing
Quantity of
VPM Pulses
Binary
Register Bit Field
Decimal Equivalent
Code
0
0000 0001
1
1
0000 0010
2
2
0000 0100
4
3
0000 1000
8
4
0001 0000
16
5
0010 0000
32
6
0100 0000
64
Bit Field Selection
Address Code Format
(Decimal Equivalent)
Code 5
Code in Binary
(Binary)
1 0 1
Fuse Blowing
Target Bits
Bit 2
Fuse Blowing
Address Code Format
Bit 0
Code 4
Code 1
(Decimal Equivalents)
Figure 9: Example of Code 5 Broken into Its Binary
Components
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Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
Bit Field (Fuse)
Address Codes
Register (and Mode) Selection Key
2
3
4
5
VPL
GND
6
7
8
9
10 11
Blow
Pulse
1
2
3
Code 8 Bit 3
1
Bit 2
VPM
Bit 1
VCC
VPH
tLOW
A1162
Figure 10: Example of Blow Mode Programming Pulses Applied to the VCC Pin
In this example, the BOP Magnitude Selection register (BOPSEL) is addressed to code 8 (bit 3, or 3 VPM pulses) and its value is permanently
blown.
Note: After blowing, the programming is not reversible, even
after cycling the supply power. Although a register bit field fuse
cannot be reset after it is blown, additional bits within the same
register can be blown at any time until the device is locked. For
example, if bit 1 (binary 10) has been blown, it is still possible to
blow bit 0. The end result would be binary 11 (decimal code 3).
LOCKING THE DEVICE
After the required code for each parameter is programmed, the
device can be locked to prevent further programming of any
parameters. To do so, perform the following steps:
1.
2.
3.
4.
Ensure that the CBLOW capacitor is mounted.
Select the Output/Lock Bit register key.
Select Blow mode selection key.
Address bit 4 (10000) by sending four VPM pulses.
5. Send one Blow pulse, at IPP and SRBLOW, and sustain it for
tBLOW.
6. Delay for a tLOW interval, then power-down.
7. Optionally check all fuses.
FUSE CHECKING
Incorporated in the A1162 is circuitry to simultaneously check
the integrity of the fuse bits. The fuse-checking feature is enabled
by using the Fuse Checking registers, and while in Try mode,
applying the codes shown in Table 3. The register is only valid
in Try mode and is available before or after the programming
LOCK bit is set.
Selecting the Fuse Threshold High register checks that all blown
fuses are properly blown. Selecting the Fuse Threshold Low
register checks all un-blown fuses are properly intact. The supply
current (ICC ) increases by 250 μA if a marginal fuse is detected.
If all fuses are correctly blown or fully intact, there will be no
change in supply current.
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Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
Table 3: Programming Logic Table
Register Name
(Selection Key)
Bit Field Address (Code)
Binary
(MSB → LSB)
Notes
Decimal
Equivalent
TRY MODE REGISTER SELECTION: any VPM pulse after the register selection sequence will move the counter and change the selected
register code
BOP Trim Up-Counting
[2 × VPH]
000000 111111
0
63
Increases BOP. Code 1 automatically selected when register entered; wraps
back to code 0.
BOP Trim Down-Counting
[2 × VPH → 4 × VPM → VPH]
111111
000000
63
0
Decreases BOP. Code 63 automatically selected when register entered; wraps
back to code 0.
BOP Trim Up-Counting, Bit Wise
[2 × VPH → 9 × VPM → VPH]
000000
000001
000010
000100
001000
010000
100000
0
1
2
4
8
16
32
Bit 1 automatically selected when register entered.
BHYS Trim
[VPH → 3 × VPM → VPH]
00
11
0
3
Code 1 automatically selected when register entered.
Parity Bit
[VPH → VPM → VPH]
0
0
Code 1 automatically selected when register entered.
Fuse Threshold Low
[VPH → 3 × VPM → VPH → 7 × VPM]
Checks un-blown fuses.
Fuse Threshold High
[VPH → 3 × VPM → VPH → 8 × VPM]
Checks blown fuses.
BLOW MODE REGISTER SELECTION
BOP Selection
[2 × VPH → 11 × VPM → VPH → (n) ×
VPM → VPH_BLOW]
000000
111111
0
63
BOP magnitude selection.
Code 0 = BOP(min) (default – no fuse blowing required.)
Code 63 = BOP(max)
BHYS Selection
[VPH → 3 × VPM → VPH → 11 × VPM
→ VPH → (n) × VPM → VPH_BLOW]
00
11
0
3
BHYS magnitude selection.
Code 0 = BHYS(min) (default – no fuse blowing required)
Code 3 = BHYS(max)
Parity Bit
[VPH → VPM → VPH → 11 × VPM →
VPH → VPH_BLOW]
0
0
Blow decision is made automatically.
Lock Bit
[VPH → 3 × VPM → VPH → 11 × VPM
→ VPH → 4 × VPM → VPH_BLOW]
Locks access to BOP and BHYS selection registers.
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17
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
toring the state of the VOUT pin. A complete example is shown
in Figure 11.
ADDITIONAL GUIDELINES
The additional guidelines in this section should be followed to
ensure the proper behavior of these devices:
• The power supply used for programming must be capable of
delivering at least VPH and 175 mA.
Read mode uses the same register selection keys as Blow mode
(see Table 3), allowing direct addressing of the individual fuses
in the BOPSEL register (do not inadvertently send a Blow pulse
while in Read mode). After sending the register and mode selection keys, that is, after the falling edge of the final VPH pulse in
the key, the first bit (the LSB) is selected. Each additional VPM
pulse addresses the next bit in the selected register, up to the
MSB. Read mode is available only before the LOCK bit has been
set.
• Be careful to observe the tLOW delay time before powering
down the device after blowing each bit.
• Set the LOCK bit (only after all other parameters have
been programmed and validated) to prevent any further
programming of the device.
READ MODE
After the final VPH key pulse, and after each VPM address pulse,
if VOUT is low, the corresponding fuse can be considered blown.
If the output state is high, the fuse can be considered un-blown.
During Read mode VOUT must be pulled high using a pull-up
resistor (see RLOAD in the Typical Application Circuit diagram).
The A1162 features a Read mode that allows the status of each
programmable fuse to be read back individually. The status,
blown or not blown, of the addressed fuse is determined by moni-
Register (and Mode) Selection Key
Bit Field (Fuse) Address Codes
VPM
1
2
3
4
5
6
8
9
10 11
1
2
3
4
5
6
7
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 2 Un-Blown
Bit 3 Blown
Bit 4 Blown
Bit 5 Un-Blown
Bit 6 Blown
Bit 7 Un-Blown
Don’t Care
Bit 1
VPM
Bit 0
VPH
Bit 1 Un-Blown
VPL
GND
VOUT
7
Bit 0 Blown
VCC
VPH
VPL
Fuse intact
Fuse blown
GND
Read-out on VOUT pin
Figure 11: Read Mode Example
Pulse sequence for accessing the BOP Selection register (BOPSEL) and reading back the status of each of the eight bit fields. In this example,
the code (blown fuses) is 20 + 23 + 24 + 26 = 89 (0101 1001). After each address pulse is sent, the voltage on the VOUT pin will be at GND for
blown fuses and at VCC (at VPL or VPM) for un-blown fuses.
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Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
BOP SELECTION
The A1162 allows accurate trimming of the magnetic operate
point (BOP ) within the application. This programmable feature
reduces effects due to mechanical placement tolerances and
improves performance when used in proximity or vane sensing
applications.
BOP can be set to any value within the range allowed by the
BOPSEL registers. However, switching is recommended only
within the Programmable BOP Range, specified in the Operating
Characteristics table.
stage, BOP is adjusted temporarily using the Try mode programming features, to find the fuse value that corresponds to the
optimum BOP . After a value is determined, then it can be permanently set using the Blow mode features.
As an aid to programming, the A1162 has two options available
in Try Mode for adjusting the BOP parameter. As shown in Figure
12, this allows the BOP parameter to either trim-up (i.e., start at
the BOP minimum value and increase to the maximum value) or
trim-down (i.e., start at the BOP maximum value and decrease to
the minimum value).
B+ (south)
BOP(max)
BOP Setpoint
0
BOP(min)
0
255
Try Mode, Bit Field Code
(A) BOP, Trim Up-Counting Register
Magnetic Field Intensity, B (G)
Magnetic Field Intensity, B (G)
Trimming of BOP is typically done in two stages. In the first
B+ (south)
BOP(max)
BOP Setpoint
0
BOP(min)
0
255
Try Mode, Bit Field Code
(B) BOP, Trim Down-Counting Register
Figure 12: BOP Profiles for Each of the BOP Selection Virtual Registers Available in Try Mode.
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Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for switch
point accuracy is the small signal voltage developed across the
Hall element. This voltage is disproportionally small relative to
the offset that can be produced at the output of the Hall sensor IC.
This makes it difficult to process the signal while maintaining an
accurate, reliable output over the specified operating temperature
and voltage ranges. Chopper stabilization is a proven approach
used to minimize Hall offset on the chip.
The patented Allegro technique, namely Dynamic Quadrature
Offset Cancellation, removes key sources of the output drift
induced by thermal and mechanical stresses. This offset reduction
technique is based on a signal modulation-demodulation process.
The undesired offset signal is separated from the magnetic fieldinduced signal in the frequency domain through modulation.
twice the chopper frequency. This high-frequency operation
allows a greater sampling rate, which results in higher accuracy
and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses,
and produces devices that have extremely stable quiescent Hall
output voltages and precise recoverability after temperature
cycling. This technique is made possible through the use of a
BiCMOS process, which allows the use of low-offset, low-noise
amplifiers in combination with high-density logic integration and
sample-and-hold circuits.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field-induced signal to recover
its original spectrum at baseband, while the DC offset becomes a
high-frequency signal. The magnetic signal then can pass through
a low-pass filter, while the modulated DC offset is suppressed.
The chopper stabilization technique uses a high frequency clock,
generally at hundreds of kilohertz. A sample-and-hold technique
is used for demodulation, where the sampling is performed at
Regulator
Clock/Logic
Hall
Element
Low-Pass
Filter
Amp.
Sample and Hold
Figure 13: Model of Chopper Stabilization Circuit
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Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
POWER DERATING
The device must be operated below the maximum junction temperature of the device (TJ(max)). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems website.)
The Package Thermal Resistance (RθJA) is a figure of merit summarizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity
(K) of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case (RθJC) is
a relatively small component of RθJA. Ambient air temperature
(TA) and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × IIN
(1)
ΔT = PD × RθJA
(2)
TJ = TA + ΔT
(3)
For example, given common conditions such as: TA= 25°C,
VIN = 12 V, IIN = 5 mA, and RθJA = 145°C/W, then:
A worst-case estimate, PD(max), represents the maximum allowable power level, without exceeding TJ(max), at a selected RθJA
and TA.
Example: Reliability for VCC at TA = 150°C, package LE, using a
4-layer PCB.
Observe the worst-case ratings for the device, specifically:
RθJA = 145°C/W, TJ(max) = 165°C, VCC(max) = 24 V, and
ICC(max) = 5 mA.
Calculate the maximum allowable power level (PD(max)). First,
invert equation 3:
ΔTmax = TJ(max) – TA = 165°C – 150°C = 15°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 145°C/W = 103 mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max) = 103 mW ÷ 5 mA = 20.6 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤ VCC(est).
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced
RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and
VCC(max) is reliable under these conditions.
PD = VIN × IIN = 12 V × 5 mA = 60 mW
ΔT = PD × RθJA = 60 mW × 145°C/W = 8.7°C
TJ = TA + ΔT = 25°C + 8.7°C = 33.7°C
For 5 V ±5% systems, in diagnostic mode: RθJA = 145°C/W,
TJ(max) = 165ºC, VCC = 5.25 V, and ICC(DIAG)max = 25 mA.
Calculate the maximum allowable power level with equation 1:
PD(max) = VCC × ICC(DIAG)max = 5.25 V × 25 mA = 131.25 mW
Then determine the allowable increase to temperature with equation 2:
ΔTmax = PD(max) × RθJA = 131.25 mW × 145°C/W = 19°C
Finally, inverting equation 3 results in the maximum ambient
temperature:
TA(max) = TJ(max) + ΔTmax = 165°C + 19°C = 146°C
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21
Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference MO-153 AA)
Dimensions in millimeters - NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
3.00 ±0.10
D
0.11
8º
0º
E
8
8
1.70
0.02
0.09
6.40 BSC
4.40 ±0.10
6.40 BSC
+0.15
0.60
-0.10
A
D
1.00 REF
1
2
1
Branded Face
0.25 BSC
C
8X
1.10 MAX
0.10 C
0.15
0.05
0.30
0.19
B
2
PCB Layout Reference View
SEATING PLANE
GAUGE PLANE
SEATING
PLANE
0.65 BSC
A
Terminal #1 mark area
B
Reference land pattern layout (reference IPC7351 SOP65P640X110-8M);
all pads minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias can improve thermal dissipation
(reference EIA/JEDEC Standard JESD51-5)
NNN
YYWW
C
Branding scale and appearance at supplier discretion
D
Hall element, not to scale
E
Active Area Depth = 0.36 mm REF
1
C
Standard Branding Reference View
N = Last 3 digits of device part number
= Supplier emblem
Y = Last two digits of year of manufacture
W = Week of manufacture
Figure 14: Package LE, 8-Pin eTSSOP
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Programmable Precision Hall-Effect
Switch with Advanced Diagnostics
A1162
Revision History
Revision
Revision Date
–
January 27, 2016
Description of Revision
Initial Release
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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23