AD AD9520-4BCPZ-REEL7 12 lvpecl/24 cmos output clock generator with integrated 1.6 ghz vco Datasheet

12 LVPECL/24 CMOS Output Clock
Generator with Integrated 1.6 GHz VCO
AD9520-4
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9520-41 provides a multioutput clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 1.4 GHz to
1.8 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz
can also be used.
1
FUNCTIONAL BLOCK DIAGRAM
CP
REF1
REFIN
REFIN
CLK
REF2
LF
STATUS
MONITOR
PLL
OPTIONAL
SWITCHOVER
AND MONITOR
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 1.4 GHz to 1.8 GHz
Supports external 0 V to 5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVDS, or LVPECL references to 250 MHz
Accepts 16.67 MHz to 33.3 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Auto and manual reference switchover/holdover modes,
with selectable revertive/nonrevertive switching
Glitch-free switchover between references
Automatic recover from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Twelve 1.6 GHz LVPECL outputs divided into 4 groups
Each group of 4 has a 1-to-32 divider with phase delay
Additive output jitter as low as 225 fS rms
Channel-to-channel skew grouped outputs <16 ps
Each LVPECL output can be configured as two CMOS
outputs (for fOUT ≤ 250 MHz)
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs as needed
SPI- and I²C-compatible serial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration settings
DIVIDER
AND MUXs
VCO
ZERO
DELAY
LVPECL/
CMOS
DIV/Φ
OUT0
OUT1
OUT2
DIV/Φ
OUT3
OUT4
OUT5
DIV/Φ
OUT6
OUT7
OUT8
DIV/Φ
OUT9
OUT10
OUT11
SPI/I2C CONTROL
PORT AND
DIGITAL LOGIC
EEPROM
AD9520
07217-001
FEATURES
Figure 1.
The AD9520 serial interface supports both SPI and I2C® ports.
An in-package EEPROM can be programmed through the serial
interface and store user-defined register setting for power-up
and chip reset.
The AD9520 features 12 LVPECL outputs in four groups. Any
of the 1.6 GHz LVPECL outputs can be reconfigured as two
250 MHz CMOS outputs.
Each group of outputs has a divider that allows both the divide
ratio (from 1 to 32) and phase (coarse delay) to be set.
The AD9520 is available in a 64-lead LFCSP and can be operated
from a single 3.3 V supply. The external VCO can have an
operating voltage up to 5.5 V. A separate output driver power
supply can be from 2.375 V to 3.465 V.
The AD9520 is specified for operation over the standard industrial
range of −40°C to +85°C.
The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-4 is used, it is referring to that specific
member of the AD9520 family.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD9520-4
TABLE OF CONTENTS
Features .............................................................................................. 1
Mode 1: Clock Distribution or External
VCO <1600 MHz ................................................................... 30
Applications ....................................................................................... 1
Mode 2: High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz .................................................. 32
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Phase-Locked Loop (PLL) .................................................... 34
Revision History ............................................................................... 3
Configuration of the PLL ...................................................... 34
Specifications..................................................................................... 4
Phase Frequency Detector (PFD) ........................................ 34
Power Supply Requirements ....................................................... 4
Charge Pump (CP)................................................................. 35
PLL Characteristics ...................................................................... 4
On-Chip VCO ........................................................................ 35
Clock Inputs .................................................................................. 7
PLL External Loop Filter ....................................................... 35
Clock Outputs ............................................................................... 7
PLL Reference Inputs ............................................................. 35
Timing Characteristics ................................................................ 8
Reference Switchover ............................................................. 36
Timing Diagrams ..................................................................... 9
Reference Divider R ............................................................... 36
Clock Output Additive Phase Noise (Distribution Only; VCO
Divider Not Used) ...................................................................... 10
VCXO/VCO Feedback Divider N: P, A, B, R ..................... 36
Clock Output Absolute Phase Noise (Internal VCO Used) .. 11
Digital Lock Detect (DLD) ................................................... 38
Clock Output Absolute Time Jitter (Clock Generation Using
Internal VCO) ............................................................................. 11
Analog Lock Detect (ALD) ................................................... 38
Clock Output Absolute Time Jitter (Clock Cleanup Using
Internal VCO) ............................................................................. 11
External VCXO/VCO Clock Input (CLK/CLK) ................ 39
Current Source Digital Lock Detect (CSDLD) .................. 38
Holdover .................................................................................. 39
Clock Output Absolute Time Jitter (Clock Generation Using
External VCXO) ......................................................................... 12
Manual Holdover Mode ........................................................ 39
Clock Output Additive Time Jitter (VCO Divider Not Used)
....................................................................................................... 12
Frequency Status Monitors ................................................... 41
Automatic/Internal Holdover Mode.................................... 39
Clock Output Additive Time Jitter (VCO Divider Used) ..... 13
VCO Calibration .................................................................... 42
Serial Control Port—SPI Mode ................................................ 13
Zero Delay Operation ................................................................ 43
Serial Control Port—I2C Mode ................................................ 14
Internal Zero Delay Mode..................................................... 43
PD, SYNC, and RESET Pins ..................................................... 15
External Zero Delay Mode .................................................... 43
Serial Port Setup Pins: SP1, SP0 ............................................... 15
Clock Distribution ..................................................................... 44
LD, STATUS, REFMON Pins.................................................... 15
Operation Modes ................................................................... 44
Power Dissipation ....................................................................... 16
CLK or VCO Direct-to-LVPECL Outputs.......................... 44
Absolute Maximum Ratings.......................................................... 17
Clock Frequency Division..................................................... 45
Thermal Resistance .................................................................... 17
VCO Divider ........................................................................... 45
ESD Caution ................................................................................ 17
Channel Dividers ................................................................... 45
Pin Configuration and Function Descriptions ........................... 18
Synchronizing the Outputs—SYNC Function ................... 47
Typical Performance Characteristics ........................................... 21
LVPECL Output Drivers ....................................................... 48
Terminology .................................................................................... 26
CMOS Output Drivers .......................................................... 49
Detailed Block Diagram ................................................................ 27
Reset Modes ................................................................................ 49
Theory of Operation ...................................................................... 28
Power-On Reset ...................................................................... 49
Operational Configurations ...................................................... 28
Hardware Reset via the RESET Pin ..................................... 49
Mode 0: Internal VCO and Clock Distribution ................. 28
Soft Reset via the Serial Port ................................................. 49
Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via
the Serial Port ......................................................................... 49
Rev. 0 | Page 2 of 84
AD9520-4
Power-Down Modes ...................................................................49
EEPROM Operations ..................................................................... 58
Chip Power-Down via PD .....................................................49
Writing to the EEPROM ............................................................ 58
PLL Power-Down ....................................................................50
Reading from the EEPROM ...................................................... 58
Distribution Power-Down .....................................................50
Programming the EEPROM Buffer Segment.......................... 59
Individual Clock Output Power-Down................................50
Register Section Definition Group ....................................... 59
Individual Clock Channel Power-Down .............................50
IO_UPDATE (Operational Code 0x80) .............................. 59
Serial Control Port ..........................................................................51
End-of-Data (Operational Code 0xFF) ............................... 59
SPI/I2C Port Selection ................................................................51
Pseudo-End-of-Data (Operational Code 0xFE) ................. 59
I2C Serial Port Operation ...........................................................51
Thermal Performance..................................................................... 61
I C Bus Characteristics ...........................................................51
Register Map .................................................................................... 62
Data Transfer Process .............................................................52
Register Map Descriptions ............................................................. 67
Data Transfer Format .............................................................53
Applications Information ............................................................... 82
I2C Serial Port Timing ............................................................53
Frequency Planning Using the AD9520 .................................. 82
SPI Serial Port Operation ...........................................................54
Using the AD9520 Outputs for ADC Clock Applications .... 82
Pin Descriptions ......................................................................54
LVPECL Clock Distribution ...................................................... 82
SPI Mode Operation ...............................................................54
CMOS Clock Distribution ......................................................... 83
Communication Cycle—Instruction Plus Data ..................54
Outline Dimensions ........................................................................ 84
Write .........................................................................................54
Ordering Guide ........................................................................... 84
2
Read ..........................................................................................54
SPI Instruction Word (16 Bits) ..................................................55
SPI MSB/LSB First Transfers .....................................................55
REVISION HISTORY
9/08—Revision 0: Initial Version
Rev. 0 | Page 3 of 84
AD9520-4
SPECIFICATIONS
Typical (typ) is given for VS = VS_DRV = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise
noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
VS
VS_DRV
VCP
RSET Pin Resistor
CPRSET Pin Resistor
Min
3.135
2.375
VS
BYPASS Pin Capacitor
Typ
3.3
Max
3.465
VS
5.25
4.12
5.1
Unit
V
V
V
kΩ
kΩ
220
nF
Test Conditions/Comments
3.3 V ± 5%
This is nominally 2.5 V to 3.3 V ± 5%
This is nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA); actual
current can be calculated by: CP_lsb = 3.06/CPRSET; connect to ground
Bypass for internal LDO regulator; necessary for LDO stability; connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
Frequency Range
VCO Gain (KVCO)
Tuning Voltage (VT)
Min
1400
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled)
with DC Offset Off
Input Frequency (AC-Coupled)
with DC Offset On
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled
with DC Offset Off )
Input Sensitivity (AC-Coupled
with DC Offset On)
Input Logic High, DC Offset Off
Input Logic Low, DC Offset Off
Input Current
Input Capacitance
Max
Unit
Test Conditions/Comments
1800
MHz
MHz/V
V
See Figure 13
See Figure 8
VCP ≤ VS when using internal VCO
MHz/V
dBc/Hz
dBc/Hz
dBc/Hz
f = 1625 MHz
f = 1625 MHz
f = 1625 MHz
35
0.5
Frequency Pushing (Open-Loop)
Phase Noise @ 1 kHz Offset
Phase Noise @ 100 kHz Offset
Phase Noise @ 1 MHz Offset
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Typ
VCP −
0.5
1
−58
−111
−130
0
Differential mode (can accommodate single-ended
input by ac grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled;
be careful to match VCM (self-bias voltage)
250
MHz
1.75
1.60
5.9
6.4
mV p-p
V
V
kΩ
kΩ
250
MHz
250
MHz
0
0.55
250
3.28
MHz
V p-p
Slew rate must be > 50 V/μs, and input amplitude
sensitivity specification must be met; see input sensitivity
Slew rate > 50 V/μs; CMOS levels
VIH should not exceed VS
1.5
2.78
V p-p
VIH should not exceed VS
0.8
+100
V
V
μA
pF
Each pin, REFIN (REF1)/REFIN (REF2)
1.34
1.30
4.0
4.4
280
1.60
1.50
4.8
5.3
10
2.0
−100
2
Rev. 0 | Page 4 of 84
Self-bias voltage of REFIN 1
Self-bias voltage of REFIN1
Self-biased1
Self-biased1
Two single-ended CMOS-compatible inputs
Slew rate must be > 50 V/μs
AD9520-4
Parameter
Crystal Oscillator
Crystal Resonator Frequency Range
Maximum Crystal Motional Resistance
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Max
Unit
33.33
30
MHz
Ω
100
45
50
1.3
2.9
6.0
MHz
MHz
MHz
ns
ns
ns
CHARGE PUMP (CP)
ICP Sink/Source
High Value
4.8
mA
Low Value
0.60
mA
Reference Input Clock Doubler Frequency
Antibacklash Pulse Width
Absolute Accuracy
CPRSET Range
ICP High Impedance Mode Leakage
Sink-and-Source Current Matching
ICP vs. VCP
ICP vs. Temperature
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
PLL N DIVIDER DELAY
000
001
010
011
100
101
110
111
PLL R DIVIDER DELAY
000
001
010
011
100
101
110
111
Min
Typ
16.67
0.004
2.5
1
1
%
kΩ
nA
%
1.5
2
%
%
2.7
10
300
600
900
600
1000
2400
3000
3000
300
Off
410
530
650
770
890
1010
1130
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Test Conditions/Comments
Antibacklash pulse width = 1.3 ns, 2.9 ns
Antibacklash pulse width = 6.0 ns
Antibacklash pulse width = 1.3 ns, 2.9 ns
0x017[1:0] = 01b
0x017[1:0] = 00b; 0x017[1:0] = 11b
0x017[1:0] = 10b
Programmable
With CPRSET = 5.1 kΩ; higher ICP is possible by
changing CPRSET
With CPRSET = 5.1 kΩ; lower ICP is possible by
changing CPRSET
Charge pump voltage set to VCP/2
0.5 < VCP < VCP − 0.5 V; VCP is the voltage on the CP (charge
pump) pin; VCP is the voltage on the VCP power supply pin
0.5 < VCP < VCP − 0.5 V
VCP = VCP/2 V
A, B counter input frequency (prescaler input
frequency divided by P)
Register 0x019[2:0]; see Table 53
ps
ps
ps
ps
ps
ps
ps
Register 0x019[5:3]; see Table 53
Off
370
490
610
730
850
970
1090
ps
ps
ps
ps
ps
ps
ps
Rev. 0 | Page 5 of 84
AD9520-4
Parameter
PHASE OFFSET IN ZERO DELAY
Phase Offset (REF-to-LVPECL Clock Output
Pins) in Internal Zero Delay Mode
Phase Offset (REF-to-LVPECL Clock Output
Pins) in Internal Zero Delay Mode
Phase Offset (REF-to-CLK Input Pins) in
External Zero Delay Mode
Phase Offset (REF-to-CLK Input Pins) in
External Zero Delay Mode
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge Pump/
Phase Frequency Detector (In-Band
Means Within the LBW of the PLL)
@ 500 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
Min
Typ
Max
Unit
560
1060
1310
ps
Test Conditions/Comments
REF refers to REFIN (REF1)/REFIN (REF2)
When N delay and R delay are bypassed
−320
+50
+240
ps
When N delay = Setting 110 and R delay is bypassed
140
630
870
ps
When N delay and R delay are bypassed
−460
−20
+200
ps
When N delay = Setting 011 and R delay is bypassed
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output of
the VCO and subtracting 20 log(N) (where N is the value
of the N divider)
−165
−162
−152
−144
−222
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
3.5
7.5
3.5
ns
ns
ns
7
15
11
ns
ns
ns
PLL DIGITAL LOCK DETECT WINDOW 2
Lock Threshold (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Unlock Threshold (Hysteresis)2
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
1
2
Reference slew rate > 0.5 V/ns; FOM + 10 log(fPFD) is an
approximation of the PFD/CP in-band phase noise (in
the flat region) inside the PLL loop bandwidth; when
running closed-loop, the phase noise, as observed at
the VCO output, is increased by 20 log(N); PLL figure of
merit decreases with decreasing slew rate; see Figure 12
Signal available at LD, STATUS, and REFMON pins when
selected by appropriate register settings; lock detect
window settings can be varied by changing the
CPRSET resistor
Selected by 0x017[1:0] and 0x018[4]
(this is the threshold to go from unlock to lock)
0x017[1:0] = 00b, 01b,11b; 0x018[4] = 1b
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
0x017[1:0] = 10b; 0x018[4] = 0b
This is the threshold to go from lock to unlock
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
0x017[1:0] = 10b; 0x018[4] = 0b
The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. 0 | Page 6 of 84
AD9520-4
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
Input Frequency
Min
Typ
01
01
Input Sensitivity, Differential
Unit
2.4
1.6
GHz
GHz
150
Input Level, Differential
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
1
Max
1.3
1.3
3.9
1.57
150
4.7
2
mV p-p
2
V p-p
1.8
1.8
V
V
mV p-p
kΩ
pF
5.7
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed); this is the
frequency range supported by the channel divider
Measured at 2.4 GHz; jitter performance is improved with
slew rates > 1 V/ns
Larger voltage swings can turn on the protection diodes
and can degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2, OUT3, OUT4,
OUT5, OUT6, OUT7, OUT8,
OUT9, OUT10, OUT11
Output Frequency, Maximum
Output High Voltage, VOH
Output Low Voltage, VOL
Output Differential Voltage, VOD
CMOS CLOCK OUTPUTS
OUT0A, OUT0B, OUT1A, OUT1B,
OUT2A, OUT2B, OUT3A, OUT3B,
OUT4A, OUT4B, OUT5A, OUT5B,
OUT6A, OUT6B, OUT7A, OUT7B,
OUT8A, OUT8B, OUT9A, OUT9B,
OUT10A, OUT10B, OUT11A,
OUT11B
Output Frequency
Output Voltage High, VOH
Output Voltage Low, VOL
Output Voltage High, VOH
Output Voltage Low, VOL
Output Voltage High, VOH
Output Voltage Low, VOL
Min
Typ
Max
2400
VS_DRV −
1.07
VS_DRV −
1.95
660
VS_DRV −
0.96
VS_DRV −
1.79
820
VS_DRV −
0.84
VS_DRV −
1.64
950
Unit
Test Conditions/Comments
Termination = 50 Ω to VS_DRV − 2 V
Differential (OUT, OUT)
MHz
Using direct to output; see Figure 21 (higher
frequencies are possible, but amplitude will not
meet the VOD specification); the maximum
output frequency is limited by either the
maximum VCO frequency or the frequency at
the CLK inputs, depending on the AD9520
configuration
V
V
mV
Single-ended; termination = 10 pF
250
VS − 0.1
0.1
2.7
0.5
1.8
0.6
Rev. 0 | Page 7 of 84
MHz
V
V
V
V
V
V
See Figure 22
@ 1 mA load, VS_DRV = 3.3 V/2.5 V
@ 1 mA load, VS_DRV = 3.3 V/2.5 V
@ 10 mA load, VS_DRV = 3.3 V
@ 10 mA load, VS_DRV = 3.3 V
@ 10 mA load, VS_DRV = 2.5 V
@ 10 mA load, VS_DRV = 2.5 V
AD9520-4
TIMING CHARACTERISTICS
Table 5.
Parameter
LVPECL OUTPUT RISE/FALL TIMES
Output Rise Time, tRP
Min
Output Fall Time, tFP
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT
For All Divide Values
850
800
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS 1
LVPECL Outputs That Share the Same Divider
LVPECL Outputs on Different Dividers
All LVPECL Outputs Across Multiple Parts
CMOS OUTPUT RISE/FALL TIMES
Output Rise Time, tRC
Output Fall Time, tFC
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT
For All Divide Values
2.1
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS1
CMOS Outputs That Share the Same Divider
All CMOS Outputs on Different Dividers
Typ
Max
Unit
130
170
ps
130
170
ps
1050
970
1.0
1280
1180
ps
ps
ps/°C
5
5
5
5
16
20
45
60
190
ps
ps
ps
ps
ps
750
715
965
890
960
890
1280
1100
ps
ps
ps
ps
2.75
3.35
2
3.55
ns
ns
ps/°C
7
10
10
10
85
105
240
285
600
620
ps
ps
ps
ps
ps
ps
1.76
1.78
2.48
2.50
ns
ns
All CMOS Outputs Across Multiple Parts
OUTPUT SKEW, LVPECL-TO-CMOS OUTPUT1
Output(s) That Share the Same Divider
Output(s) That Are on Different Dividers
1
1.18
1.20
Test Conditions/Comments
Termination = 50 Ω to VS_DRV − 2 V
20% to 80%, measured differentially (rise/fall
time are independent of VS and are valid for
VS_DRV = 3.3 V and 2.5 V)
80% to 20%, measured differentially (rise/fall
time are independent of VS and are valid for
VS_DRV = 3.3 V and 2.5 V)
High frequency clock distribution configuration
Clock distribution configuration
Termination = open
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V and 2.5 V
Termination = open
20% to 80%; CLOAD = 10 pF; VS_DRV = 3.3 V
80% to 20%; CLOAD = 10 pF; VS_DRV = 3.3 V
20% to 80%; CLOAD = 10 pF; VS_DRV = 2.5 V
80% to 20%; CLOAD = 10 pF; VS_DRV = 2.5 V
Clock distribution configuration
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V and 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
All settings identical; different logic type
LVPECL to CMOS on same part
LVPECL to CMOS on same part
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
Rev. 0 | Page 8 of 84
AD9520-4
Timing Diagrams
tCLK
SINGLE-ENDED
CLK
80%
CMOS
10pF LOAD
tCMOS
Figure 4. CMOS Timing, Single-Ended, 10 pF Load
Figure 2. CLK/CLK to Clock Output Timing, Div = 1
DIFFERENTIAL
80%
LVPECL
tFP
07217-061
20%
tRP
tFC
07217-060
tRC
Figure 3. LVPECL Timing, Differential
Rev. 0 | Page 9 of 84
07217-063
20%
tPECL
AD9520-4
CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)
Table 6.
Parameter
CLK-TO-LVPECL ADDITIVE PHASE NOISE
CLK = 1 GHz, OUTPUT = 1 GHz
Divider = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 100 MHz Offset
CLK = 1 GHz, OUTPUT = 200 MHz
Divider = 5
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK-TO-CMOS ADDITIVE PHASE NOISE
CLK = 1 GHz, OUTPUT = 250 MHz
Divider = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK = 1 GHz, OUTPUT = 50 MHz
Divider = 20
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
Min
Typ
−107
−117
−127
−135
−142
−145
−147
−150
Max
Unit
Test Conditions/Comments
Distribution section only; does not include PLL
and VCO
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
−122
−132
−143
−150
−156
−157
−157
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Distribution section only; does not include PLL
and VCO
Input slew rate > 1 V/ns
−107
−119
−125
−134
−144
−148
−154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
−126
−133
−140
−148
−157
−160
−163
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. 0 | Page 10 of 84
AD9520-4
CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter
LVPECL ABSOLUTE PHASE NOISE
Min
Typ
VCO = 1.8 GHz; OUTPUT = 1.8 GHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
VCO = 1.625 GHz; OUTPUT = 1.625 GHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
VCO = 1.45 GHz; OUTPUT = 1.45 GHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
Max
Unit
Test Conditions/Comments
Internal VCO; direct-to-LVPECL output and for
loop bandwidths < 1 kHz
−54
−84
−108
−128
−143
−148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−58
−87
−111
−130
−144
−148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−62
−91
−115
−133
−143
−148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
Min
VCO = 1.475 GHz; LVPECL = 245.76 MHz; PLL LBW = 39 kHz
Typ
Max
109
269
114
263
146
291
VCO = 1.475 GHz; LVPECL = 122.88 MHz; PLL LBW = 39 kHz
VCO = 1.475 GHz; LVPECL = 61.44 MHz; PLL LBW = 39 kHz
Unit
fS rms
fS rms
fS rms
fS rms
fS rms
fS rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
clean, so a wider PLL loop bandwidth is
used; reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
Min
VCO = 1.555 GHz; LVPECL = 155.52 MHz; PLL LBW = 1.8 kHz
VCO = 1.474 GHz; LVPECL = 122.88 MHz; PLL LBW = 1.9 kHz
Typ
440
360
Rev. 0 | Page 11 of 84
Max
Unit
fS rms
fS rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
jittery, so a narrower PLL loop bandwidth
is used; reference = 10.0 MHz; R = 20
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
AD9520-4
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
Min
Typ
Max
54
77
109
79
114
163
124
176
259
Unit
fS rms
fS rms
fS rms
fS rms
fS rms
fS rms
fS rms
fS rms
fS rms
Test Conditions/Comments
Application example based on a typical setup using an
external 245.76 MHz VCXO (Toyocom TCO-2112);
reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz
Any LVPECL Output = 622.08 MHz
Divide Ratio = 1
CLK = 622.08 MHz
Any LVPECL Output = 155.52 MHz
Divide Ratio = 4
CLK = 1000 MHz
Any LVPECL Output = 100 MHz
Divide Ratio = 10
CLK = 500 MHz
Any LVPECL Output = 100 MHz
Divide Ratio = 5
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 200 MHz
Any CMOS Output Pair = 100 MHz
Divide Ratio = 2
Min
Typ
Max
46
fs rms
Test Conditions/Comments
Distribution section only; does not include
PLL and VCO; measured at rising edge of
clock signal
BW = 12 kHz − 20 MHz
64
fs rms
BW = 12 kHz − 20 MHz
223
fs rms
Calculated from SNR of ADC method
Broadband jitter
209
fs rms
Calculated from SNR of ADC method
Broadband jitter
325
Rev. 0 | Page 12 of 84
Unit
fs rms
Distribution section only; does not include
PLL and VCO
Calculated from SNR of ADC method
Broadband jitter
AD9520-4
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
Min
Typ
Max
Unit
CLK = 1.0 GHz; VCO DIV = 5; LVPECL = 100 MHz;
Divider = 2; Duty-Cycle Correction = Off
CLK = 500 MHz; VCO DIV = 5; LVPECL = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = On
CMOS OUTPUT ADDITIVE TIME JITTER
230
fS rms
215
fS rms
CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = Off
CLK = 1600 MHz; VCO DIV = 2; CMOS = 100 MHz;
Divider = 8; Duty-Cycle Correction = Off
326
fS rms
362
fS rms
Test Conditions/Comments
Distribution section only; does not include PLL and
VCO; uses rising edge of clock signal
Calculated from SNR of ADC method (broadband
jitter)
Calculated from SNR of ADC method (broadband
jitter)
Distribution section only; does not include PLL and
VCO; uses rising edge of clock signal
Calculated from SNR of ADC method (broadband
jitter)
Calculated from SNR of ADC method (broadband
jitter)
SERIAL CONTROL PORT—SPI MODE
Table 13.
Parameter
CS (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Min
Max
Unit
0.8
3
−110
V
V
μA
μA
2
pF
2.0
Input Capacitance
SCLK (INPUT) IN SPI MODE
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO (WHEN AN INPUT IN BIDIRECTIONAL MODE)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup and Hold, tS, tC
CS Minimum Pulse Width High, tPWH
Typ
Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
The minus sign indicates that current is flowing out of
the AD9520, which is due to the internal pull-up resistor
SCLK has an internal 30 kΩ pull-down resistor in
SPI mode, but not in I2C mode
2.0
2
V
V
μA
μA
pF
1
1
2
V
V
μA
μA
pF
0.8
110
1
2.0
0.8
2.7
0.4
25
16
16
4
0
11
2
3
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
Rev. 0 | Page 13 of 84
AD9520-4
SERIAL CONTROL PORT—I²C MODE
Table 14.
Parameter
SDA, SCL (WHEN INPUTS)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Current with an Input Voltage Between
0.1 VS and 0.9 VS
Hysteresis of Schmitt Trigger Inputs
Pulse width of Spikes That Must Be Suppressed by the
Input Filter, tSP
SDA (WHEN OUTPUTTING DATA)
Output Logic 0 Voltage at 3 mA Sink Current
Output Fall Time from VIHMIN to VILMAX with a Bus
Capacitance from 10 pF to 400 pF
Min
Typ
Max
Unit
0.3 × VS
+10
V
V
μA
50
ns
0.4
250
V
ns
0.7 × VS
−10
0.015 × VS
20 + 0.1 Cb (Cb =
capacitance of
one bus line in pF)
Note that all I2C timing values
referred to VIHMIN (0.3 × VS) and
VILMAX levels (0.7 × VS)
TIMING
Clock Rate (SCL, fI2C)
Bus Free Time Between a Stop and Start Condition, tIDLE
Setup Time for a Repeated Start Condition, tSET; STR
Hold Time (Repeated) Start Condition (After This Period,
the First Clock Pulse Is Generated, tHLD; STR)
Setup Time for Stop Condition, tSET; STP
Low Period of the SCL Clock, tLOW
High Period of the SCL Clock, tHIGH
SCL, SDA Rise Time, tRISE
SCL, SDA Fall Time, tFALL
Data Setup Time, tSET; DAT
1.3
0.6
0.6
400
kHz
μs
μs
μs
0.6
1.3
0.6
20 + 0.1 Cb
20 + 0.1 Cb
120
μs
μs
μs
ns
ns
ns
Data Hold Time, tHLD; DAT
140
Capacitive Load for Each Bus Line, Cb
1
Test Conditions/Comments
300
300
880
ns
400
pF
This is a minor deviation from
the original I²C specification of
100 ns minimum
This is a minor deviation from
the original I²C specification of
0 ns minimum 1
According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL
falling edge.
Rev. 0 | Page 14 of 84
AD9520-4
PD, SYNC, AND RESET PINS
Table 15.
Parameter
INPUT CHARACTERISTICS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Min
Typ
Max
Unit
0.8
1
−110
V
V
μA
μA
2
pF
2.0
Capacitance
RESET TIMING
Pulse Width Low
RESET Inactive to Start of Register Programming
50
100
ns
ns
SYNC TIMING
Pulse Width Low
1.3
ns
Test Conditions/Comments
These pins each have a 30 kΩ internal pull-up resistor
The minus sign indicates that current is flowing out of
the AD9520, which is due to the internal pull-up resistor
High speed clock is CLK input signal
SERIAL PORT SETUP PINS: SP1, SP0
Table 16.
Parameter
SP1, SP0
Logic Level 0
Logic Level ½
Min
0.4 × VS
Logic Level 1
0.8 × VS
Typ
Max
Unit
0.25 × VS
0.65 × VS
V
V
Test Conditions/Comments
These pins do not have internal pull-up/pull-down resistors
VS is the voltage on the VS pin
User can float these pins to get Logic Level ½; if floating this pin, user should
connect a capacitor to ground
V
LD, STATUS, REFMON PINS
Table 17.
Parameter
OUTPUT CHARACTERISTICS
Min
Output Voltage High, VOH
Output Voltage Low, VOL
MAXIMUM TOGGLE RATE
2.7
Max
Unit
0.4
100
V
V
MHz
3
pF
On-chip capacitance; used to calculate RC time constant
for analog lock detect readback; use a pull-up resistor
1.02
MHz
8
kHz
Frequency above which the monitor indicates the
presence of the reference
Frequency above which the monitor indicates the
presence of the reference
ANALOG LOCK DETECT
Capacitance
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range
Extended Range
LD PIN COMPARATOR
Trip Point
Hysteresis
Typ
1.6
260
V
mV
Rev. 0 | Page 15 of 84
Test Conditions/Comments
When selected as a digital output (CMOS); there are other
modes in which these pins are not CMOS digital outputs;
see Table 53, 0x017, 0x01A, and 0x01B
Applies when mux is set to any divider or counter output,
or PFD up/down pulse; also applies in analog lock detect
mode; usually debug mode only; beware that spurs can
couple to output when any of these pins are toggling
AD9520-4
POWER DISSIPATION
Table 18.
Parameter
POWER DISSIPATION, CHIP
Typ
Max
Unit
Power-On Default
PLL Locked; One LVPECL Output Enabled
1.32
0.55
1.5
0.64
W
W
PLL Locked; One CMOS Output Enabled
0.52
0.62
W
Distribution Only Mode; VCO Divider On;
One LVPECL Output Enabled
Distribution Only Mode; VCO Divider Off;
One LVPECL Output Enabled
Maximum Power, Full Operation
0.39
0.46
W
0.36
0.42
W
1.5
1.7
W
PD Power-Down
60
80
mW
PD Power-Down, Maximum Sleep
24
33
mW
4
4.8
mW
32
25
40
30
mW
mW
REF1, REF2 (Single-Ended) On/Off
15
20
mW
VCO On/Off
PLL Dividers and Phase Detector On/Off
LVPECL Channel
67
51
121
104
63
144
mW
mW
mW
LVPECL Driver
CMOS Channel
51
145
73
180
mW
mW
CMOS Driver On/Off
Channel Divider Enabled
11
40
24
57
mW
mW
Zero Delay Block On/Off
30
34
mW
VCP Supply
POWER DELTAS, INDIVIDUAL FUNCTIONS
VCO Divider On/Off
REFIN (Differential) Off
Min
Test Conditions/Comments
Does not include power dissipated in external resistors; all
LVPECL outputs terminated with 50 Ω to VCC − 2 V; all CMOS
outputs have 10 pF capacitive loading; VS_DRV = 3.3 V
No clock; no programming; default register values
fREF = 25 MHz; fOUT = 250 MHz; VCO = 1.5 GHz; VCO divider = 2;
one LVPECL output and output divider enabled; zero delay off;
ICP = 4.8 mA
fREF = 25 MHz; fOUT = 62.5 MHz; VCO = 1.5 GHz; VCO divider = 2;
one CMOS output and output divider enabled; zero delay off;
ICP = 4.8 mA
fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider = 2; one LVPECL
output and output divider enabled; zero delay off
fCLK = 1.6 GHz; fOUT = 200 MHz; VCO divider bypassed; one
LVPECL output and output divider enabled; zero delay off
PLL on; internal VCO = 160 MHz; VCO divider = 2; all channel
dividers on; 12 LVPECL outputs @ 125 MHz; zero delay on
PD pin pulled low; does not include power dissipated in
terminations
PD pin pulled low; PLL power-down 0x010[1:0] = 01b; SYNC
power-down 0x230[2] = 1b; power-down distribution reference
0x230[1] = 1b
PLL operating; typical closed-loop configuration
Power delta when a function is enabled/disabled
VCO divider not used
Delta between reference input off and differential reference
input mode
Delta between reference inputs off and one singled-ended
reference enabled; double this number if both REF1 and REF2
are both powered up
Internal VCO disabled; CLK input selected
PLL off to PLL on, normal operation; no reference enabled
No LVPECL output on to one LVPECL output on; channel divider
set to 1
Second LVPECL output turned on, same channel
No CMOS output on to one CMOS output on; channel divider
set to 1; fOUT = 62.5 MHz and 10 pF of capacitive loading
Additional CMOS outputs within the same channel turned on
Delta between divider bypassed (divide-by-1) and divide-by-2 to
divide-by-32
Rev. 0 | Page 16 of 84
AD9520-4
ABSOLUTE MAXIMUM RATINGS
Table 19.
Parameter or Pin
VS
VCP, CP
VS_DRV
REFIN, REFIN
RSET, LF, BYPASS
CPRSET
CLK, CLK
CLK
SCLK/SCL, SDIO/SDA, SDO, CS
OUT0, OUT0, OUT1, OUT1,
OUT2, OUT2, OUT3, OUT3,
OUT4, OUT4, OUT5, OUT5,
OUT6, OUT6, OUT7, OUT7,
OUT8, OUT8, OUT9, OUT9,
OUT10, OUT10, OUT11, OUT11
SYNC, RESET , PD
REFMON, STATUS, LD
SP0, SP1, EEPROM
Junction Temperature 1
Storage Temperature Range
Lead Temperature (10 sec)
1
With
Respect to
GND
GND
GND
GND
GND
GND
GND
CLK
GND
GND
Rating
−0.3 V to +3.6 V
−0.3 V to +5.8 V
−0.3 V to +3.6 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−1.2 V to +1.2 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Thermal impedance measurements were taken on a JEDEC51-5
2S2P test board in still air in accordance with JEDEC JESD51-2.
See the Thermal Performance section for more details.
Table 20.
Package Type
64-Lead LFCSP (CP-64-4)
ESD CAUTION
GND
GND
GND
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
150°C
−65°C to +150°C
300°C
See Table 20 for θJA.
Rev. 0 | Page 17 of 84
θJA
22
Unit
°C/W
AD9520-4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
REFIN (REF1)
REFIN (REF2)
CPRSET
VS
VS
GND
RSET
VS
OUT0 (OUT0A)
OUT0 (OUT0B)
VS_DRV
OUT1 (OUT1A)
OUT1 (OUT1B)
OUT2 (OUT2A)
OUT2 (OUT2B)
VS
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
AD9520
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OUT3 (OUT3A)
OUT3 (OUT3B)
VS_DRV
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
VS
VS
OUT8 (OUT8B)
OUT8 (OUT8A)
OUT7 (OUT7B)
OUT7 (OUT7A)
VS_DRV
OUT6 (OUT6B)
OUT6 (OUT6A)
NOTES
1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
07217-003
SDIO/SDA
SDO
GND
SP1
SP0
EEPROM
RESET
PD
OUT9 (OUT9A)
OUT9 (OUT9B)
VS_DRV
OUT10 (OUT10A)
OUT10 (OUT10B)
OUT11 (OUT11A)
OUT11 (OUT11B)
VS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VS
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
LF
BYPASS
VS
VS
CLK
CLK
CS
SCLK/SCL
Figure 5. Pin Configuration
Table 21. Pin Function Descriptions
Pin No.
1, 11, 12,
32, 40, 41,
49, 57, 60,
61
2
3
4
5
6
7
Input/
Output
I
Pin
Type
Power
Mnemonic
VS
Description
3.3 V Power Pins.
O
O
I
O
O
I
3.3 V CMOS
3.3 V CMOS
Power
Loop filter
3.3 V CMOS
3.3 V CMOS
REFMON
LD
VCP
CP
STATUS
REF_SEL
8
I
3.3 V CMOS
SYNC
9
10
13
I
O
I
LF
BYPASS
CLK
14
I
Loop filter
Loop filter
Differential
clock input
Differential
clock input
Reference Monitor (Output). It has multiple selectable outputs.
Lock Detect (Output). It has multiple selectable outputs.
Power Supply for Charge Pump (CP); VS < VCP < 5.0 V.
Charge Pump (Output). It connects to external loop filter.
Programmable Status Output.
Reference Select. It selects REF1 (low) or REF2 (high). This pin has an internal
30 kΩ pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
Loop Filter (Input). It connects internally to the VCO control voltage node.
This pin is for bypassing the LDO to ground with a capacitor.
Along with CLK, this is the differential input for the clock distribution section.
CLK
Along with CLK, this is the differential input for the clock distribution section.
Rev. 0 | Page 18 of 84
AD9520-4
Pin No.
15
Input/
Output
I
Pin
Type
3.3 V CMOS
Mnemonic
CS
16
I
3.3 V CMOS
SCLK/SCL
17
18
19, 59
20
I/O
O
I
I
SDIO/SDA
SDO
GND
SP1
21
I
22
I
3.3 V CMOS
3.3 V CMOS
GND
Three-level
logic
Three-level
logic
3.3 V CMOS
23
24
25
I
I
O
RESET
PD
OUT9 (OUT9A)
26
O
27, 35,
46, 54
28
I
3.3 V CMOS
3.3 V CMOS
LVPECL or
CMOS
LVPECL or
CMOS
Power
O
OUT10 (OUT10A)
29
O
30
O
31
O
33
O
34
O
36
O
37
O
38
O
39
O
42
O
43
O
44
O
45
O
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
SP0
EEPROM
OUT9 (OUT9B)
VS_DRV
OUT10 (OUT10B)
OUT11 (OUT11A)
OUT11 (OUT11B)
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
OUT8 (OUT8A)
OUT8 (OUT8B)
OUT5 (OUT5B)
OUT5 (OUT5A)
OUT4 (OUT4B)
OUT4 (OUT4A)
Description
Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up
resistor.
Serial Control Port Clock Signal. This pin has an internal 30 kΩ pull-down resistor
in SPI mode, but is high impedance in I²C mode.
Serial Control Port Bidirectional Serial Data In/Out.
Serial Control Port Unidirectional Serial Data Out.
Ground Pins.
Select SPI or I²C as serial interface port and select I²C slave address in I²C mode.
Three-level logic. This pin is internally biased for the open logic level.
Select SPI or I²C as serial interface port and select I²C slave address in I²C mode.
Three-level logic. This pin is internally biased for the open logic level.
Setting this pin high selects the register values stored in the internal EEPROM to
be loaded at reset and/or power-up. Setting this pin low causes the AD9520 to
load the hard-coded default register values at power-up/reset. This pin has an
internal 30 kΩ pull-down resistor.
Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor.
Chip Power Down, Active Low. This pin has an internal 30 kΩ pull-up resistor.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Output Driver Power Supply Pins. As a group, these pins can be set to either
2.5 V or 3.3 V. All four pins must be set to the same voltage.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
Output, or as a single-ended CMOS output.
Rev. 0 | Page 19 of 84
AD9520-4
Pin No.
47
Input/
Output
O
48
O
50
O
51
O
52
O
53
O
55
O
56
O
58
O
62
O
63
I
64
I
EPAD
Pin
Type
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
Current set
resistor
Current set
resistor
Reference
input
Reference
input
GND
Mnemonic
OUT3 (OUT3B)
OUT3 (OUT3A)
OUT2 (OUT2B)
OUT2 (OUT2A)
OUT1 (OUT1B)
OUT1 (OUT1A)
OUT0 (OUT0B)
OUT0 (OUT0A)
RSET
CPRSET
REFIN (REF2)
REFIN (REF1)
GND
Description
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output, or as a single-ended CMOS output.
Clock Distribution Current Set Resistor. Connect a 4.12 kΩ resistor from this
pin to GND.
Charge Pump Current Set Resistor. Connect a 5.1 kΩ resistor from this pin to GND.
Along with REFIN, this is the differential input for the PLL reference. Alternatively,
this pin is a single-ended input for REF2.
Along with REFIN, this is the differential input for the PLL reference. Alternatively,
this pin is a single-ended input for REF1.
Exposed die pad must be connected to GND.
Rev. 0 | Page 20 of 84
AD9520-4
TYPICAL PERFORMANCE CHARACTERISTICS
350
5
3 CHANNELS—6 LVPECL
CURRENT FROM CP PIN (mA)
CURRENT (mA)
300
3 CHANNELS—3 LVPECL
250
2 CHANNELS—2 LVPECL
200
150
4
PUMP DOWN
PUMP UP
3
2
1
0
500
1000
1500
2000
2500
0
07217-108
100
3000
FREQUENCY (MHz)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOLTAGE ON CP PIN (V)
Figure 6. Total Current vs. Frequency, CLK-to-Output (PLL Off),
LVPECL Outputs Terminated 50 Ω to VS_DRV − 2 V
07217-111
1 CHANNEL—1 LVPECL
Figure 9. Charge Pump Characteristics @ VCP = 3.3 V
240
5
3 CHANNELS—6 CMOS
CURRENT FROM CP PIN (mA)
220
CURRENT (mA)
200
180
3 CHANNELS—3 CMOS
160
140
2 CHANNELS—2 CMOS
120
4
PUMP DOWN
PUMP UP
3
2
1
1 CHANNEL—1 CMOS
50
100
150
200
250
FREQUENCY (MHz)
0
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Figure 10. Charge Pump Characteristics @ VCP = 5.0 V
–140
PFD PHASE NOISE REFERRED TO PFD INPUT
(dBc/Hz)
50
45
40
35
30
25
1.55
1.65
VCO FREQUENCY (GHz)
1.75
07217-010
KVCO (MHz/V)
1.0
VOLTAGE ON CP PIN (V)
Figure 7. Total Current vs. Frequency, CLK-to-Output (PLL Off),
CMOS Outputs with 10 pF Load
20
1.45
0.5
–145
–150
–155
–160
–165
–170
0.1
1
10
100
PFD FREQUENCY (MHz)
Figure 11. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
Figure 8. KVCO vs. VCO Frequency
Rev. 0 | Page 21 of 84
07217-013
0
07217-109
80
07217-112
100
AD9520-4
–208
0
–10
–20
–212
–30
–214
POWER (dBm)
PLL FIGURE OF MERIT (dBc/Hz)
–210
–216
–218
–40
–50
–60
DIFFERENTIAL INPUT
–70
–220
–80
–222
–90
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
INPUT SLEW RATE (V/ns)
–100
122.38
07217-114
–224
Figure 12. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN
122.58
122.78
122.98
123.18
07217-117
SINGLE-ENDED INPUT
123.38
FREQUENCY (MHz)
Figure 15. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz;
LBW = 127 kHz; ICP = 3.0 mA; fVCO = 1474.56 MHz
2.1
3.5
1.9
3.0
VS_DRV = 3.135V
VS_DRV = 2.5V
2.5
1.7
VOH (V)
1.5
VS_DRV = 2.35V
2.0
1.5
1.3
1.0
1.1
1.50
1.55
1.60
1.65
1.70
1.75
1.80
FREQUENCY (GHz)
0
10k
07217-115
0.9
1.45
0.5
1k
100
RESISTIVE LOAD (Ω)
Figure 13. VCO Tuning Voltage vs. Frequency
07217-118
VCO TUNING VOLTAGE (V)
VS_DRV = 3.3V
Figure 16. CMOS Output VOH (Static) vs. RLOAD (to Ground)
0
1.2
–10
0.8
DIFFERENTIAL OUTPUT (V)
–20
–40
–50
–60
–70
–80
0.4
0
–0.4
–0.8
–100
100
105
110
115
120
125
130
135
140
FREQUENCY (MHz)
145
Figure 14. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz;
LBW = 127 kHz; ICP = 3.0 mA; fVCO = 1474.56 MHz
–1.2
0
2
4
6
8
10
12
14
16
18
20
22
TIME (ns)
Figure 17. LVPECL Output (Differential) @ 100 MHz
Rev. 0 | Page 22 of 84
24
07217-014
–90
07217-116
POWER (dBm)
–30
2.0
0.6
1.8
0.2
–0.2
–0.6
–1.0
0
0.5
1.0
1.5
TIME (ns)
1.2
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
Figure 21. LVPECL Differential Voltage Swing vs. Frequency
4.0
3.2
2.8
3.5
2.4
3.0
2pF
AMPLITUDE (V)
2.0
1.6
1.2
0.8
2.5
2.0
10pF
1.5
20pF
1.0
0.4
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
0
07217-018
0
0
200
300
400
500
600
700
FREQUENCY (MHz)
Figure 19. CMOS Output with 10 pF Load @ 25 MHz
Figure 22. CMOS Output Swing vs. Frequency and Capacitive Load
–40
2pF LOAD
3.2
100
07217-124
0.5
–50
2.8
–60
2.4
PHASE NOISE (dBc/Hz)
10pF
LOAD
2.0
1.6
1.2
0.8
–70
–80
–90
–100
–110
–120
–130
0.4
–140
0
1
2
3
4
5
6
7
8
9
10
TIME (ns)
Figure 20. CMOS Output with 2 pFand 10 pF Load @ 250 MHz
–150
1k
07217-019
0
10k
100k
1M
FREQUENCY (Hz)
10M
100M
07217-023
AMPLITUDE (V)
1.4
1.0
Figure 18. LVPECL Differential Voltage Swing @ 1600 MHz
AMPLITUDE (V)
1.6
07217-123
DIFFERENTIAL SWING (V p-p)
1.0
07217-015
DIFFERENTIAL SWING (V p-p)
AD9520-4
Figure 23. Internal VCO Phase Noise (Absolute), Direct-to-LVPECL @ 1450 MHz
Rev. 0 | Page 23 of 84
AD9520-4
–40
–100
–50
–110
–70
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–60
–80
–90
–100
–110
–120
–130
–120
–130
–140
–150
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–160
10
07217-024
–150
1k
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 24. Internal VCO Phase Noise (Absolute) Direct-to-LVPECL @ 1625 MHz
07217-129
–140
Figure 27. Additive (Residual) Phase Noise, CLK-to-LVPECL @
200 MHz, Divide-by-5
–40
–100
–50
–110
–70
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–60
–80
–90
–100
–110
–120
–130
–120
–130
–140
–150
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–160
10
07217-025
–150
1k
–120
PHASE NOISE (dBc/Hz)
–110
1M
10M
100M
–130
–140
–150
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 26. Additive (Residual) Phase Noise CLK-to-LVPECL @
245.76 MHz, Divide-by-1
–170
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 29. Additive (Residual) Phase Noise, CLK-to-CMOS @
50 MHz, Divide-by-20
Rev. 0 | Page 24 of 84
07217-131
–160
10
100k
–160
–150
07217-128
PHASE NOISE (dBc/Hz)
–110
–140
10k
Figure 28. Additive (Residual) Phase Noise CLK-to-LVPECL @
1600 MHz, Divide-by-1
–100
–130
1k
FREQUENCY (Hz)
Figure 25. Internal VCO Phase Noise (Absolute) Direct-to-LVPECL @ 1800 MHz
–120
100
07217-130
–140
AD9520-4
–100
–80
INTEGRATED RMS JITTER (12kHz TO 20MHz): 442 fS
–90
PHASE NOISE (dBc/Hz)
–120
–130
–140
–150
–110
–120
–130
–140
–150
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–160
1k
07217-132
–160
10
–100
Figure 30. Additive (Residual) Phase Noise, CLK-to-CMOS @
250 MHz, Divide-by-4
10k
100k
1M
10M
100M
FREQUENCY (Hz)
07217-034
PHASE NOISE (dBc/Hz)
–110
Figure 32. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 1.552 GHz;
PFD = 19.44 MHz; LBW = 1.84 kHz; LVPECL Output = 155.52 MHz
–100
–120
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–110
–120
–130
–140
–130
–140
–150
10k
100k
1M
FREQUENCY (Hz)
10M
100M
–160
1k
07217-033
–160
1k
Figure 31. Phase Noise (Absolute) Clock Generation; Internal VCO @
1.475 GHz; PFD = 15.36 MHz; LBW = 40 kHz; LVPECL Output = 122.88 MHz
10k
100k
1M
FREQUENCY (Hz)
10M
100M
07217-135
–150
Figure 33. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)
@ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
Rev. 0 | Page 25 of 84
AD9520-4
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is called phase jitter. Although many causes can
contribute to phase jitter, one major cause is random noise,
which is characterized statistically as being Gaussian (normal)
in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hertz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in decibels) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of ADCs,
DACs, and RF mixers. It lowers the achievable dynamic range of
the converters and mixers, although they are affected in somewhat
different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When observing
a sine wave, the time of successive zero crossings varies. In a square
wave, the time jitter is a displacement of the edges from their
ideal (regular) times of occurrence. In both cases, the variations in
timing from the ideal are the time jitter. Because these variations
are random in nature, the time jitter is specified in units of
seconds root mean square (rms) or 1 sigma of the Gaussian
distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured. The
phase noise of any external oscillators or clock sources are
subtracted. This makes it possible to predict the degree to which
the device impacts the total system phase noise when used in
conjunction with the various oscillators and clock sources, each
of which contribute its own phase noise to the total. In many
cases, the phase noise of one element dominates the system
phase noise. When there are multiple contributors to phase
noise, the total is the square root of the sum of squares of the
individual contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is attributable to
the device or subsystem being measured. The time jitter of any
external oscillators or clock sources are subtracted. This makes
it possible to predict the degree to which the device impacts the
total system time jitter when used in conjunction with the various
oscillators and clock sources, each of which contribute its own time
jitter to the total. In many cases, the time jitter of the external
oscillators and clock sources dominates the system time jitter.
Rev. 0 | Page 26 of 84
AD9520-4
DETAILED BLOCK DIAGRAM
VS
GND
RSET
REFMON
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
STATUS
BUF
LOCK
DETECT
PLL
REFERENCE
STATUS
REF2
R
DIVIDER
CLOCK
DOUBLER
REF1
OPTIONAL
REFIN
CPRSET VCP
PROGRAMMABLE
R DELAY
REF_SEL
HOLD
REFIN
AMP
BYPASS
STATUS
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
N DIVIDER
LF
ZERO DELAY BLOCK
STATUS
DIVIDE BY 1,
2, 3, 4, 5, OR 6
VS_DRV
CLK
OUT0
CLK
1
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
0
DIGITAL
LOGIC
OUT1
OUT1
EEPROM
RESET
OUT2
OUT2
EEPROM
OUT3
SP1
SP0
OUT3
SERIAL
PORT
DECODE
DIVIDE BY
1 TO 32
OUT4
I2C
INTERFACE
OUT5
SCLK/SCL
SDIO/SDA
SDO
CS
OUT5
OUT6
OUT6
DIVIDE BY
1 TO 32
LVPECL/CMOS OUTPUT
OUT4
SPI
INTERFACE
OUT7
OUT7
OUT8
OUT8
OUT9
OUT9
DIVIDE BY
1 TO 32
OUT10
OUT10
AD9520
OUT11
Figure 34.
Rev. 0 | Page 27 of 84
07217-028
OUT11
AD9520-4
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
Table 22. Settings When Using Internal VCO
The AD9520 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 49 to Table 60). Each section or function must be
individually programmed by setting the appropriate bits in the
corresponding control register or registers. Once the desired
configuration is programmed, the user can store these values in
the on-board EEPROM to allow the part to powerup in the desired
configuration without user intervention.
Register
0x010[1:0] = 00b
0x010 to 0x01E
Mode 0: Internal VCO and Clock Distribution
When using the internal VCO and PLL, the VCO divider must
be employed to ensure that the frequency presented to the channel
dividers does not exceed its specified maximum frequency (see
Table 3). The internal PLL uses an external loop filter to set the
loop bandwidth. The external loop filter is also crucial to the
loop stability.
0x1E1[1] = 1b
0x01C[2:0]
0x1E0[2:0]
0x1E1[0] = 0b
0x018[0] = 0
0x232[0] = 1
0x018[0] = 1,
0x232[0] = 1
When using the internal VCO, it is necessary to calibrate the
VCO (0x018[0]) to ensure optimal performance.
For internal VCO and clock distribution applications, the
register settings shown in Table 22 should be used.
Rev. 0 | Page 28 of 84
Description
PLL normal operation (PLL on)
PLL settings; select and enable a reference
input; set R, N (P, A, B), PFD polarity, and ICP
according to the intended loop configuration
VCO selected as the source
Enable reference inputs
Set VCO divider
Use the VCO divider as source for
distribution section
Reset VCO calibration and issue IO_UPDATE
(not necessary for first time after power-up,
but must be done subsequently)
Initiate VCO calibration, Issue IO_UPDATE
AD9520-4
VS
GND
RSET
REFMON
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
STATUS
BUF
LOCK
DETECT
PLL
REFERENCE
STATUS
REF2
R
DIVIDER
CLOCK
DOUBLER
REF1
OPTIONAL
REFIN
CPRSET VCP
PROGRAMMABLE
R DELAY
REF_SEL
HOLD
REFIN
AMP
BYPASS
STATUS
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
N DIVIDER
LF
ZERO DELAY BLOCK
STATUS
DIVIDE BY 1,
2, 3, 4, 5, OR 6
VS_DRV
CLK
OUT0
CLK
1
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
0
DIGITAL
LOGIC
OUT1
OUT1
EEPROM
RESET
OUT2
OUT2
EEPROM
OUT3
SP1
SP0
OUT3
SERIAL
PORT
DECODE
DIVIDE BY
1 TO 32
OUT4
I2C
INTERFACE
OUT5
SCLK/SCL
SDIO/SDA
SDO
CS
OUT5
OUT6
OUT6
DIVIDE BY
1 TO 32
LVPECL/CMOS OUTPUT
OUT4
SPI
INTERFACE
OUT7
OUT7
OUT8
OUT8
OUT9
OUT9
DIVIDE BY
1 TO 32
OUT10
OUT10
AD9520
OUT11
Figure 35. Internal VCO and Clock Distribution (Mode 0)
Rev. 0 | Page 29 of 84
07217-030
OUT11
AD9520-4
Mode 1: Clock Distribution or External VCO <1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is <1600 MHz, a configuration that bypasses the
VCO divider can be used. This is the only difference from Mode 2.
Bypassing the VCO divider limits the frequency of the clock
source to <1600 MHz (due to the maximum input frequency
allowed at the channel dividers).
Table 24. Settings for Using Internal PLL with External VCO
< 1600 MHz
Register
0x1E1[0] = 1b
0x010[1:0] = 00b
Description
Bypass the VCO divider as source for
distribution section
PLL normal operation (PLL on) along
with other appropriate PLL settings in
0x010 to 0x01E
Configuration and Register Settings
For clock distribution applications where the external clock is
<1600 MHz, the register settings shown in Table 23 should be used.
Table 23. Settings for Clock Distribution < 1600 MHz
Register
0x010[1:0] = 01b
0x1E1[0] = 1b
0x1E1[1] = 0b
Description
PLL asynchronous power-down (PLL off )
Bypass the VCO divider as source for
distribution section
CLK selected as the source
When using the internal PLL with an external VCO < 1600 MHz,
the PLL must be turned on.
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the VCO/
VCXO. This loop filter determines the loop bandwidth and stability
of the PLL. Make sure to select the proper PFD polarity for the
VCO/VCXO being used.
Table 25. Setting the PFD Polarity
Register
0x010[7] = 0
0x010[7] = 1
Rev. 0 | Page 30 of 84
Description
PFD polarity positive (higher control voltage
produces higher frequency)
PFD polarity negative (higher control voltage
produces lower frequency)
AD9520-4
VS
GND
RSET
REFMON
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
STATUS
BUF
LOCK
DETECT
PLL
REFERENCE
STATUS
REF2
R
DIVIDER
CLOCK
DOUBLER
REF1
OPTIONAL
REFIN
CPRSET VCP
PROGRAMMABLE
R DELAY
REF_SEL
HOLD
REFIN
AMP
BYPASS
STATUS
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
N DIVIDER
LF
ZERO DELAY BLOCK
STATUS
DIVIDE BY 1,
2, 3, 4, 5, OR 6
VS_DRV
CLK
OUT0
CLK
1
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
0
DIGITAL
LOGIC
OUT1
OUT1
EEPROM
RESET
OUT2
OUT2
EEPROM
OUT3
SP1
SP0
OUT3
SERIAL
PORT
DECODE
DIVIDE BY
1 TO 32
OUT4
I2C
INTERFACE
OUT5
SCLK/SCL
SDIO/SDA
SDO
CS
OUT5
OUT6
OUT6
DIVIDE BY
1 TO 32
LVPECL/CMOS OUTPUT
OUT4
SPI
INTERFACE
OUT7
OUT7
OUT8
OUT8
OUT9
OUT9
DIVIDE BY
1 TO 32
OUT10
OUT10
AD9520
OUT11
Figure 36. Clock Distribution or External VCO < 1600 MHz (Mode 1)
Rev. 0 | Page 31 of 84
07217-031
OUT11
AD9520-4
Mode 2: High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz
Table 26. Default Register Settings for Clock Distribution Mode
The AD9520 power-up default configuration has the PLL
powered off and the routing of the input set so that the CLK/
CLK input is connected to the distribution section through the
VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/
divide-by-5/divide-by-6). This is a distribution-only mode that
allows for an external input up to 2400 MHz (see Table 3). The
maximum frequency that can be applied to the channel dividers
is 1600 MHz; therefore, higher input frequencies must be divided
down before reaching the channel dividers.
When the PLL is enabled, this routing also allows the use of the
PLL with an external VCO or VCXO with a frequency <2400 MHz.
In this configuration, the internal VCO is not used and is powered
off. The external VCO/VCXO feeds directly into the prescaler.
The register settings shown in Table 26 are the default values of
these registers at power-up or after a reset operation.
Register
0x010[1:0] = 01b
0x1E0[2:0] = 000b
0x1E1[0] = 0b
0x1E1[1] = 0b
Description
PLL asynchronous power-down (PLL off )
Set VCO divider = 2
Use the VCO divider
CLK selected as the source
When using the internal PLL with an external VCO, the PLL
must be turned on.
Table 27. Settings When Using an External VCO
Register
0x010[1:0] = 00b
0x010 to 0x01E
0x1E1[1] = 0b
Description
PLL normal operation (PLL on)
PLL settings; select and enable a
reference input; set R, N (P, A, B), PFD
polarity, and ICP according to the intended
loop configuration
CLK selected as the source
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This
loop filter determines the loop bandwidth and stability of the
PLL. Make sure to select the proper PFD polarity for the VCO
being used.
Table 28. Setting the PFD Polarity
Register
0x010[7] = 0b
0x010[7] = 1b
Rev. 0 | Page 32 of 84
Description
PFD polarity positive (higher control
voltage produces higher frequency)
PFD polarity negative (higher control
voltage produces lower frequency)
AD9520-4
VS
GND
RSET
REFMON
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
STATUS
BUF
LOCK
DETECT
PLL
REFERENCE
STATUS
REF2
R
DIVIDER
CLOCK
DOUBLER
REF1
OPTIONAL
REFIN
CPRSET VCP
PROGRAMMABLE
R DELAY
REF_SEL
HOLD
REFIN
AMP
BYPASS
STATUS
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
N DIVIDER
LF
ZERO DELAY BLOCK
STATUS
DIVIDE BY 1,
2, 3, 4, 5, OR 6
VS_DRV
CLK
OUT0
CLK
1
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
0
DIGITAL
LOGIC
OUT1
OUT1
EEPROM
RESET
OUT2
OUT2
EEPROM
OUT3
SP1
SP0
OUT3
SERIAL
PORT
DECODE
DIVIDE BY
1 TO 32
OUT4
I2C
INTERFACE
OUT5
SCLK/SCL
SDIO/SDA
SDO
CS
OUT5
OUT6
OUT6
DIVIDE BY
1 TO 32
LVPECL/CMOS OUTPUT
OUT4
SPI
INTERFACE
OUT7
OUT7
OUT8
OUT8
OUT9
OUT9
DIVIDE BY
1 TO 32
OUT10
OUT10
AD9520
OUT11
Figure 37. High Frequency Clock Distribution or External VCO > 1600 MHz (Mode 2)
Rev. 0 | Page 33 of 84
07217-029
OUT11
AD9520-4
Phase-Locked Loop (PLL)
VS
GND
RSET
REFMON
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
STATUS
BUF
REFIN
BYPASS
LOCK
DETECT
PLL
REFERENCE
STATUS
REF2
R
DIVIDER
CLOCK
DOUBLER
REF1
OPTIONAL
REFIN
CPRSET VCP
PROGRAMMABLE
R DELAY
REF_SEL
HOLD
STATUS
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
N DIVIDER
LF
ZERO DELAY BLOCK
STATUS
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLK
FROM CHANNEL
DIVIDER 0
1
VS_DRV
07217-064
CLK
0
Figure 38. PLL Functional Block
The AD9520 includes an on-chip PLL with an on-chip VCO.
The PLL blocks can be used either with the on-chip VCO to
create a complete phase-locked loop or with an external VCO
or VCXO. The PLL requires an external loop filter, which
usually consists of a small number of capacitors and resistors.
The configuration and components of the loop filter help to
establish the loop bandwidth and stability of the operating PLL.
The AD9520 PLL is useful for generating clock frequencies
from a supplied reference frequency. This includes conversion
of reference frequencies to much higher frequencies for subsequent
division and distribution. In addition, the PLL can be exploited
to clean up jitter and phase noise on a noisy reference. The
exact choice of PLL parameters and loop dynamics is application
specific. The flexibility and depth of the AD9520 PLL allows
the part to be tailored to function in many different applications
and signal environments.
Configuration of the PLL
The AD9520 allows flexible configuration of the PLL,
accomodating various reference frequencies, PFD comparison
frequencies, VCO frequencies, internal or external VCO/VCXO,
and loop dynamics. This is accomplished by the various settings
that include the R divider, the N divider, the PFD polarity (only
applicable to external VCO/VCXO), the antibacklash pulse
width, the charge pump current, the selection of internal VCO
or external VCO/VCXO, and the loop bandwidth. These are
managed through programmable register settings (see Table 49
and Table 53) and by the design of the external loop filter.
Successful PLL operation and satisfactory PLL loop performance
are highly dependent upon proper configuration of the PLL
settings, and the design of the external loop filter is crucial to
the proper operation of the PLL.
ADIsimCLK™ (V1.3 or later) is a free program that can help
with the design and exploration of the capabilities and features
of the AD9520, including the design of the PLL loop filter. The
AD9516 model found in ADIsimCLK Version 1.2 can also be
used for modeling the AD9520 loop filter. It is available at
www.analog.com/clocks.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R divider and N divider and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD
transfer function and minimizes phase noise and reference
spurs. The antibacklash pulse width is set by 0x017[1:0].
An important limit to keep in mind is the maximum frequency
allowed into the PFD. The maximum input frequency into the
PFD is a function of the antibacklash pulse setting, as specified
in the Phase/Frequency Detector (PFD) parameter in Table 2.
Rev. 0 | Page 34 of 84
AD9520-4
Charge Pump (CP)
AD9520
On-Chip VCO
The AD9520 includes an on-chip VCO covering the frequency
range shown in Table 2. Achieving low VCO phase noise was a
priority in the design of the VCO.
To tune over the wide range of frequencies covered by this VCO,
ranges are used. This is largely transparent to the user but is the
reason that the VCO must be calibrated when the PLL loop is
first set up. The calibration procedure ensures that the VCO is
operating within the correct band range for the desired VCO
frequency. See the VCO Calibration section for additional
information.
The on-chip VCO is powered by an on-chip, low dropout (LDO),
linear voltage regulator. The LDO provides some isolation of
the VCO from variations in the power supply voltage level.
The BYPASS pin should be connected to ground by a 220 nF
capacitor to ensure stability. This LDO employs the same
technology used in the anyCAP® line of regulators from Analog
Devices, Inc., making it insensitive to the type of capacitor used.
Driving an external load from the BYPASS pin is not supported.
PLL External Loop Filter
When using the internal VCO, the external loop filter should be
referenced to the BYPASS pin for optimal noise and spurious
performance. An example of an external loop filter for the PLL
is shown in Figure 39. A loop filter must be calculated for each
desired PLL configuration. The values of the components depend
upon the VCO frequency, the KVCO, the PFD frequency, the CP
current, the desired loop bandwidth, and the desired phase margin.
The loop filter affects the phase noise, the loop settling time,
and the loop stability. A knowledge of PLL theory is necessary
for understanding loop filter design. There are tools available,
such as the ADIsimCLK, that can help with the calculation of a
loop filter according to the application requirements.
LF
VCO
R2
CP
CHARGE
PUMP
R1
BYPASS
C1
CBP = 220nF
C2
C3
07217-065
The charge pump is controlled by the PFD. The PFD monitors
the phase and frequency relationship between its two inputs and
tells the CP to pump up or pump down to charge or discharge the
integrating node (part of the loop filter). The integrated and
filtered CP current is transformed into a voltage that drives the
tuning node of the internal VCO through the LF pin (or the
tuning pin of an external VCO) to move the VCO frequency up
or down. The CP can be set (0x010[6:4]) for high impedance
(allows holdover operation), for normal operation (attempts to
lock the PLL loop), for pump-up, or for pump-down (test modes).
The CP current is programmable in eight steps from (nominally)
600 μA to 4.8 mA. The exact value of the CP current LSB is set
by the CP_RSET resistor, which is nominally 5.1 kΩ.
Figure 39. Example of External Loop Filter for PLL
PLL Reference Inputs
The AD9520 features a flexible PLL reference input circuit that
allows a fully differential input, two separate single-ended inputs,
or a 16.67 MHz to 32 MHz crystal oscillator with an on-chip
maintaining amplifier. An optional reference clock doubler
can be used to double the PLL reference frequency. The input
frequency range for the reference inputs is specified in Table 2.
Both the differential and the single-ended inputs are self-biased,
allowing for easy ac coupling of input signals.
Either a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential input and the single-ended inputs share two pins,
REFIN (REF1)/REFIN (REF2). The desired reference input type is
selected and controlled by 0x01C (see Table 49 and Table 53).
When the differential reference input is selected, the self-bias
level of the two sides is offset slightly to prevent chattering of
the input buffer when the reference is slow or missing. The
specification for this voltage level can be found in Table 2.
The input hysteresis increases the voltage swing required of
the driver to overcome the offset.
The single-ended inputs can be driven by either a dc-coupled
CMOS level signal or an ac-coupled sine wave or square wave.
To avoid input buffer chatter when a single-ended ac-coupled
input signal stops toggling, the user can set 0x018[7] to 1. This
shifts the dc offset bias point down 140 mV. To increase isolation
and reduce power, each single-ended input can be independently
powered down.
The differential reference input receiver is powered down when
the differential reference input is not selected or when the PLL
is powered down. The single-ended buffers power down when
the PLL is powered down, or when their respective individual
power down registers are set. When the differential mode is
selected, the single-ended inputs are powered down.
Rev. 0 | Page 35 of 84
AD9520-4
In differential mode, the reference input pins are internally selfbiased so that they can be ac-coupled via capacitors. It is possible to
dc couple to these inputs. If the differential REFIN is driven by
a single-ended signal, the unused side (REFIN) should be
decoupled via a suitable capacitor to a quiet ground. Figure 40
shows the equivalent circuit of REFIN.
VS
There are several configurable modes of reference switchover.
The switchover can be performed manually or automatically.
The manual switchover is done either through a register setting
(0x01C) or by using the REF_SEL pin. The automatic switchover
occurs when REF1 disappears. There is also a switchover deglitch
feature, which ensures that the PLL does not receive rising edges
that are far out of alignment with the newly selected reference.
There are two reference automatic switchover modes (0x01C):
• Prefer REF1. Switch from REF1 to REF2 when REF1 disappears.
Return to REF1 from REF2 when REF1 returns.
85kΩ
REF1
• Stay on REF2. Automatically switch to REF2 if REF1 disappears,
but do not switch back to REF1 if it reappears. The reference
can be set back to REF1 manually at an appropriate time.
VS
10kΩ
12kΩ
REFIN
150Ω
REFIN
150Ω
10kΩ
10kΩ
VS
REF2
07217-066
85kΩ
Figure 40. REFIN Equivalent Circuit for NonXTAL Mode
Crystal mode is nearly identical to differential mode. The user
enables a maintaining amplifier by setting the Enable XTAL
OSC bit, and putting a series resonant, AT fundamental cut
crystal across the REFIN pins.
Reference Switchover
The AD9520 supports dual single-ended CMOS inputs, as well
as a single differential reference input. In the dual single-ended
reference mode, the AD9520 supports automatic and manual
PLL reference clock switching between REF1 (on Pin REFIN)
and REF2 (on Pin REFIN). This feature supports networking
and other applications that require redundant references.
The AD9520 features an optional dc offset option in singleended mode. This option is designed to eliminate the risk of the
reference inputs chattering when they are ac-coupled and the
reference clock disappears. When using the reference switchover,
the single-ended reference inputs should be dc-coupled CMOS
levels (with the AD9520 dc offset feature disabled). Alternatively,
the inputs can be ac-coupled and dc offset feature enabled. The
user should keep in mind, however, that the minimum input
amplitude for the reference inputs is greater when the dc offset
is turned on.
In automatic mode, REF1 is monitored by REF2. If REF1
disappears (two consecutive falling edges of REF2 without an
edge transition on REF1), REF1 is considered missing. On the
next subsequent rising edge of REF2, REF2 is used as the reference
clock to the PLL. If 0x01C[3] = 0b (default), when REF1 returns
(four rising edges of REF1 without two falling edges of REF2
between the REF1 edges), the PLL reference switches back to
REF1. If 0x01C[3] = 1b, the user can control when to switch
back to REF1. This is done by programming the part to manual
reference select mode (0x01C[4] = 0b) and by ensuring that the
registers and/or REF_SEL pin are set to select the desired
reference. Automatic mode can be reenabled once REF1 is
reselected.
Manual switchover requires the presence of a clock on the reference
input that is being switched to or that the deglitching feature be
disabled (0x01C[7]).
Reference Divider R
The reference inputs are routed to the reference divider, R. R (a
14-bit counter) can be set to any value from 0 to 16,383 by writing
to 0x011 and 0x012. (Both R = 0 and R = 1 give divide-by-1.) The
output of the R divider goes to one of the PFD inputs to be
compared with the VCO frequency divided by the N divider.
The frequency applied to the PFD must not exceed the maximum
allowable frequency, which depends on the antibacklash pulse
setting (see Table 2).
The R divider has its own reset. R divider can be reset using the
shared reset bit of the R, A, and B counters. It can also be reset
by a SYNC operation.
VCXO/VCO Feedback Divider N: P, A, B, R
The N divider is a combination of a prescaler (P) and two counters,
A and B. The total divider value is
N = (P × B) + A
where P can be 2, 4, 8, 16, or 32.
Rev. 0 | Page 36 of 84
AD9520-4
Prescaler
A and B Counters
The prescaler of the AD9520 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3 and a dual modulus (DM)
mode where the prescaler divides by P and (P + 1) {2 and 3, 4
and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes of
operation are given in Table 53, 0x016[2:0]. Not all modes are
available at all frequencies (see Table 2).
The AD9520 B counter can be bypassed (B = 1). This B counter
bypass mode is only valid when using the prescaler in FD mode.
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32.
When operating the AD9520 in dual modulus mode, P/(P + 1),
the equation used to relate the input reference frequency to the
VCO output frequency is
fVCO = (fREF/R) × (P × B + A) = fREF × N/R
However, when operating the prescaler in FD mode 1, 2, or 3,
the A counter is not used (A = 0) and the equation simplifies to
fVCO = (fREF/R) × (P × B) = fREF × N/R
Unlike the R counter, an A = 0 is actually zero. The B counter
must be ≥3 or bypassed.
The maximum input frequency to the A/B counter is reflected
in the maximum prescaler output frequency (~300 MHz) specified
in Table 2. This is the prescaler input frequency (VCO or CLK)
divided by P.
Although manual reset is not normally required, the A/B counters
have their own reset bit. The A and B counters can be reset using
the shared reset bit of the R, A, and B counters. They can also
be reset through a SYNC operation.
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32.
R, A, and B Counters: SYNC Pin Reset
By using combinations of DM and FD modes, the AD9520 can
achieve values of N all the way down to N = 1. Table 29 shows
how a 10 MHz reference input can be locked to any integer
multiple of N.
The R, A, and B counters can also be reset simultaneously
through the SYNC pin. This function is controlled by 0x019[7:6]
(see Table 53). The SYNC pin reset is disabled by default.
Note that the same value of N can be derived in different ways,
as illustrated by the case of N = 12. The user can choose a fixed
divide mode P = 2 with B = 6, use the dual modulus mode 2/3
with A = 0, B = 6, or use the dual modulus mode 4/5 with
A = 0, B = 3.
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays can be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See 0x019 in Table 53.
Table 29. How a 10 MHz Reference Input Can Be Locked to Any Integer Multiple of N
fREF (MHz)
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
1
R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
1
2
1
1
1
2
2
2
2
2
2
2
2
2
2
4
4
A
X1
X1
X1
X1
X1
X1
0
1
2
1
X1
0
1
X1
0
0
1
B
1
1
3
4
5
3
3
3
3
4
5
5
5
6
6
3
3
N
1
2
3
4
5
6
6
7
8
9
10
10
11
12
12
12
13
fVCO (MHz)
10
20
30
40
50
60
60
70
80
90
100
100
110
120
120
120
130
Mode
FD
FD
FD
FD
FD
FD
DM
DM
DM
DM
FD
DM
DM
FD
DM
DM
DM
X = don’t care.
Rev. 0 | Page 37 of 84
Notes
P = 1, B = 1 (bypassed)
P = 2, B = 1 (bypassed)
P = 1, B = 3
P = 1, B = 4
P = 1, B = 5
P = 2, B = 3
P and P + 1 = 2 and 3, A = 0, B = 3
P and P + 1 = 2 and 3, A = 1, B = 3
P and P + 1 = 2 and 3, A = 2, B = 3
P and P + 1 = 2 and 3, A = 1, B = 4
P = 2, B = 5
P and P + 1 = 2 and 3, A = 0, B = 5
P and P + 1 = 2 and 3, A = 1, B = 5
P = 2, B = 6
P and P + 1 = 2 and 3, A = 0, B = 6
P and P + 1 = 4 and 5, A = 0, B = 3
P and P + 1 = 4 and 5, A = 1, B = 3
AD9520-4
VS = 3.3V
Digital Lock Detect (DLD)
The lock detect window timing depends on the value of the
CPRSET resistor, as well as three settings: the digital lock detect
window bit (0x018[4]), the antibacklash pulse width setting
(0x017[1:0], see Table 2), and the lock detect counter
(0x018[6:5]). The lock and unlock detection values in Table 2
are for the nominal value of CPRSET = 5.11 kΩ. Doubling the
CPRSET value to 10 kΩ doubles the values in Table 2.
A lock is not indicated until there is a programmable number of
consecutive PFD cycles with a time difference less than the lock
detect threshold. The lock detect circuit continues to indicate a
lock until a time difference greater than the unlock threshold
occurs on a single subsequent cycle. For the lock detect to work
properly, the period of the PFD frequency must be greater than
the unlock threshold. The number of consecutive PFD cycles
required for lock is programmable (0x018[6:5]).
Note that it is possible in certain low (<500 Hz) loop bandwidth,
high phase margin cases that the DLD can chatter during acquisition, which can cause the AD9520 to automatically enter and exit
holdover. To avoid this potential problem, it is recommended
that the user make provisions for a capacitor to ground on the
LD pin so that current source digital lock detect (CSDLD) mode
can be used.
Analog Lock Detect (ALD)
The AD9520 provides an ALD function that can be selected for
use at the LD pin. There are two operating modes for ALD:
• N-channel open-drain lock detect. This signal requires a pullup resistor to the positive supply, VS. The output is normally
high with short, low-going pulses. Lock is indicated by the
minimum duty cycle of the low-going pulses.
• P-channel open-drain lock detect. This signal requires a pulldown resistor to GND. The output is normally low with short,
high-going pulses. Lock is indicated by the minimum duty
cycle of the high-going pulses.
LD
R1
ALD
R2
VOUT
07217-067
C
Figure 41. Example of Analog Lock Detect Filter, Using
N-Channel Open-Drain Driver
Current Source Digital Lock Detect (CSDLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This is possible by using the
current source lock detect function. This function is enabled by
putting a capacitor to ground on the DLD pin, and by selecting
DLD as the output for the LD pin (0x01A[5:0] = 0x00h).
Enabling the LD pin comparator (0x01D[3] = 1) allows the user:
• To use CSDLD in conjunction with automatic switchover
and holdover.
• To view the CSDLD status on the STATUS and REFMON pins.
The current source lock detect provides a current of 110 μA when
DLD is true and shorts to ground when DLD is false. If a capacitor
is connected to the LD pin, it charges at a rate determined by the
current source during the DLD true time but is discharged nearly
instantly when DLD is false. By monitoring the voltage at the
LD pin (top of the capacitor), LD = high will only happen after the
DLD is true for a sufficiently long time. Any momentary DLD
false resets the charging. By selecting a properly sized capacitor,
it is possible to delay a lock detect indication until the PLL is
stably locked and the lock detect does not chatter.
The voltage on the capacitor can be sensed by an external
comparator connected to the LD pin. However, there is an
internal LD pin comparator that can be read at the REFMON
pin control (0x01B[4:0]) or the STATUS pin control (0x017[7:2])
as an active high signal. It is also available as an active low signal
(REFMON, 0x01B[4:0] and STATUS, 0x017[7:2]). The internal LD
pin comparator trip point and hysteresis are given in Table 17.
Using the CSDLD also permits the user to asynchronously enable
individual clock outputs only when CSDLD is high. To enable
this feature, set the appropriate bits in the enable output on the
CSDLD registers (0x0FC and 0x0FD).
The analog lock detect function requires an R-C filter to provide a
logic level indicating lock/unlock. The ADIsimCLK tool can be
used to help the user select the right passive component values
for ALD to ensure its correct operation.
AD9520
110µA
DLD
LD
VOUT
C
LD PIN
COMPARATOR
REFMON
OR
STATUS
Figure 42. Current Source Lock Detect
Rev. 0 | Page 38 of 84
07217-068
By selecting the proper output through the mux on each pin, the
DLD function is available at the LD, STATUS, and REFMON pins.
The digital lock detect circuit indicates a lock when the time
difference of the rising edges at the PFD inputs is less than a
specified value (the lock threshold). The loss of a lock is indicated
when the time difference exceeds a specified value (the unlock
threshold). Note that the unlock threshold is wider than the
lock threshold, which allows some phase error in excess of the
lock window to occur without chattering on the lock indicator.
AD9520
AD9520-4
External VCXO/VCO Clock Input (CLK/CLK)
Manual Holdover Mode
This differential input is used to drive the AD9520 clock
distribution section. This input can receive up to 2.4 GHz.
The pins are internally self-biased and the input signal should
be ac-coupled via capacitors.
A manual holdover mode can be enabled that allows the user to
place the charge pump into a high impedance state when the
SYNC pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump enters a high impedance state
immediately. To take the charge pump out of a high impedance
state, take the SYNC pin high. The charge pump then leaves the
high impedance state synchronously with the next PFD rising
edge from the reference clock. This prevents extraneous charge
pump events from occurring during the time between SYNC
going high and the next PFD event. This also means that the
charge pump stays in a high impedance state if there is no
reference clock present.
CLOCK INPUT
STAGE
VS
CLK
CLK
2.5kΩ
2.5kΩ
5kΩ
07217-032
5kΩ
Figure 43. CLK Equivalent Input Circuit
The CLK/CLK input can be used either as a distribution only
input (with the PLL off), or as a feedback input for an external
VCO/VCXO using the internal PLL, when the internal VCO is
not used. These inputs are also used as a feedback path for the
external zero delay mode.
Holdover
The AD9520 PLL has a holdover function. Holdover is
implemented by putting the charge pump into a high impedance
state. This function is useful when the PLL reference clock is
lost. Holdover mode allows the VCO to maintain a relatively
constant frequency even though there is no reference clock.
Without this function, the charge pump is placed into a constant
pump-up or pump-down state, resulting in a massive VCO
frequency shift. Because the charge pump is placed in a high
impedance state, any leakage that occurs at the charge pump
output or the VCO tuning node causes a drift of the VCO
frequency. This can be mitigated by using a loop filter that
contains a large capacitive component because this drift is
limited by the current leakage induced slew rate (ILEAK/C) of
the VCO control voltage.
Both a manual holdover, using the SYNC pin, and an automatic
holdover mode are provided. To use either function, the holdover
function must be enabled (0x01D[0]).
The B counter (in the N divider) is reset synchronously with the
charge pump leaving the high impedance state on the reference
path PFD event. This helps align the edges out of the R and N
dividers for faster settling of the PLL. Because the prescaler is
not reset, this feature works best when the B and R numbers are
close because this results in a smaller phase difference for the
loop to settle out.
When using this mode, the channel dividers should be set to
ignore the SYNC pin (at least after an initial SYNC event). If the
dividers are not set to ignore the SYNC pin, any time SYNC is
taken low to put the part into holdover, the distribution outputs
turn off. The channel divider ignore SYNC function is found in
0x191[6], 0x194[6], 0x197[6], and 0x19A[6] for Channel
Divider 0, Channel Divider 1, Channel Divider 2, Channel Divider 3,
respectively.
Automatic/Internal Holdover Mode
When enabled, this function automatically puts the charge
pump into a high impedance state when the loop loses lock.
The assumption is that the only reason the loop loses lock is due
to the PLL losing the reference clock; therefore, the holdover
function puts the charge pump into a high impedance state to
maintain the VCO frequency as close as possible to the original
frequency before the reference clock disappeared.
A flow chart of the automatic/internal holdover function
operation is shown in Figure 44.
Note that the VCO cannot be calibrated with the holdover enabled
because the holdover resets the N divider during calibration,
which prevents proper calibration. Disable holdover before
issuing a VCO calibration.
Rev. 0 | Page 39 of 84
AD9520-4
PLL ENABLED
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEAVES LOCK AS DETERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
NO
DLD == LOW
YES
NO
ANALOG LOCK DETECT PIN INDICATES
LOCK WAS PREVIOUSLY ACHIEVED.
(0x01D<3> = 1; USE LD PIN VOLTAGE
WITH HOLDOVER.
0x01D<3> = 0; IGNORE LD PIN VOLTAGE,
TREAT LD PIN AS ALWAYS HIGH.)
WAS
LD PIN == HIGH
WHEN DLD WENT
LOW?
YES
CHARGE PUMP IS MADE
HIGH IMPEDANCE.
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
HIGH IMPEDANCE
CHARGE PUMP
YES
NO
CHARGE PUMP REMAINS HIGH
IMPEDANCE UNTIL THE REFERENCE
HAS RETURNED.
REFERENCE
EDGE AT PFD?
YES
YES
RELEASE
CHARGE PUMP
HIGH IMPEDANCE
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE. PLL CAN
NOW RESETTLE.
NO
DLD == HIGH
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES (PROGRAMMING OF THE DLD
DELAY COUNTER) WITH THE REFERENCE AND
FEEDBACK CLOCKS INSIDE THE LOCK WINDOW AT
THE PFD. THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE AND LOCK
BEFORE THE HOLDOVER FUNCTION CAN BE
RETRIGGERED.
07217-069
YES
Figure 44. Flowchart of Automatic/Internal Holdover Mode
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the
DLD, ALD, or current source LD mode. It is possible to disable
the LD comparator (0x01D[3]), which causes the holdover
function to always sense LD as being high. If DLD is used, it is
possible for the DLD signal to chatter while the PLL is
reacquiring lock. The holdover function may retrigger, thereby
preventing the holdover mode from terminating. Use of the
current source lock detect mode is recommended to avoid this
situation (see the Current Source Digital Lock Detect section).
Once in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
As in the external holdover mode, the B counter (in the N divider)
is reset synchronously with the charge pump leaving high
impedance state on the reference path PFD event. This helps
align the edges out of the R and N dividers for faster settling of
the PLL and reduces frequency errors during settling. Because
the prescaler is not reset, this feature works best when the B and
R numbers are close because this results in a smaller phase
difference for the loop to settle out.
Rev. 0 | Page 40 of 84
AD9520-4
For example, to use automatic holdover with
After leaving holdover, the loop then reacquires lock and the
LD pin must charge (if 0x01D[3] = 1) before it can reenter
holdover (CP high impedance).
• Automatic reference switchover, prefer REF1.
• Digital lock detect: five PFD cycles, high range window.
The holdover function always responds to the state of the
currently selected reference (0x01C). If the loop loses lock
during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference
clock edge at the PFD.
• Automatic holdover using the LD pin comparator.
The following registers are set (in addition to the normal PLL
registers):
The following registers affect the automatic/internal holdover
function:
• 0x018[6:5] = 00b; lock detect counter = five cycles.
• 0x018[4] = 0b; digital lock detect window = high range.
• 0x018[6:5]—lock detect counter. This changes how many
consecutive PFD cycles with edges inside the lock detect
window are required for the DLD indicator to indicate lock.
This impacts the time required before the LD pin can begin
to charge as well as the delay from the end of a holdover
event until the holdover function can be re-engaged.
• 0x018[3] = 0b; disable DLD normal operation.
• 0x018[3]—disable digital lock detect. This bit must be set to a
0 to enable the DLD circuit. Internal/automatic holdover does
not operate correctly without the DLD function enabled.
• 0x01C[2:1] = 11b; enable REF1 and REF2 input buffers.
• 0x01A[5:0]—lock detect pin control. Set this to 000100b to
put it in the current source lock detect mode if using the LD
pin comparator. Load the LD pin with a capacitor of an
appropriate value.
• 0x01D[3]—LD pin comparator enable. 1 = enable; 0 =
disable. When disabled, the holdover function always senses
the LD pin as high.
• 0x01D[1]—external holdover control.
• 0x01D[0]—holdover enable and ignore reference frequency
status. If holdover is disabled, both external and
automatic/internal holdover are disabled.
VS
GND
RSET
• 0x01C[4] = 1b; enable automatic switchover.
• 0x01C[3] = 0b; prefer REF1.
• 0x01D[3] = 1b; enable LD pin comparator.
• 0x01D[1] = 0b; disable external holdover mode and use
automatic/internal holdover mode.
• 0x01D[0] = 1b; enable holdover.
Frequency Status Monitors
The AD9520 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. A diagram showing their location in the PLL is
shown in Figure 45.
The PLL reference monitors have two threshold frequencies:
normal and extended (see Table 17). The reference frequency
monitor thresholds are selected in 0x01F.
REFMON
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
STATUS
BUF
REFIN
BYPASS
LOCK
DETECT
PLL
REFERENCE
STATUS
REF2
R
DIVIDER
CLOCK
DOUBLER
REF1
OPTIONAL
REFIN
CPRSET VCP
PROGRAMMABLE
R DELAY
REF_SEL
• 0x01A[5:0] = 000100b; program LD pin control to current
source lock detect mode.
HOLD
VCO STATUS
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
N DIVIDER
LF
ZERO DELAY BLOCK
STATUS
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLK
1
VS_DRV
07217-070
FROM CHANNEL
DIVIDER 0
CLK
0
Figure 45. Reference and VCO Status Monitors
Rev. 0 | Page 41 of 84
AD9520-4
VCO Calibration
The AD9520 on-chip VCO must be calibrated to ensure proper
operation over process and temperature. The VCO calibration
is controlled by a calibration controller running off a divided
REFIN clock. The calibration requires that the PLL be set up
properly to lock the PLL loop and that the REFIN clock be
present. The REFIN clock must come from a stable source
external to the AD9520.
VCO calibration can be performed two ways: automatically at
power up and manually. Automatic VCO calibration occurs when
the EEPROM is set to automatically load the preprogrammed
values in the EEPROM, and then automatically calibrate the
VCO. A valid reference must be provided at power-up in order
for the automatic calibration to complete. If this is not the case,
the user must calibrate the VCO manually.
During the first initialization after a power-up or a reset of the
AD9520, a manual VCO calibration sequence is initiated by
setting 0x018[0] = 1b. This can be done as part of the initial
setup before executing update registers (0x232[0] = 1b).
Subsequent to the initial setup, a VCO calibration sequence is
initiated by resetting 0x018[0] = 0b, executing an update registers
operation, setting 0x018[0] = 1b, and executing another update
registers operation. A readback bit (0x01F[6]) indicates when a
VCO calibration is finished by returning a logic true (that is, 1b).
The sequence of operations for the VCO calibration follows:
calibration occurs at the PFD frequency divided by the calibration
divider setting. Lower VCO calibration clock frequencies result in
longer times for a calibration to be completed.
The VCO calibration clock frequency is given by
fCAL_CLOCK = fREFIN/(R × cal_div)
where:
fREFIN is the frequency of the REFIN signal.
R is the value of the R counter.
cal_div is the division set for the VCO calibration divider
(0x018[2:1]).
The user should choose a calibration divider such that the
calibration frequency is less than 6.25 MHz. Table 30 shows the
appropriate value for the calibration divider.
Table 30. VCO Calibration Divider Values for Different
Phase Detector Frequencies
PFD Rate (MHz)
<12
12 to 25
25 to 50
50 to 100
Recommended VCO Cal Divider
Any
4, 8, 16
8, 16
16
The VCO calibration takes 4400 calibration clock cycles.
Therefore, the VCO calibration time in PLL reference clock
cycles is given by
• Program the PLL registers to the proper values for the PLL loop.
Time to Calibrate VCO =
• For the initial setting of the registers after a power-up or
reset, initiate a VCO calibration by setting 0x018[0] = 1b.
Subsequently, whenever a calibration is desired, set 0x018[0] =
0b, update registers, and set 0x018[0] = 1b, update registers.
4400 × R × cal_div PLL Reference Clock Cycles
• A SYNC operation is initiated internally, causing the outputs
to go to a static state determined by normal SYNC function
operation.
• VCO calibrates to the desired setting for the requested VCO
frequency.
• Internally, the SYNC signal is released, allowing outputs to
continue clocking.
• PLL loop is closed.
• PLL locks.
A SYNC is executed during the VCO calibration; therefore,
the outputs of the AD9520 are held static during the calibration,
which prevents unwanted frequencies from being produced.
However, at the end of a VCO calibration, the outputs may
resume clocking before the PLL loop is completely settled.
The VCO calibration clock divider is set as shown in Table 53
(0x018[2:1]).
The calibration divider divides the PFD frequency (reference
frequency divided by R) down to the calibration clock. The
The AD9520 does not automatically recalibrate its VCO when
the PLL settings change. This allows for flexibility in deciding
what order to program registers and when to initiate a
calibration, instead of having it happen every time certain PLL
registers have their values change. For example, this allows for
the VCO frequency to be changed by small amounts without
having an automatic calibration occur each time; this should be
done with caution and only when the user knows the VCO control
voltage is not going to exceed the nominal best performance limits.
For example, a few 100 kHz steps are fine, but a few MHz may
not be. Additionally, because the calibration procedure results
in rapid changes in the VCO frequency, the distribution section
is automatically placed in SYNC until the calibration is finished.
Therefore, this temporary loss of outputs must be expected.
Initiate a VCO calibration under the following conditions:
• After changing any of the PLL R, P, B, and A divider settings,
or after a change in the PLL reference clock frequency. This,
in effect, means any time a PLL register or reference clock is
changed such that a different VCO frequency results.
• Whenever system calibration is desired. The VCO is designed
to operate properly over extremes of temperatures even when
it is first calibrated at the opposite extreme. However, a VCO
calibration can be initiated at any time, if desired.
Rev. 0 | Page 42 of 84
AD9520-4
REFIN/
REFIN
R
DIVIDER
AD9520
R
DELAY
PFD
N
DIVIDER
LOOP
FILTER
CP
N
DELAY
REG 0x01E<1> = 1
MUX1
MUX3
INTERNAL FEEDBACK PATH
ZERO DELAY FEEDBACK CLOCK
LF
EXTERNAL FEEDBACK PATH
REG 0x01E<0>
DIVIDE BY 1,
2, 3, 4, 5, OR 6
ZERO DELAY
CLK/CLK
CHANNEL DIVIDER 0
OUT0 TO OUT2
CHANNEL DIVIDER 1
OUT3 TO OUT5
CHANNEL DIVIDER 2
OUT6 TO OUT8
CHANNEL DIVIDER 3
OUT9 TO OUT11
0
07217-053
1
Figure 46. Zero Delay Function
ZERO DELAY OPERATION
External Zero Delay Mode
Zero delay operation aligns the phase of the output clocks with
the phase of the external PLL reference input. There are two
zero delay modes on the AD9520: internal and external.
The external zero delay function of the AD9520 is achieved by
feeding one clock output back to the CLK input and ultimately
back to the PLL N divider. In Figure 46, the change in signal
routing for external zero delay mode is shown in red.
Internal Zero Delay Mode
The internal zero delay function of the AD9520 is achieved by
feeding the output of Channel Divider 0 back to the PLL N
divider. In Figure 46, the change in signal routing for internal
zero delay mode is shown in blue.
Internal zero delay mode is selected by setting Register
0x01E[2:1] = 01b. In the default internal zero delay mode,
the output of Channel Divider 0 is routed back to the PLL (N
divider) through Mux3 and Mux1 (feedback path shown in blue
in Figure 46). The PLL synchronizes the phase/edge of the output
of Channel Divider 0 with the phase/edge of the reference input.
The user can also specify Channel Divider 1, Channel Divider 2,
or Channel Divider 3 for zero delay feedback by changing the
value in Register 0x01E[4:3].
External zero delay mode is selected by setting 0x01E[2:1] = 11.
In external zero delay mode, one of the twelve output clocks
(OUT0 to OUT11) can be routed back to the PLL (N divider)
through the CLK/CLK pins and through Mux3 and Mux1. This
feedback path is shown in red in Figure 46.
The PLL synchronizes the phase/edge of the feedback output clock
with the phase/edge of reference input. Because the channel
dividers are synchronized to each other, the clock outputs are
synchronous with the reference input. Both the R delay and the
N delay inside the PLL can be programmed to compensate for
the propagation delay from the PLL components to minimize the
phase offset between the feedback clock and the reference input.
Because the channel dividers are synchronized to each other,
the outputs of the channel divider are synchronous with the
reference input. Both the R delay and the N delay inside the
PLL can be programmed to compensate for the propagation
delay from the output drivers and PLL components to minimize
the phase offset between the clock output and the reference
input to achieve zero delay.
Rev. 0 | Page 43 of 84
AD9520-4
PLL
PLL
CLK
LF
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLK
LF
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLK
CLK
1
CLK
0
DISTRIBUTION
CLOCK
1
CLOCK
DISTRIBUTION
MODE 0 (INTERNAL VCO MODE)
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLK
0
DISTRIBUTION
CLOCK
1
CLOCK
DISTRIBUTION
MODE 1 (CLOCK DISTRIBUTION MODE)
0
DISTRIBUTION
CLOCK
CLOCK
DISTRIBUTION
MODE 2 (HF CLOCK DISTRIBUTION MODE)
07217-054
LF
PLL
Figure 47. Simplified Diagram of the Three Clock Distribution Operation Modes
CLOCK DISTRIBUTION
Operation Modes
A clock channel consists of three LVPECL clock outputs or six
CMOS clock outputs that share a common divider. A clock
output consists of the drivers that connect to the output pins.
The clock outputs have either LVPECL or CMOS at the pins.
There are three clock distribution operating modes, and these
are shown in Figure 47. One of these modes uses the internal
VCO, while the other two bypass the internal VCO and use the
signal provided on the CLK/CLK pins.
The AD9520 has four clock channels. Each channel has its own
programmable divider that divides the clock frequency applied
to its input. The channel dividers can divide by any integer from
1 to 32.
In Mode 0 (internal VCO mode), there are two signal paths
available. In the first path, the VCO signal is sent to the VCO
divider and then to the individual channel dividers. In the
second path, the user bypasses the VCO and channel dividers
and sends the VCO signal directly to the drivers.
The AD9520 features a VCO divider that divides the VCO output
by 1, 2, 3, 4, 5, or 6 before going to the individual channel dividers.
The VCO divider has two purposes. The first is to limit the
maximum input frequency of the channel dividers to 1.6 GHz. The
other is to allow the AD9520 to generate even lower frequencies
than would be possible with only a simple postdivider. External
clock signals connected to the CLK input can also use the VCO
divider.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for N + 1
input clock cycles and low for M + 1 input clock cycles (where
D = N + M + 2). For example, a divide-by-5 can be high for one
divider input cycle and low for four cycles, or a divide-by-5 can
be high for three divider input cycles and low for two cycles.
Other combinations are also possible.
The channel dividers include a duty-cycle correction function
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 15 input clock cycles. For instance, if
the frequency at the input of the channel divider is 1 GHz, the
channel divider output can be delayed by up to 15 ns. The
divider outputs can also be set to start high or to start low.
When CLK is selected as the source, it is not necessary to use the
VCO divider if the CLK frequency is less than the maximum
channel divider input frequency (1600 MHz); otherwise, the
VCO divider must be used to reduce the frequency going to
the channel dividers.
Table 31 shows how the VCO, CLK, and VCO divider are selected.
0x1E1[1:0] selects the channel divider source and determines
whether the VCO divider is used. It is not possible to select the
VCO without using the VCO divider.
Table 31. Operation Modes
Mode
2
1
0
0x1E1
[1]
[0]
0
0
0
1
1
0
1
1
Channel Divider Source
CLK
CLK
VCO
Not allowed
VCO Divider
Used
Not used
Used
Not allowed
CLK or VCO Direct-to-LVPECL Outputs
It is possible to connect either the internal VCO or the CLK
(whichever is selected as the input to the VCO divider) directly
to the LVPECL outputs. This configuration can pass frequencies
up to the maximum frequency of the VCO directly to the LVPECL
outputs. However, the LVPECL outputs may not be able to meet
the VOD specification in Table 4 at the highest frequencies.
Rev. 0 | Page 44 of 84
AD9520-4
Either the internal VCO or the CLK can be selected as the
source for the direct-to-output signal routing. To connect the
LVPECL outputs directly to the internal VCO or CLK, the user
must select the VCO divider as the source to the distribution
section, even if no channel uses it.
Table 32. Routing VCO Divider Input Directly to the Outputs
Register Setting
0x1E1[1:0] = 00b
0x1E1[1:0] = 10b
0x192[1] = 1b
0x195[1] = 1b
0x198[1] = 1b
0x19B[1] = 1b
Selection
CLK is the source; VCO divider selected
VCO is the source; VCO divider selected
Direct-to-output OUT0, OUT1, OUT2
Direct-to-output OUT3, OUT4, OUT5
Direct-to-output OUT6, OUT7, OUT8
Direct-to-output OUT9, OUT10, OUT11
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (1, 2, 3, 4, 5, and 6)
and the division of the channel divider. Table 33 indicates how the
frequency division for a channel is set.
Table 33. Frequency Division
CLK or VCO
Selected
CLK or VCO
input
CLK or VCO
input
CLK or VCO
input
CLK or VCO
input
CLK (internal
VCO off)
CLK (internal
VCO off)
1
1 to 6
Channel
Divider
Setting
Don’t
care
2 to 32
Disable
2 to 6
Bypass
Disable
1
Bypass
Disable
VCO Divider
Bypassed
VCO Divider
Bypassed
Bypass
Don’t
care
Don’t
care
VCO
Divider
Setting1
1 to 6
2 to 32
Direct to
Output
Setting
Enable
Resulting
Frequency
Division
1
However, when the VCO divider is set to 1, none of the channel
output dividers can be bypassed.
Channel Dividers
A channel divider drives each group of three LVPECL outputs.
There are four channel dividers (0, 1, 2, and 3) driving twelve
LVPECL outputs (OUT0 to OUT11). Table 34 gives the register
locations used for setting the division and other functions of
these dividers. The division is set by the values of M and N. The
divider can be bypassed (equivalent to divide-by-1, divider circuit
is powered down) by setting the bypass bit. The duty-cycle
correction can be enabled or disabled according to the setting of
the disable div DCC bits.
Table 34. Setting DX for the Output Dividers
Divider
0
1
2
3
Low
Cycles M
0x190[7:4]
0x193[7:4]
0x196[7:4]
0x199[7:4]
High
Cycles N
0x190[3:0]
0x193[3:0]
0x196[3:0]
0x199[3:0]
Bypass
0x191[7]
0x194[7]
0x197[7]
0x19A[7]
Disable
Div DCC
0x192[0]
0x195[0]
0x198[0]
0x19B[0]
Channel Frequency Division (0, 1, 2, and 3)
For each channel (where the channel number is x: 0, 1, 2, or 3),
the frequency division, DX, is set by the values of M and N
(four bits each, representing Decimal 0 to Decimal 15), where
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
(1 to 6) ×
(2 to 32)
(2 to 6) × (1)
The cycles are cycles of the clock signal currently routed to the
input of the channel dividers (VCO divider out or CLK).
Output static
(illegal state)
1
Otherwise, DX = (N + 1) + (M + 1) = N + M + 2. This allows
each channel divider to divide by any integer from 1 to 32.
2 to 32
The duty cycle of the clock signal at the output of a channel is a
result of some or all of the following conditions:
The bypass VCO divider (0x1E1[0] = 1) is not the same as VCO divider = 1.
The channel dividers feeding the output drivers contain one 2to-32 frequency divider. This divider provides for division-by-1
to division-by-32. Division-by-1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal at
their inputs up to 1600 MHz. The features and settings of the
dividers are selected by programming the appropriate setup
and control registers (see Table 49 through Table 60).
VCO Divider
The VCO divider provides frequency division between the
internal VCO or the external CLK input and the clock
distribution channel dividers. The VCO divider can be set
to divide by 1, 2, 3, 4, 5, or 6 (see Table 56, 0x1E0[2:0]).
When a divider is bypassed, DX = 1.
Duty Cycle and Duty-Cycle Correction
• The M and N values for the channel
• DCC enabled/disabled
• VCO divider enabled/bypassed
• The CLK input duty cycle (note that the internal VCO has a
50% duty cycle)
The DCC function is enabled by default for each channel divider.
However, the DCC function can be disabled individually for
each channel divider by setting the disable divider DCC bit for
that channel.
Certain M and N values for a channel divider result in a non50% duty cycle. A non-50% duty cycle can also result with an
even division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle.
Rev. 0 | Page 45 of 84
AD9520-4
Duty-cycle correction requires the following channel divider
conditions:
Table 37. Channel Divider Output Duty Cycle When the
VCO Divider is Enabled and Set to 1
• An even division must be set as M = N
Input
Clock
Duty Cycle
Any
N+M+2
Even
50%
Odd
The duty cycle at the output of the channel divider for various
configurations is shown in Table 35 to Table 38.
X%
Odd
Table 35. Channel Divider Output Duty Cycle with VCO
Divider ≠ 1, Input Duty Cycle Is 50%
Note Channel Divider must be enabled when VCO Divider = 1.
• An odd division must be set as M = N + 1
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2) expressed as a percent.
DX
VCO
Divider
Even
Even, odd
N+M+2
Channel
divider
bypassed
Channel
divider
bypassed
Channel
divider
bypassed
Even
Even, odd
Odd
Odd = 3
Odd = 5
Output Duty Cycle
Disable Divider
Disable Div
DCC = 1
DCC = 0
50%
50%
33.3%
50%
(N + 1)/(N + M + 2)
50%; requires
M=N
50%; requires
M=N+1
(N + 1)/(N + M + 2)
Table 36. Channel Divider Output Duty Cycle with VCO
Divider ≠ 1 and Input Duty Cycle Is X%
DX
VCO
Divider
Even
Even
N+M+2
Channel
divider
bypassed
Channel
divider
bypassed
Channel
Divider
bypassed
Even
Even
Odd
Odd = 3
Even
Odd = 3
Odd
Odd = 3
Odd = 5
Odd = 5
Even
Odd = 5
Odd
Input
Clock
Duty Cycle
Any
(1 + X%)/3
40%
(2 + X%)/5
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
50%, requires M = N
DX
Any
N+M+2
Chanel
divider
bypassed
Even
50%
Odd
X%
Odd
Output Duty Cycle
Disable Div
DCC = 1
Disable Div DCC = 0
Same as input Same as input duty
duty cycle
cycle
50%, requires M = N
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
50%, requires M = N + 1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
The internal VCO has a duty cycle of 50%. Therefore, when the
VCO is connected directly to the output, the duty cycle is 50%.
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
Phase Offset or Coarse Time Delay
Output Duty Cycle
Disable Div
DCC = 1
Disable Div DCC = 0
50%
50%
33.3%
Output Duty Cycle
Disable Div
DCC = 1
Disable Div DCC = 0
50%, requires M = N
(N + 1)/
(M + N + 2)
50%, requires M = N + 1
(N + 1)/
(M + N + 2)
(N + 1)/
(N + 1 + X%)/(2 × N + 3),
(M + N + 2)
requires M = N + 1
Table 38. Channel Divider Output Duty Cycle When the
VCO Divider Is Bypassed
50%
40%
DX
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 39).
These settings determine the number of cycles (successive rising
edges) of the channel divider input frequency by which to offset, or
delay, the rising edge of the output of the divider. This delay is
with respect to a nondelayed output (that is, with a phase offset
of zero). The amount of the delay is set by five bits loaded into
the phase offset (PO) register plus the start high (SH) bit for
each channel divider. When the start high bit is set, the delay is
also affected by the number of low cycles (M) programmed for
the divider.
50%, requires M = N + 1
50%, requires M = N
It is necessary to use the SYNC function to make phase offsets
effective (see the Synchronizing the Outputs—SYNC Function
section.)
Table 39. Setting Phase Offset and Division
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
50%, requires M = N
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
Divider
0
1
2
3
Rev. 0 | Page 46 of 84
Start
High (SH)
0x191[4]
0x194[4]
0x197[4]
0x19A[4]
Phase
Offset (PO)
0x191[3:0]
0x194[3:0]
0x197[3:0]
0x19A[3:0]
Low Cycles
M
0x190[7:4]
0x193[7:4]
0x196[7:4]
0x199[7:4]
High Cycles
N
0x190[3:0]
0x193[3:0]
0x196[3:0]
0x199[3:0]
AD9520-4
Let
Δt = delay (in seconds).
Δc = delay (in cycles of clock signal at input to DX).
TX = period of the clock signal at the input of the divider, DX (in
seconds).
Φ=
16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide by is set as N = high cycles and M = low
cycles.
Case 1
For Φ ≤ 15,
Δt = Φ × TX
Δc = Δt/TX = Φ
Case 2
For Φ ≥ 16,
Δt = (Φ − 16 + M + 1) × TX
Δc = Δt/TX
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 48 shows the results of setting such a coarse
offset between outputs.
CHANNEL
DIVIDER INPUT
0
1
2
Tx
3
4
5
6
7
8
9
10 11 12 13 14 15
CHANNEL DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
DIVIDER 1
SH = 0
PO = 1
DIVIDER 2
SH = 0
PO = 2
07217-071
SH = 0
DIVIDER 0 PO = 0
1 × Tx
2 × Tx
Figure 48. Effect of Coarse Phase Offset (or Delay)
Synchronizing the Outputs—SYNC Function
The AD9520 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions. These conditions include the
divider ratio and phase offsets for a given channel divider. This
allows the user to specify different divide ratios and phase offsets
for each of the four channel dividers. Releasing the SYNC pin
allows the outputs to continue clocking with the preset conditions
applied.
Synchronization of the outputs is executed in several ways:
• The SYNC pin is forced low and then released (manual sync).
• By setting and then resetting any one of the following three
bits: the soft SYNC bit (0x230[0]), the soft reset bit (0x000[5]
[mirrored]), and the power-down distribution reference bit
(0x230[1]).
• The RESET pin is forced low and then released (chip reset).
• The PD pin is forced low and then released (chip power-down).
• Whenever a VCO calibration is completed, an internal SYNC
signal is automatically asserted at the beginning and released
upon the completion of a VCO calibration.
The most common way to execute the SYNC function is to use
the SYNC pin to perform a manual synchronization of the
outputs. This requires a low-going signal on the SYNC pin,
which is held low and then released when synchronization is
desired. The timing of the SYNC operation is shown in Figure 49
(using the VCO divider) and in Figure 50 (the VCO divider not
used). There is an uncertainty of up to 1 cycle of the clock at the
input to the channel divider due to the asynchronous nature of
the SYNC signal with respect to the clock edges inside the
AD9520.
The pipeline delay from the SYNC rising edge to the beginning
of the synchronized output clocking is between 14 cycles and
15 cycles of clock at the channel divider input, plus either one
cycle of the VCO divider input (see Figure 49), or one cycle of
the channel divider input (see Figure 50), depending on whether
the VCO divider is used. Cycles are counted from the rising
edge of the signal. In addition, there is an additional 1.2 ns (typical)
delay from the SYNC signal to the internal synchronization logic,
as well as the propagation delay of the output driver. The driver
propagation delay is approximately 100 ps for the LVPECL
driver and approximately 1.5 ns for the CMOS driver.
Another common way to execute the SYNC function is by
setting and resetting the soft SYNC bit at 0x230[0]. Both setting
and resetting of the soft SYNC bit requires an update all registers
(0x232[0] = 1) operation to take effect.
A SYNC operation brings all outputs that have not been excluded
(by the ignore SYNC bit) to a preset condition before allowing
the outputs to begin clocking in synchronicity. The preset condition
takes into account the settings in each of the channel’s start high
bit and its phase offset. These settings govern both the static state
of each output when the SYNC operation is happening and the
state and relative phase of the outputs when they begin clocking
again upon completion of the SYNC operation. Between outputs
and after synchronization, this allows for the setting of phase offsets.
The AD9520 differential LVPECL outputs are four groups of
three, sharing a channel divider per triplet. In the case of CMOS,
each LVPECL differential pair can be configured as two singleended CMOS outputs. The synchronization conditions apply to
all of the drivers that belong to that channel divider.
Each channel (a divider and its outputs) can be excluded from
any SYNC operation by setting the no sync bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a SYNC operation, and their
outputs are not synchronized with those of the included channels.
• Synchronization of the outputs can be executed as part of the
chip power-up sequence.
Rev. 0 | Page 47 of 84
AD9520-4
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER OUTPUT STATIC
INPUT TO VCO DIVIDER
1
1
INPUT TO CHANNEL DIVIDER
2
3
4
5
6
7
8
9
10
11
12
13
14
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
07217-073
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
Figure 49. SYNC Timing Pipeline Delay When VCO Divider Is Used—CLK or VCO Is Input
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER OUTPUT STATIC
INPUT TO CLK
INPUT TO CHANNEL DIVIDER
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
07217-074
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
Figure 50. SYNC Timing Pipeline Delay When VCO Divider Is Not Used—CLK Input Only
LVPECL Output Drivers
The LVPECL differential voltage (VOD) is selectable (from
~400 mV to 960 mV, see Bit 1 and Bit 2 in Register 0x0F0 to
Register 0x0FB. The LVPECL outputs have dedicated pins for
power supply (VS_DRV), allowing a separate power supply to
be used. VS_DRV can be from 2.5 V to 3.3 V.
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
For this reason, the LVPECL outputs have two power-down
modes: total power-down and safe power-down.
In total power-down mode, all output drivers are shut off
simultaneously. This mode must not be used if there is an
external voltage bias network (such as Thevenin equivalent
termination) on the output pins that will cause a dc voltage to
appear at the powered down outputs. However, total powerdown mode is allowed when the LVPECL drivers are terminated
using only pull-down resistors. The total power-down mode is
activated by setting 0x230[1].
The primary power-down mode is the safe power-down mode.
This mode continues to protect the output devices while powered
down. There are three ways to activate safe power-down mode:
individually set the power-down bit for each driver, power down an
individual output channel (all of the drivers associated with that
channel are powered down automatically), and activate sleep mode.
Rev. 0 | Page 48 of 84
AD9520-4
Hardware Reset via the RESET Pin
SW1B
SW1A
R2
200Ω
R1
200Ω
N1
N2
RESET, a hard reset (an asynchronous hard reset is executed by
briefly pulling RESET low), restores the chip either to the setting
stored in EEPROM (the EEPROM pin = 1) or to the on-chip
setting (the EEPROM pin = 0). A hard reset also executes a
SYNC operation, which brings the outputs into phase
alignment according to the default settings. When EEPROM is
inactive (the EEPROM pin = 0), it takes ~2 μs for the outputs to
begin toggling after RESET is issued. When EEPROM is active
(the EEPROM pin = 1), it takes ~20 ms for the outputs to toggle
after RESET is brought high.
QN1
OUT
QN2
OUT
07217-058
SW2
4.4mA
Soft Reset via the Serial Port
Figure 51. LVPECL Output Simplified Equivalent Circuit
CMOS Output Drivers
The user can also individually configure each LVPECL output
as a pair of CMOS outputs, which provides up to 24 CMOS
outputs. When an output is configured as CMOS, the CMOS
Output A and CMOS Output B are automatically turned on. For
a given differential pair, either the CMOS Output A or Output B
can be turned on or off independently. The user can also select
the relative polarity of the CMOS outputs for any combination of
inverting and noninverting (see Register 0x0F0 to Register 0x0FB).
The user can power down each CMOS output as needed to save
power. The CMOS output power-down is individually controlled
by the enable CMOS output register (0x0F0[6:5] to 0x0FB[6:5]).
The CMOS driver is in tristate when it is powered down.
VS_DRV
The serial port control register allows for a soft reset by setting
Bit 2 and Bit 5 in Register 0x000. When Bit 5 and Bit 2 are set,
the chip enters a soft reset mode and restores the chip either to
the setting stored in EEPROM (the EEPROM pin = 1) or to the
on-chip setting (the EEPROM pin = 0), except for Register 0x000.
These bits are self-clearing. During the internal reset, the outputs
are held static.
Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via
the Serial Port
The serial port control register allows the chip to be reset to
settings in EEPROM when the EEPROM pin = 1 via 0xB02[1].
This bit is self-clearing. This bit does not have any effect when
EEPROM pin = 0. It takes ~20 ms for the outputs to begin
toggling after soft_EEPROM register is cleared.
POWER-DOWN MODES
Chip Power-Down via PD
OUT1/
OUT1
07217-035
The AD9520 can be put into a power-down condition by
pulling the PD pin low. Power-down turns off most of the
functions and currents inside the AD9520. The chip remains in
this power-down state until PD is brought back to logic high.
When taken out of power down mode, the AD9520 returns to
the settings programmed into its registers prior to the powerdown, unless the registers are changed by new programming
while the PD pin is held low.
Figure 52. CMOS Equivalent Output Circuit
RESET MODES
The AD9520 has a power-on reset (POR) and several other
ways to apply a reset condition to the chip.
Power-On Reset
During chip power-up, a power-on reset pulse is issued when
VS reaches ~2.6 V (<2.8 V) and restores the chip either to the
setting stored in EEPROM (with the EEPROM pin = 1) or to
the on-chip setting (with the EEPROM pin = 0). At power-on,
the AD9520 also executes a SYNC operation, which brings the
outputs into phase alignment according to the default settings.
It takes ~70 ms for the outputs to begin toggling after the
power-on reset pulse signal is internally generated.
Powering down the chip shuts down the currents on the chip,
except the bias current necessary to maintain the LVPECL
outputs in a safe shutdown mode. The LVPECL bias currents are
needed to protect the LVPECL output circuitry from damage that
can be caused by certain termination and load configurations
when tristated. Because this is not a complete power-down, it
can be called sleep mode. The AD9520 contains special circuitry to
prevent runt pulses on the outputs when the chip is entering or
exiting sleep mode.
Rev. 0 | Page 49 of 84
AD9520-4
Distribution Power-Down
When the AD9520 is in a PD power-down, the chip is in the
following state:
•
The PLL is off (asynchronous power-down).
•
The VCO is off.
•
The CLK input buffer is off, but the CLK input dc bias
circuit is on.
•
In differential mode, the reference input buffer is off, but
the dc bias circuit is still on.
•
In singled-ended mode, the reference input buffer is off,
but the dc bias circuit is off.
•
All dividers are off.
•
All CMOS outputs are tristated.
•
All LVPECL outputs are in safe off mode.
•
The serial control port is active, and the chip responds to
commands.
PLL Power-Down
The PLL section of the AD9520 can be selectively powered
down. There are two PLL power-down modes set by
Register 0x010[1:0]: asynchronous and synchronous.
In asynchronous power-down mode, the device powers down as
soon as the registers are updated. In synchronous power-down
mode, the PLL power-down is gated by the charge pump to
prevent unwanted frequency jumps. The device goes into powerdown on the occurrence of the next charge pump event after the
registers are updated.
The distribution section can be powered down by writing
0x230[1] = 1b, which turns off the bias to the distribution
section. If the LVPECL power-down mode is in normal
operation (0b), it is possible for a low impedance load on that
LVPECL output to draw significant current during this powerdown. If the LVPECL power-down mode is set to 1b, the
LVPECL output is not protected from reverse bias and can be
damaged under certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down
into safe power-down mode by individually writing to the
appropriate registers. The register map details the individual
power-down settings for each output. These settings are found
in 0x0F0[0] to 0x0FD[0].
Individual Clock Channel Power-Down
Any of the clock distribution channels can be powered down
individually by writing to the appropriate registers. Powering
down a clock channel is similar to powering down an individual
driver, but it saves more power because the dividers are also
powered down. Powering down a clock channel also automatically
powers down the drivers connected to it. The register map
details the individual power-down settings for each output
channel. These settings are found in 0x192[2], 0x195[2],
0x198[2], and 0x19B[2].
Rev. 0 | Page 50 of 84
AD9520-4
SERIAL CONTROL PORT
The AD9520 serial control port is a flexible, synchronous serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9520 serial control port is compatible with most synchronous
transfer formats, including Philips I2C, Motorola® SPI®, and
Intel® SSR® protocols. The AD9520 I2C implementation deviates
from the classic I2C specification on two specifications, and these
deviations are documented in Table 14. The serial control port
allows read/write access to all registers that configure the AD9520.
SPI/I²C PORT SELECTION
The AD9520 has two serial interfaces, SPI and I2C. Users can
select either SPI or I2C depending on the states of the three
logic level (high, open, low) input pins, SP1 and SP0. When
both SP1 and SP0 are high, SPI interface is active. Otherwise,
I2C is active with eight different I2C slave address (seven bits
wide) settings, see Table 40. The four MSBs of the slave address
are hardware coded as 1011 and the three LSBs are
programmed by SP1 and SP0.
Table 40. Serial Port Mode Selection
Abbreviation
S
Sr
P
A
A
W
R
Definition
Start
Repeated start
Stop
Acknowledge
No acknowledge
Write
Read
One pulse on the SCL clock line is generated for each data bit
transferred.
The data on the SDA line must not change during the high
period of the clock. The state of the data line can only change when
the clock on the SCL line is low.
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
SDA
Address
I²C, 1011000
I²C, 1011001
I²C, 1011010
I²C, 1011011
I²C, 1011100
I²C, 1011101
I²C, 1011110
I²C, 1011111
SPI
07217-160
SP0
Low
Open
High
Low
Open
High
Low
Open
High
Table 41. I2C Bus Definitions
SCL
Figure 53. Valid Bit Transfer
A start condition is a transition from high-to-low on the SDA
line while SCL is high. The start condition is always generated
by the master to initial data transfer.
A stop condition is a transition from low-to-high on the SDA
line while SCL is high. The stop condition is always generated
by the master to end data transfer.
I²C SERIAL PORT OPERATION
SDA
The AD9520 I2C port is designed based on the I2C fast mode
standard. The AD9520 supports both I2C protocols: standard
mode (100 kHz) and fast mode (400 kHz).
The AD9520 I2C port has a 2-wire interface consisting of a serial
data line (SDA) and a serial clock line (SCL). In an I2C bus system,
the AD9520 is connected to the serial bus (data bus SDA and
clock bus SCL) as a slave device, meaning that no clock is generated
by the AD9520. The AD9520 uses direct 16-bit (2 bytes) memory
addressing instead of traditional 8-bit (1 byte) memory addressing.
SCL
S
P
START
CONDITION
STOP
CONDITION
07217-161
SP1
Low
Low
Low
Open
Open
Open
High
High
High
I2C Bus Characteristics
Figure 54. Start and Stop Condition
A byte on the SDA line is always 8-bits long. An Acknowledge
Bit must follow every byte. Bytes are sent MSB first.
The acknowledge bit is the ninth bit attached to any 8-bit data
byte. An acknowledge bit is always generated by the receiving
device (receiver) to inform the transmitter that the byte has
been received. It is done by pulling the SDA line low during the
ninth clock pulse after each 8-bit data byte.
Rev. 0 | Page 51 of 84
AD9520-4
MSB
ACKNOWLEDGE FROM
SLAVE-RECEIVER
1
SCL
2
3 TO 7
8
9
1
ACKNOWLEDGE FROM
SLAVE-RECEIVER
2
3 TO 7
8
9
S
10
P
07217-162
SDA
Figure 55. Acknowledge Bit
MSB = 0
1
SCL
2
3 TO 7
8
9
1
ACKNOWLEDGE FROM
SLAVE-RECEIVER
2
3 TO 7
8
9
S
10
P
07217-163
ACKNOWLEDGE FROM
SLAVE-RECEIVER
10
P
07217-164
SDA
Figure 56. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration)
MSB = 1
SDA
ACKNOWLEDGE FROM
MASTER-RECEIVER
1
SCL
2
3 TO 7
8
9
1
NO ACKNOWLEDGE
FROM
SLAVE-RECEIVER
2
3 TO 7
8
S
9
Figure 57. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration)
No acknowledge bit: this bit is the ninth bit attached to any
8-bit data byte. A no acknowledge bit is always generated by
the receiving device (receiver) to inform the transmitter that the
byte has not been received. It is done by leaving the SDA line
high during the ninth clock pulse after each 8-bit data byte.
Data Transfer Process
The master initiates data transfer by asserting a start condition.
This indicates that a data stream follows. All I2C slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device
(0 = write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other
devices on the bus remain idle while the selected device waits
for data to be read from or written to it. If the R/W bit is 0, the
master (transmitter) writes to the slave device (receiver). If the
R/W bit is 1, the master (receiver) reads from the slave device
(transmitter).
The format for these commands is described in the Data
Transfer Format section.
Data is then sent over the serial bus in the format of nine clock
pulses, one data byte (8-bit) from either master (write mode) or
from slave (read mode) followed by an acknowledge bit from
the receiving device. The number of bytes that can be transmitted
per transfer is unrestricted. In write mode, the first two data
bytes immediately after the slave address byte are the internal
memory (control registers) address bytes with the high address
byte first. This addressing scheme gives a memory address up to
216 − 1 = 65535. The data bytes after these two memory address
bytes are register data written into the control registers. In read
mode, the data bytes after the slave address byte are register
data read from the control registers.
When all data bytes are read or written, stop conditions are
established. In write mode, the master (transmitter) asserts a
stop condition to end data transfer during the (10th) clock
pulse following the acknowledge bit for the last data byte from
slave device (receiver). In read mode, the master device (receiver)
receives the last data byte from the slave device (transmitter)
but does not pull it low during the ninth clock pulse. This is
known as a no acknowledge bit. By receiving the no acknowledge
bit, the slave device knows the data transfer is finished and
releases the SDA line. The master then takes the data line low
during the low period before the 10th clock pulse, and high
during the 10th clock pulse to assert a stop condition.
A repeated start (Sr) condition can be used in place of a stop
condition. Furthermore, a start or stop condition can occur at
any time and partially transferred bytes are discarded.
Rev. 0 | Page 52 of 84
AD9520-4
Data Transfer Format
Send byte format—the send byte protocol is used to set up the register address for subsequent commands.
S
Slave Address
W
A
RAM Address High Byte
A
RAM Address Low Byte
A
P
Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
S
Slave Address
W
A
RAM Address
High Byte
A
RAM Address
Low Byte
A
RAM Data 0
A
RAM Data 1
A
RAM Data 2
A
P
Receive byte format—the receive byte protocol is used to read the data byte(s) from RAM starting from the current address.
S
Slave Address
R
A
RAM Data 0
A
RAM Data 1
A
A
RAM Data 2
P
Read byte format—the combined format of the send byte and the receive byte.
S
Slave
Address
W
RAM Address
High Byte
A
A
RAM Address
Low Byte
A
Sr
Slave
Address
R
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
I²C Serial Port Timing
SDA
tSET; DAT
tFALL
tLOW
tFALL
tHLD; STR
tRISE
tSPIKE
tRISE
tIDLE
tHLD; STR
tHLD; DAT
S
tHIGH
tSET; STP
tSET; STR
Sr
Figure 58. I²C Serial Port Timing
Table 42. I2C Timing Definitions
Parameter
fI2C
tIDLE
tHLD; STR
tSET; STR
tSET; STP
tHLD; DAT
tSET; DAT
tLOW
tHIGH
tRISE
tFALL
tSPIKE
Description
I²C clock frequency
Bus idle time between stop and start conditions
Hold time for repeated start condition
Setup time for repeated start condition
Setup time for stop condition
Hold time for data
Setup time for data
Duration of SCL clock low
Duration of SCL clock high
SCL/SDA rise time
SCL/SDA fall time
Voltage spike pulse width that must be suppressed by input filter
Rev. 0 | Page 53 of 84
P
S
07217-165
SCL
P
AD9520-4
SPI SERIAL PORT OPERATION
Pin Descriptions
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and writes.
Write data bits are registered on the rising edge of this clock,
and read data bits are registered on the falling edge. This pin is
internally pulled down by a 30 kΩ resistor to ground.
SDIO (serial data input/output) is a dual purpose pin and acts
either as an input only (unidirectional mode) or as both an
input/output (bidirectional mode). The AD9520 defaults to the
bidirectional I/O mode (0x000[7] = 0).
SDO (serial data out) is used only in the unidirectional I/O
mode (0x000[7]) as a separate output pin for reading back data.
CS (chip select bar) is an active low control that gates the read
and write cycles. When CS is high, SDO and SDIO are in a high
impedance state. This pin is internally pulled up by a 30 kΩ
resistor to VS.
15
16
SDIO/SDA
17
SDO
18
AD9520
SERIAL
CONTROL
PORT
07217-036
CS
SCLK/SCL
Figure 59. Serial Control Port
SPI Mode Operation
In SPI mode, single or multiple byte transfers are supported, as
well as MSB first or LSB first transfer formats. The AD9520
serial control port can be configured for a single bidirectional
I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/
SDO). By default, the AD9520 is in bidirectional mode. Short
instruction mode (8-bit instructions) is not supported. Only
long (16-bit) instruction mode is supported.
A write or a read operation to the AD9520 is initiated by pulling
CS low.
The CS stalled high mode is supported in data transfers where
three or fewer bytes of data (plus instruction data) are transferred
(see Table 43). In this mode, the CS pin can temporarily return
high on any byte boundary, allowing time for the system controller
to process the next byte. CS can go high on byte boundaries only
and can go high during either part (instruction or data) of the
transfer.
During this period, the serial control port state machine enters
a wait state until all data is sent. If the system controller decides
to abort the transfer before all of the data is sent, the state machine
must be reset by either completing the remaining transfers or by
returning the CS low for at least one complete SCLK cycle (but
less than eight SCLK cycles). Raising the CS pin on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
In the streaming mode (see Table 43), any number of data bytes
can be transferred in a continuous stream. The register address
is automatically incremented or decremented (see the SPI
MSB/LSB First Transfers section). CS must be raised at the end
of the last byte to be transferred, thereby ending the stream mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9520.
The first writes a 16-bit instruction word into the AD9520,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9520 serial control port with information
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
If the instruction word is for a write operation, the second part
is the transfer of data into the serial control port buffer of the
AD9520. Data bits are registered on the rising edge of SCLK.
The length of the transfer (one, two, or three bytes or streaming
mode) is indicated by two bits (W1:W0) in the instruction byte.
When the transfer is one, two, or three bytes, but not streaming,
CS can be raised after each sequence of eight bits to stall the bus
(except after the last byte, where it ends the cycle). When the bus
is stalled, the serial transfer resumes when CS is lowered. Raising
the CS pin on a nonbyte boundary resets the serial control port.
During a write, streaming mode does not skip over reserved or
blank registers; therefore, the user must know what bit pattern
to write to the reserved registers to preserve proper operation of
the part. It does not matter what data is written to blank registers.
Because data is written into a serial control port buffer area, not
directly into the actual control registers of the AD9520, an
additional operation is needed to transfer the serial control port
buffer contents to the actual control registers of the AD9520,
thereby causing them to become active. The update registers
operation consists of setting 0x232[0] = 1b (this bit is selfclearing). Any number of bytes of data can be changed before
executing an update registers. The update registers simultaneously
actuates all register changes that have been written to the buffer
since any previous update.
Read
The AD9520 supports only the long instruction mode. If the
instruction word is for a read operation, the next N × 8 SCLK
cycles clock out the data from the address specified in the
instruction word, where N is 1 to 3 as determined by W1:W0.
If N = 4, the read operation is in streaming mode, continuing
until CS is raised. Streaming mode does not skip over reserved
or blank registers. The readback data is valid on the falling
edge of SCLK.
Rev. 0 | Page 54 of 84
AD9520-4
The default mode of the AD9520 serial control port is the
bidirectional mode. In bidirectional mode, both the sent data
and the readback data appear on the SDIO pin. It is also possible to
set the AD9520 to unidirectional mode (0x000[7] = 1 and
0x000[0] = 1). In unidirectional mode, the readback data appears
on the SDO pin.
SPI MSB/LSB FIRST TRANSFERS
The AD9520 uses Register Address 0x000 to Register Address 0xB03.
The default for the AD9520 is MSB first.
SDO
SERIAL
CONTROL
PORT
UPDATE
REGISTERS
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from the high address to the
low address. In MSB first mode, the serial control port internal
address generator decrements for each data byte of the multibyte
transfer cycle.
07217-037
SDIO/SDA
When LSB first is set by 0x000[2] and 0x000[6], it takes effect
immediately, because it only affects the operation of the serial
control port and does not require that an update be executed.
ACTIVE REGISTERS
CS
SCLK/SCL
BUFFER REGISTERS
A readback request reads the data that is in the serial control
port buffer area, or the data in the active registers (see Figure 60).
Readback of the buffer or active registers is controlled by 0x004[0].
The AD9520 instruction word and byte data can be MSB first
or LSB first. Any data written to 0x000 must be mirrored, the
upper four bits ([7:4]) must mirror the lower four bits ([3:0]).
This makes it irrelevant whether LSB first or MSB first is in
effect. As an example of this mirroring, see the default setting
for 0x000, which mirrors Bit 4 and Bit 3. This sets the long
instruction mode, which is the default and the only mode
supported.
WRITE REGISTER 0x232 = 0x001
TO UPDATE REGISTERS
Figure 60. Relationship Between Serial Control Port Buffer Registers and
Active Registers of the AD9520
SPI INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits
(W1:W0) indicate the length of the transfer in bytes. The final
13 bits are the address (A12:A0) at which to begin the read or
write operation.
When LSB first is active, the instruction and data bytes must be
written from LSB to MSB. Multibyte data transfers in LSB first
format start with an instruction byte that includes the register
address of the least significant data byte followed by multiple
data bytes. In a multibyte transfer cycle, the internal byte
address generator of the serial port increments for each byte.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits W1:W0, see Table 43.
The AD9520 serial control port register address decrements
from the register address just written toward 0x000 for multibyte
I/O operations if the MSB first mode is active (default). If the
LSB first mode is active, the register address of the serial control
port increments from the address just written toward 0x232 for
multibyte I/O operations.
Table 43. Byte Transfer Count
W1
0
0
1
1
W0
0
1
0
1
Bytes to Transfer
1
2
3
Streaming mode
Streaming mode always terminates when it reaches 0x232. Note
that unused addresses are not skipped during multibyte I/O
operations.
A12:A0: These 13 bits select the address within the register map
that is written to or read from during the data transfer portion
of the communications cycle. Only Bits[A9:A0] are needed to
cover the range of the 0x232 registers used by the AD9520.
Bits[A12:A10] must always be 0b. For multibyte transfers, this
address is the starting byte address. In MSB first mode, subsequent
bytes increment the address.
Table 44. Streaming Mode (No Addresses Are Skipped)
Write Mode
LSB first
MSB first
Address Direction
Increment
Decrement
Stop Sequence
0x230, 0x231, 0x232, stop
0x001, 0x000, 0x232, stop
Table 45. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
LSB
R/W
W1
W0
A12 = 0
A11 = 0
A10 = 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Rev. 0 | Page 55 of 84
AD9520-4
CS
SCLK DON'T CARE
SDIO DON'T CARE
R/W W1 W0 A12 A11 A10 A9
A8
A7
A6 A5
A4 A3 A2
A1 A0
D7 D6 D5
16-BIT INSTRUCTION HEADER
D4 D3
D2 D1
D0
D7
D6 D5
REGISTER (N) DATA
D4 D3 D2
D1 D0
DON'T CARE
REGISTER (N – 1) DATA
07217-038
DON'T CARE
Figure 61. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data
CS
SCLK
DON'T CARE
SDIO
DON'T CARE
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDO DON'T CARE
REGISTER (N) DATA
REGISTER (N – 1) DATA
REGISTER (N – 2) DATA
REGISTER (N – 3) DATA
DON'T
CARE
07217-039
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER
Figure 62. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data
tHIGH
tDS
tS
DON'T CARE
SDIO
DON'T CARE
tLOW
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
07217-040
SCLK
tC
tCLK
tDH
CS
Figure 63. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
CS
SCLK
DATA BIT N
07217-041
tDV
SDIO
SDO
DATA BIT N – 1
Figure 64. Timing Diagram for Serial Control Port Register Read
CS
SCLK DON'T CARE
A0 A1 A2 A3
A4
A5 A6 A7
A8
A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4
16-BIT INSTRUCTION HEADER
D5 D6
REGISTER (N) DATA
D7
D0
D1 D2
D6
REGISTER (N + 1) DATA
Figure 65. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data
Rev. 0 | Page 56 of 84
D3 D4 D5
D7
DON'T CARE
07217-042
SDIO DON'T CARE
DON'T CARE
AD9520-4
tS
tC
CS
tCLK
tHIGH
SCLK
tLOW
tDS
SDIO
BIT N
BIT N + 1
Figure 66. Serial Control Port Timing—Write
Table 46. Serial Control Port Timing
Parameter
tDS
tDH
tCLK
tS
tC
tHIGH
tLOW
tDV
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CS falling edge and SCLK rising edge (start of communication cycle)
Setup time between SCLK rising edge and CS rising edge (end of communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 64)
Rev. 0 | Page 57 of 84
07217-043
tDH
AD9520-4
EEPROM OPERATIONS
The readback register STATUS_EEPROM (0xB00[0]) is
used to indicate the data transfer status between the
EEPROM and the control registers (0 = done/inactive;
1 = in process/ active). At the beginning of the data
transfer, STATUS_EEPROM is set to 1 by the EEPROM
controller and cleared to 0 at the end of the data transfer.
The user can access STATUS_EEPROM through the
STATUS pin when the STATUS pin is programmed to
monitor STATUS_EEPROM. Alternately, the user can
monitor the STATUS_EEPROM bit.
The AD9520 contains an internal EEPROM (nonvolatile memory).
The EEPROM can be programmed by customers to create and
store a user-defined register setting file when power is off. This
setting file can be used for power-up and chip reset as a default
setting. The EEPROM size is 512 bytes.
During the data transfer process, the write and read registers via
the serial port are generally not available except for one readback
register, STATUS_EEPROM.
To determine the data transfer state through the serial port
in SPI mode, users can read the value of STATUS_EEPROM
(1 = in process and 0 = completed).
•
In I2C mode, the user can address the AD9520 slave port with
the external I2C master (send an address byte to the AD9520). If
the AD9520 responds with a no acknowledge bit, the data transfer
process is not done. If the AD9520 responds with an acknowledge
bit, the data transfer process is completed. The user can monitor
the STATUS_EEPROM register or program the STATUS pin to
monitor the status of the data transfer.
WRITING TO THE EEPROM
The EEPROM cannot be programmed directly through the serial
port interface. To program the EEPROM and store a register
setting file, do the following:
•
•
Program the AD9520 registers to the desired circuit state. If
the user wants the PLL to lock automatically after power-up,
the VCO calibration now bit (0x018[0]) must be set to 1.
This allows VCO calibration to start automatically after
register loading. Note that a valid input reference signal
must be present during VCO calibration.
Program the EEPROM buffer registers, if necessary (see
the Programming the EEPROM Buffer Segment section).
This is only necessary if users want to use the EEPROM to
control the default setting of some (but not all) of the
AD9520 registers, or if they want to control the register
setting update sequence during power-up or chip reset.
•
Set the enable EEPROM write bit (0xB02[0]) to 1 to enable
the EEPROM.
•
Set the REG2EEPROM bit (0xB03[0]) to 1.
•
Set the IO_UPDATE bit (0x232[0]) to 1, which starts the
process of writing data into the EEPROM to create the
EEPROM setting file. This enables the AD9520 EEPROM
controller to transfer the current register values, as well as
the memory address and instruction bytes from the EEPROM
buffer segment into the EEPROM. After the write process
is completed, the internal controller sets 0xB03[0]
(REG2EEPROM) back to 0.
After the data transfer process is done (0xB00[0] = 0), set
the enable EEPROM write register (0xB02[0]) to 0 to disable
the EEPROM.
To verify that the data transfer has completed correctly, the user
can verify that 0xB01[0] = 0. A value of 1 in this register indicates a
data transfer error.
READING FROM THE EEPROM
The following reset-related events can start the process of
restoring the settings stored in EEPROM to control registers.
When the EEPROM pin is set high, do any of the following:
•
Power-up
•
Perform a hardware chip reset by pulling the RESET pin
low, and then releasing RESET
•
Set the self-clearing soft reset bit (0x000[5]) to 1
When the EEPROM pin is set low, set the self-clearing
Soft_EEPROM bit (0xB02[1]) to 1. The AD9520 then starts to
read the EEPROM and loads the values into the AD9520.
If the EEPROM pin is low during reset or power-up, the
EEPROM is not active, and the AD9520 default values are
loaded instead.
Note that when using the EEPROM to automatically load the
AD9520 register values and lock the PLL, the VCO calibration
now bit (0x018[0]) must be set to 1 when the register values are
written to the EEPROM. This allows VCO calibration to start
automatically after register loading. A valid input reference
signal must be present during VCO calibration.
To verify that the data transfer has completed correctly, the user
can verify that 0xB01[0] = 0. A value of 1 in this register indicates a
data transfer error.
Rev. 0 | Page 58 of 84
AD9520-4
PROGRAMMING THE EEPROM BUFFER SEGMENT
IO_UPDATE (Operational Code 0x80)
The EEPROM buffer segment is a register space on the AD9520
that allows the user to specify which groups of registers are stored
to the EEPROM during EEPROM programming. Normally, this
segment does not need to be programmed by the user. Instead, the
default power-up values for the EEPROM buffer segment allow
the user to store all of the AD9520 register values from
Register 0x000 to Register 0x231 to the EEPROM.
The EEPROM controller uses this operational code to generate
an IO_UPDATE signal to update the active control register
bank from the buffer register bank during the download process.
For example, a user only wants to load the output driver settings
from the EEPROM without disturbing the PLL register settings
currently stored in the AD9520. The user can alter the EEPROM
buffer segment to include only the registers that apply to the
output drivers and exclude the registers that apply to the PLL
configuration.
There are two parts to the EEPROM buffer segment: register
section definition groups and operational codes. Each register
section definition group contains the starting address and
number of bytes to be written to the EEPROM.
If the AD9520 register map were continuous from Address 0x000
to Address 0x232, only one register section definition group
would consist of a starting address of 0x000 and a length of 563
bytes. However, this is not the case. The AD9520 register map is
noncontiguous, and the EEPROM is only 512 bytes long.
Therefore, the register section definition group tells the EEPROM
controller how the AD9520 register map is segmented.
There are three operational codes: IO_UPDATE, end-of-data,
and pseudo-end-of-data. It is important that the EEPROM buffer
segment always have either an end-of-data or a pseudo-end-of-data
operational code and that an IO_UPDATE operation code appear
at least once before the end-of-data operational code.
Register Section Definition Group
The register section definition group is used to define a continuous
register section for the EEPROM profile. It consists of three bytes.
The first byte defines how many continuous register bytes are in
this group: If the user puts 0x000 in the first byte, it means there
is only one byte in this group. If the user puts 0x001, it means
there are two bytes in this group. The maximum number of
registers in one group is 128.
At a minimum, there should be at least one IO_UPDATE
operational code after the end of the final register section definition
group. The reason this is needed is so that at least one IO_UPDATE
occurs after all of the AD9520 registers are loaded when the
EEPROM is read. If this operational code is absent during a
write to the EEPROM, the register values loaded from the
EEPROM are not transferred to the active register space, and
these values do not take effect after they are loaded from the
EEPROM to the AD9520.
End-of-Data (Operational Code 0xFF)
The EEPROM controller uses this operational code to terminate
the data transfer process between EEPROM and the control
register during the upload and download process. The last item
appearing in the EEPROM buffer segment should be either this
operational code or the pseudo-end-of-data operational code.
Pseudo-End-of-Data (Operational Code 0xFE)
The AD9520 EEPROM buffer segment has 23 bytes that can
contain up to seven register section definition groups. If users
want to define more than seven register section definition
groups, the pseudo-end-of-data operational code can be used.
During the upload process, when the EEPROM controller
receives the pseudo-end-of-data operational code, it halts the
data transfer process and clears the REG2EEPROM bit and
enables the AD9520 serial port. Users can then program the
EEPROM buffer segment again and reinitiate the data transfer
process by setting the REG2EEPROM bit (0xB03) to 1 and the
IO_UPDATE register (0x232) to 1. The internal I2C master then
begins writing to the EEPROM starting from the EEPROM address
held from the last writing.
This sequence permits the user with more discrete instructions
that can be written to the EEPROM than would have otherwise
been possible due to the limited size of the EEPROM buffer
segment. It also permits the user to write the same register
multiple times with a different value each time.
The next two bytes are the low byte and high byte of the
memory address (16-bit) of the first register in this group.
Rev. 0 | Page 59 of 84
AD9520-4
Table 47. Example of EEPROM Buffer Segment
Reg Addr (Hex)
Bit 7 (MSB)
Start EEPROM Buffer Segment
0xA00
0
0xA01
Bit 5
Bit 4
Bit 3
Bit 2
Number of bytes [6:0] of first group of registers
Address [7:0] of first group of registers
0
Number of bytes [6:0] of second group of registers
0xA04
Address [15:8] of second group of registers
0xA05
Address [7:0] of second group of registers
0xA06
Bit 1
Address [15:8] of first group of registers
0xA02
0xA03
Bit 6
0
Number of bytes [6:0] of third group of registers
0xA07
Address [15:8] of third group of registers
0xA08
Address [7:0] of third group of registers
0xA09
IO_UPDATE operational code (0x80)
0xA0A
End-of-data operational code (0xFF)
Rev. 0 | Page 60 of 84
Bit 0 (LSB)
AD9520-4
THERMAL PERFORMANCE
Table 48. Thermal Parameters for 64-Lead LFCSP
Symbol
θJA
θJMA
θJMA
ΨJB
θJC
ΨJT
Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board
Junction-to-ambient thermal resistance, 0.0 m/sec air flow per JEDEC JESD51-2 (still air)
Junction-to-ambient thermal resistance, 1.0 m/sec air flow per JEDEC JESD51-6 (moving air)
Junction-to-ambient thermal resistance, 2.0 m/sec air flow per JEDEC JESD51-6 (moving air)
Junction-to-board characterization parameter, 1.0 m/sec air flow per JEDEC JESD51-6 (moving air) and
JEDEC JESD51-8
Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1
Junction-to-top-of-package characterization parameter, 0 m/sec air flow per JEDEC JESD51-2 (still air)
The AD9520 is specified for a case temperature (TCASE). To ensure
that TCASE is not exceeded, an airflow source can be used.
Use the following equation to determine the junction
temperature on the application PCB:
Value (°C/W)
22.0
19.2
17.2
11.6
1.3
0.1
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order
approximation of TJ by the equation
TJ = TA + (θJA × PD)
where TA is the ambient temperature (°C).
TJ = TCASE + (ΨJT × PD)
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by the customer at
the top center of package.
ΨJT is the value from Table 48.
PD is the power dissipation (see the total power dissipation in
the Table 18).
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of ΨJB are provided for package comparison and PCB
design considerations.
Rev. 0 | Page 61 of 84
AD9520-4
REGISTER MAP
Register addresses that are not listed in Table 49 are not used, and writing to those registers has no effect. Writing to register addresses
marked unused also has no effect.
Table 49. Register Map Overview
Addr
(Hex) Parameter
Serial Port Configuration
000
Serial port config
(SPI mode)
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value
(Hex)
SDO active
LSB first/
addr incr
Soft reset
(selfclearing)
Soft reset
(selfclearing)
Unused
Unused
LSB first/
addr incr
SD0 active
00
Unused
Unused
Soft reset
(selfclearing)
Soft reset
(selfclearing)
Unused
Unused
00
Serial port config
(I²C mode)
Unused
001
002
Unused
Reserved
N/A
003
004
Reserved
N/A
00
Readback
control
EEPROM ID
005
EEPROM
customer
006
version ID
007
to
00F
PLL
010
PFD charge
pump
011
R counter
012
013
A counter
014
B counter
015
016
PLL_CTRL_1
N/A
Unused
PFD polarity
017
PLL_CTRL_2
018
PLL_CTRL_3
019
PLL_CTRL_4
01A
PLL_CTRL_5
Enable STATUS
pin divider
01B
PLL_CTRL_6
Enable VCO
frequency
monitor
01C
PLL_CTRL_7
Disable
switchover
deglitch
01D
PLL_CTRL_8
Enable
Status_EEPROM
at STATUS pin
Enable CMOS
reference input
dc offset
EEPROM customer version ID (LSB)
00
EEPROM customer version ID (MSB)
00
Unused
00
Charge pump current
Charge pump mode
PLL power-down
14-bit R counter, Bits[7:0] (LSB)
14-bit R counter, Bits[13:8] (MSB)
6-bit A counter
13-bit B counter, Bits[7:0] (LSB)
Unused
Unused
Set CP pin
to VCP/2
Readback
active regs
Unused
Reset
R counter
Reset
Reset all
A and B
counters
counters
STATUS pin control
R, A, B counters
SYNC pin reset
Ref freq
monitor
threshold
Enable
REF2
(REFIN)
frequency
monitor
Select
REF2
Enable
XTAL
OSC
01
00
00
03
13-bit B counter, Bits[12:8] (MSB)
B counter
Prescaler P
bypass
00
06
Antibacklash pulse width
Disable
Digital
digital
lock
lock detect
detect
window
R path delay
Lock detect counter
VCO calibration divider
VCO
calibration
now
N path delay
Use
REF_SEL
pin
Enable
clock
doubler
06
00
REFMON pin control
Enable
automatic
reference
switchover
Disable
PLL status
register
00
00
LD pin control
Enable
REF1
(REFIN)
frequency
monitor
7D
00
Stay on REF2
Enable
REF2
Enable
REF1
Enable
differential
reference
00
Enable LD
pin
comparator
Unused
Enable
external
holdover
Enable
holdover
80
Rev. 0 | Page 62 of 84
AD9520-4
Addr
(Hex)
01E
01F
Parameter
PLL_CTRL_9
Bit 7 (MSB)
PLL_Readback
(read-only)
Unused
Bit 6
Unused
VCO cal
finished
Bit 5
Holdover
active
Bit 4
Bit 3
External zero delay
feedback
channel divider select
REF2
VCO freq >
selected
threshold
Bit 2
Enable
external
zero delay
REF2
freq >
threshold
Bit 1
Enable
zero delay
Bit 0 (LSB)
Unused
REF1 freq >
threshold
Digital lock
detect
N/A
OUT0
LVPECL
power-down
OUT1
LVPECL
power-down
OUT2
LVPECL
power-down
OUT3
LVPECL
power-down
OUT4
LVPECL
power-down
OUT5
LVPECL
power-down
OUT6
LVPECL
power-down
OUT7
LVEPCL
power-down
OUT8
LVPECL
power-down
OUT9
LVPECL
power-down
OUT10
LVPECL
power-down
OUT11
LVPECL
power-down
CSDLD En
OUT0
CSDLD En
OUT8
64
Output Driver Control
0F0
OUT0 Control
OUT0 format
OUT0 CMOS
configuration
OUT0 polarity
OUT0 LVPECL
differential voltage
0F1
OUT1 Control
OUT1 format
OUT1 CMOS
configuration
OUT1 polarity
OUT1 LVPECL
differential voltage
0F2
OUT2 Control
OUT2 format
OUT2 CMOS
configuration
OUT2 polarity
OUT2 LVPECL
differential voltage
0F3
OUT3 Control
OUT3 format
OUT3 CMOS
configuration
OUT3 polarity
OUT 3 LVPECL
differential voltage
0F4
OUT4 Control
OUT4 format
OUT4 CMOS
configuration
OUT4 polarity
OUT4 LVPECL
differential voltage
0F5
OUT5 Control
OUT5 format
OUT5 CMOS
configuration
OUT5 polarity
OUT5 LVPECL
differential voltage
0F6
OUT6 Control
OUT6 format
OUT6 CMOS
configuration
OUT6 polarity
OUT6 LVPECL
differential voltage
0F7
OUT7 Control
OUT7 format
OUT7 CMOS
configuration
OUT7 polarity
OUT7 LVPECL
differential voltage
0F8
OUT8 Control
OUT8 format
OUT8 CMOS
configuration
OUT8 polarity
OUT8 LVPECL
differential voltage
0F9
OUT9 Control
OUT9 format
OUT9 CMOS
configuration
OUT9 polarity
OUT9 LVPECL
differential voltage
0FA
OUT10 Control
OUT10 format
OUT10 CMOS
configuration
OUT10 polarity
OUT10 LVPECL
differential voltage
0FB
OUT11 Control
OUT11 format
OUT11 CMOS
configuration
OUT11 polarity
OUT11 LVPECL
differential voltage
0FC
Enable output
on CSDLD
Enable output
on CSDLD
CSDLD En
OUT7
Unused
0FD
0FE
to
18F
LVPECL Channel Dividers
190
Divider 0 (PECL)
191
Divider 0
bypass
192
CSDLD En
OUT6
Unused
CSDLD En
OUT5
Unused
Divider 0 low cycles
Divider 0
Divider 0
force
ignore
high
SYNC
Unused
CSDLD En
OUT 4
Unused
CSDLD En
OUT3
CSDLD En
OUT11
Unused
CSDLD En
OUT1
CSDLD En
OUT9
Unused
64
64
64
64
64
64
64
64
64
64
64
00
00
00
Divider 0 high cycles
Divider 0
phase offset
Divider 0
start high
Rev. 0 | Page 63 of 84
CSDLD En
OUT2
CSDLD En
OUT10
Default
Value
(Hex)
00
Channel 0
powerdown
Channel 0
direct-tooutput
77
00
Disable
Divider 0
DCC
00
AD9520-4
Addr
(Hex)
193
194
Parameter
Divider 1 (PECL)
Bit 7 (MSB)
Divider 1
bypass
195
196
197
Bit 6
Bit 5
Divider 1 Low Cycles
Divider 1
Divider 1
force
ignore
SYNC
high
Unused
Divider 2 (PECL)
Divider 3 (PECL)
19A
Divider 3
bypass
Unused
A03
Disable
Divider 1
DCC
Channel 2
Channel 2
powerdirect-todown
output
Divider 3 high cycles
Disable
Divider 2
DCC
Channel 3
powerdown
Channel 3
direct-tooutput
00
Disable
Divider 3
DCC
Power down
clock
input
section
Powerdown VCO
clock
interface
Unused
Disable
power-on
SYNC
Unused
VCO divider
Powerdown
VCO
and CLK
Select
VCO or CLK
00
Bypass VCO
divider
Powerdown
SYNC
Powerdown
distribution
reference
Unused
Soft
SYNC
00
00
IO_UPDATE
(self-clearing)
Unused
0
20
00
Unused
0
00
00
Unused
Unused
(default =
1)
00
00
Divider 3
phase offset
Unused
00
11
00
Unused
231
Update All Registers
232
IO_UPDATE
A02
Bit 0 (LSB)
Channel 1
Channel 1
direct-topowerdown
output
Divider 2 High Cycles
Divider 2
phase offset
Divider 3
start high
Unused
Input CLKs
EEPROM
Buffer Segment
Register 2
EEPROM
Buffer Segment
Register 3
EEPROM
Buffer Segment
Register 4
Unused
Bit 2
Bit 1
Divider 0 high cycles
Divider 1
phase offset
Unused
1E2
to
22A
System
230
Power-down
and SYNC
A01
Divider 2
start high
Divider 3
Divider 3
ignore
force
SYNC
high
Unused
19C
to
1DF
VCO Divider and CLK Input
1E0
VCO divider
233
to
9FF
EEPROM Buffer Segment
A00
EEPROM
Buffer Segment
Register 1
Unused
Divider 3 low cycles
19B
1E1
Bit 3
Divider 1
start high
Divider 2 low cycles
Divider 2
Divider 2
ignore
force
SYNC
high
Unused
Divider 2
bypass
198
199
Bit 4
Default
Value
(Hex)
33
00
00
00
EEPROM Buffer Segment Register 1 (default: number of bytes for Group 1)
00
EEPROM Buffer Segment Register 2 (default: Bits[15:8] of starting register address for Group 1)
00
EEPROM Buffer Segment Register 3 (default: Bits[7:0] of starting register address for Group 1)
00
EEPROM Buffer Segment Register 4 (default: number of bytes for Group 2)
02
Rev. 0 | Page 64 of 84
AD9520-4
Addr
(Hex)
A04
A05
A06
A07
A08
A09
A0A
A0B
A0C
A0D
A0E
A0F
A10
A11
A12
A13
A14
A15
A16
A17
to
AFF
Parameter
EEPROM
Buffer Segment
Register 5
EEPROM
Buffer Segment
Register 6
EEPROM
Buffer Segment
Register 7
EEPROM
Buffer Segment
Register 8
EEPROM
Buffer Segment
Register 9
EEPROM
Buffer Segment
Register 10
EEPROM
Buffer Segment
Register 11
EEPROM
Buffer Segment
Register 12
EEPROM
Buffer Segment
Register 13
EEPROM
Buffer Segment
Register 14
EEPROM
Buffer Segment
Register 15
EEPROM
Buffer Segment
Register 16
EEPROM
Buffer Segment
Register 17
EEPROM
Buffer Segment
Register 18
EEPROM
Buffer Segment
Register 19
EEPROM Buffer
Segment
Register 20
EEPROM
Buffer Segment
Register 21
EEPROM Buffer
Segment
Register 22
EEPROM
Buffer Segment
Register 23
Bit 7 (MSB)
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
EEPROM Buffer Segment Register 5 (default: Bits[15:8] of starting register address for Group 2)
Default
Value
(Hex)
00
EEPROM Buffer Segment Register 6 (default: Bits[7:0] of starting register address for Group 2)
04
EEPROM Buffer Segment Register 7 (default: number of bytes for Group 3)
0E
EEPROM Buffer Segment Register 8 (default: Bits[15:8] of starting register address for Group 3)
00
EEPROM Buffer Segment Register 9 (Default: Bits[7:0] of starting register address for Group 3)
10
EEPROM Buffer Segment Register 10 (default: number of bytes for Group 4)
0E
EEPROM Buffer Segment Register 11 (default: Bits[15:8] of starting register address for Group 4)
00
EEPROM Buffer Segment Register 12 (default: Bits[7:0] of starting register address for Group 4)
F0
EEPROM Buffer Segment Register 13 (default: number of bytes for Group 5)
0B
EEPROM Buffer Segment Register 14 (default: Bits[15:8] of starting register address for Group 5)
01
EEPROM Buffer Segment Register 15 (default: Bits[7:0] of starting register address for Group 5)
90
EEPROM Buffer Segment Register 16 (default: number of bytes for Group 6)
01
EEPROM Buffer Segment Register 17 (default: Bits[15:8] of starting register address for Group 6)
01
EEPROM Buffer Segment Register 18 (default: Bits [7:0] of starting register address for Group 6)
E0
EEPROM Buffer Segment Register 19 (default: number of bytes for Group 7)
01
EEPROM Buffer Segment Register 20 (default: Bits[15:8] of starting register address for Group 7)
02
EEPROM Buffer Segment Register 21 (default: Bits[7:0] of starting register address for Group 7)
30
EEPROM Buffer Segment Register 22 (default: IO_UPDATE from EEPROM)
80
EEPROM Buffer Segment Register 23 (default: end of data)
FF
Unused
00
Rev. 0 | Page 65 of 84
AD9520-4
Addr
(Hex) Parameter
EEPROM Control
B00
EEPROM status
(read-only)
B01
EEPROM error
checking
(read-only)
B02
EEPROM
Control 1
B03
EEPROM
Control 2
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0 (LSB)
Unused
Unused
00
Unused
Unused
STATUS_
EEPROM
EEPROM
data error
Unused
Soft_EEPROM
(self-clearing)
Unused
Enable
EEPROM write
REG2EEPROM
(self-clearing)
00
Unused
Rev. 0 | Page 66 of 84
Bit 2
Default
Value
(Hex)
00
00
AD9520-4
REGISTER MAP DESCRIPTIONS
Table 50 through Table 60 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal
address. Reference to a specific bit or range of bits within a register is indicated by square brackets. For example, [3] refers to Bit 3 and
[5:2] refers to the range of bits from Bit 5 through Bit 2.
Table 50. SPI Mode Serial Port Configuration
Reg Addr (Hex)
000
Bit(s)
[7]
Name
SDO active
000
[6]
LSB first/addr incr
000
[5]
Soft reset
000
000
[4]
[3:0]
Unused
Mirror[7:4]
004
[0]
Readback active registers
Description
Selects unidirectional or bidirectional data transfer mode.
[7] = 0; SDIO pin used for write and read; SDO is high impedance (default).
[7] = 1; SDO used for read; SDIO used for write; unidirectional mode.
SPI MSB or LSB data orientation. (This register is ignored in I2C mode.)
[6] = 0; data-oriented MSB first; addressing decrements (default).
[6] = 1; data-oriented LSB first; addressing increments.
Soft Reset.
[5] = 1 (self-clearing). Soft reset; restores default values to internal registers.
Bits[3:0] should always mirror[7:4] so that it does not matter whether the part
is in MSB or LSB first mode (see Register 0x000[6]). User should set bits as follows:
[0] = [7]
[1] = [6]
[2] = [5]
[3] = [4]
Select register bank used for a readback.
[0] = 0; read back buffer registers (default).
[0] = 1; read back active registers.
Table 51. I2C Mode Serial Port Configuration
Reg Addr (Hex)
000
000
Bit(s)
[7:6]
[5]
Name
Unused
Soft reset
000
000
[4]
[3:0]
Unused
Mirror[7:4]
004
[0]
Readback active registers
Description
Soft Reset.
[5] = 1 (self-clearing). Soft reset; restores default values to internal registers.
Bits[3:0] should always mirror[7:4] so that it does not matter whether the part is
in MSB or LSB first mode (see Register 0x000[6]). Set bits as follows:
[0] = [7]
[1] = [6]
[2] = [5]
[3] = [4]
Select register bank used for a readback.
[0] = 0; read back buffer registers. (default)
[0] = 1; read back active registers.
Table 52. EEPROM ID
Reg Addr (Hex)
005
Bit(s)
[7:0]
Name
EEPROM customer
version ID (LSB)
006
[7:0]
EEPROM customer
version ID (MSB)
Description
16-bit EEPROM ID[7:0]. This register, along with 0x006, allow the user to store a
unique ID to identify which version of the AD9520 register settings is stored in the
EEPROM. It does not affect AD9520 operation in any way (default: 0x00).
16-bit EEPROM ID[15:8]. This register, along with 0x005, allow the user to store a
unique ID to identify which version of AD9520 register settings is stored in the
EEPROM. It does not affect AD9520 operation in any way (default: 0x00).
Rev. 0 | Page 67 of 84
AD9520-4
Table 53. PLL
Reg.
Addr
(Hex) Bit(s) Name
010 [7]
PFD polarity
010
[6:4]
CP current
010
[3:2]
CP mode
010
[1:0]
011
[7:0]
012
[5:0]
013
[5:0]
014
[7:0]
015
[4:0]
016
[7]
016
[6]
016
[5]
016
[4]
Description
Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip
VCO requires positive polarity [7] = 0.
[7] = 0; positive (higher control voltage produces higher frequency; default).
[7] = 1; negative (higher control voltage produces lower frequency).
Charge pump current (with CPRSET = 5.1 kΩ).
[6] [5]
[4]
ICP (mA)
0
0
0
0.6
0
0
1
1.2
0
1
0
1.8
0
1
1
2.4
1
0
0
3.0
1
0
1
3.6
1
1
0
4.2
1
1
1
4.8 (default)
Charge pump operating mode.
[3]
[2]
Charge Pump Mode
0
0
High impedance state.
0
1
Force source current (pump up).
1
0
Force sink current (pump down).
1
1
Normal operation (default)
PLL operating mode.
PLL powerdown
[1]
[0]
Mode
0
0
Normal operation; this mode must be selected to use the PLL
0
1
Asynchronous power-down (default)
1
0
Unused
1
1
Synchronous power-down
14-bit R counter, Reference divider LSBs—lower eight bits. The reference divider (also called the R divider or R counter) is
Bits[7:0] (LSB)
14 bits long. The lower eight bits are in this register (default: 0x01).
14-bit R counter, Reference divider MSBs—upper six bits. The reference divider (also called the R divider or R counter) is
Bits[13:8] (MSB) 14 bits long. The upper six bits are in this register (default: 0x00).
6-bit A counter A counter (part of N divider). The N divider is also called the feedback divider (default: 0x00).
13-bit B counter,
Bits[7:0] (LSB)
13-bit B counter,
Bits[12:8] (MSB)
Set CP pin
to VCP/2
B counter (part of N divider)—lower eight bits. The N divider is also called the feedback divider (default: 0x03).
B counter (part of N divider)—upper five bits. The N divider is also called the feedback divider (default: 0x00).
Sets the CP pin to one-half of the VCP supply voltage.
[7] = 0; CP normal operation (default).
[7] = 1; CP pin set to VCP /2.
Reset R counter Reset R counter (R divider).
[6] = 0; normal (default).
[6] = 1; hold R counter in reset.
Reset A and B counters (part of N divider).
Reset A and B
counters
[5] = 0; normal (default).
[5] = 1; hold A and B counters in reset.
Reset R, A, and B counters.
Reset all
counters
[4] = 0; normal (default).
[4] = 1; hold R, A, and B counters in reset.
Rev. 0 | Page 68 of 84
AD9520-4
Reg.
Addr
(Hex) Bit(s) Name
016 [3]
B counter
bypass
016
[2:0]
Prescaler P
017
[7:2]
STATUS
pin control
Description
B counter bypass. This is only valid when operating the prescaler in FD mode.
[3] = 0; normal (default).
[3] = 1; B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for
the N divider.
Prescaler: DM = dual modulus and FD = fixed divide. The Prescalar P is part of the feedback divider.
[2]
[1] [0] Mode
Prescaler
0
0
0
FD
Divide-by-1.
0
0
1
FD
Divide-by-2.
0
1
0
DM
Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0.
0
1
1
DM
Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0.
1
0
0
DM
Divide-by-8 and divide-by-9 when A ≠ 0; divide-by-8 when A = 0.
1
0
1
DM
Divide-by-16 and divide-by-17 when A ≠ 0; divide-by-16 when A = 0.
1
1
0
DM
Divide-by-32 and divide-by-33 when A ≠ 0; divide-by-32 when A = 0 (default).
1
1
1
FD
Divide-by-3.
Selects the signal that appears at the STATUS pin. 0x01D[7] must be 0 to reprogram the STATUS pin.
Level or
Dynamic
[7]
[6] [5] [4] [3]
[2] Signal
Signal at STATUS Pin
0
0
0
0
0
0
LVL
Ground, dc (default).
0
0
0
0
0
1
DYN
N divider output (after the delay).
0
0
0
0
1
0
DYN
R divider output (after the delay).
0
0
0
0
1
1
DYN
A divider output.
0
0
0
1
0
0
DYN
Prescaler output.
0
0
0
1
0
1
DYN
PFD up pulse.
0
0
0
1
1
0
DYN
PFD down pulse.
0
X
X
X
X
X
LVL
Ground (dc); for all other cases of 0XXXXX not specified.
The selections that follow are the same as REFMON.
1
0
0
0
0
0
LVL
Ground (dc).
1
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
0
1
0
DYN
REF2 clock (N/A in differential mode).
1
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when in
differential mode).
1
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential
mode).
1
0
0
1
0
1
LVL
Status of selected reference (status of differential reference);
active high.
1
0
0
1
1
0
LVL
Status of unselected reference (not available in differential
mode); active high.
1
0
0
1
1
1
LVL
Status REF1 frequency (active high).
1
0
1
0
0
0
LVL
Status REF2 frequency (active high).
1
0
1
0
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
1
LVL
Status of VCO frequency (active high).
1
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
1
0
1
LVL
DLD; active high.
1
0
1
1
1
0
LVL
Holdover active (active high).
1
0
1
1
1
1
LVL
N/A internal holdover comparator output (active high).
1
1
0
0
0
0
LVL
VS (PLL power supply).
1
1
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
1
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in
differential mode).
Rev. 0 | Page 69 of 84
AD9520-4
Reg.
Addr
(Hex) Bit(s) Name
017
[1:0]
018
[7]
018
[6:5]
018
[4]
018
[3]
018
[2:1]
Description
[7]
1
[6]
1
[5] [4]
0
1
[3]
0
Level or
Dynamic
[2] Signal
0
DYN
1
1
0
1
0
1
LVL
1
1
0
1
1
0
LVL
Signal at STATUS Pin
Unselected reference to PLL (not available when in
differential mode).
Status of selected reference (status of differential reference);
active low.
Status of unselected reference (not available in differential
mode); active low.
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
(Status of REF1 frequency) AND (status of REF2 frequency).
(DLD) AND (Status of selected reference) AND (status of VCO).
Status of VCO frequency (active low).
Selected reference (low = REF2, high = REF1).
DLD (active low).
Holdover active (active low).
LD pin comparator output (active low).
1
1
0
1
1
1
LVL
1
1
1
0
0
0
LVL
1
1
1
0
0
1
LVL
1
1
1
0
1
0
LVL
1
1
1
0
1
1
LVL
1
1
1
1
0
0
LVL
1
1
1
1
0
1
LVL
1
1
1
1
1
0
LVL
1
1
1
1
1
1
LVL
Antibacklash
[1]
[0]
Antibacklash Pulse Width (ns)
pulse width
0
0
2.9 (default)
0
1
1.3
1
0
6.0
1
1
2.9
Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost.
Enable CMOS
reference input [7] = 0; disable dc offset (default).
dc offset
[7] = 1; enable dc offset.
Lock detect
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates
counter
a locked condition.
[6]
[5]
PFD Cycles to Determine Lock
0
0
5 (default)
0
1
16
1
0
64
1
1
255
Digital lock
If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time,
detect window the digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock
threshold.
[4] = 0; high range (default).
[4] = 1; low range.
Disable digital Digital lock detect operation.
lock detect
[3] = 0; normal lock detect operation (default).
[3] = 1; disable lock detect.
VCO calibration VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock (see the
divider
VCO Calibration section for the recommended setting of the VCO calibration divider based on the PFD rate.)
[2]
[1] VCO Calibration Clock Divider
0
0
2
0
1
4
1
0
8
1
1
16 (default)
Rev. 0 | Page 70 of 84
AD9520-4
Reg.
Addr
(Hex) Bit(s) Name
Description
018 [0]
VCO calibration Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. The
now
sequence to initiate a calibration follows: program to 0, followed by an IO_ UPDATE bit (Register 0x232[0]);
then programmed to 1, followed by another IO_ UPDATE bit (Register 0x232[0]). This sequence gives
complete control over when the VCO calibration occurs relative to the programming of other registers that
can impact the calibration (default = 0).
019 [7:6] R, A, B counters [7]
[6]
Action
SYNC pin reset 0
0
Do nothing on SYNC (default).
0
1
1
019
019
01A
[5:3]
[2:0]
[7]
01A
[6]
01A
[5:0]
1
0
1
Asynchronous reset.
Synchronous reset.
Do nothing on SYNC.
R path delay
N path delay
Enable STATUS
pin divider
[5:3] R Path Delay, see Table 2, (default: 0x00).
[2:0] N Path Delay, see Table 2, (default: 0x0).
Enables a divide-by-4 on the STATUS pin. This makes it easier to look at low duty-cycle signals out of the
pulse-swallow R and N dividers.
[7] = 0; divide-by-4 disabled on STATUS pin (default).
[7] = 1; divide-by-4 enabled on STATUS pin.
Ref freq monitor Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect
threshold
the VCO frequency monitor’s detection threshold (see Table 17, REF1, REF2, and VCO frequency status
monitor parameter).
[6] = 0; frequency valid if frequency is above 750 kHz (default).
[6] = 1; frequency valid if frequency is above 6 kHz.
LD pin control
Selects the signal that is connected to the LD pin.
Level or
Dynamic
[5] [4] [3]
[2]
[1] [0] Signal
Signal at LD Pin
0
0
0
0
0
0
LVL
Digital lock detect (high = lock, low = unlock, default).
0
0
0
0
0
1
DYN
P-channel, open-drain lock detect (analog lock detect).
0
0
0
0
1
0
DYN
N-channel, open-drain lock detect (analog lock detect).
0
0
0
0
1
1
HIZ
Tristate (high-Z) LD pin.
0
0
0
1
0
0
CUR
Current source lock detect (110 μA when DLD is true).
0
X
X
X
X
X
LVL
Ground (dc); for all other cases of 0XXXXX not specified.
The selections that follow are the same as REFMON.
1
0
0
0
0
0
LVL
Ground (dc).
1
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
0
1
0
DYN
REF2 clock (N/A in differential mode).
1
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when in
differential mode).
1
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
0
1
0
1
LVL
Status of selected reference (status of differential reference);
active high.
1
0
0
1
1
0
LVL
Status of unselected reference (not available in differential
mode); active high.
1
0
0
1
1
1
LVL
Status REF1 frequency (active high).
1
0
1
0
0
0
LVL
Status REF2 frequency (active high).
1
0
1
0
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
1
LVL
Status of VCO frequency (active high).
1
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
1
0
1
LVL
DLD; active high.
1
0
1
1
1
0
LVL
Holdover active (active high).
1
0
1
1
1
1
LVL
N/A, do not use.
1
1
0
0
0
0
LVL
VS (PLL supply).
1
1
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
Rev. 0 | Page 71 of 84
AD9520-4
Reg.
Addr
(Hex) Bit(s) Name
01B
[7]
Enable VCO
frequency
monitor
01B
[6]
01B
[5]
Enable REF2
(REFIN)
frequency
monitor
Enable REF1
(REFIN)
frequency
monitor
01B
[4:0]
REFMON pin
control
Description
Level or
Dynamic
[5] [4] [3]
[2]
[1] [0] Signal
Signal at LD Pin
1
1
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in
differential mode).
1
1
0
1
0
0
DYN
Unselected reference to PLL (not available when in differential
mode).
1
1
0
1
0
1
LVL
Status of selected reference (status of differential reference);
active low.
1
1
0
1
1
0
LVL
Status of unselected reference (not available in differential
mode); active low.
1
1
0
1
1
1
LVL
Status of REF1 frequency (active low).
1
1
1
0
0
0
LVL
Status of REF2 frequency (active low).
1
1
1
0
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
1
1
0
1
0
LVL
(DLD) AND (Status of selected reference) AND (status of VCO).
1
1
1
0
1
1
LVL
Status of VCO frequency (active low).
1
1
1
1
0
0
LVL
Selected reference (low = REF2, high = REF1).
1
1
1
1
0
1
LVL
DLD; active low.
1
1
1
1
1
0
LVL
Holdover active (active low).
1
1
1
1
1
1
LVL
N/A, do not use.
Enables or disables VCO frequency monitor.
[7] = 0; disable VCO frequency monitor (default).
[7] = 1; enable VCO frequency monitor.
Enables or disables REF2 frequency monitor.
[6] = 0; disable REF2 frequency monitor (default).
[6] = 1; enable REF2 frequency monitor.
REF1 (REFIN) frequency monitor enabled; this is for both REF1 (single-ended) and REFIN (differential) inputs
(as selected by differential reference mode).
[5] = 0; disable REF1 (REFIN) frequency monitor (default).
[5] = 1; enable REF1 (REFIN) frequency monitor.
Selects the signal that is connected to the REFMON pin.
Level or
Dynamic
[4] [3] [2] [1] [0] Signal
Signal at REFMON Pin
0
0
0
0
0
LVL
Ground, dc, (default).
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
0
0
0
1
0
DYN
REF2 clock (N/A in differential mode).
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential
mode).
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
0
0
1
0
1
LVL
Status of selected reference (status of differential reference);
active high.
0
0
1
1
0
LVL
Status of unselected reference (not available in differential mode);
active high.
0
0
1
1
1
LVL
Status REF1 frequency (active high).
0
1
0
0
0
LVL
Status REF2 frequency (active high).
0
1
0
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
0
1
0
1
1
LVL
Status of VCO frequency (active high).
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2).
0
1
1
0
1
LVL
DLD; active low.
Rev. 0 | Page 72 of 84
AD9520-4
Reg.
Addr
(Hex) Bit(s) Name
Description
[4]
0
0
1
1
1
1
01C
[7]
Disable
switchover
deglitch
01C
[6]
Select REF2
01C
[5]
Use REF_SEL
pin
01C
[4]
Enable
automatic
reference
switchover
01C
[3]
Stay on REF2
01C
[2]
Enable REF2
01C
[1]
Enable REF1
01C
[0]
Enable
differential
reference
[3]
1
1
0
0
0
0
[2]
1
1
0
0
0
0
[1]
1
1
0
0
1
1
Level or
Dynamic
[0] Signal
0
LVL
1
LVL
0
LVL
1
DYN
0
DYN
1
DYN
Signal at REFMON Pin
Holdover active (active high).
N/A, do not use.
VS (PLL supply).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
1
0
1
0
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference);
active low.
1
0
1
1
0
LVL
Status of unselected reference (not available in differential mode);
active low.
1
0
1
1
1
LVL
Status of REF1 frequency (active low).
1
1
0
0
0
LVL
Status of REF2 frequency (active low).
1
1
0
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
1
0
1
1
LVL
Status of VCO frequency (active low).
1
1
1
0
0
LVL
Selected reference (low = REF2, high = REF1).
1
1
1
0
1
LVL
DLD; active low.
1
1
1
1
0
LVL
Holdover active (active low).
1
1
1
1
1
LVL
N/A, do not use.
Disables or enables the switchover deglitch circuit.
[7] = 0; enable switchover deglitch circuit (default).
[7] = 1; disable switchover deglitch circuit.
If Register 0x01C[5] = 0, selects reference for PLL when in manual; register selected reference control.
[6] = 0; select REF1 (default).
[6] = 1; select REF2.
If Register 0x01C[4] = 0 (manual), sets method of PLL reference selection.
[5] = 0; use Register 0x01C[6] (default).
[5] = 1; use REF_SEL pin.
Automatic or manual reference switchover. Single-ended reference mode must be selected by
Register 0x01C[0] = 0.
[4] = 0; manual reference switchover (default).
[4] = 1; automatic reference switchover.
Setting this bit also powers on REF1 and REF2, and overrides the setting in Register 0x01C[2:1].
Stays on REF2 after switchover.
[3] = 0; return to REF1 automatically when REF1 status is good again (default).
[3] = 1; stay on REF2 after switchover. Do not automatically return to REF1.
This bit turns the REF2 power on. This bit is overridden when automatic reference switchover is enabled.
[2] = 0; REF2 power off (default).
[2] = 1; REF2 power on.
This bit turns the REF1 power on. This bit is overridden when automatic reference switchover is enabled.
[1] = 0; REF1 power off (default).
[1] = 1; REF1 power on.
Selects the PLL reference mode, differential or single-ended.
Register 0x01C[2:1] should be cleared when this bit is set.
[0] = 0; single-ended reference mode (default).
[0] = 1; differential reference mode.
Rev. 0 | Page 73 of 84
AD9520-4
Reg.
Addr
(Hex) Bit(s) Name
Description
01D [7]
Enables the Status_EEPROM signal at the STATUS pin.
Enable
Status_EEPROM [7] = 0; the STATUS pin is controlled by 0x017[7:2] selection.
at STATUS pin
[7] = 1; select Status_EEPROM signal at STATUS pin. This bit overrides 0x017[7:2] (default).
01D [6]
Enables the maintaining amplifier needed by a crystal oscillator at the PLL reference input.
Enable
XTAL OSC
[6] = 0; crystal oscillator maintaining amplifier disabled (default).
[6] = 1; crystal oscillator maintaining amplifier enabled.
01D [5]
Enables PLL reference input clock doubler.
Enable clock
doubler
[5] = 0; doubler disabled (default).
[5] = 1; doubler enabled.
01D [4]
Disables the PLL status register readback.
Disable PLL
status register
[4] = 0; PLL status register enable (default).
[4] = 1; PLL status register disable. If this bit is set, Register 01F is not automatically updated.
01D [3]
Enable LD pin
Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode.
comparator
When the AD9520 is in internal (automatic) holdover mode, this enables the use of the voltage on the
LD pin to determine if the PLL was previously in a locked state (see Figure 44). Otherwise, this can be used
with the REFMON and STATUS pins to monitor the voltage on this pin.
[3] = 0; disable LD pin comparator and ignore the LD pin voltage; internal/automatic holdover
controller treats this pin as true (high, default).
[3] = 1; enable LD pin comparator (use LD pin voltage to determine if the PLL was previously locked).
01D [1]
Enable external Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
holdover
[1] = 0; automatic holdover mode, holdover controlled by automatic holdover circuit (default).
01D
[0]
01E
[4:3]
01E
[2]
01E
[1]
01F
[6]
01F
[5]
01F
[4]
01F
[3]
[1] = 1; external holdover mode, holdover controlled by SYNC pin.
Enables the internally controlled holdover function.
[0] = 0; holdover disabled (default).
[0] = 1; holdover enabled.
External zero
[4]
[3]
Select Which Channel Divider to Use in the External Zero-Delay Path
delay
0
0
Select Channel Divider 0 (default)
feedback
0
1
Select Channel Divider 1
channel
1
0
Select Channel Divider 2
divider select
1
1
Select Channel Divider 3
Enable external Selects which zero-delay mode to use.
zero delay
[2] = 0; enables internal zero-delay mode if 0x01E[1] = 1 (default).
[2] = 1; enables external zero-delay mode if 0x01E[1] = 1.
Enables zero-delay function.
Enable zero
delay
[1] = 0; disables zero-delay function (default).
[1] = 1; enables zero-delay function.
VCO calibration Readback register; status of the VCO calibration.
finished
[6] = 0; VCO calibration not finished.
(read-only)
[6] = 1; VCO calibration finished.
Holdover active Readback register. Indicates if the part is in the holdover state (see Figure 44). This is not the same as
(read-only)
holdover enabled.
[5] = 0; not in holdover.
[5] = 1; holdover state active.
Readback register. Indicates which PLL reference is selected as the input to the PLL.
REF2 selected
(read-only)
[4] = 0; REF1 selected (or differential reference if in differential mode).
[4] = 1; REF2 selected.
VCO frequency Readback register. Indicates if the VCO frequency is greater than the threshold (see Table 17, REF1, REF2, and
> threshold
VCO frequency status monitor parameter).
(read-only)
[3] = 0; VCO frequency is less than the threshold.
[3] = 1; VCO frequency is greater than the threshold.
Enable
holdover
Rev. 0 | Page 74 of 84
AD9520-4
Reg.
Addr
(Hex) Bit(s) Name
01F [2]
REF2 frequency
> threshold
(read-only)
01F
[1]
01F
[0]
Description
Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x01A[6].
[2] = 0; REF2 frequency is less than threshold frequency.
[2] = 1; REF2 frequency is greater than threshold frequency.
REF1 frequency Readback register. Indicates if the frequency of the signal at REF1 is greater than the threshold frequency
> threshold
set by Register 0x01A[6].
(read-only)
[1] = 0; REF1 frequency is less than threshold frequency.
[1] = 1; REF1 frequency is greater than threshold frequency.
Readback register. Digital lock detect.
Digital lock
detect
[0] = 0; PLL is not locked.
(read-only)
[0] = 1; PLL is locked.
Table 54. Output Driver Control
Reg.
Addr
(Hex) Bit(s) Name
0F0 [7]
OUT0 format
0F0
[6:5]
OUT0 CMOS
configuration
0F0
[4:3]
OUT0 polarity
0F0
[2:1]
OUT0 LVPECL
differential
voltage
0F0
[0]
OUT 0 LVPECL
power-down
0F1
0F2
0F3
0F4
0F5
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
OUT1 control
OUT2 control
OUT3 control
OUT4 control
OUT5 control
Description
Selects the output type for OUT0.
[7] = 0; LVPECL (default).
[7] = 1; CMOS.
Sets the CMOS output configuration for OUT0 when 0x0F0[7] = 1.
F0[6:5]
OUT0A
OUT0B
00
Tristate
Tristate
01
On
Tristate
10
Tristate
On
11 (default)
On
On
Sets the output polarity for OUT0.
F0[7]
F0[4]
F0[3]
Output Type
OUT0A
OUT 0B
0 (default)
X
0 (default)
LVPECL
Noninverting
Inverting
0
X
1
LVPECL
Inverting
Noninverting
1
0 (default)
0
CMOS
Noninverting
Noninverting
1
0
1
CMOS
Inverting
Inverting
1
1
0
CMOS
Noninverting
Inverting
1
1
1
CMOS
Inverting
Noninverting
Sets the LVPECL output differential voltage (VOD).
[3]
[2]
VOD (mV)
0
0
400
0
1
600
1 (default)
0 (default)
780
1
1
960
LVPECL power-down
[0] = 0; normal operation (default).
[0] = 1; safe power-down.
This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.
Rev. 0 | Page 75 of 84
AD9520-4
Reg.
Addr
(Hex)
0F6
0F7
0F8
0F9
0FA
0FB
0FC
Bit(s)
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
Name
OUT6 control
OUT7 control
OUT8 control
OUT9 control
OUT10 control
OUT11 control
CSDLD En OUT 7
0FC
0FC
0FC
0FC
0FC
0FC
0FC
0FD
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[3]
0FD
[2]
0FD
0FD
[1]
[0]
CSDLD En OUT 6
CSDLD En OUT 5
CSDLD En OUT 4
CSDLD En OUT 3
CSDLD En OUT 2
CSDLD En OUT 1
CSDLD En OUT 0
CSDLD
En OUT 11
Output 10 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD
En OUT 10
CSDLD En OUT 9 Output 9 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT 8 Output 8 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Description
This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.
Output 7 enabled only if CSDLD is high.
0FC[7]
CSDLD Signal Output 7 Enable Status
0
0
Not affected by CSDLD signal. (default)
1
0
Asynchronous power down.
1
1
Asynchronously enable Output 7 if not powered down by other settings.
To use this feature, the user must use current source digital lock detect,
and set the enable LD pin comparator bit (0x01D[3]).
Output 6 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Output 5 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Output 4 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Output 3 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Output 2 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Output 1 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Output 0 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Output 11 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Table 55. LVPECL Channel Dividers
Reg.
Addr
(Hex) Bit(s) Name
190
[7:4] Divider 0 low cycles
190
[3:0]
Divider 0 high cycles
191
[7]
Divider 0 bypass
191
[6]
Divider 0 ignore SYNC
191
[5]
Divider 0 force high
191
[4]
Divider 0 start high
191
[3:0]
Divider 0 phase offset
Description
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x7 means the divider is high for eight input clock cycles (default: 0x7).
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
No SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that no SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset (default: 0x0).
Rev. 0 | Page 76 of 84
AD9520-4
Reg.
Addr
(Hex) Bit(s) Name
192
[2]
Channel 0 power-down
192
[1]
Channel 0 direct-to-output
192
[0]
Disable Divider 0 DCC
193
[7:4]
Divider 1 low cycles
193
[3:0]
Divider 1 high cycles
194
[7]
Divider 1 bypass
194
[6]
Divider 1 ignore SYNC
194
[5]
Divider 1 force high
194
[4]
Divider 1 start high
194
195
[3:0]
[2]
Divider 1 phase offset
Channel 1 power-down
195
[1]
Channel 1 direct-to-output
195
[0]
Disable Divider 1 DCC
196
[7:4]
Divider 2 low cycles
196
[3:0]
Divider 2 high cycles
197
[7]
Divider 2 bypass
Description
Channel 0 power-down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 are put into safe powerdown mode by setting this bit.)
Connects OUT0, OUT1, and OUT2 to Divider 0 or directly to VCO or CLK.
[1] = 0: OUT0, OUT1, and OUT2 are connected to Divider 0 (default).
[1] = 1:
If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0, OUT1, and OUT2.
If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0, OUT1, and OUT2.
If 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x3 means the divider is low for four input clock cycles (default: 0x3).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x3 means the divider is high for four input clock cycles (default: 0x3).
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
No SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that no SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset (default: 0x0).
Channel 1 power-down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT3/OUT3, OUT4/OUT4, and OUT5/OUT5 are put into safe powerdown mode by setting this bit.)
Connects OUT3, OUT4, and OUT5 to Divider 1 or directly to VCO or CLK.
[1] = 0; OUT3, OUT4, and OUT5 are connected to Divider 1. (default)
[1] = 1:
If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT3, OUT4, and OUT5.
If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT3, OUT4, and OUT5.
If 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x1 means the divider is low for two input clock cycles (default: 0x1).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x1 means the divider is high for two input clock cycles (default: 0x1).
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
Rev. 0 | Page 77 of 84
AD9520-4
Reg.
Addr
(Hex) Bit(s) Name
197
[6]
Divider 2 ignore SYNC
197
[5]
Divider 2 force high
197
[4]
Divider 2 start high
197
198
[3:0]
[2]
Divider 2 phase offset
Channel 2 power-down
198
[1]
Channel 2 direct-to-output
198
[0]
Disable Divider 2 DCC
199
[7:4]
Divider 3 low cycles
199
[3:0]
Divider 3 high cycles
19A
[7]
Divider 3 bypass
19A
[6]
Divider 3 ignore SYNC
19A
[5]
Divider 3 force high
19A
[4]
Divider 3 start high
19A
[3:0]
Divider 3 phase offset
19B
[2]
Channel 3 power-down
19B
[1]
Channel 3 direct-to-output
Description
No SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that no SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset.
Channel 2 power-down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 are put into safe powerdown mode by setting this bit.)
Connects OUT6, OUT7, and OUT8 to Divider 2 or directly to VCO or CLK.
[1] = 0; OUT6, OUT7 and OUT8 are connected to Divider 2 (default).
[1] = 1:
If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT6, OUT7, and OUT8.
If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT6, OUT7, and OUT8.
If 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means the divider is low for one input clock cycle (default: 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means the divider is high for one input clock cycle (default: 0x0).
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
No SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that no SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset (default: 0x0).
Channel 3 power-down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 are also put into
safe power-down mode by setting this bit.)
Connects OUT9, OUT10, and OUT11 to Divider 3 or directly to VCO or CLK.
[1] = 0; OUT9, OUT10, and OUT11 are connected to Divider 3 (default).
[1] = 1:
If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT9, OUT10, and OUT11.
If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT9, OUT10, and OUT11.
If 0x1E1[1:0] = 01b, there is no effect.
Rev. 0 | Page 78 of 84
AD9520-4
Reg.
Addr
(Hex) Bit(s) Name
19B
[0]
Disable Divider 3 DCC
Description
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Table 56. VCO Divider and CLK Input
Reg.
Addr
(Hex) Bit(s) Name
1E0 [2:0] VCO divider
1E1
[4]
1E1
[3]
1E1
[2]
1E1
[1]
1E1
[0]
Description
[2]
[1]
[0]
Divide
0
0
0
2 (default)
0
0
1
3
0
1
0
4
0
1
1
5
1
0
0
6
1
0
1
Output static
1
1
0
1 (bypass)
1
1
1
Output static
Power-down clock input section Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
[4] = 0; normal operation (default).
[4] = 1; power down.
Power-down VCO clock interface Powers down the interface block between VCO and clock distribution.
[3] = 0; normal operation (default).
[3] = 1; power down.
Power-down VCO and CLK
Powers down both VCO and CLK input.
[2] = 0; normal operation (default).
[2] = 1; power down.
Select VCO or CLK
Selects either the VCO or the CLK as the input to VCO divider.
[1] = 0; select external CLK as input to VCO divider (default).
[1] = 1; select VCO as input to VCO divider; cannot bypass VCO divider when this is
selected. This bit must be set to use the PLL with the internal VCO.
Bypass VCO divider
Bypasses or uses the VCO divider.
[0] = 0; use VCO divider (default).
[0] = 1; bypass VCO divider; cannot select VCO as input when this is selected.
Rev. 0 | Page 79 of 84
AD9520-4
Table 57. System
Reg.
Addr
(Hex) Bit(s) Name
230 [3]
Disable power-on SYNC
230
[2]
Power-down SYNC
230
[1]
Power-down distribution reference
230
[0]
Soft SYNC
Description
Power-on SYNC mode. Used to disable the antiruntpulse circuitry.
[3] = 0; enable the antiruntpulse circuitry (default).
[3] = 1; disable the antiruntpulse circuitry.
Powers down the SYNC function.
[2] = 0; normal operation of the SYNC function (default).
[2] = 1; power-down SYNC circuitry.
Powers down the reference for the distribution section.
[1] = 0; normal operation of the reference for the distribution section (default).
[1] = 1; powers down the reference for the distribution section.
The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit
is reversed; that is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a SYNC.
[0] = 0; same as SYNC high.
[0] = 1; same as SYNC low.
Table 58. Update All Registers
Reg.
Addr
(Hex) Bit(s) Name
232 [0]
IO_UPDATE
Description
This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens
on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.
[0] = 1 (self-clearing); update all active registers to the contents of the buffer registers.
Table 59. EEPROM Buffer Segment
Reg.
Addr
(Hex) Bit(s) Name
A00 to
EEPROM Buffer
A16
Segment Register 1
to EEPROM Buffer
Segment Register 23
Description
The EEPROM buffer segment section stores the starting address and number of bytes that are to be
stored and read back to and from the EEPROM. Because the AD9520 register space is noncontiguous,
the EEPROM controller needs to know the starting address and number of bytes in the AD9520 register
space to store and retrieve from the EEPROM. In addition, there are special instructions for the EEPROM
controller, operational codes (that is, IO_UPDATE and end-of-data) that are also stored in the EEPROM
buffer segment. The on-chip default setting of the EEPROM buffer segment registers is designed such
that all registers are transferred to/from the EEPROM, and an IO_UPDATE is issued after transfer. See the
Programming the EEPROM Buffer Segment section for more information.
Rev. 0 | Page 80 of 84
AD9520-4
Table 60. EEPROM Control
Reg.
Addr
(Hex) Bit(s) Name
Description
B00 [0]
STATUS_EEPROM This read-only register indicates the status of the data transferred between the EEPROM and the buffer
(read-only)
register bank during the writing and reading of the EEPROM. This signal is also available at the STATUS pin
when 0x01D[7] is set.
[0] = 0; data transfer is done.
[0] = 1; data transfer is not done.
B01 [0]
This read-only register indicates an error during the data transferred between the EEPROM and the buffer.
EEPROM
data error
[1] = 0; no error. Data is correct.
(read-only)
[1] = 1; incorrect data detected.
B02 [1]
Soft_EEPROM
When EEPROM pin is tied low, setting Soft_EEPROM resets the AD9520 using the settings saved in EEPROM.
[1] = 1; soft reset with EEPROM settings (self-clearing).
B02 [0]
Enable EEPROM Enables the user to write to the EEPROM.
write
[0] = 0; EEPROM write protection is enabled. User cannot write to EEPROM (default).
[0] = 1; EEPROM write protection is disabled. User can write to EEPROM.
B03 [0]
REG2EEPROM
Transfers data from the buffer register to the EEPROM (self-clearing).
[0] = 1; setting this bit initiates the data transfer from the buffer register to the EEPROM (writing process);
it is reset by the I²C master after the data transfer is done.
Rev. 0 | Page 81 of 84
AD9520-4
APPLICATIONS INFORMATION
Within the AD9520 family, lower VCO frequencies generally
result in slightly better jitter. The difference in integrated jitter
(from 12 kHz to 20 MHz offset) for the same output frequency
is usually less than 150 fs over the entire VCO frequency range
(1.4 GHz to 2.95 GHz) of the AD9520 family. If the desired
frequency plan can be achieved with a version of the AD9520
that has a lower VCO frequency, choosing the lower frequency
part results in the best phase noise and the lowest jitter. However,
choosing a higher VCO frequency can result in more flexibility
in frequency planning.
Choosing a nominal charge pump current in the middle of the
allowable range as a starting point allows the designer to increase or
decrease the charge pump current, and thus allows the designer
to fine-tune the PLL loop bandwidth in either direction.
ADIsimCLK is a powerful PLL modeling tool that can be
downloaded from www.analog.com and is a very accurate tool
for determining the optimal loop filter for a given application.
USING THE AD9520 OUTPUTS FOR ADC CLOCK
APPLICATIONS
⎞
⎟
⎟
⎠
where:
fA is the highest analog frequency being digitized.
tJ is the rms jitter on the sampling clock.
18
16
90
tJ =
100
fS
tJ =
200
fS
t
80
70
60
J
=4
00f
tJ =
1ps
tJ =
S
2ps
50
40
tJ =
10p
14
12
10
8
s
6
30
10
100
1k
fA (MHz)
Figure 67. SNR and ENOB vs. Analog Input Frequency
See the AN-756 application note and the AN-501 application note
at www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The differential LVPECL outputs of the AD9520 enable clock
solutions that maximize converter SNR performance.
The input requirements of the ADC (differential or singleended, logic level termination) should be considered when
selecting the best clocking/converter solution.
LVPECL CLOCK DISTRIBUTION
Any high speed ADC is extremely sensitive to the quality of the
sampling clock of the AD9520. An ADC can be thought of as a
sampling mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the analog-todigital output. Clock integrity requirements scale with the analog
input frequency and resolution, with higher analog input
frequency applications at ≥14-bit resolution being the most
stringent. The theoretical SNR of an ADC is limited by the ADC
resolution and the jitter on the sampling clock. Considering an
ideal ADC of infinite resolution where the step size and
quantization error can be ignored, the available SNR can be
expressed approximately by
⎛ 1
SNR(dB) = 20log ⎜
⎜ 2πf t
A J
⎝
1
SNR = 20log 2πf t
A J
100
ENOB
The AD9520 has four frequency dividers: the reference (or R)
divider, the feedback (or N) divider, the VCO divider, and the
channel divider. When trying to achieve a particularly difficult
frequency divide ratio requiring a large amount of frequency
division, some of the frequency division can be done by either
the VCO divider or the channel divider, thus allowing a higher
phase detector frequency and more flexibility in choosing the
loop bandwidth.
110
07217-044
The AD9520 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9520, the following guidelines
should be kept in mind.
Figure 67 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
SNR (dB)
FREQUENCY PLANNING USING THE AD9520
The LVPECL outputs of the AD9520 provide the lowest jitter
clock signals available from the AD9520. The LVPECL outputs
(because they are open emitter) require a dc termination to bias
the output transistors. The simplified equivalent circuit in
Figure 51 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
(see Figure 68) or Y-termination (see Figure 69) is recommended.
In both cases, VS of the receiving buffer should match the VS_DRV.
If not, ac coupling is recommended (Figure 70).
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue.
Rev. 0 | Page 82 of 84
AD9520-4
The circuit is identical for the case where VS_DRV = 2.5 V, except
that the pull-down resistor is 62.5 Ω and the pull-up is 250 Ω.
VS_DRV
50Ω
LVPECL
127Ω
127Ω
SINGLE-ENDED
(NOT COUPLED)
VS
LVPECL
Point-to-point connections should be designed such that each
driver has only one receiver, if possible. Connecting outputs in
this manner allows for simple termination schemes and minimizes
ringing due to possible mismatched impedances on the output
trace. Series termination at the source is generally required to
provide transmission line matching and/or to reduce current
transients at the driver.
The value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS
outputs are also limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
3 inches are recommended to preserve signal rise/fall times and
signal integrity.
50Ω
83Ω
CMOS
07217-045
83Ω
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9520 do not supply enough current
to provide a full voltage swing with a low impedance resistive, farend termination, as shown in Figure 72. The far-end termination
network should match the PCB trace impedance and provide the
desired switching point. The reduced signal swing may still meet
receiver input requirements in some applications. This can be
useful when driving long trace lengths on less critical nets.
50Ω
50Ω
LVPECL
07217-047
50Ω
LVPECL
Z0 = 50Ω
Figure 69. DC-Coupled 3.3V LVPECL Y-Termination
VS_DRV
VS
0.1nF
LVPECL
100Ω DIFFERENTIAL
100Ω
(COUPLED)
0.1nF TRANSMISSION LINE
VS
LVPECL
CMOS
200Ω
10Ω
50Ω
100Ω
CMOS
100Ω
07217-046
200Ω
CMOS
Figure 71. Series Termination of CMOS Output
VS = VS_DRV
Z0 = 50Ω
60.4Ω
(1.0 INCH)
MICROSTRIP
Figure 68. DC-Coupled 3.3V LVPECL Far-End Thevenin Termination
VS_DRV
10Ω
07217-077
VS_DRV
When single-ended CMOS clocking is used, some of the
following guidelines should be used.
07217-076
Thevenin-equivalent termination uses a resistor network to
provide 50 Ω termination to a dc voltage that is below VOL of
the LVPECL driver. In this case, VS_DRV on the AD9520
should equal VS of the receiving buffer. Although the resistor
combination shown results in a dc bias point of VS_DRV − 2 V,
the actual common-mode voltage is VS_DRV − 1.3 V because
there is additional current flowing from the AD9520 LVPECL
driver through the pull-down resistor.
Figure 72. CMOS Output with Far-End Termination
Figure 70. AC-Coupled LVPECL with Parallel Transmission Line
CMOS CLOCK DISTRIBUTION
The output drivers of the AD9520 can be configured as CMOS
drivers. When selected as a CMOS driver, each output becomes
a pair of CMOS outputs, each of which can be individually
turned on or off and set as inverting or noninverting. These
outputs are 3.3 V or 2.5 V CMOS compatible. However, every
output driver (including the LVPECL drivers) must be run at
either 2.5 V or 3.3 V. The user cannot mix and match 2.5 V and
3.3 V outputs.
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9520 offers LVPECL outputs
that are better suited for driving long traces where the inherent
noise immunity of differential signaling provides superior
performance for clocking converters.
Rev. 0 | Page 83 of 84
AD9520-4
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
48
64
49
1
PIN 1
INDICATOR
PIN 1
INDICATOR
0.50
BSC
0.50
0.40
0.30
1.00
0.85
0.80
SEATING
PLANE
33
32
16
17
0.05 MAX
0.02 NOM
0.30
0.23
0.18
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
6.35
6.20 SQ
6.05
EXPOSED PAD
(BOTTOM VIEW)
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
091707-C
8.75
BSC SQ
TOP VIEW
Figure 73. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
CP-64-4
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9520-4BCPZ 1
AD9520-4BCPZ-REEL71
AD9520-4/PCBZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
Z = RoHS Compliant Part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07217-0-9/08(0)
Rev. 0 | Page 84 of 84
Package Option
CP-64-4
CP-64-4