DRAM MT4C4001J Austin Semiconductor, Inc. PIN ASSIGNMENT 1 MEG x 4 DRAM (Top View) Fast Page Mode DRAM 20-Pin DIP (C, CN) AVAILABLE AS MILITARY SPECIFICATIONS DQ1 DQ2 WE\ RAS\ A9 A0 A1 A2 A3 Vcc • SMD 5962-90847 • MIL-STD-883 FEATURES • Industry standard x4 pinout, timing, functions, and packages • High-performance, CMOS silicon-gate process • Single +5V±10% power supply • Low-power, 2.5mW standby; 300mW active, typical • All inputs, outputs, and clocks are fully TTL and CMOS compatible • 1,024-cycle refresh distributed across 16ms • Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\ (CBR), and HIDDEN • FAST PAGE MODE access cycle • CBR with WE\ a HIGH (JEDEC test mode capable via WCBR) OPTIONS -7 -8 -10 -12 • Packages Ceramic DIP (300 mil) Ceramic DIP (400 mil) Ceramic LCC* Ceramic ZIP Ceramic SOJ Ceramic SOJ w/ Cu J-lead Ceramic Gull Wing CN C ECN CZ ECJ ECJA ECG 20-Pin DIP (CZ) DQ3 3 Vss 5 DQ2 7 RAS\ 9 A0 11 A2 13 Vcc 15 A5 17 A7 19 DQ1 DQ2 WE\ RAS\ A9 A0 A1 A2 A3 Vcc 2 3 4 5 1 26 25 24 23 22 Vss DQ4 DQ3 CAS\ OE\ 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 2 CAS\ 4 DQ4 6 DQ1 8 WE\ 10 A9 12 A1 14 A3 16 A4 18 A6 20 A8 GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS\ is used to latch the first 10 bits and CAS\ the later 10 bits. A READ or WRITE cycle is selected with the WE\ input. A logic HIGH on WE\ dictates READ mode while a logic LOW on WE\ dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE\ or CAS\, whichever occurs last. If WE\ goes LOW prior to CAS\ going LOW, the output pin(s) remain open (High-Z) until the next CAS\ cycle. If WE\ goes LOW after data reaches the output pin(s), Qs are activated and retain the selected cell data as long as CAS\ remains low (regardless of WE\ or RAS\). This LATE WE\ pulse results in a READ-WRITE cycle. The four data inputs and four data outputs are routed through four pins using common I/O and pin direction is controlled by WE\ and OE\. FAST-PAGEMODE operations allow faster data operations (READ, WRITE, or READ-MODIFY-WRITE) within a row address (A0-A9) defined page boundary. The FAST PAGE MODE (continued) No. 103 No. 104 No. 202 No. 400 No. 504 No. 504A No. 600 *NOTE: If solder-dip and lead-attach is desired on LCC packages, lead-attach must be done prior to the solderdip operation. For more products and information please visit our web site at www.austinsemiconductor.com MT4C4001J Rev. 2.2 06/05 Vss DQ4 DQ3 CAS\ OE\ A8 A7 A6 A5 A4 OE\ 1 MARKING • Timing 70ns access 80ns access 100ns access 120ns access 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20-Pin SOJ (ECJ,ECJA), 20-Pin LCC (ECN), & 20-Pin Gull Wing (ECG) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 DRAM MT4C4001J Austin Semiconductor, Inc. GENERAL DESCRIPTION (cont.) cycle is always initiated with a row address strobe-in by RAS\ followed by a column address strobed-in by CAS\. CAS\ may be toggled-in by holding RAS\ LOW and strobing-in different column addresses, thus executing faster memory cycles. Returning RAS\ HIGH terminates the FAST PAGE MODE operation. Returning RAS\ and CAS\ HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS\ HIGH time. Memory cell data is retained in its corrected stated by maintaining power and executing any RAS\ cycle (READ, WRITE, RAS\-ONLY, CAS\-BEFORE-RAS\, or HIDDEN REFRESH) so that all 1,024 combinations of RAS\ addresses (A0-A9) are executed at least every 16ms, regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS\ addressing. FUNCTIONAL BLOCK DIAGRAM FAST PAGE MODE 4 DATA IN BUFFER WE\ CAS\ *EARLY-WRITE DETECTION CIRCUIT DATA OUT BUFFER 4 DQ1 DQ2 DQ3 DQ4 4 NO. 2 CLOCK GENERATOR OE\ 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 COLUMN DECODER 10 4 Vcc Vss 1024 SENSE AMPLIFIERS I/O GATING REFRESH CONTROLLER 1024 x 4 ROW DECODER REFRESH COUNTER 10 10 RAS\ COLUMN ADDRESS BUFFER ROW ADDRESS BUFFERS (10) 10 1024 MEMORY ARRAY NO. 1 CLOCK GENERATOR NOTE: WE\ LOW prior to CAS\ LOW, EW detection circuit output is a HIGH (EARLY-WRITE) CAS\ LOW prior to WE\ LOW, EW detection circuit output is a LOW (LATE-WRITE) MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 DRAM MT4C4001J Austin Semiconductor, Inc. TRUTH TABLE ADDRESSES FUNCTION Standby READ EARLY-WRITE READ-WRITE FAST-PAGE-MODE READ FAST-PAGE-MODE EARLY-WRITE FAST-PAGE-MODE READ-WRITE RAS\-ONLY REFRESH 1st Cycle 2nd Cycle 1st Cycle 2nd Cycle 1st Cycle 2nd Cycle READ WRITE CAS\-BEFORE-RAS\ REFRESH HIDDEN REFRESH MT4C4001J Rev. 2.2 06/05 RAS\ H L L L L L L L L L L L H L L H L H L CAS\ H X L L L H L H L H L H L H L H L H L L L WE\ X H L H L H H L L H L H L X H L H OE\ X L X L H L L X X L H L H X L X X t R X ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW ROW ROW X t C X COL COL COL COL COL COL COL COL COL n/a COL COL X DATA IN/OUT DQ1-DQ4 High-Z Data Out Data In Data Out/Data In Data Out Data Out Data In Data In Data Out/Data In Data Out/Data In High-Z Data Out Data In High-Z Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 DRAM MT4C4001J Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Vss.................-1.0V to +7.0V Storage Temperature.......................................-65oC to +150oC Power Dissipation.................................................................1W Short Circuit Output Current...........................................50mA Lead Temperature (soldering 5 seconds).....................+270oC *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (NOTES: 1, 3, 4, 6, 7) (-55°C < TA < 125°C; VCC = 5V ±10%) PARAMETER/CONDITION Supply Voltage SYM MIN MAX UNITS VCC 4.5 5.5 V Input High (Logic 1) Voltage, All Inputs VIH 2.4 VCC+0.5 V Input Low (Logic 0) Voltage, All Inputs VIL -0.5 0.8 V II -5 5 µA IOZ -5 5 µA OUTPUT LEVELS Output High Voltage (IOUT = -5mA) VOH 2.4 Output Low Voltage (IOUT = 4.2mA) VOL INPUT LEAKAGE CURRENT Any Input 0V < VIN < 5.5V Vcc = 5.5V (All other pints not under test = 0V) OUTPUT LEAKAGE CURRENT (Q is Disabled, 0V < VOUT < 5.5V) Vcc = 5.5V PARAMETER/CONDITION STANDBY CURRENT (TTL) (RAS\ = CAS\ = VIH) NOTES V 0.4 MAX -10 V SYM -7 -8 ICC1 4 4 4 4 mA STANDBY CURRENT (CMOS) (RAS\ = CAS\ = VCC -0.2V; all other inputs = VCC -0.2V) ICC2 2 2 2 2 mA OPERATING CURRENT: Random READ/WRITE Average Power-Supply Current (RAS\, CAS\, Address Cycling: tRC = tRC(MIN)) ICC3 85 75 65 70 mA 3, 4 OPERATING CURRENT: FAST PAGE MODE Average Power-Supply Current (RAS\ = VIL, CAS\, Address Cycling: tPC = tPC (MIN)) ICC4 60 50 45 40 mA 3, 4 REFRESH CURRENT: RAS\-ONLY Average Power-Supply Current (RAS\ Cycling, CAS\ = VIH: tRC = tRC (MIN)) ICC5 85 75 65 70 mA 3 REFRESH CURRENT: CAS\-BEFORE-RAS\ Average Power-Supply Current (RAS\, CAS\, Address Cycling: tRC = tRC (MIN)) ICC6 85 75 65 70 mA 3, 5 MT4C4001J Rev. 2.2 06/05 -12 UNITS NOTES Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 DRAM MT4C4001J Austin Semiconductor, Inc. CAPACITANCE PARAMETER Input Capacitance: A0-A10 SYM MIN MAX UNITS NOTES CI1 7 pF 2 Input Capacitance: RAS\, CAS\, WE\, OE\ CI2 7 pF 2 Input/Output Capacitance: DQ CIO 8 pF 2 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C < TC < 125°C; VCC = 5V ±10%) -7 PARAMETER Random READ or WRITE cycle time READ-WRITE cycle time FAST-PAGE-MODE READ or WRITE cycle time FAST-PAGE-MODE READ-WRITE cycle time -8 MAX MIN -10 MAX MIN tRC 130 150 190 220 tRWC 180 200 240 255 ns tPC 40 45 55 70 ns tPRWC 90 90 MIN -12 SYM MAX 110 MIN MAX UNITS NOTES ns 140 ns Access time from RAS\ tRAC 70 80 90 120 ns 14 Access time from CAS\ tCAC 20 20 25 30 ns 15 Access time from column address tAA 35 40 45 60 ns Access time from CAS\ precharge tCPA 35 40 45 60 ns RAS\ pulse width tRAS 70 10,000 80 10,000 100 10,000 120 100,000 ns RAS\ pulse width (FAST PAGE MODE) tRASP 70 100,000 80 100,000 100 100,000 120 100,000 ns RAS\ hold time tRSH 20 20 25 30 RAS\ precharge time tRP 50 60 70 90 ns CAS\ pulse width tCAS 20 30 ns CAS\ hold time tCSH 70 80 100 120 ns CAS\ precharge time tCPN 10 10 12 15 ns CAS\ precharge time (FAST PAGE MODE) tCP 10 10 12 15 ns RAS\ to CAS\ delay time tRCD 20 CAS\ to RAS\ precharge time tCRP 5 10,000 50 20 20 10,000 60 5 25 25 10,000 75 5 25 ns 90 10 16 ns 17 ns Row address setup time tASR 0 0 0 0 ns Row address hold time tRAH 10 10 15 15 ns RAS\ to column address delay time tRAD 15 Column address setup time tASC 0 0 0 0 ns Column address hold time tCAH 15 15 20 25 ns Column address hold time (referenced to RAS\) tAR 50 60 70 85 ns Column address to RAS\ lead time tRAL 35 40 50 60 ns Read command setup time tRCS 0 0 0 0 ns Read command hold time (referenced to CAS\) tRCH 0 0 0 0 ns 19 Read command hold time (referenced to RAS\) tRRH 0 0 0 0 ns 19 CAS\ to output in Low-Z tCLZ 0 0 0 0 ns Output buffer turn-off delay tOFF 0 WE\ command setup time tWCS 0 MT4C4001J Rev. 2.2 06/05 35 20 15 0 0 40 20 20 0 0 50 20 20 0 0 60 20 ns 18 ns 20 ns 21, 27 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 DRAM MT4C4001J Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C < TC < 125°C; VCC = 5V ±10%) -7 PARAMETER -8 MAX MIN -10 MAX MIN -12 SYM MIN MAX MIN Write command hold time tWCH 15 15 20 25 MAX UNITS ns Write command hold time (referenced to RAS\) NOTES tWCR 50 60 70 80 ns Write command pulse width tWP 15 15 20 25 ns Write command to RAS\ lead time tRWL 20 20 25 30 ns Write commend to CAS\ lead time tCWL 20 20 25 30 ns Data-in setup time tDS 0 0 0 0 ns 22 Data-in hold time tDH 12 15 18 25 ns 22 Data-in hold time (referenced to RAS\) tDHR 50 60 70 90 ns RAS\ to WE\ delay time tRWD 95 105 130 140 ns Column address to WE\ delay time tAWD 60 65 80 90 ns 21 CAS\ to WE\ delay time tCWD 45 45 55 60 ns 21 tT 3 Transition time (rise or fall) 50 3 16 50 3 16 50 3 16 50 ns 16 ms 21 Refresh period (1,024 cycles) tREF RAS\ to CAS\ precharge time tRPC 0 0 0 0 CAS\ setup time (CAS\-BEFORE-RAS\ REFRESH) tCSR 5 10 10 10 ns 5 CAS\ hold time (CAS\-BEFORE-RAS\ REFRESH) tCHR 10 15 20 25 ns 5 WE\ hold time (CAS\-BEFORE-RAS\ REFRESH) tWRH 10 10 10 10 ns 25, 28 WE\ setup time (CAS\-BEFORE-RAS\ REFRESH) tWRP 10 10 10 10 ns 25, 28 WE\ hold time (WCBR test cycle) tWTH 10 10 10 10 ns 25, 28 WE\ setup time (WCBR test cycle) tWTS 10 10 10 10 ns 25, 28 OE\ setup prior to RAS during HIDDEN REFRESH cycle tORD 0 0 0 0 ns ns Output disable tOD 15 20 25 25 ns 27 Output enable tOE 15 20 25 25 ns 23 ns 26 OE\ hold time from WE\ during READ-MODIFY-WRITE cycle MT4C4001J Rev. 2.2 06/05 tOEH 20 20 25 25 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 DRAM Austin Semiconductor, Inc. MT4C4001J NOTES: point only; if tRAD is greater than the specified tRAD (MAX) limit, then access time is controlled exclusively by tAA. 19. Either tRCH or tRRH must be satisfied for a READ cycle. 20. tOFF (MAX) defines the time at which the output achieves the open circuit conditions and is not referenced to VOH or VOL. 21. tWCS, tRWD, tAWD, and tCWD are not restrictive operating parameters. tWCS applies to EARLY-WRITE cycles. tRWD, tAWD, and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS > tWCS (MIN), the cycle is an EARLY-WRITE cycles and the data output will remain an open circuit throughout the entire cycle. If tRWD > tRWD (MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-MODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of the data out is indeterminate. OE\ held HIGH and WE\ taken LOW after CAS\ goes LOW results in a LATE-WRITE (OE\ controlled) cycle. t WCS , t RWD , t CWD, and t AWD are not applicable in a LATE-WRITE cycle. 22. These parameters are referenced to CAS\ leading edge in EARLY-WRITE cycle and WE\ leading edge in LATE-WRITE cycles and WE\ leading edge in LATE-WRITE or READ-MODIFY-WRITE cycle. 23. If OE\ is tied permanently LOW, LATE-WRITE or READ-MODIFY-WRITE operations are not possible. 24. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE\=LOW and OE\=HIGH. 25. tWTS and tWTH are setup and hold specifications for the WE\ pin being held LOW to enable the JEDEC test mode (with CBR timing constraints). These two parameters are the inverts of tWRP and tWRH in the CBR REFRESH cycle. 26. LATE-WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE\ HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS\ remains LOW and OE\ is taken back LOW after tOEH is met. If CAS\ goes HIGH prior to OE\ going back LOW, the DQs will remain open. 27. The DQs open during READ cycles once tOD or tOFF occur. If CAS\ goes HIGH first, OE\ becomes a “don’t care.” If OE\ goes HIGH and CAS\ stays LOW, OE\ is not a “don’t care;” and the DQs will provide the previously read data if OE\ is taken back LOW (while CAS\ remains LOW). 28. JEDEC test mode only. 1. All voltages referenced to Vss. 2. This parameter is sampled, not 100% tested. Capacitance is measured with Vcc=5V, f=1 MHz at less than 50mVrms, TA = 25°C ±3°C, Vbias = 2.4V applied to each input and output individually with remaining inputs and outputs open. 3. Icc is dependent on cycle rates. 4. Icc is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the output open. 5. Enables on-chip refresh and address counters. 6. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-55°C < TA < 125°C) is assured. 7. An initial pause of 100µs is required after power-up followed by eight RAS\ refresh cycles (RAS\-ONLY or CBR with WE\ HIGH) before proper device operation is assured. The eight RAS\ cycle wake-up should be repeated any time the 16ms refresh requirement is exceeded. 8. AC characteristics assume tT = 5ns. 9. V IH (MIN) and V IL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 10. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 11. If CAS\ = VIH, data outputs (DQs) are High-Z. 12. If CAS\ = VIL, data outputs (DQs) may contain data from the last valid READ cycle. 13. Measured with a load equivalent to two TTL gates and 100pF. 14. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 15. Assumes that tRCD > tRCD (MAX) 16. If CAS\ is LOW at the falling edge of RAS\, DQs will be maintained from the previous cycle. To initiate a new cycle and clear the data out buffer, CAS\ must be pulsed HIGH for tCPN. 17. Operation within the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, then access time is controlled exclusively by tCAC. 18. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 DRAM Austin Semiconductor, Inc. MT4C4001J READ CYCLE EARLY-WRITE CYCLE MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 DRAM Austin Semiconductor, Inc. MT4C4001J READ-WRITE CYCLE (LATE-WRITE and READ-MODIFY-WRITE CYCLES) FAST-PAGE-MODE READ CYCLE MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 DRAM Austin Semiconductor, Inc. MT4C4001J FAST-PAGE-MODE EARLY-WRITE CYCLE FAST-PAGE-MODE READ-WRITE CYCLE (LATE-WRITE and READ-MODIFY-WRITE CYCLES) *tPC = LATE-WRITE cycle tPRWC = FAST READ-MODIFY-WRITE cycle MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 DRAM Austin Semiconductor, Inc. MT4C4001J RAS\-ONLY REFRESH CYCLE (ADDR = A0-A9; WE\ = Don’t Care) CAS\-BEFORE-RAS\ REFRESH CYCLE (A0-A9, and OE\ = DON’T CARE) HIDDEN REFRESH CYCLE24 (WE\ = HIGH, OE\ = LOW) MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 DRAM Austin Semiconductor, Inc. MT4C4001J POWER-UP 4 MEG POWER-UP AND REFRESH CONSTRAINTS The EIA/JEDEC 4 Meg DRAM introduces two potential incompatibilities compared to the previous generation 1 Meg DRAM. The incompatibilities involve refresh and power-up. Understanding these incompatibilities and providing for them will offer the designer and system user greater compatibility between the 1 Meg and 4 Meg. REFRESH The most commonly used refresh mode of the 1 Meg is the CBR (CAS\-BEFORE-RAS\) REFRESH cycle. The CBR for the 1 Meg specifies the WE\ pin as a “don’t care.” The 4 Meg, on the other hand, specifies the CBR REFRESH mode with the WE\ pin held at a voltage HIGH level. A CBR cycle with WE\ LOW will put the 4 Meg into the JEDEC specified test mode (WCBR). The 4 Meg JEDEC test mode constraint may introduce another problem. The 1 Meg POWER-UP cycle requires a 100µs delay followed by any eight RAS\ cycles. The 4 Meg POWER-UP is more restrictive in that eight RAS\-ONLY or CBR REFRESH (WE\ held HIGH) cycles must be used. The restriction is needed since the 4 Meg may power-up in the JEDEC specified test mode and must exit out of the test mode. The only way to exit the 4 Meg JEDEC test mode is with either a RAS\-ONLY or a CBR REFRESH cycle (WE\ held HIGH). SUMMARY 1. The 1 Meg CBR REFRESH allows the WE\ pin to be “don’t care” while the 4 Meg CBR requires WE\ to be HIGH. 2. The eight RAS\ wake-up cycles on the 1 Meg may be any valid RAS\ cycle while the 4 Meg may only use RAS\-ONLY or CBR REFRESH cycles (WE\ held HIGH). COMPARISON OF 4 MEG TEST MODE AND WCBR TO 1 MEG CBR MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 DRAM MT4C4001J Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #103 (Package Designator CN) SMD 5962-90847, Case Outline R D A Q L E S1 b2 e b Pin 1 R eA c SMD Specifications SYMBOL A b b2 c D E eA e Q L S1 R MIN --0.014 0.045 0.008 --0.220 MAX 0.200 0.026 0.065 0.018 1.060 0.310 0.300 BSC 0.100 BSC 0.015 0.125 0.005 90° 0.070 0.200 --105° NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits. * All measurements are in inches. MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 DRAM MT4C4001J Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #104 (Package Designator C) SMD 5962-90847, Case Outline U D D1 A Q L E S1 b2 e b Pin 1 eA c SMD Specifications SYMBOL A b b2 c D D1 E eA e Q L S1 MIN --0.015 0.045 0.008 0.980 0.890 0.380 0.385 MAX 0.175 0.021 0.065 0.014 1.030 0.910 0.410 0.420 0.100 BSC 0.015 0.125 --- 0.060 0.200 0.070 NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits. * All measurements are in inches. MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 DRAM Austin Semiconductor, Inc. MT4C4001J MECHANICAL DEFINITIONS* ASI Case #400 (Package Designator CZ) SMD 5962-90847, Case Outline N SMD SPECIFICATIONS SYMBOL MIN MAX A 0.355 0.405 b 0.016 0.023 b2 0.035 0.045 c 0.008 0.015 e 0.045 0.055 eA 0.085 0.115 D 1.035 1.065 E 0.100 0.130 L 0.125 0.200 L1 0.015 0.050 NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits. * All measurements are in inches. MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 DRAM MT4C4001J Austin Semiconductor, Inc. ASI Case #202 (Package Designator ECN) SMD 5962-90847, Case Outline T L1 S e E1 E b R L D A A1 SYMBOL A A1 b D E E1 e L L1 R S SMD SPECIFICATIONS MIN MAX 0.060 0.080 0.035 TYP 0.022 0.028 0.343 0.357 0.665 0.685 0.590 0.610 0.050 TYP 0.045 0.055 0.080 0.100 0.006 0.010 0.025 0.050 NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits. * All measurements are in inches. MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 DRAM Austin Semiconductor, Inc. MT4C4001J MECHANICAL DEFINITION* ASI Case #504 (Package Designator ECJ) NOTE: The Difference between the ECJ & ECJA packages is that the ECJA has different lead attach with 5% Sn / 95% Pb solder connection whereas the ECJ package uses compression weld lead attach. Both package’s lead material is JEDEC TYPE MO-110 option A ‘J’ Form Copper material. SYMBOL A A1 b b1 b2 D D1 E E1 e L ASI SPECIFICATIONS MIN MAX 0.12 0.14 0.035 TYP 0.012 DIA 0.016 DIA 0.050 TYP 0.09 0.110 0.665 0.685 0.592 0.608 0.345 0.355 0.300 0.315 0.045 0.055 0.055 0.065 *All measurements are in inches. MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 17 DRAM Austin Semiconductor, Inc. MT4C4001J MECHANICAL DEFINITION* ASI Case #504A (Package Designator ECJA) NOTE: The Difference between the ECJ & ECJA packages is that the ECJA has different lead attach with 5% Sn / 95% Pb solder connection whereas the ECJ package uses compression weld lead attach. Both package’s lead material is JEDEC TYPE MO-110 option A ‘J’ Form Copper material. SYMBOL A A1 b b1 b2 D D1 E E1 e L ASI SPECIFICATIONS MIN MAX 0.12 0.14 0.035 TYP 0.012 DIA 0.016 DIA 0.050 TYP 0.09 0.110 0.665 0.685 0.592 0.608 0.345 0.355 0.300 0.315 0.045 0.055 0.055 0.065 *All measurements are in inches. MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 18 DRAM Austin Semiconductor, Inc. MT4C4001J MECHANICAL DEFINITION* ASI Case #600 (Package Designator ECG) SYMBOL A A1 b b1 b2 D D1 E E1 E2 e e1 L ASI PACKAGE SPECIFICATIONS MIN MAX 0.120 0.140 0.066 0.078 0.022 0.028 0.050 TYP 0.090 0.110 0.665 0.685 0.592 0.608 0.345 0.355 0.482 0.498 0.442 0.458 0.045 0.055 0.014 Dia. TYP 0.057 0.063 *All measurements are in inches. MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 19 DRAM Austin Semiconductor, Inc. MT4C4001J ORDERING INFORMATION EXAMPLE: MT4C4001JCN-8/883C Device Package Speed ns Number Type MT4C4001J CN -7 MT4C4001J CN -8 MT4C4001J CN -10 MT4C4001J CN -12 EXAMPLE: MT4C4001JCZ-7/883C Device Package Speed ns Number Type MT4C4001J CZ -7 MT4C4001J CZ -8 MT4C4001J CZ -10 MT4C4001J CZ -12 EXAMPLE: MT4C4001JECJ-7/IT Device Package Speed ns Number Type MT4C4001J ECJ -7 MT4C4001J ECJ -8 MT4C4001J ECJ -10 MT4C4001J ECJ -12 EXAMPLE: MT4C4001JECJA-7/IT Device Package Speed ns Number Type MT4C4001J ECJA -7 MT4C4001J ECJA -8 MT4C4001J ECJA -10 MT4C4001J ECJA -12 EXAMPLE: MT4C4001JC-12/883C Device Package Speed ns Number Type MT4C4001J C -7 MT4C4001J C -8 MT4C4001J C -10 MT4C4001J C -12 Process /* /* /* /* EXAMPLE: MT4C4001JECN-10/XT Device Package Speed ns Number Type MT4C4001J ECN -7 MT4C4001J ECN -8 MT4C4001J ECN -10 MT4C4001J ECN -12 Process /* /* /* /* EXAMPLE: MT4C4001JECG-12/IT Device Package Speed ns Number Type MT4C4001J ECG -7 MT4C4001J ECG -8 MT4C4001J ECG -10 MT4C4001J ECG -12 Process /* /* /* /* /* /* /* /* Process /* /* /* /* Process /* /* /* /* Process /* /* /* /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing MT4C4001J Rev. 2.2 06/05 Process Temperature -40oC to +85oC -55oC to +125oC -55oC to +125oC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 20 DRAM Austin Semiconductor, Inc. MT4C4001J ASI TO DSCC PART NUMBER CROSS REFERENCE* ASI Package Designator CZ ASI Part # MT4C4001JCZ-8/883C MT4C4001JCZ-10/883C MT4C4001JCZ-12/883C ASI Package Designator C SMD Part # 5962-9084703MNA 5962-9084702MNA 5962-9084701MNA ASI Part # MT4C4001JC-8/883C MT4C4001JC-10/883C MT4C4001JC-12/883C ASI Package Designator CN ASI Part # MT4C4001JCN-8/883C MT4C4001JCN-10/883C MT4C4001JCN-12/883C SMD Part # 5962-9084703MUA 5962-9084702MUA 5962-9084701MUA ASI Package Designator ECN SMD Part # 5962-9084703MRA 5962-9084702MRA 5962-9084701MRA ASI Part # MT4C4001JECN-8/883C MT4C4001JECN-10/883C MT4C4001JECN-12/883C SMD Part # 5962-9084703MTA 5962-9084702MTA 5962-9084701MTA * ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 21