SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003 D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Contain Four Flip-Flops With Double-Rail Outputs Typical tpd = 13 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Applications Include: − Buffer/Storage Registers − Shift Registers − Pattern Generators SN54HC175 . . . FK PACKAGE (TOP VIEW) 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4Q 4Q 4D 3D 3Q 3Q CLK 1Q 1D NC 2D 2Q 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4Q 4D NC 3D 3Q 2Q GND NC CLK 3Q CLR 1Q 1Q 1D 2D 2Q 2Q GND 1Q CLR NC VCC 4Q SN54HC175 . . . J OR W PACKAGE SN74HC175 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) NC − No internal connection description/ordering information These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. The ’HC175 devices feature complementary outputs from each flip-flop. ORDERING INFORMATION PACKAGE† TA PDIP − N SN74HC175N Tube of 40 SN74HC175D Reel of 2500 SN74HC175DR Reel of 250 SN74HC175DT SOP − NS Reel of 2000 SN74HC175NSR HC175 SSOP − DB Reel of 2000 SN74HC175DBR HC175 Tube of 90 SN74HC175PW Reel of 2000 SN74HC175PWR Reel of 250 SN74HC175PWT CDIP − J Tube of 25 SNJ54HC175J SNJ54HC175J CFP − W Tube of 150 SNJ54HC175W SNJ54HC175W LCCC − FK Tube of 55 SNJ54HC175FK TSSOP − PW −55°C −55 C to 125 125°C C TOP-SIDE MARKING Tube of 25 SOIC − D −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER SN74HC175N HC175 HC175 SNJ54HC175FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* &)$#!" #&(! ! 0121 (( &%!%" % !%"!%) $(%"" !+%-"% !%)* (( !+% &)$#!" &)$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003 description/ordering information (continued) Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output. FUNCTION TABLE (each flip-flop) INPUTS CLR CLK OUTPUTS D Q Q H L X X L H ↑ H H L H ↑ L L H H L X Q0 Q0 logic diagram (positive logic) CLR CLK 1D 1 9 4 1D 2 1Q C1 R 3 1Q To Three Other Channels Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 3) SN54HC175 VCC Supply voltage VIH VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO Input voltage NOM MAX 2 5 6 NOM MAX 2 5 6 1.5 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition rise/fall time MIN 1.5 0 Output voltage ∆t/∆v MIN VCC = 4.5 V VCC = 6 V Low-level input voltage SN74HC175 0 VCC VCC 0 1000 1000 500 500 400 400 V V V ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS Ci SN54HC175 MIN MAX SN74HC175 MIN MAX UNIT 2V 1.9 1.998 1.9 1.9 IOH = −20 µA 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 IOH = −4 mA IOH = −5.2 mA 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 2V 0.002 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 8 160 80 µA 10 10 10 pF VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, TA = 25°C MIN TYP MAX 4.5 V IOL = 4 mA IOL = 5.2 mA II ICC VCC IO = 0 6V 2 V to 6 V POST OFFICE BOX 655303 3 • DALLAS, TEXAS 75265 V V 3 SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency CLR low tw Pulse duration CLK high or low Data tsu Setup time before CLK↑ CLR inactive th CLK↑ Hold time, data after CLK TA = 25°C MIN MAX SN54HC175 MIN MAX SN74HC175 MIN MAX 2V 6 4.2 5 4.5 V 31 21 25 6V 36 25 29 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 0 0 0 4.5 V 0 0 0 6V 0 0 0 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax CLR Any tpd CLK tt Any Any VCC MIN TA = 25°C TYP MAX SN54HC175 MIN MAX SN74HC175 MIN 2V 6 12 4.2 5 4.5 V 31 50 21 25 6V 36 60 25 29 MAX UNIT MHz 2V 52 150 255 190 4.5 V 15 30 45 38 6V 13 26 38 32 2V 58 150 255 190 4.5 V 16 30 45 38 6V 13 26 38 32 2V 38 75 110 90 4.5 V 8 15 22 19 6V 6 13 19 16 ns ns operating characteristics, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance per flip-flop POST OFFICE BOX 655303 No load • DALLAS, TEXAS 75265 TYP 30 UNIT pF SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 50% 10% 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 14-Mar-2007 PACKAGING INFORMATION (1) Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 84089012A ACTIVE LCCC FK 20 1 TBD 8408901EA ACTIVE CDIP J 16 1 TBD Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type 8408901FA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type JM38510/65308BEA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type JM38510/65308BFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type N / A for Pkg Type SN54HC175J ACTIVE CDIP J 16 1 TBD A42 SNPB SN74HC175D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175DBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175DBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175DE4 ACTIVE SOIC D 16 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175DT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175DTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74HC175NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74HC175NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175PWLE OBSOLETE TSSOP PW 16 SN74HC175PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC175PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54HC175FK ACTIVE LCCC FK 20 1 TBD SNJ54HC175J ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type SNJ54HC175W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type 40 TBD The marketing status values are defined as follows: Addendum-Page 1 Call TI Call TI POST-PLATE N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 14-Mar-2007 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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