ALSC AS7C34098A-20JCN 3.3 v 256 k x 16 cmos sram Datasheet

AS7C34098A
August 2004
®
3.3 V 256 K × 16 CMOS SRAM
Features
• Pin compatible with AS7C34098
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Low power consumption: ACTIVE
- 650 mW /max @ 10 ns
• Low power consumption: STANDBY
- 28.8 mW /max CMOS
• Individual byte read/write controls
Logic block diagram
44-pin (400 mil) SOJ
TSOP2
VCC
Row Decoder
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
Pin arrangement for SOJ and TSOP 2
1024 × 256 × 16
Array
(4,194,304)
I/O
buffer
Control circuit
Column decoder
A5
A9
A10
A11
A14
A15
A16
A17
WE
UB
OE
LB
CE
A0
A1
A2
A3
A4
CE
I/O1
I/O2
I/O3
I/O4
VCC
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
Selection guide
–10
–12
–15
–20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
4
5
6
7
ns
Industrial
180
160
140
110
mA
Commercial
170
150
130
100
mA
8
8
8
8
mA
Maximum operating current
Maximum CMOS standby current
8/17/04, v. 2.1
Alliance Semiconductor
P. 1 of 10
Copyright © Alliance Semiconductor. All rights reserved.
AS7C34098A
®
Functional description
The AS7C34098A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
262,144 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 4/5/6/7 ns are
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.
When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in
CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input
pins I/O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 3.3V (AS7C34098A) supply. The device is
available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
Vt1
–0.50
+5.0
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC +0.50
V
Power dissipation
PD
–
1.5
W
Storage temperature (plastic)
Tstg
–65
+150
°C
Ambient temperature with VCC applied
Tbias
–55
+125
°C
DC current into outputs (low)
IOUT
–
±20
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
LB
UB
I/O1–I/O8
I/O9–I/O16
Mode
H
X
X
X
X
High Z
High Z
Standby (ISB, ISB1)
High Z
High Z
Output disable (ICC)
L
H
H
X
X
L
X
X
H
H
L
H
DOUT
High Z
L
H
L
H
L
High Z
DOUT
L
L
DOUT
DOUT
L
H
DIN
High Z
H
L
High Z
DIN
L
L
DIN
DIN
L
L
X
Read (ICC)
Write (ICC)
Key: X = Don’t care, L = Low, H = High.
8/17/04,v. 2.1
Alliance Semiconductor
P. 2 of 10
AS7C34098A
®
Recommended operating conditions
Parameter
Symbol
Supply voltage
Min Typical
VCC (10/12/15/20)
VIH
Unit
3.0
3.3
3.6
V
2.0
–
VCC + 0.5
V
VIL*
–0.5
–
0.8
V
commercial
TA
0
–
70
°C
industrial
TA
–40
–
85
°C
Input voltage
Ambient operating temperature
**
Max
*
VIL min = –1.0V for pulse width less than 5ns.
** V max = V + 2.0V for pulse width less than 5ns.
IH
CC
DC operating characteristics (over the operating range)1
–10
Test conditions
–12
–15
–20
Parameter
Symbol
Input leakage
current
|ILI|
VCC = Max
VIN = GND to VCC
–
1
–
1
–
1
–
1
µA
Output leakage
current
|ILO|
VCC = Max
CE = VIH or OE = VIH
or WE = VIL
VI/O = GND to VCC
–
1
–
1
–
1
–
1
µA
Operating
power supply
current
Industrial
–
180
–
160
–
140
–
110 mA
ICC
Commercial
-
170
-
150
-
130
-
100 mA
–
60
–
60
–
60
–
60
mA
–
8
–
8
–
8
–
8
mA
VCC = Max
CE ≤ VIL, f = fmax IOUT = 0mA
VCC = Max
CE ≥ VIH, f = Max
ISB
Standby power
supply current
ISB1
Min Max Min Max Min Max Min Max Unit
VCC = Max
CE ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or
VIN ≤ 0.2V, f = 0
Output voltage
VOL
IOL = 8 mA, VCC = Min
–
0.4
–
0.4
–
0.4
–
0.4
V
VOH
IOH = –4 mA, VCC = Min
2.4
–
2.4
–
2.4
–
2.4
–
V
Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)2
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
CIN
A, CE, WE, OE, UB, LB
VIN = 0V
6
pF
I/O capacitance
CI/O
I/O
VIN = VOUT = 0V
8
pF
8/17/04,v. 2.1
Alliance Semiconductor
P. 3 of 10
AS7C34098A
®
Read cycle (over the operating range)3,9
–10
Parameter
–12
–15
–20
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit Notes
Read cycle time
tRC
10
–
12
–
15
–
20
–
ns
Address access time
tAA
–
10
–
12
–
15
–
20
ns
Chip enable (CE) access time
tACE
–
10
–
12
–
15
–
20
ns
Output enable (OE) access time
tOE
–
4
–
5
–
6
–
7
ns
Output hold from address change
tOH
3
–
3
–
3
–
3
–
ns
5
CE Low to output in low Z
tCLZ
3
–
3
–
3
–
3
–
ns
4, 5
CE High to output in high Z
tCHZ
–
5
–
6
–
7
–
9
ns
4, 5
OE Low to output in low Z
tOLZ
0
–
0
–
0
–
0
–
ns
4, 5
OE High to output in high Z
tOHZ
–
5
–
6
–
7
–
9
ns
4, 5
LB, UB access time
tBA
–
5
–
6
–
7
–
8
ns
LB, UB Low to output in low Z
tBLZ
0
–
0
–
0
–
0
–
ns
LB, UB High to output in high Z
tBHZ
–
5
–
6
–
7
–
9
ns
Power up time
tPU
0
–
0
–
0
–
0
–
ns
5
Power down time
tPD
–
10
–
12
–
15
–
20
ns
5
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)6,7,9
tRC
Address
tOH
DataOUT
8/17/04,v. 2.1
tAA
Previous data valid
tOH
Data valid
Alliance Semiconductor
P. 4 of 10
AS7C34098A
®
Read waveform 2 (CE, OE, UB, LB controlled)6,8,9
tRC
Address
tAA
OE
tOHZ
tOE
tOH
tOLZ
CE
tACE
tCLZ
tCHZ
LB, UB
tBA
tBHZ
tBLZ
DataOUT
Data valid
Write cycle (over the operating range)10
–10
Parameter
Symbol Min
–12
–15
–20
Max
Min
Max
Min
Max
Min
Max
Unit
Note
Write cycle time
tWC
10
–
12
–
15
–
20
–
ns
Chip enable (CE) to write end
tCW
7
–
8
–
10
–
12
–
ns
Address setup to write end
tAW
7
–
8
–
10
–
12
–
ns
Address setup time
tAS
0
–
0
–
0
–
0
–
ns
Write pulse width (OE = High)
tWP1
7
–
8
–
10
–
12
–
ns
Write pulse width (OE = Low)
tWP2
10
–
12
–
15
–
20
–
ns
Write recovery time
tWR
0
–
0
–
0
–
0
–
ns
Address hold from end of write
tAH
0
–
0
–
0
–
0
–
ns
Data valid to write end
tDW
5
–
6
7
–
9
–
ns
Data hold time
tDH
0
–
0
–
0
–
0
–
ns
4, 5
Write enable to output in High-Z
tWZ
0
5
0
6
0
7
0
9
ns
4, 5
Output active from write end
tOW
3
–
3
–
3
–
3
–
ns
4, 5
Byte enable Low to write end
tBW
7
–
8
–
10
–
12
–
ns
4, 5
8/17/04,v. 2.1
Alliance Semiconductor
P. 5 of 10
AS7C34098A
®
Write waveform 1(WE controlled)10
tWC
tAH
tWR
Address
tCW
CE
tBW
LB, UB
tAW
tAS
tWP
WE
tDW
DataIN
Data valid
tWZ
DataOUT
tDH
tOW
Data undefined
High Z
Write waveform 2 (CE controlled)10
tWC
tAH
tWR
Address
tAS
CE
tCW
tAW
tBW
LB, UB
tWP
WE
tDW
DataIN
DataOUT
8/17/04,v. 2.1
tCLZ
High Z
tWZ
Data undefined
Alliance Semiconductor
tDH
Data valid
tOW
High Z
P. 6 of 10
AS7C34098A
®
Write waveform 3 10
tWC
tAH
tWR
Address
tAS
tCW
CE
tAW
tBW
LB, UB
tWP
WE
tDW
DataIN
Data valid
tDH
tWZ
DataOUT
Data undefined
High Z
High Z
AC test conditions
-
Output load: see Figure B.
Input pulse level: GND to 3.0V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
320Ω
+3.0V
GND
+3.3V
90%
90%
10%
10%
2 ns
Figure A: Input pulse
DOUT
350Ω
C11
Thevenin equivalent:
168Ω
DOUT
+1.728V
GND
Figure B: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A and B.
tCLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
C=30pF, except on High Z and Low Z parameters, where C=5pF.
8/17/04,v. 2.1
Alliance Semiconductor
P. 7 of 10
AS7C34098A
®
Package dimensions
c
44 434241403938373635343332313029282726252423
e He
44-pin TSOP 2
1 2 3 4 5 6 7 8 9 101112131415161718 19202122
d
l
A2
A
0–5°
A1
E
b
e
E1E2
Pin 1
c
B
A
A2
A1
8/17/04,v. 2.1
A
A1
A2
B
b
c
D
E
E1
E2
e
44-pin SOJ 400 mils
Min(mils) Max(mils)
0.128
0.148
0.025
0.105
0.115
0.026
0.032
0.015
0.020
0.007
0.013
1.120
1.130
0.370 NOM
0.395
0.405
0.435
0.445
0.050 NOM
D
44-pin SOJ
b
A
A1
A2
b
c
d
e
He
E
l
44-pin TSOP 2
Min (mm) Max (mm)
1.2
0.05
0.15
0.95
1.05
0.3
0.45
0.21
0.12
18.31
18.52
10.06
10.26
11.68
11.94
0.80 (typical)
0.40
0.60
Seating
Plane
E
Alliance Semiconductor
P. 8 of 10
AS7C34098A
®
Ordering Codes
Package
SOJ
TSOP 2
Temperature
10 ns
12 ns
15 ns
20 ns
Commercial
AS7C34098A-10JC
AS7C34098A-12JC
AS7C34098A-15JC
AS7C34098A-20JC
Industrial
AS7C34098A-10JI
AS7C34098A-12JI
AS7C34098A-15JI
AS7C34098A-20JI
Commercial
AS7C34098A-10TC
AS7C34098A-12TC
AS7C34098A-15TC
AS7C34098A-20TC
Industrial
AS7C34098A-10TI
AS7C34098A-12TI
AS7C34098A-15TI
AS7C34098A-20TI
Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts. (EX: AS7C34098A - 10TCN)
Part numbering system
AS7C
SRAM prefix
X
4098A
–XX
J or T
Voltage:
Device Access
3 - 3.3V CMOS number time
8/17/04,v. 2.1
Packages:
J: SOJ 400 mil
T: TSOP 2
Alliance Semiconductor
X
X
Temperature ranges:
C: Commercial, 0°C to 70°C N = Lead Free Parts
I: Industrial, –40°C to 85°C
P. 9 of 10
AS7C34098A
®
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C34098A
Document Version: v. 2.1
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related
to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and
Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of
Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other
intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems
where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such lifesupporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.