HANBit HMS12832M4 HAN SRAM MODULE 512KByte (128K x 32-Bit) BIT Part No. HMS12832M4 GENERAL DESCRIPTION The HMS12832M4 is a high-speed static random access memory (SRAM) module containing 131,072 words organized in a x32-bit configuration. The module consists of four 128K x 8 SRAMs mounted on a 64-pin, singlesided, FR4-printed circuit board. PD0 and PD1 identify the module’s density allowing interchangeable use of alternate density, industry- standard modules. Four chip enable inputs, (/CE1, /CE2, /CE3 and /CE4) are used to enable the module’s 4 bytes independently. Output enable(/OE) and write enable(/WE) can set the memory input and output. Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW. Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW. For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be powered from a single +5V DC power supply and all inputs and outputs are fully TTL-compatible. PIN ASSIGNMENT FEATURES Access times : 12, 15 and 20ns High-density 512KByte design High-reliability, high-speed design Single + 5V ±0.5V power supply Easy memory expansion with /CE and /OE functions All inputs and outputs are TTL-compatible Industry-standard pinout FR4-PCB design OPTIONS MARKING Timing 8ns access - 8 10ns access -10 Vss 1 /CE4 33 PD0 2 /CE3 34 PD1 3 NC 35 DQ0 4 A16 36 DQ8 5 /OE 37 DQ1 6 Vss 38 DQ9 7 DQ24 39 DQ2 8 DQ16 40 DQ10 9 DQ25 41 DQ3 10 DQ11 11 DQ17 42 Vcc 12 A0 13 DQ18 44 A7 14 A1 15 DQ19 46 A8 16 A2 17 A10 48 A9 18 DQ12 19 A11 50 DQ4 20 DQ13 21 A12 52 DQ5 22 DQ14 23 A13 54 DQ6 24 DQ15 25 DQ20 56 DQ26 43 DQ27 45 A3 47 A4 49 A5 51 Vcc 53 A6 55 12ns access -12 15ns access -15 DQ7 26 Vss 27 DQ21 58 20ns access -20 /WE 28 A15 29 DQ22 60 A14 30 /CE2 31 DQ23 62 Packages 64-pin SIMM M DQ28 57 DQ29 59 DQ30 61 DQ31 63 /CE1 32 Vss 64 SIMM TOP VIEW 1 PD0 = Open PD1 = Open HANBit Electronics Co.,Ltd. HANBit HMS12832M4 FUNCTIONAL BLOCK DIAGRAM 32 DQ0 - DQ31 A0 - A16 17 A0-16 DQ 0-7 /WE U1 /OE /CE /CE1 A0-16 DQ 8-15 /WE U2 /OE /CE /CE2 A0-16 DQ16-23 /WE U3 /OE /CE /CE3 A0-16 DQ24-31 /WE /WE /OE /OE U4 /CE PRESENCE-DETECT /CE4 PD0 = Open PD1 = Open TRUTH TABLE MODE /OE /CE /WE DQ POWER STANDBY X H X HIGH-Z STANDBY NOT SELECTED H L H HIGH-Z ACTIVE READ L L H Dout ACTIVE WRITE X L L Din ACTIVE 2 HANBit Electronics Co.,Ltd. HANBit HMS12832M4 ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING VIN,OUT -0.5V to Vcc+0.5V Voltage on Vcc Supply Relative to Vss VCC -0.5V to +7.0V Power Dissipation PD 4.0W TSTG -65oC to +150oC Voltage on Any Pin Relative to Vss Storage Temperature Operating Temperature TA 0oC to +70oC Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER * ( TA=0 to 70 o C ) SYMBOL MIN TYP. MAX Supply Voltage VCC 4.5V 5.0V 5.5V Ground VSS 0 0 0 Input High Voltage VIH 2.2 - Vcc+0.5V** Input Low Voltage VIL -0.5* - 0.8V VIL(Min.) = -2.0V ac (Pulse Width ≤ 10ns) for I ≤ 20 mA ** VIH(Min.) = Vcc+2.0V ac (Pulse Width ≤ 10ns) for I ≤ 20 mA DC AND OPERATING CHARACTERISTICS (1)(0oC ≤ TA ≤ 70 oC ; Vcc = 5V ± 10% ) PARAMETER Input Leakage Current Output Leakage Current TEST CONDITIONS VIN=Vss to Vcc /CE=VIH or /OE =VIH or /WE=VIL VOUT=Vss to VCC SYMBO L MIN MAX UNITS ILI -2 2 µA IL0 -2 2 µA 2.4 Output High Voltage IOH = -4.0mA VOH Output Low Voltage IOL = 8.0mA VOL V 0.4 V * Vcc=5.0V, Temp=25 oC 3 HANBit Electronics Co.,Ltd. HANBit HMS12832M4 DC AND OPERATING CHARACTERISTICS (2) MAX DESCRIPTION TEST CONDITIONS Min. Cycle, 100% Duty /CE=VIL, VIN=VIH or VIL, IOUT=0mA Power Supply Current:Operating Power Supply Current:Standby CAPACITANCE SYMBOL -12 -15 -20 UNIT ICC 75 73 70 mA Min. Cycle, /CE=VIH ISB 30 30 30 mA f=0MHZ, /CE≥VCC-0.2V, VIN≥ VCC-0.2V or VIN≤0.2V ISB1 5 5 5 mA (TA =25 oC , f= 1.0Mhz) DESCRIPTION TEST CONDITIONS SYMBOL MAX UNIT Input /Output Capacitance VI/O=0V CI/O 8 pF Input Capacitance VIN=0V CIN 8 pF * NOTE : Capacitance is sampled and not 100% tested AC CHARACTERISTICS (0oC ≤ TA ≤ 70 oC ; Vcc = 5V ± 0.5V, unless otherwise specified) Test conditions PARAMETER VALUE Input Pulse Level 0V to 3V Input Rise and Fall Time 3ns Input and Output Timing Reference Levels 1.5V Output Load See below Output Load Output Load (B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5V +5V 480Ω 480Ω DOUT 255Ω DOUT 30pF* 255Ω 5pF* READ CYCLE -12 PARAMETER -15 -20 SYMBOL UNIT MIN Read Cycle Time tRC Address Access Time tAA MAX 12 MAX 15 12 4 MIN MIN MAX 20 15 ns 20 HANBit Electronics Co.,Ltd. ns HANBit HMS12832M4 Chip Select to Output tCO 12 15 20 ns Output Enable to Output tOE 6 7 9 ns Output Enable to Low-Z Output tOLZ 0 0 0 ns Chip Enable to Low-Z Output tLZ 3 3 3 ns Output Disable to High-Z Output tOHZ 0 6 0 7 0 9 ns Chip Disable to High-Z Output tHZ 0 6 0 7 0 9 ns Output Hold from Address Change tOH 3 3 3 ns Chip Select to Power Up Time tPU 0 0 0 ns Chip Select to Power Down Time tPD - 12 15 20 ns WRITE CYCLE -12 PARAMETER -15 -20 SYMBOL UNIT MIN MAX MIN MAX MIN MAX Write Cycle Time tWC 12 15 20 ns Chip Select to End of Write tCW 8 10 12 ns Address Set-up Time tAS 0 0 0 ns Address Valid to End of Write tAW 8 9 10 ns Write Pulse Width tWP 8 9 10 ns Write Recovery Time tWR 0 0 0 ns Write to Output High-Z tWHZ 0 Data to Write Time Overlap tDW 6 7 8 ns Data Hold from Write Time tDH 0 0 0 ns End of Write to Output Low-Z tOW 3 3 3 ns 6 0 7 0 9 TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(Address Controlled) ( /CE =/ OE = VIL , /WE = VIH) tRC Address tAA tOH Data out Previous Data Valid Data Valid 5 HANBit Electronics Co.,Ltd. ns HANBit HMS12832M4 TIMING WAVEFORM OF READ CYCLE ( /CE Controlled ) tRC Address tHZ(3,4,5) tAA tCO /CE tLZ(4,5) tOHZ tOE /OE tOH tOLZ Data Out Vcc Supply Current High-Z Data Valid tPD tPU lCC 50% 50% lSB Notes (Read Cycle) 1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device to device. 5. Transition is measured ± 200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CE = VIL. 7. Address valid prior to coincident with /CE transition low. TIMING WAVEFORM OF WRITE CYCLE (/OE=Clock ) tWC Address tAW tWR(5) /OE tCW(3) /CE tAS(4) tWP(2) /WE tDW Data In tDH High-Z Data Valid tOHZ(6) tOW Data Out High-Z 6 HANBit Electronics Co.,Ltd. HANBit HMS12832M4 TIMING WAVEFORM OF WRITE CYCLE ( /OE Low Fixed ) tWC Address tAW tWR(5) tCW(3) /CE tAS(4) tOH /WE tWP(2) tDW tDH High-Z Data In Data Valid tWHZ(6,7) tOW (10) (9) High-Z(8) Data Out Notes(Write Cycle) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among /CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CE going low to the end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high. 6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10. When /CE is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION /CE /WE /OE MODE I/O PIN SUPPLY CURRENT H X* X Not Select High-Z l SB, l SB1 L H H Output Disable High-Z lCC L H L Read DOUT lCC L L X Write DIN lCC Note: X means Don't Care 7 HANBit Electronics Co.,Ltd. HANBit HMS12832M4 PACKAGING INFORMATION 98.04 mm 10.16 mm 6.35 mm 16 mm 1 64 2.03 mm 1.02 mm 6.35 mm 6.35 mm 1.27 mm 3.34 mm 85.09 mm 2.54 mm 0.25 mm MAX MIN Gold : 1.04±0.10 mm 1.27 1.29±0.08 mm Solder : 0.914±0.10 mm (Solder & Gold Plating Lead) 8 HANBit Electronics Co.,Ltd. HANBit HMS12832M4 ORDERING INFORMATION 1 2 3 4 5 6 7 8 H M S 128 32 M 4 -15 15ns Access Time HANBit Component Memory Modules SIMM x32bit SRAM 128K 1. - Product Line Identifier HANBit ------------------------------------------------------ H 2. - Memory Modules 3. - SRAM 4. - Depth : 128K 5. - Width : x 32bit 6. - Package Code SIMM ------------------------------------------------------- M 7. - Number of Memory Components 8. - Access time 10 ----------------------------------------------------------- 10ns 12 ----------------------------------------------------------- 12ns 15 ----------------------------------------------------------- 15ns 17 ----------------------------------------------------------- 17ns 20 ----------------------------------------------------------- 20ns 9 HANBit Electronics Co.,Ltd.