Intersil ICM7555CBA General purpose timer Datasheet

ICM7555, ICM7556
®
Data Sheet
August 24, 2006
FN2867.9
General Purpose Timers
Features
The ICM7555 and ICM7556 are CMOS RC timers providing
significantly improved performance over the standard
SE/NE 555/6 and 355 timers, while at the same time being
direct replacements for those devices in most applications.
Improved parameters include low supply current, wide
operating supply voltage range, low THRESHOLD,
TRIGGER and RESET currents, no crowbarring of the
supply current during output transitions, higher frequency
performance and no requirement to decouple CONTROL
VOLTAGE for stable operation.
• Exact Equivalent in Most Cases for SE/NE555/556 or
TLC555/556
Specifically, the ICM7555 and ICM7556 are stable
controllers capable of producing accurate time delays or
frequencies. The ICM7556 is a dual ICM7555, with the two
timers operating independently of each other, sharing only
V+ and GND. In the one shot mode, the pulse width of each
circuit is precisely controlled by one external resistor and
capacitor. For astable operation as an oscillator, the free
running frequency and the duty cycle are both accurately
controlled by two external resistors and one capacitor. Unlike
the regular bipolar SE/NE 555/6 devices, the CONTROL
VOLTAGE terminal need not be decoupled with a capacitor.
The circuits are triggered and reset on falling (negative)
waveforms, and the output inverter can source or sink
currents large enough to drive TTL loads, or provide minimal
offsets to drive CMOS loads.
• Low Supply Current
- ICM7555 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60μA
- ICM7556 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120μA
• Extremely Low Input Currents . . . . . . . . . . . . . . . . . 20pA
• High Speed Operation . . . . . . . . . . . . . . . . . . . . . . . 1MHz
• Guaranteed Supply Voltage Range . . . . . . . . . 2V to 18V
• Temperature Stability . . . . . . . . . . . . 0.005%/°C at +25°C
• Normal Reset Function - No Crowbarring of Supply During
Output Transition
• Can be Used with Higher Impedance Timing Elements
than Regular 555/6 for Longer RC Time Constants
• Timing from Microseconds through Hours
• Operates in Both Astable and Monostable Modes
• Adjustable Duty Cycle
• High Output Source/Sink Driver can Drive TTL/CMOS
• Outputs have Very Low Offsets, HI and LO
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Precision Timing
• Pulse Generation
• Sequential Timing
• Time Delay Generation
• Pulse Width Modulation
• Pulse Position Modulation
• Missing Pulse Detector
Pinouts
ICM7555 (8 LD PDIP, SOIC)
TOP VIEW
ICM7556 (14 LD PDIP, CERDIP)
TOP VIEW
DISCHARGE 1
GND 1
8 VDD
TRIGGER 2
7 DISCHARGE
OUTPUT 3
6 THRESHOLD
5 CONTROL
VOLTAGE
RESET 4
THRESH- 2
OLD
CONTROL 3
VOLTAGE
RESET 4
OUTPUT 5
TRIGGER 6
GND 7
1
14 VDD
13 DISCHARGE
12 THRESHOLD
11
CONTROL
VOLTAGE
10 RESET
9 OUTPUT
8 TRIGGER
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002, 2004, 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ICM7555, ICM7556
Ordering Information
PART NUMBER
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
ICM7555CBA
7555 CBA
0 to +70
8 Ld SOIC
M8.15
ICM7555CBA-T
7555 CBA
0 to +70
8 Ld SOIC Tape and Reel
M8.15
ICM7555CBAZ (Note)
7555 CBAZ
0 to +70
8 Ld SOIC (Pb-free)
M8.15
ICM7555CBAZ-T (Note)
7555 CBAZ
0 to +70
8 Ld SOIC (Pb-free)
Tape and Reel
M8.15
ICM7555IBA
7555 IBA
-25 to +85
8 Ld SOIC
M8.15
ICM7555IBAT
7555 IBA
-25 to +85
8 Ld SOIC Tape and Reel
M8.15
ICM7555IBAZ (Note)
7555 IBAZ
-25 to +85
8 Ld SOIC (Pb-free)
M8.15
ICM7555IBAZ-T (Note)
7555 IBAZ
-25 to +85
8 Ld SOIC (Pb-free)
Tape and Reel
M8.15
ICM7555IPA
7555 IPA
-25 to +85
8 Ld PDIP
E8.3
ICM7555IPAZ (Note)
7555 IPAZ
-25 to +85
8 Ld PDIP** (Pb-free)
E8.3
ICM7556IPD
ICM7556IPD
-25 to +85
14 Ld PDIP
E14.3
ICM7556IPDZ (Note)
ICM7556IPDZ
-25 to +85
14 Ld PDIP** (Pb-free)
E14.3
ICM7556MJD
ICM7556MJD
-55 to +125
14 Ld Cerdip
F14.3
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN2867.9
August 24, 2006
ICM7555, ICM7556
Absolute Maximum Ratings
Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V
Input Voltage
Trigger, Control Voltage, Threshold,
Reset (Note 1) . . . . . . . . . . . . . . . . . . . . . V+ +0.3V to GND -0.3V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical, Note 2)
θJA (°C/W) θJC (°C/W)
14 Lead CERDIP Package. . . . . . . . . .
80
24
14 Lead PDIP Package* . . . . . . . . . . .
115
N/A
8 Lead PDIP Package* . . . . . . . . . . . .
130
N/A
8 Lead SOIC Package . . . . . . . . . . . . .
170
N/A
Maximum Junction Temperature (Hermetic Package) . . . . . . . +175°C
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
* Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Temperature Range
ICM7555C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ICM7555I, ICM7556I . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C
ICM7556M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than
V+ +0.3V or less than V- -0.3V may cause destructive latchup. For this reason it is recommended that no inputs from external sources not
operating from the same power supply be applied to the device before its power supply is established. In multiple supply systems, the supply
of the ICM7555 and ICM7556 must be turned on first.
2. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details.
Electrical Specifications
Applies to ICM7555 and ICM7556, unless otherwise specified
(NOTE 4)
-55°C TO +125°C
TA = +25°C
PARAMETER
SYMBOL
Static Supply Current
IDD
ICM7555
ICM7556
Monostable Timing Accuracy
TYP
MAX
MAX
UNITS
VDD = 5V
40
200
300
μA
VDD = 15V
60
300
300
μA
VDD = 5V
80
400
600
μA
VDD = 15V
120
600
600
μA
TEST CONDITIONS
MIN
RA = 10K, C = 0.1μF, VDD = 5V
MIN
TYP
2
%
858
Drift with Temperature
(Note 3)
Drift with Supply (Note 3)
150
ppm/°C
VDD = 10V
200
ppm/°C
VDD = 15V
250
ppm/°C
0.5
%/V
0.5
RA = RB = 10K, C = 0.1μF, VDD = 5V
2
%
1717
Drift with Temperature
(Note 3)
Drift with Supply (Note 3)
2323
μs
VDD = 5V
150
ppm/°C
VDD = 10V
200
ppm/°C
VDD = 15V
250
ppm/°C
0.5
%/V
VDD = 5V to 15V
Threshold Voltage
μs
VDD = 5V
VDD = 5V to 15V
Astable Timing Accuracy
1161
0.5
VTH
VDD = 15V
62
67
71
61
72
% VDD
Trigger Voltage
VTRIG
VDD = 15V
28
32
36
27
37
% VDD
Trigger Current
ITRIG
VDD = 15V
10
50
nA
Threshold Current
ITH
VDD = 15V
10
50
nA
Control Voltage
VCV
VDD = 15V
72
% VDD
3
62
67
71
61
FN2867.9
August 24, 2006
ICM7555, ICM7556
Electrical Specifications
Applies to ICM7555 and ICM7556, unless otherwise specified (Continued)
(NOTE 4)
-55°C TO +125°C
TA = +25°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
1.0
0.2
MAX
UNITS
1.2
V
Reset Voltage
VRST
VDD = 2V to 15V
Reset Current
IRST
VDD = 15V
10
50
nA
Discharge Leakage
IDIS
VDD = 15V
10
50
nA
Output Voltage
VOL
VDD = 15V, ISINK = 20mA
0.4
1.0
1.25
V
VDD = 5V, ISINK = 3.2mA
0.2
0.4
0.5
V
VOH
Discharge Output Voltage
VDIS
0.4
TYP
VDD = 15V, ISOURCE = 0.8mA
14.3
14.6
14.2
V
VDD = 5V, ISOURCE = 0.8mA
4.0
4.3
3.8
V
VDD = 5V, ISINK = 15mA
0.2
0.4
VDD = 15V, ISINK = 15mA
Supply Voltage (Note 3)
Functional Operation
VDD
2.0
18.0
3.0
0.6
V
0.4
V
16.0
V
Output Rise Time (Note 3)
tR
RL = 10M, CL = 10pF, VDD = 5V
75
ns
Output Fall Time (Note 3)
tF
RL = 10M, CL = 10pF, VDD = 5V
75
ns
VDD = 5V, RA = 470Ω, RB = 270Ω,
C = 200pF
1
MHz
Oscillator Frequency
(Note 3)
fMAX
NOTES:
3. These parameters are based upon characterization data and are not tested.
4. Applies only to military temperature range product (M suffix).
Functional Diagram
VDD
8
R
THRESHOLD
6
5
CONTROL
VOLTAGE
4
FLIP-FLOP
RESET
OUTPUT
DRIVERS
COMPARATOR
A
+
OUTPUT
-
3
7
R
DISCHARGE
n
+
TRIGGER
2
1
COMPARATOR
B
1
GND
R
NOTE:
This functional diagram reduces the circuitry down to its simplest equivalent components. Tie down unused inputs.
TRUTH TABLE
THRESHOLD VOLTAGE
TRIGGER VOLTAGE
RESET
OUTPUT
DISCHARGE SWITCH
Don’t Care
Don’t Care
Low
Low
On
>2/3(V+)
>1/3(V+)
High
Low
On
<2/3(V+)
>1/3(V+)
High
Stable
Stable
Don’t Care
<1/3(V+)
High
High
Off
NOTE: RESET will dominate all other inputs: TRIGGER will dominate over THRESHOLD.
4
FN2867.9
August 24, 2006
ICM7555, ICM7556
Schematic Diagram
VDD
P
P
P
P
R
THRESHOLD
N
N
NPN
CONTROL
VOLTAGE
R
OUTPUT
P
P
TRIGGER
R
N
N
N
N
N
N
RESET
N
GND
DISCHARGE
R = 100kΩ ±20% (TYP)
Application Information
General
The ICM7555 and ICM7556 devices are, in most instances,
direct replacements for the NE/SE 555/6 devices. However,
it is possible to effect economies in the external component
count using the ICM7555 and ICM7556. Because the bipolar
NE/SE 555/6 devices produce large crowbar currents in the
output driver, it is necessary to decouple the power supply
lines with a good capacitor close to the device. The ICM7555
and ICM7556 devices produce no such transients. See
Figure 1.
500
POWER SUPPLY CONSIDERATIONS
Although the supply current consumed by the ICM7555 and
ICM7556 devices is very low, the total system supply current
can be high unless the timing components are high
impedance. Therefore, use high values for R and low values
for C in Figures 2A, 2B, and 3.
400
300
GND
SE/NE555
TRIGGER
200
100
VDD
1
8
2
7
3
6
4
5
VDD
DISCHARGE
THRESHOLD
CONTROL
VOLTAGE
RESET
0
R
ICM7555/56
0
200
400
TIME (ns)
600
10K
C
ALTERNATE OUTPUT
VDD
OUTPUT
SUPPLY CURRENT (mA)
TA = 25°C
The ICM7555 and ICM7556 produce supply current spikes
of only 2mA - 3mA instead of 300mA - 400mA and supply
decoupling is normally not necessary. Also, in most
instances, the CONTROL VOLTAGE decoupling capacitors
are not required since the input impedance of the CMOS
comparators on chip are very high. Thus, for many
applications, two capacitors can be saved using an ICM7555
and three capacitors with an ICM7556.
OPTIONAL
CAPACITOR
800
FIGURE 2A. ASTABLE OPERATION
FIGURE 1. SUPPLY CURRENT TRANSIENT COMPARED WITH
A STANDARD BIPOLAR 555 DURING AN OUTPUT
TRANSITION
5
FN2867.9
August 24, 2006
ICM7555, ICM7556
VDD
1
tOUTPUT = -ln
RA
(1/3) RAC = 1.1RAC
8
2
7
OUTPUT
3
6
VDD
4
5
RB
1
8
TRIGGER
2
7
OUTPUT
3
RESET
4
6
5
RA
DISCHARGE
THRESHOLD
CONTROL
VOLTAGE
OPTIONAL
CAPACITOR
OPTIONAL
CAPACITOR
C
ICM7555
VDD
C
VDD ≤18V
FIGURE 2B. ALTERNATE ASTABLE CONFIGURATION
FIGURE 3. MONOSTABLE OPERATION
CONTROL VOLTAGE
OUTPUT DRIVE CAPABILITY
The output driver consists of a CMOS inverter capable of
driving most logic families including CMOS and TTL. As
such, if driving CMOS, the output swing at all supply
voltages will equal the supply voltage. At a supply voltage of
4.5V or more, the ICM7555 and ICM7556 will drive at least
two standard TTL loads.
ASTABLE OPERATION
The circuit can be connected to trigger itself and free run as
a multivibrator, see Figure 2A. The output swings from rail to
rail, and is a true 50% duty cycle square wave. (Trip points
and output swings are symmetrical.) Less than a 1%
frequency variation is observed over a voltage range of +5V
to +15V.
1
f = -----------------1.4 RC
(EQ. 1)
The timer can also be connected as shown in Figure 2B. In this
circuit, the frequency is:
f = 1.44 ⁄ ( R A + 2R B ) C
(EQ. 2)
The CONTROL VOLTAGE terminal permits the two trip
voltages for the THRESHOLD and TRIGGER internal
comparators to be controlled. This provides the possibility of
oscillation frequency modulation in the astable mode or even
inhibition of oscillation, depending on the applied voltage. In
the monostable mode, delay times can be changed by
varying the applied voltage to the CONTROL VOLTAGE pin.
RESET
The RESET terminal is designed to have essentially the
same trip voltage as the standard bipolar 555/6, i.e., 0.6V to
0.7V. At all supply voltages it represents an extremely high
input impedance. The mode of operation of the RESET
function is, however, much improved over the standard
bipolar NE/SE 555/6 in that it controls only the internal flipflop, which in turn controls simultaneously the state of the
OUTPUT and DISCHARGE pins. This avoids the multiple
threshold problems sometimes encountered with slow falling
edges in the bipolar devices.
The duty cycle is controlled by the values of RA and RB, by the
equation:
D = ( RA + R B ) ⁄ ( R A + 2R B )
(EQ. 3)
MONOSTABLE OPERATION
In this mode of operation, the timer functions as a one-shot.
See Figure 3. Initially the external capacitor (C) is held
discharged by a transistor inside the timer. Upon application of
a negative TRIGGER pulse to pin 2, the internal flip-flop is set
which releases the short circuit across the external capacitor
and drives the OUTPUT high. The voltage across the capacitor
now increases exponentially with a time constant t = RAC.
When the voltage across the capacitor equals 2/3 V+, the
comparator resets the flip-flop, which in turn discharges the
capacitor rapidly and also drives the OUTPUT to its low state.
TRIGGER must return to a high state before the OUTPUT can
return to a low state.
6
FN2867.9
August 24, 2006
ICM7555, ICM7556
1200
MINIMUM PULSE WIDTH (ns)
SUPPLY CURRENT (ICM7555) (μA)
TA = 25°C
1100
1000
900
800
700
600
500
VDD = 2V
400
300
200
VDD = 5V
100
VDD = 18V
0
200
400
180
360
160
320
140
280
TA = -20°C
120
100
160
60
TA = 70°C
10
20
30
80
20
40
0
0
40
2
4
8
10
12
14
16
18
20
FIGURE 5. SUPPLY CURRENT vs SUPPLY VOLTAGE
100
-0.1
TA = 25°C
TA = -20°C
OUTPUT SINK CURRENT (mA)
OUTPUT SOURCE CURRENT (mA)
6
SUPPLY VOLTAGE (V)
FIGURE 4. MINIMUM PULSE WIDTH REQUIRED FOR
TRIGGERING
VDD = 2V
-1.0
VDD = 5V
-10.0
VDD = 18V
-1.0
-0.1
OUTPUT VOLTAGE REFERENCED TO VDD (V)
10.0
VDD = 18V
VDD = 5V
VDD = 2V
1.0
0.1
0.01
-0.01
0.1
1.0
10.0
OUTPUT LOW VOLTAGE (V)
FIGURE 6. OUTPUT SOURCE CURRENT vs OUTPUT VOLTAGE
FIGURE 7. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE
100
100
TA = 70°C
OUTPUT SINK CURRENT (mA)
TA = 25°C
OUTPUT SINK CURRENT (mA)
120
40
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE (%VDD)
VDD = 18V
VDD = 5V
10.0
VDD = 2V
1.0
0.1
0.01
200
TA = 25°C
80
0
0
-100
-10
240
SUPPLY CURRENT (ICM7556) (μA)
Typical Performance Curves
0.1
1.0
OUTPUT LOW VOLTAGE (V)
10.0
FIGURE 8. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE
7
VDD = 18V
10.0
VDD = 5V
VDD = 2V
1.0
0.1
0.01
0.1
1.0
10.0
OUTPUT LOW VOLTAGE (V)
FIGURE 9. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE
FN2867.9
August 24, 2006
ICM7555, ICM7556
(Continued)
8
100
TA = 25°C
6
DISCHARGE SINK CURRENT (mA)
NORMALIZED FREQUENCY DEVIATION (%)
Typical Performance Curves
4
2
RA = RB = 10MΩ
C = 100pF
0
2
RA = RB = 10kΩ
C = 0.1μF
4
6
8
0.1
1.0
10.0
SUPPLY VOLTAGE (V)
NORMALIZED FREQUENCY DEVIATION (%)
PROPAGATION DELAY (ns)
VDD = 5V
500
400
300
TA = 70°C
TA = 25°C
TA = -20°C
100
0
0
10
20
10.0
VDD = 2V
1.0
0.1
1.0
DISCHARGE LOW VOLTAGE (V)
30
40
+1.0
RA = RB = 10kΩ
C = 0.1μF
+0.9
+0.8
+0.7
+0.6
VDD = 5V
+0.5
+0.4
VDD = 18V
+0.3
+0.2
VDD = 2V
+0.1
VDD = 2V
0
-0.1
-20
20
0
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE (%VDD)
FIGURE 12. PROPAGATION DELAY vs VOLTAGE LEVEL OF
TRIGGER PULSE
80
1.0
TA = 25°C
100m
TA = 25°C
RA
10m
1kΩ
10kΩ
100kΩ
1MΩ
10MΩ
100MΩ
(RA + 2RB)
1m
100μ
10μ
1μ
100n
CAPACITANCE (F)
CAPACITANCE (F)
60
TEMPERATURE (°C)
10m
10n
1m
100μ
10μ
1μ
100n
1kΩ
10kΩ
100kΩ
1MΩ
10MΩ
100MΩ
10n
1n
1n
100p
100p
10p
1p
0.1
40
FIGURE 13. NORMALIZED FREQUENCY STABILITY IN THE
ASTABLE MODE vs TEMPERATURE
1.0
100m
10.0
FIGURE 11. DISCHARGE OUTPUT CURRENT vs DISCHARGE
OUTPUT VOLTAGE
600
200
VDD = 5V
VDD = 18V
0.1
0.01
100.0
FIGURE 10. NORMALIZED FREQUENCY STABILITY IN THE
ASTABLE MODE vs SUPPLY VOLTAGE
TA = 25°C
10p
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 14. FREE RUNNING FREQUENCY vs RA, RB AND C
8
1p
100n
1μ
10μ
100μ
1m
10m 100m
1
10
TIME DELAY (s)
FIGURE 15. TIME DELAY IN THE MONOSTABLE MODE vs
RA AND C
FN2867.9
August 24, 2006
ICM7555, ICM7556
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
-
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
α
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
H
N
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
9
FN2867.9
August 24, 2006
ICM7555, ICM7556
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
e
0.100 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
eB
-
L
0.115
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
N
8
0.355
10.16
5
2.54 BSC
-
7.62 BSC
6
0.430
-
0.150
2.93
10.92
3.81
8
7
4
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
10
FN2867.9
August 24, 2006
ICM7555, ICM7556
Dual-In-Line Plastic Packages (PDIP)
N
E14.3 (JEDEC MS-001-AA ISSUE D)
E1
INDEX
AREA
1 2 3
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N/2
INCHES
-B-
SYMBOL
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
eA
A1
eC
B
0.010 (0.25) M
C
L
C A B S
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
MILLIMETERS
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.15
1.77
8
C
0.008
0.014
0.204
0.355
-
D
0.735
0.775
18.66
D1
0.005
-
0.13
19.68
-
5
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
6
eB
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
14
14
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
11
FN2867.9
August 24, 2006
ICM7555, ICM7556
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.785
-
19.94
5
E
0.220
0.310
5.59
7.87
5
eA
e
ccc M
C A-B S
eA/2
c
aaa M C A - B S D S
D S
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105°
90°
105°
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90°
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
14
14
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN2867.9
August 24, 2006