PD - 94506A
IRFR3505
IRFU3505
AUTOMOTIVE MOSFET
HEXFET® Power MOSFET
Features
●
●
●
●
●
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
D
VDSS = 55V
RDS(on) = 0.013Ω
G
ID = 30A
S
Description
Specifically designed for Automotive applications, this HEXFET® Power
MOSFET utilizes the latest processing techniques to achieve extremely
low on-resistance per silicon area. Additional features of this product are
a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this
design an extremely efficient and reliable device for use in Automotive
applications and a wide variety of other applications.
The D-Pak is designed for surface mounting using vapor phase, infrared,
or wave soldering techniques. The straight lead version (IRFU series) is
for through-hole mounting applications. Power dissipation levels up to
1.5 watts are possible in typical surface mount applications.
D-Pak
IRFR3505
I-Pak
IRFU3505
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
VGS
EAS
EAS (tested)
IAR
EAR
dv/dt
TJ
TSTG
Max.
Continuous Drain Current, VGS @ 10V (Silicon limited)
Continuous Drain Current, VGS @ 10V (See Fig.9)
Continuous Drain Current, VGS @ 10V (Package limited)
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Units
71
49
30
280
140
0.92
± 20
210
410
See Fig.12a, 12b, 15, 16
4.0
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
Junction-to-Case
Junction-to-Ambient (PCB mount)
Junction-to-Ambient
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Typ.
Max.
Units
–––
–––
–––
1.09
40
110
°C/W
1
12/11/02
IRFR/U3505
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
55
–––
–––
2.0
41
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.057
0.011
–––
–––
–––
–––
–––
–––
62
17
22
13
74
43
54
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
4.5
LS
Internal Source Inductance
–––
7.5
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
2030
470
91
2600
330
630
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
0.013 Ω
VGS = 10V, ID = 30A
4.0
V
VDS = 10V, ID = 250µA
–––
S
VDS = 25V, ID = 30A
20
VDS = 55V, VGS = 0V
µA
250
VDS = 55V, VGS = 0V, TJ = 125°C
200
VGS = 20V
nA
-200
VGS = -20V
93
ID = 30A
26
nC
VDS = 44V
33
VGS = 10V
–––
VDD = 28V
–––
ID = 30A
ns
–––
RG = 6.8Ω
–––
VGS = 10V
D
Between lead,
–––
6mm (0.25in.)
nH
G
from package
–––
and center of die contact
S
–––
VGS = 0V
–––
pF
VDS = 25V
–––
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 44V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 44V
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
2
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
71
––– –––
showing the
A
G
integral reverse
––– ––– 280
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 30A, VGS = 0V
––– 70 105
ns
TJ = 25°C, IF = 30A, VDD = 28V
––– 180 270
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRFR/U3505
1000
1000
VGS
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
100
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
10
4.5V
20µs PULSE WIDTH
Tj = 25°C
1
0.1
1
10
100
4.5V
10
20µs PULSE WIDTH
Tj = 175°C
1
0.1
100
1
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100
Fig 2. Typical Output Characteristics
70
G fs , Forward Transconductance (S)
1000
ID, Drain-to-Source Current (Α)
10
VDS, Drain-to-Source Voltage (V)
T J = 25°C
T J = 175°C
100
10
VDS = 25V
T J = 25°C
60
50
40
T J = 175°C
30
20
10
VDS = 25V
20µs PULSE WIDTH
20µs PULSE WIDTH
1
0
4.0
5.0
6.0
7.0
8.0
9.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10.0
0
10
20
30
40
50
60
70
80
90
ID,Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
Vs. Drain Current
3
IRFR/U3505
4000
ID= 30A
VGS , Gate-to-Source Voltage (V)
Coss
3000
C, Capacitance (pF)
20
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
= Cds + Cgd
Ciss
2000
Coss
1000
12
8
4
Crss
0
0
1
VDS= 44V
VDS= 28V
VDS= 11V
16
10
0
100
20
40
60
80
100
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000.0
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100.0
100
T J = 175°C
10.0
T J = 25°C
1.0
100µsec
10
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
0.0
0.5
1.0
1.5
2.0
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10msec
1
2.5
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFR/U3505
80
2.5
60
40
20
0
25
50
75
100
125
150
175
ID = 30A
VGS = 10V
2.0
(Normalized)
RDS(on) , Drain-to-Source On Resistance
ID , Drain Current (A)
LIMITED BY PACKAGE
1.5
1.0
0.5
-60 -40 -20
T C , Case Temperature (°C)
0
20
40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Normalized On-Resistance
Vs. Temperature
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR/U3505
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
VGS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS, Single Pulse Avalanche Energy (mJ)
400
15V
ID
12A
21A
BOTTOM 30A
TOP
300
200
100
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGD
4.0
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
VGS(th) Gate threshold Voltage (V)
QGS
3.6
3.2
ID = 250µA
2.8
2.4
2.0
1.6
-75 -50 -25
VGS
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage Vs. Temperature
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IRFR/U3505
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
0.05
10
0.10
1
0.1
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
EAR , Avalanche Energy (mJ)
240
T OP
Single Pulse
BOTT OM 10% Duty Cycle
ID = 30A
200
160
120
80
40
0
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P D (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I av = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRFR/U3505
D.U.T
Driver Gate Drive
+
-
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
*
RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
Period
P.W.
+
VDD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
VDS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRFR/U3505
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
-A1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018)
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
1.02 (.040)
1.64 (.025)
10.42 (.410)
9.40 (.370)
1
2
1 - GATE
0.51 (.020)
MIN.
-B1.52 (.060)
1.15 (.045)
3X
2X
1.14 (.045)
0.76 (.030)
LEAD ASSIGNMENTS
3
0.89 (.035)
0.64 (.025)
0.25 (.010)
2 - DRAIN
3 - SOURCE
4 - DRAIN
0.58 (.023)
0.46 (.018)
M A M B
NOTES:
2.28 (.090)
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
4.57 (.180)
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
D-Pak (TO-252AA) Part Marking Information
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9
IRFR/U3505
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
-A1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
0.58 (.023)
0.46 (.018)
LEAD ASSIGNMENTS
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
1.52 (.060)
1.15 (.045)
1
2
2.28 (.090)
1.91 (.075)
1.14 (.045)
0.76 (.030)
2.28 (.090)
2X
3 - SOURCE
4 - DRAIN
3
-B-
3X
1 - GATE
2 - DRAIN
3X
9.65 (.380)
8.89 (.350)
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
0.89 (.035)
0.64 (.025)
1.14 (.045)
0.89 (.035)
0.25 (.010)
M A M B
0.58 (.023)
0.46 (.018)
I-Pak (TO-251AA) Part Marking Information
10
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IRFR/U3505
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating; pulse width limited by
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.47mH Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
R G = 25Ω, IAS = 30A, VGS =10V. Part not
avalanche performance.
recommended for use above this value.
This value determined from sample failure population. 100%
ISD ≤ 30A, di/dt ≤ 300A/µs, VDD ≤ V(BR)DSS,
tested to this value in production.
TJ ≤ 175°C
When mounted on 1" square PCB (FR-4 or G-10 Material) .
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
For recommended footprint and soldering techniques refer to
application note #AN-994
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11