DAC712 DA C7 12 DA C7 1 2 www.ti.com ................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 16-BIT DIGITAL-TO-ANALOG CONVERTER with 16-Bit Bus Interface FEATURES DESCRIPTION 1 • HIGH-SPEED, 16-BIT PARALLEL DOUBLE-BUFFERED INTERFACE • VOLTAGE OUTPUT: ±10V • 13-, 14-, AND 15-BIT LINEARITY GRADES • 16-BIT MONOTONIC OVER TEMPERATURE (L GRADE) • POWER DISSIPATION: 600mW max • GAIN AND OFFSET ADJUST: Convenient for Auto-Cal D/A Converters • 28-LEAD DIP AND SOIC PACKAGES The DAC712 is a complete 16-bit resolution digital-to-analog (D/A) converter with 16 bits of monotonicity over temperature. 2 The DAC712 has a precision +10V temperature-compensated voltage reference, ±10V output amplifier, and 16-bit port bus interface. The digital interface is fast, 60ns minimum write pulse width, double-buffered, and has a CLEAR function that resets the analog output to bipolar zero. GAIN and OFFSET adjustment inputs are arranged so that they can be easily trimmed by external D/A converters as well as by potentiometers. The DAC712 is available in two linearity error performance grades: ±4LSB and ±2LSB, and three differential linearity grades: ±4LSB, ±2LSB, and ±1LSB. The DAC712 is specified at power-supply voltages of ±12V and ±15V. The DAC712 is packaged in a 28-pin, 0.3" wide plastic DIP and in a 28-lead, wide-body plastic SOIC. The DAC712P, U, PB, and UB are specified over the –40°C to +85°C temperature range and the DAC712PK, UK, PL, and UL are specified over the 0°C to +70°C range. DB0 DB15 A1 Input Latch A0 16 WR CLR D/A Latch 16 Reference Circuit Gain Adjust 16-Bit D/A Converter VOUT VREF OUT +10V Bipolar Offset Adjust 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2009, Texas Instruments Incorporated DAC712 SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT LINEARITY ERROR MAX AT +25°C DIFFERENTIAL LINEARITY ERROR MAX AT +25°C PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE DAC712P ±4LSB ±4LSB PDIP-28 NT –40°C to +85°C DAC712U ±4LSB ±4LSB SOIC-28 DW –40°C to +85°C DAC712PB ±2LSB ±2LSB PDIP-28 NT –40°C to +85°C DAC712UB ±2LSB ±2LSB SOIC-28 DW –40°C to +85°C DAC712PK ±2LSB ±2LSB PDIP-28 NT 0°C to +70°C DAC712UK ±2LSB ±2LSB SOIC-28 DW 0°C to +70°C DAC712PL ±2LSB ±1LSB PDIP-28 NT 0°C to +70°C DAC712UL ±2LSB ±1LSB SOIC-28 DW 0°C to +70°C (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) DAC712 UNIT +VCC to COMMON 0, +17 V –VCC to COMMON 0, –17 V +VCC to –VCC Digital Inputs to COMMON External Voltage Applied to BPO and Range Resistors VREF V V ±VCC V Indefinite Short to COMMON OUT VOUT Indefinite Short to COMMON Power Dissipation Storage Temperature Range (1) 34 –1 to +VCC – 0.7 750 mW –60 to +150 °C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. TRUTH TABLE 2 A0 A1 WR CLR DESCRIPTION 0 1 1→0→1 1 Load Input Latch 1 0 1→0→1 1 Load D/A Latch 1 1 1→0→1 1 No Change 0 0 0 1 Latches Transparent X X 1 1 No Change X X X 0 Reset D/A Latch Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 DAC712 www.ti.com ................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 ELECTRICAL CHARACTERISTICS: DAC712P, U, PB, UB At TA = +25°C, +VCC = +12V and +15V, and –VCC = –12V and –15V, unless otherwise noted. PARAMETER TEST CONDITIONS DAC712PB, UB (1) DAC712P, U MIN TYP MAX MIN TYP MAX UNIT INPUT RESOLUTION Resolution 16 Bits DIGITAL INPUTS Input Code Binary Twos Complement Logic Levels (2) VIH +2.0 +VCC – 1.4 VIL 0 V +0.8 V IIH (VI = +2.7V) ±10 µA IIL (VI = +0.4V) ±10 µA TRANSFER CHARACTERISTICS ACCURACY Linearity Error ±4 ±2 LSB TMIN to TMAX ±8 ±4 LSB ±4 ±2 LSB ±8 ±4 LSB Differential Linearity Error TMIN to TMAX Monotonicity Over Temperature Gain Error 13 14 (3) Bits ±0.1 TMIN to TMAX ±0.2 Bipolar Zero Error (3) TMIN to TMAX Power-Supply Sensitivity of Full-Scale % ±0.15 % ±0.1 % FSR (4) ±20 mV ±0.2 ±0.15 ±40 ±30 % FSR mV ±0.003 % FSR/% VCC ±30 ppm FSR/% VCC DYNAMIC PERFORMANCE Settling Time (to ±0.003%FSR, 5kΩ || 500pF Load) (5) 6 1LSB Output Step (6) 4 µs 10 V/µs 0dB, 1001Hz, fS = 100kHz 0.005 % –20dB, 1001Hz, fS = 100kHz 0.03 % –60dB, 1001Hz, fS = 100kHz 3.0 % Output Slew Rate 10 µs 20V Output Step Total Harmonic Distortion + Noise SINAD 1001Hz, fS = 100kHz 87 dB Digital Feedthrough (6) 2 nV-s Digital-to-Analog Glitch Impulse (6) 15 nV-s Output Noise Voltage (Includes Reference) 120 nV/√Hz (1) (2) (3) (4) (5) (6) Shaded cells indicate same specification as the DAC712P, U grade. Digital inputs are TTL- and +5V CMOS-compatible over the specified temperature range. Errors externally adjustable to zero. FSR means Full-Scale Range. For example, for a ±10V output, FSR = 20V. Maximum represents the 3σ limit. Not 100% tested for this parameter. For the worst-case code changes: FFFFh to 0000h and 0000h to FFFFh. These are binary twos complement (BTC) codes. Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 3 DAC712 SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS: DAC712P, U, PB, UB (continued) At TA = +25°C, +VCC = +12V and +15V, and –VCC = –12V and –15V, unless otherwise noted. PARAMETER TEST CONDITIONS DAC712PB, UB (1) DAC712P, U MIN TYP MAX MIN TYP MAX UNIT ANALOG OUTPUT Output Voltage Range +VCC, –VCC = ±11.4V Output Current ±10 V ±5 mA Output Impedance Ω 0.1 Short-Circuit to ACOM, Duration Indefinite REFERENCE VOLTAGE Voltage +9.975 TMIN to TMAX Output Resistance Source Current +10.000 +9.960 +10.025 +10.040 V Ω 1 2 Short-Circuit to ACOM, Duration V mA Indefinite POWER-SUPPLY REQUIREMENTS Voltage +VCC +11.4 +15 +16.5 V –VCC –11.4 –15 –16.5 V +VCC 13 15 mA –VCC 22 25 mA 525 600 mW Current (No Load, ±15V Supplies) Power Dissipation (7) TEMPERATURE RANGES Specified Temperature Range (All Grades) –40 +85 °C Storage Temperature Range –60 +150 °C Thermal Coefficient, θJA (7) 4 DIP Package 75 °C/W SOIC Package 75 °C/W Typical supply voltages times maximum currents. Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 DAC712 www.ti.com ................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 ELECTRICAL CHARACTERISTICS: DAC712PK, UK, PL, UL At TA = +25°C, +VCC = +12V and +15V, and –VCC = –12V and –15V, unless otherwise noted. PARAMETER TEST CONDITIONS DAC712PL, UL (1) DAC712PK, UK MIN TYP MAX MIN TYP MAX UNIT INPUT RESOLUTION Resolution 16 Bits DIGITAL INPUTS Input Code Binary Twos Complement Logic Levels (2) VIH +2.0 +VCC – 1.4 VIL 0 V +0.8 V IIH (VI = +2.7V) ±10 µA IIL (VI = +0.4V) ±10 µA Linearity Error ±2 LSB TMIN to TMAX ±2 LSB TRANSFER CHARACTERISTICS ACCURACY Differential Linearity Error TMIN to TMAX Monotonicity Over Temperature Gain Error ±2 ±1 LSB ±2 ±1 LSB 15 16 (3) Bits ±0.1 TMIN to TMAX ±0.15 Bipolar Zero Error (3) TMIN to TMAX Power-Supply Sensitivity of Full-Scale % ±0.2 % ±0.1 % FSR (4) ±20 mV ±0.15 % FSR ±30 mV ±0.003 % FSR/% VCC ±30 ppm FSR/% VCC 10 µs DYNAMIC PERFORMANCE Settling Time (to ±0.003%FSR, 5kΩ || 500pF Load) (5) 20V Output Step 6 1LSB Output Step (6) 4 µs 10 V/µs 0dB, 1001Hz, fS = 100kHz 0.005 % –20dB, 1001Hz, fS = 100kHz 0.03 % –60dB, 1001Hz, fS = 100kHz 3.0 % Output Slew Rate Total Harmonic Distortion + Noise SINAD 1001Hz, fS = 100kHz 87 dB Digital Feedthrough (6) 2 nV-s Digital-to-Analog Glitch Impulse (6) 15 nV-s Output Noise Voltage (Includes Reference) 120 nV/√Hz (1) (2) (3) (4) (5) (6) Shaded cells indicate same specification as the DAC712PK, UK grade. Digital inputs are TTL- and +5V CMOS-compatible over the specified temperature range. Errors externally adjustable to zero. FSR means Full-Scale Range. For example, for a ±10V output, FSR = 20V. Maximum represents the 3σ limit. Not 100% tested for this parameter. For the worst-case code changes: FFFFh to 0000h and 0000h to FFFFh. These are binary twos complement (BTC) codes. Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 5 DAC712 SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS: DAC712PK, UK, PL, UL (continued) At TA = +25°C, +VCC = +12V and +15V, and –VCC = –12V and –15V, unless otherwise noted. PARAMETER TEST CONDITIONS DAC712PL, UL (1) DAC712PK, UK MIN TYP MAX MIN TYP MAX UNIT ANALOG OUTPUT Output Voltage Range +VCC, –VCC = ±11.4V Output Current ±10 V ±5 mA Output Impedance Ω 0.1 Short-Circuit to ACOM, Duration Indefinite REFERENCE VOLTAGE Voltage +9.975 TMIN to TMAX Output Resistance Source Current +10.000 +9.960 +10.025 +10.040 V Ω 1 2 Short-Circuit to ACOM, Duration V mA Indefinite POWER-SUPPLY REQUIREMENTS Voltage +VCC +11.4 +15 +16.5 V –VCC –11.4 –15 –16.5 V +VCC 13 15 mA –VCC 22 25 mA 525 600 mW 0 +70 °C –60 +150 °C Current (No Load, ±15V Supplies) Power Dissipation (7) TEMPERATURE RANGES Specified Temperature Range (All Grades) Storage Temperature Range Thermal Coefficient, θJA (7) 6 DIP Package 75 °C/W SOIC Package 75 °C/W Typical supply voltages times maximum currents. Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 DAC712 www.ti.com ................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 PIN CONFIGURATION DW AND NT PACKAGES SOIC-28 AND PDIP-28 (TOP VIEW) DCOM 1 28 LSB D0 ACOM 2 27 D1 VOUT 3 26 D2 Offset Adjust 4 25 D3 VREF OUT 5 24 D4 Gain Adjust 6 23 D5 +VCC 7 22 D6 -VCC 8 21 D7 CLR 9 20 D8 WR 10 19 D9 A1 11 18 D10 A0 12 17 D11 D15 MSB 13 16 D12 D14 14 15 D13 DAC712 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 7 DAC712 SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com PIN DESCRIPTIONS 8 PIN NAME DESCRIPTION 1 DCOM Power-Supply return for digital currents 2 ACOM Analog Supply Return 3 VOUT 4 Offset Adjust ±10V D/A Output Offset Adjust (Bipolar) 5 VREF OUT 6 Gain Adjust Voltage Reference Output 7 +VCC +12V to +15V Supply 8 –VCC –12V to –15V Supply 9 CLR CLEAR; Sets D/A output to Bipolar Zero (Active Low) 10 WR Write (Active Low) 11 A1 Enable for D/A latch (Active Low) 12 A0 Enable for Input latch (Active Low) 13 D15 Data Bit 15 (Most Significant Bit) 14 D14 Data Bit 14 15 D13 Data Bit 13 16 D12 Data Bit 12 17 D11 Data Bit 11 18 D10 Data Bit 10 19 D9 Data Bit 9 20 D8 Data Bit 8 21 D7 Data Bit 7 22 D6 Data Bit 6 23 D5 Data Bit 5 24 D4 Data Bit 4 25 D3 Data Bit 3 26 D2 Data Bit 2 27 D1 Data Bit 1 28 D0 Data Bit 0 (Least Significant Bit) Gain Adjust Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 DAC712 www.ti.com ................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 TIMING CHARACTERISTICS tAW tAH A0, A1 tDW D0-D15 tDH WR tWP Figure 1. Timing Diagram TIMING REQUIREMENTS At TA = –40°C to +85°C, +VCC = +12V or +15V, and –VCC = –12V or –15V, unless otherwise noted. DAC712 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tDW Data Valid to End of WR 50 ns tAW A0 , A1 Valid to End of WR 50 ns tAH A0 , A1 Hold after End of WR 10 ns tDH Data Hold after End of WR 10 ns tWP (1) Write Pulse Width 50 ns tCP CLEAR Pulse Width 200 ns (1) For single-buffered operation, tWP is 80ns minimum; see the Single-Buffered Operation section. Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 9 DAC712 SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C and VCC = ±15V, unless otherwise noted. LOGIC vs V LEVEL 1k 2.0 -VCC 100 I Digital Input (mA) [Change in FSR]/[Change in Supply Voltage] (ppm of FSR/ %) POWER-SUPPLY REJECTION vs POWER-SUPPLY RIPPLE FREQUENCY +VCC 10 WR, A0, A1 1.0 CLR 0 DATA -1.0 1 -2.0 -0.85 0.1 10 100 1k 10k 100k 1M 0.85 1.7 2.55 0 3.4 4.25 5.1 5.95 6.8 V Digital Input Frequency (Hz) Figure 2. Figure 3. ± FULL-SCALE OUTPUT SWING SETTLING TIME, +10V TO –10V VOUT (V) D Around -10V (mV) 2000 +5V 1500 0V WR (V) 2500 1000 500 0 -500 -1000 -1500 -2000 -2500 Time (10ms/div) Time (1ms/div) Figure 4. Figure 5. SETTLING TIME, +10V TO –10V SPECTRAL NOISE DENSITY 2000 +5V 1500 0V WR 1000 1000 100 500 nV/ÖHz D Around +10V (mV) 2500 0 -500 10 -1000 -1500 -2000 1 -2500 Time (1ms/div) 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) Figure 6. 10 Figure 7. Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 DAC712 www.ti.com ................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 DISCUSSION OF SPECIFICATIONS LINEARITY ERROR TOTAL HARMONIC DISTORTION + NOISE Linearity error is defined as the deviation of the analog output from a straight line drawn between the end points of the transfer characteristic. Total harmonic distortion + noise is defined as the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental frequency. It is expressed in % of the fundamental frequency amplitude at sampling rate fS. DIFFERENTIAL LINEARITY ERROR Differential linearity error (DLE) is the deviation from 1LSB of an output change from one adjacent state to the next. A DLE specification of ±1/2LSB means that the output step size can range from 1/2LSB to 3/2LSB when the digital input code changes from one code word to the adjacent code word. If the DLE is more positive than –1LSB, the D/A converter is said to be monotonic. SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) SINAD includes all the harmonic and outstanding spurious components in the definition of output noise power in addition to quantizing and internal random noise power. SINAD is expressed in dB at a specified input frequency and sampling rate, fS. MONOTONICITY A D/A converter is monotonic if the output either increases or remains the same for increasing digital input values. Monotonicity of the DAC712 is ensured over the specified temperature range to 13, 14, 15, and 16 bits for performance grades DAC712P/U, DAC712PB/UB, DAC712PK/UK, and DAC712PL/UL, respectively. DIGITAL-TO-ANALOG GLITCH IMPULSE The amount of charge injected into the analog output from the digital inputs when the inputs change state. It is measured at half-scale at the input codes where as many switches as possible change state—from 7FFFh to 8000h. DIGITAL FEEDTHROUGH SETTLING TIME Settling time is the total time (including slew time) for the D/A output to settle to within an error band around its final value after a change in input. Settling times are specified to within ±0.003% of Full-Scale Range (FSR) for an output step change of 20V and 1LSB. The 1LSB change is measured at the Major Carry (FFFFh to 0000h, and 0000h to FFFFh: BTC codes), the input transition at which worst-case settling time occurs. When the analog-to-digital (A/D) converter is not selected, high-frequency logic activity on the digital inputs is coupled through the device and shows up as output noise. This noise is digital feedthrough. Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 11 DAC712 SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com OPERATION The DAC712 is a monolithic integrated-circuit, 16-bit D/A converter complete with 16-bit D/A converter switches and ladder network, voltage reference, output amplifier, and microprocessor bus interface. All latches are level-triggered. Data present when the enable inputs are logic '0' enter the latch. When the enable inputs return to logic '1', the data are latched. The CLR input resets both the input latch and the D/A latch to give a bipolar zero output. INTERFACE LOGIC The DAC712 has double-buffered data latches. The input data latch holds a 16-bit data word before loading it into the second latch, the D/A latch. This double-buffered organization permits simultaneous update of several D/A converters. All digital control inputs are active low. Refer to the block diagram of Figure 8. Gain Adjust VREF OUT +VCC -VCC 6 5 7 8 170W +10V Reference 15kW 250W 4 Bipolar Offset Adjust 3 VOUT 9750W 10kW +2.5V -VCC D/A Switches CLR 9 16-Bit D/A Latch A1 11 A0 12 WR 10 16-Bit Input Latch 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 2 DB15 ACOM MSB DB0 LSB 1 DCOM Figure 8. DAC712 Block Diagram 12 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 DAC712 www.ti.com ................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 LOGIC INPUT COMPATIBILITY GAIN AND OFFSET ADJUSTMENTS The DAC712 digital inputs are TTL-compatible (1.4V switching level) with low-leakage, high-impedance inputs. Thus, the inputs are suitable for being driven by any type of 5V logic such as 5V CMOS logic. An equivalent circuit of a digital input is shown in Figure 9. Figure 10 illustrates the relationship of offset and gain adjustments for a bipolar connected D/A converter. Offset should be adjusted first to avoid interaction of adjustments. Table 1 shows calibration values and codes. These adjustments have a minimum range of ±0.3%. Data inputs float to logic '0' and control inputs float to logic '0' if left unconnected. It is recommended that any unused inputs be connected to DCOM to improve noise immunity. Range of Gain Adjust » ±0.3% + Full-Scale 1LSB Digital inputs remain high-impedance when power is off. ESD Protection Circuit R = 1k: A0, A1, WR, CLR 3k: D0...D15 R Digital Input 6.8V Analog Output +VCC Full-Scale Range All Bits Logic 0 Bipolar Offset Range of Offset Adjust 5pF -VCC Gain Adjust Rotates the Line All Bits Logic 1 MSB on All Others Off - Full-Scale Offset Adjust Translates the Line Digital Input » ±0.3% Figure 9. Equivalent Circuit of Digital Inputs INPUT CODING The DAC712 is designed to accept positive-true binary twos complement (BTC) input codes that are compatible with bipolar analog output operation. For bipolar analog output configuration, a digital input of 7FFFh gives a positive full-scale output, 8000h gives a negative full-scale output, and 0000h gives bipolar zero output. Figure 10. Relationship of Offset and Gain Adjustments Table 1. Digital Input and Analog Output Voltage Calibration Values DAC712 CALIBRATION VALUES 1 LEAST SIGNIFICANT BIT = 305µV DIGITAL INPUT CODE BINARY TWOS COMPLEMENT, BTC ANALOG OUTPUT (V) INTERNAL REFERENCE 7FFFh +9.999695 Positive Full-Scale – 1LSB The DAC712 contains a +10V reference. 4000h +5.000000 3/4 Scale The reference output may be used to drive external loads, sourcing up to 2mA. The load current should be constant, otherwise the gain and bipolar offset of the converter will vary. 0001h +0.000305 BPZ + 1LSB 0000h 0.000000 Bipolar Zero (BPZ) FFFFh –0.000305 BPZ – 1LSB C000h –5.000000 1/4 Scale 8000h –10.00000 Negative Full-Scale OUTPUT VOLTAGE SWING The output amplifier of the DAC712 is committed to a ±10V output range. The DAC712 provides a ±10V output swing while operating on ±11.4V or higher voltage supplies. DESCRIPTION Offset Adjustment Apply the digital input code that produces the maximum negative output voltage and adjust the offset potentiometer or the offset adjust D/A converter for –10V. Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 13 DAC712 SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com Gain Adjustment Apply the digital input that gives the maximum positive voltage output. Adjust the gain potentiometer or the gain adjust D/A converter for this positive full-scale voltage. DCOM 28 2 ACOM 27 3 VOUT 26 4 INSTALLATION 5 25 VREF OUT 6 GENERAL CONSIDERATIONS +12V to +15V Because of the high accuracy of these D/A converters, system design problems such as grounding and contact resistance become very important. A 16-bit converter with a 20V full-scale range has a 1LSB value of 305mV. With a load current of 5µA, series wiring and connector resistance of only 60mΩ causes a voltage drop of 300µV. To understand what this means in terms of a system layout, the resistivity of a typical 1-ounce copper-clad printed circuit board (PCB) is 1/2mΩ per square. For a 5mA load, a 10 mil (0.010 inch) wide printed circuit conductor 60 milli-inches long results in a voltage drop of 150µV. -12V to -15V The analog output of the DAC712 has an LSB size of 305µV (–96dB). The noise floor of the D/A converter must remain below this level in the frequency range of interest. The DAC712 noise spectral density (which includes the noise contributed by the internal reference) is shown in the Typical Characteristics section. Wiring to high-resolution D/A converters should be routed to provide optimum isolation from sources of radio frequency interference (RFI) and electromagnetic interference (EMI). The key to elimination of RF radiation or pickup is a small loop area. Signal leads and the return conductors should be kept close together such that they present a small capture cross-section for any external field. Wire-wrap construction is not recommended. POWER-SUPPLY AND REFERENCE CONNECTIONS Power-supply decoupling capacitors should be added as shown in Figure 11. Best performance occurs using a 1µF to 10µF tantalum capacitor at –VCC. Applications with less critical settling time may be able to use 0.01µF at –VCC as well as at +VCC. The capacitors should be located close to the package. 14 1 0.01mF + 0.01mF + 24 23 7 +VCC 22 8 -VCC 21 9 20 10 19 11 18 12 17 13 16 14 15 Figure 11. Power-Supply Connections The DAC712 has separate ANALOG COMMON and DIGITAL COMMON pins. The current through DCOM is mostly switching transients and are up to 1mA peak in amplitude. The current through ACOM is typically 5µA for all codes. Use separate analog and digital ground planes with a single interconnection point to minimize ground loops. The analog pins are located adjacent to each other to help isolate analog from digital signals. Analog signals should be routed as far as possible from digital signals and should cross them at right angles. A solid analog ground plane around the D/A converter package, as well as under it in the vicinity of the analog and power-supply pins, isolates the D/A converter from switching currents. It is recommended that DCOM and ACOM be connected directly to the ground planes under the package. If several DAC712s are used, or if the DAC712 shares supplies with other components, connecting the ACOM and DCOM lines together once at the power supplies rather than at each chip may give better results. Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 DAC712 www.ti.com ................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 LOAD CONNECTIONS Because the reference point for VOUT and VREF OUT is the ACOM pin, it is important to connect the D/A converter load directly to the ACOM pin; see Figure 12. Lead and contact resistances are represented by R1 through R3. As long as the load resistance RL is constant, R1 simply introduces a gain error and can be removed by gain adjustment of the D/A converter or system-wide gain calibration. R2 is part of RL if the output voltage is sensed at ACOM. In some applications it is impractical to return the load to the ACOM pin of the D/A converter. Sensing the output voltage at the SYSTEM GROUND point is reasonable, because there is no change in the DAC712 ACOM current, provided that R3 is a low-resistance ground plane or conductor. In this case, DCOM may be connected to SYSTEM GROUND as well. DAC712 10kW 10kW VREF VOUT R1 Bus Interface RL DCOM Sense Output ACOM R2 Alternate Ground Sense Connection R3 To +VCC (1) 0.01mF 0.01mF System Ground Analog Power Supply To -VCC (1) Locate close to the DAC712 package. Figure 12. System Ground Considerations for High-Resolution D/A Converters Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 15 DAC712 SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com GAIN AND OFFSET ADJUST Nominal values of GAIN and OFFSET occur when the D/A converter outputs are at approximately half scale, +5V. Connections Using Potentiometers GAIN and OFFSET adjust pins provide for trim using external potentiometers. 15-turn potentiometers provide sufficient resolution. Range of adjustment of these trims is at least ±0.3% of Full-Scale Range; see Figure 13. OUTPUT VOLTAGE RANGE CONNECTIONS The DAC712 output amplifier is connected internally for the ±10V bipolar (20V) output range. That is, the bipolar offset resistor is connected to an internal reference voltage and the 20V range resistor is connected internally to VOUT. The DAC712 cannot be connected for unipolar operation. Using D/A Converters The GAIN ADJUST and OFFSET ADJUST circuits of the DAC712 have been arranged so that these points may be easily driven by external D/A converters; see Figure 14. 12-bit D/A converters provide an OFFSET adjust resolution and a GAIN adjust resolution of 30µV to 50µV per LSB step. Internal +10V Reference VREF OUT 5 R1 500W 170W R2 500W 250W 120W 180W R3 27kW R4 10kW Gain Adjust 6 Bipolar Offset Adjust 15kW 9.75kW 4 10kW » +2.5V 3 IDAC 0mA-2mA 2 ±10V VOUT ACOM (1) For no external adjustments, pins 4 and 6 are not connected. External Resistors R1 to R4 are standard ±1% values. Range of adjustment is at least ±0.3% FSR. Figure 13. Manual Offset and Gain Adjust Circuits 16 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 DAC712 www.ti.com ................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 Internal +10V Reference VREF OUT 5 10kW +10V 170W R1 340W 250W R2 500W 10kW Gain Adjust (1) Bipolar Offset Adjust 15kW -10V (2) 6 (1) 5kW 4 9.75kW R3 20kW 10kW R4 10kW 0V to 10V RFB VREF A (3) 3 IDAC 0mA-2mA ±10V VOUT 0V to +10V DAC712 RFB VREF B (4) (1) For no external adjustments, pins 4 and 6 are not connected. External Resistors R1 to R4 tolerance is ±1% values. Range of adjustment is at least ±0.3% FSR. (2) Suggested op amps: OPA177GP, GS or OPA604AP, AU. (3) Suggested op amps: single OPA177GP, GS or dual OPA2604AP, AU. (4) Suggested D/A converters: dual DAC7800 (serial input, 12-bit resolution); dual DAC7801 (8-bit port input, 12-bit resolution); dual DAC7802 (12-bit port input, 12-bit resolution); dual DAC7545 (12-bit port input, 12-bit resolution); or single DAC8043 (serial input, 12-bit resolution). BIPOLAR (complete): DAC813 (use 11-bit resolution for 0V to +10V output; no op-amps required). Figure 14. Gain and Offset Adjustment Using D/A Converters DIGITAL INTERFACE BUS INTERFACE SINGLE-BUFFERED OPERATION The DAC712 has 16-bit, double-buffered data bus interface with control lines for easy interface to interface to a 16-bit bus. The double-buffered feature permits update of several D/A converters simultaneously. To operate the DAC712 interface as a single-buffered latch, the DATA INPUT LATCH is permanently enabled by connecting A0 to DCOM. If A1 is not used to enable the D/A converter, it should be connected to DCOM as well. For this mode of operation, the width of WR must be at least 80ns minimum to pass data through the DATA INPUT LATCH and into the D/A LATCH. A0 is the enable control for the DATA INPUT LATCH. is the enable for the D/A LATCH. WR is used to strobe data into latches enabled by A0 and A1 . Refer to the block diagram of Figure 8 and to Figure 1. A1 CLR sets the INPUT DATA LATCH to all zeros and the D/A LATCH to a code that gives bipolar 0V at the D/A converter output. TRANSPARENT INTERFACE The digital interface of the DAC712 can be made transparent by asserting A0 , A1 , and WR LOW, and asserting CLR HIGH. Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 17 DAC712 SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (September 200) to Revision A ................................................................................................. Page • • 18 Updated document format to current standards .................................................................................................................... 1 Changed max specification for Accuracy, Gain Error, TMIN to TMAX parameter in Electrical Characteristics: DAC712PK, UK, PL, UL table................................................................................................................................................ 5 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated Product Folder Link(s): DAC712 PACKAGE OPTION ADDENDUM www.ti.com 28-Oct-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) (Requires Login) DAC712P NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PB NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PBG4 NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PG4 NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PK NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PKG4 NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PL NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PLG4 NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712U ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC712UB ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC712UB/1K OBSOLETE SOIC DW 28 TBD Call TI Call TI DAC712UB/1KG4 OBSOLETE SOIC DW 28 TBD Call TI Call TI DAC712UBG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC712UG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC712UK ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC712UK/1K OBSOLETE SOIC DW 28 TBD Call TI Call TI DAC712UK/1KG4 OBSOLETE SOIC DW 28 TBD Call TI Call TI DAC712UKG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) Addendum-Page 1 Samples CU NIPDAU Level-3-260C-168 HR PACKAGE OPTION ADDENDUM www.ti.com 28-Oct-2011 Orderable Device Status (1) Package Type Package Drawing Pins DAC712UL ACTIVE SOIC DW 28 DAC712UL/1K OBSOLETE SOIC DW 28 DAC712UL/1KG4 OBSOLETE SOIC DW 28 DAC712ULG4 ACTIVE SOIC DW 28 Package Qty 20 Eco Plan (2) Green (RoHS & no Sb/Br) TBD TBD 20 Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-3-260C-168 HR Call TI Call TI Call TI Call TI CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page www.ti.com/video e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2011, Texas Instruments Incorporated