HCF4076B 4 BIT D TYPE REGISTERS ■ ■ ■ ■ ■ ■ ■ ■ ■ THREE STATE OUTPUTS INPUT DISABLE WITHOUT GATING THE CLOCK GATED OUTPUT CONTROL LINES FOR ENABLING OR DISABLING THE OUTPUTS BUFFERED INPUTS AND OUTPUTS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF4076B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4076B is a four bit register consisting of D-TYPE flip-flops that feature three state outputs. Data Disable inputs are provided to control the entry of data into the flip-flops. When both Data DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF4076BEY HCF4076BM1 HCF4076M013TR Disable inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the clock input. Output Disable inputs are also provided. When the Output Disable inputs are both low, the normal logic states of the four outputs are available to the load. The outputs are disabled independently of the clock by a high logic level at either Output Disable input, and present a high impedance. PIN CONNECTION September 2002 1/9 HCF4076B IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 14, 13, 12, 11 DATA1 to DATA 4 10, 9 G1, G2 1, 2 7 15 8 M, N CLOCK RESET VSS 16 VDD NAME AND FUNCTION D Inputs Data Input Disable Control Output Disable Control Clock Input Reset Input Negative Supply Voltage Positive Supply Voltage TRUTH TABLE DATA INPUT DISABLE DATA D NEXT STATE OUTPUT X X X X L Q NO CHANGE H X X Q NO CHANGE L X H X Q NO CHANGE L L L H H L L L L L X X X Q NO CHANGE X X X Q NO CHANGE RESET CLOCK G1 G2 X X L H L L X L H L X : Don’t Care When either Output Disable M or N is high, the outputs are disabled (high impedance state) : however sequential operation of the flip-flop is not affected. FUNCTIONAL DIAGRAM 2/9 HCF4076B LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage Value Unit -0.5 to +22 V VI DC Input Voltage -0.5 to VDD + 0.5 V II DC Input Current ± 10 mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C PD Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C 3/9 HCF4076B DC SPECIFICATIONS Test Condition Symbol IL VOH VOL VIH VIL IOH IOL II IOZ CI Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current Input Leakage Current 3-State Output Current Input Capacitance VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Value |IO| VDD (µA) (V) <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 Any Input 0/18 Any Input 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 TA = 25°C Min. Typ. Max. 0.04 0.04 0.04 0.08 5 10 20 100 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 4.95 9.95 14.95 3.5 7 11 1.5 3 4 -3.2 -1 -2.6 -6.8 1 2.6 6.8 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 µA V 0.05 0.05 0.05 V V 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 V mA mA 18 ±10-5 ±0.1 ±1 ±1 µA 18 ±10-4 ±0.4 ±12 ±12 µA 5 7.5 The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 4/9 Max. 150 300 600 3000 0.05 0.05 0.05 3.5 7 11 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 Max. Unit pF HCF4076B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time (Clock to Q Output) tPHL(R) tP(1-H) tP(L-1) tW tW tsetup tsetup fmax tr, tf Propagation Delay Time (Reset) 3-State Out H or L to High Impedance 3-State High Impedance to H or L Output Clock Pulse Width Reset Pulse Width Data Setup Time Data Input Disable Setup Time Maximum Clock Frequency Clock input Rise or Fall Time VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Value (*) Min. RL = 1KΩ RL = 1KΩ 200 100 80 120 50 40 200 80 60 180 100 70 3 6 8 15 5 5 Unit Typ. Max. 300 125 90 230 100 75 150 75 60 150 75 60 100 50 40 60 25 20 100 40 30 90 50 35 6 12 16 600 250 180 460 200 150 300 150 120 300 150 120 ns ns ns ns ns ns ns ns MHz µs (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. 5/9 HCF4076B TEST CIRCUIT TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VDD tPZH, tPHZ VSS CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) 6/9 HCF4076B Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 7/9 HCF4076B SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45˚ (typ.) D 9.8 E 5.8 10 0.385 6.2 0.228 0.393 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8 ˚ (max.) PO13H 8/9 HCF4076B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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