CDP1802AC/3 ® Data Sheet October 17, 2008 FN1441.3 Features High-Reliability CMOS 8-Bit Microprocessor The CDP1802A/3 High-Reliability LSI CMOS 8-bit register oriented Central-Processing Unit (CPU) is designed for use as a general purpose computing or control element in a wide range of stored-program systems or products. The CDP1802A/3 includes all of the circuits required for fetching, interpreting, and executing instructions which have been stored in standard types of memories. Extensive input/output (I/O) control features are also provided to facilitate system design. The 1800 Series Architecture is designed with emphasis on the total microcomputer system as an integral entity so that systems having maximum flexibility and minimum cost can be realized. The 1800 Series CPU also provides a synchronous interface to memories and external controllers for I/O devices, and minimizes the cost of interface controllers. Further, the I/O interface is capable of supporting devices operating in polled, interrupt-driven, or direct memory-access modes. For Use In Aerospace, Military, and Critical Industrial Equipment • Minimum Instruction Fetch-Execute Time of 4.5µs (Maximum Clock Frequency of 3.6MHz) at VDD = 5V, TA = +25°C • Operation Over the Full Military Temperature Range . . . . . . . . . . . . . . . -55°C to +125°C • Any Combination of Standard RAM and ROM Up to 65,536 Bytes • 8-Bit Parallel Organization With Bi-directional Data Bus and Multiplexed Address Bus • 16x16 Matrix of Registers for Use as Multiple Program Counters, Data Pointers, or Data Registers • On-Chip DMA, Interrupt, and Flag Inputs • High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of VDD • Pb-Free (RoHS compliant) The CDP1802AC/3 is functionally identical to its predecessor, the CDP1802. The “A” version includes some performance enhancements and can be used as a direct replacement in systems using the CDP1802. This type is supplied in a 40 Ld dual-in-line sidebrazed ceramic package (D suffix). Ordering Information PART NUMBER CDP1802ACD3 PART MARKING CDP1802ACD3 TEMP. RANGE (°C) CLOCK FREQUENCY AT 5V -55 to +125 Up to 3.2MHz PACKAGE 40 Ld SBDIP PKG DWG. # D40.6 NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CDP1802AC/3 Pinout CDP1802AC/3 (40 LD SBDIP) TOP VIEW CLOCK 1 40 VDD WAIT 2 39 XTAL CLEAR 3 38 DMA IN Q 4 37 DMA OUT SC1 5 36 INTERRUPT SC0 6 35 MWR MRD 7 34 TPA BUS 7 8 33 TPB BUS 6 9 32 MA7 BUS 5 10 31 MA6 BUS 4 11 30 MA5 BUS 3 12 29 MA4 BUS 2 13 28 MA3 BUS 1 14 27 MA2 BUS 0 15 26 MA1 VCC 16 25 MA0 N2 17 24 EF1 N1 18 23 EF2 N0 19 22 EF3 VSS 20 21 EF4 ADDRESS BUS CDP1852 INPUT PORT CS2 MA0–7 N0 MA0–7 MA0–4 CS1 MRD MRD CDP1802 8–BIT CPU MRD CDP1833 1k–ROM MWR MWR DATA CS1 CS2 CDP1852 OUTPUT CLOCK PORT N1 TPB DATA TPA CDP1824 32 BYTE RAM CEO TPA DATA CS DATA 8–BIT DATA BUS FIGURE 1. TYPICAL CDP1802A/3 SMALL MICROPROCESSOR SYSTEM 2 FN1441.3 October 17, 2008 CDP1802AC/3 CPU Block Diagram I/O REQUESTS MEMORY ADDRESS LINES I/O FLAGS MA6 MA4 MA2 MA0 EF1 EF3 EF2 MA7 MA5 MA3 MA1 DMA OUT MUX EF4 DMA IN INT CONTROL CLEAR WAIT CLOCK LOGIC CLOCK XTAL SCO SCI Q LOGIC TPA TPB MWR MRD CONTROL AND TIMING LOGIC TO INSTRUCTION DECODE STATE CODES SYSTEM TIMING A B ALU DF INCR/ DECR REGISTER R(0).1 R(0).0 ARRAY R(1).1 R(1).0 R R(2).1 R(2).0 R(9).1 R(9).0 R(A).1 R(A).0 D LATCH AND DECODE R(E).1 R(E).0 R(F).1 R(F).0 N0 X T P I N N1 I/O COMMANDS N2 BUS 0 BUS 1 8-BIT BIDIRECTIONAL DATA BUS BUS 2 BUS 3 BUS 4 BUS 5 BUS 6 BUS 7 3 FN1441.3 October 17, 2008 CDP1802AC/3 Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1802AC/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . ±10mA Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) SBDIP Package . . . . . . . . . . . . . . . . . . 55 15 Device Dissipation Per Output Transistor TA = Full Package Temperature Range . . . . . . . . . . . . . . .100mW Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C Storage Temperature Range (TSTG) . . . . . . . . . . . .-65°C to +150°C Lead Temperature (During Soldering) At distance 1/16 ± 1/32 In. (1.59 ±0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Recommended Operating Conditions TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER MIN MAX UNITS 4 6.5 V VSS VDD V - 1 µs DC Operating Voltage Range Input Voltage Range Maximum Clock Input Rise or Fall Time Performance Specifications Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. VDD (V) -55°C TO +25°C +125°C UNITS Minimum Instruction Time (Note 3) 5 4.5 5.9 µs Maximum DMA Transfer Rate 5 450 340 Kbytes/s Maximum Clock Input Frequency, Load Capacitance (CL) = 50pF, fCL 5 DC-3.6 DC-2.7 MHz PARAMETER NOTE: 3. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3 machine cycles - one Fetch and two Execute operations. Static Electrical Specifications All Limits are 100% Tested. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. CONDITIONS PARAMETER Quiescent Device Current, IDD Output Low Drive (Sink) Current (Except XTAL), IOL XTAL Output High Drive (Source) Current (Except XTAL), IOH XTAL Output Voltage Low-Level, VOL 4 -55°C, +25°C +125°C VOUT (V) VIN, (V) VCC, VDD (V) (Note 4) MIN MAX MIN MAX UNITS - - 5 - 100 - 250 µA 0.4 0, 5 5 1.20 - 0.90 - mA 0.4 5 5 185 - 140 - µA 4.6 0, 5 5 - -0.30 - -0.20 mA 4.6 0 5 - -135 - -100 µA - 0, 5 5 - 0.1 - 0.2 V FN1441.3 October 17, 2008 CDP1802AC/3 Static Electrical Specifications All Limits are 100% Tested. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) CONDITIONS -55°C, +25°C +125°C VOUT (V) VIN, (V) VCC, VDD (V) (Note 4) - 0, 5 5 4.9 - 4.8 - V Input Low Voltage, VIL 0.5, 4.5 - 5 - 1.5 - 1.5 V Input High Voltage, VIH PARAMETER Output Voltage High-Level, VOH MIN MAX MIN MAX UNITS 0.5, 4.5 - 5 3.5 - 3.5 - V Input Leakage Current, IIN Any Input 0, 5 5 - ±1 - ±5 µA Three-State Output Leakage Current, IOUT 0, 5 0, 5 5 - ±1 - ±5 µA NOTE: 4. 5V level characteristics apply to Part No. CDP1802AC/3, and 5V and 10V level characteristics apply to part No. CDP1802A/3. Timing Specifications As a Function of T (T = 1/fCLOCK), CL = 50 pF. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. LIMITS (Note 5) VDD (V) -55°C, +25°C +125°C UNITS 5 2T-450 2T-580 ns High-Order Memory-Address Byte Hold After TPA Time, tH 5 T/2 +0 T/2 +0 ns Low-Order Memory-Address Byte Hold After WR Time, tH 5 T-30 T-40 ns CPU Data to Bus Hold After WR Time, tH 5 T-170 T-250 ns Required Memory Access Time Address to Data, tACC 5 5T-300 5T-400 ns PARAMETER High-Order Memory-Address Byte Setup to TPA Time, tSU NOTE: 5. These limits are not directly tested. Implicit Specifications (Note 6) TA = -55°C to +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL VDD (V) TYPICAL VALUES UNITS f = 2MHz - 5 4 mW Effective Input Capacitance any Input - CIN - 5 pF Effective Three-State Terminal Capacitance Data Bus - - - 7.5 pF Minimum Data Retention Voltage - VDR - 2.4 V Data Retention Current - IDR 2.4 10 µA PARAMETER Typical Total Power Dissipation Idle “00” at M(0000), CL = 50pF NOTE: 6. These specifications are not tested. Typical values are provided for guidance only. 5 FN1441.3 October 17, 2008 CDP1802AC/3 Dynamic Electrical Specifications CL = 50pF, Timing Measurement at 0.5 VDD Point. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. -55°C TO +25°C PARAMETERS +125°C VDD (V) MIN MAX MIN MAX UNITS Clock to TPA, TPB 5 - 275 - 370 ns Clock-to-Memory High Address Byte, tPLH, tPHL 5 - 725 - 950 ns Clock-to-Memory Low Address Byte Valid, tPLH, tPHL 5 - 340 - 425 ns Clock to MRD, tPLH, tPHL 5 - 340 - 425 ns Clock to MWR, tPLH, tPHL 5 - 275 - 370 ns Clock to (CPU DATA to BUS) Valid, tPLH, tPHL 5 - 430 - 550 ns Clock to State Code, tPLH, tPHL 5 - 440 - 550 ns Clock to Q, tPLH, tPHL 5 - 375 - 475 ns Clock to N (0 to 2), tPLH, tPHL 5 - 400 - 525 ns Data Bus Input Setup, tSU 5 10 - 10 - ns Data Bus Input Hold, t H 5 175 - 230 - ns DMA Setup, tSU 5 10 - 10 - ns DMA Hold, t H 5 200 - 270 - ns Interrupt Setup, t SU 5 10 - 10 - ns Interrupt Hold, tH 5 175 - 230 - ns WAIT Setup, tSU 5 30 - 30 - ns EF1-4 Setup, tSU 5 20 - 20 - ns EF1-4 Hold, tH 5 100 - 135 - ns CLEAR Pulse Width, tWL 5 150 - 200 - ns CLOCK Pulse Width, tWL 5 140 - 185 - ns PROGAGATION DELAY TIMES, tPLH, tPHL INTERFACE TIMING REQUIREMENTS (Note 7) REQUIRED PULSE WIDTH TIMES NOTE: 7. Minimum input setup and hold times required by Part CDP1802AC/3. 6 FN1441.3 October 17, 2008 CDP1802AC/3 Timing Waveforms FETCH (READ) CLOCK ADDRESS EXECUTE (WRITE) 00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00 HI BYTE LOW BYTE HI BYTE LOW BYTE TPA TPB MRD MWR DATA VALID INPUT DATA VALID OUTPUT DATA FIGURE 1. BASIC DC TIMING WAVEFORM, ONE INSTRUCTION CYCLE 7 FN1441.3 October 17, 2008 CDP1802AC/3 Timing Waveforms (Continued) tW CLOCK 0 00 1 01 10 2 11 tPLH TPA 3 20 21 30 4 31 40 5 41 50 60 61 70 tPLH tSU MRD (MEMORY READ CYCLE) 51 7 tPLH, tPHL tPHL MWR (MEMORY WRITE CYCLE) 01 tPLH, tPHL LOW ORDER ADDRESS BYTE tH tPLH tSU tPHL tPLH tPHL tPLH tH tPLH, tPHL tPLH, tPHL tPLH tPHL tPLH, tPHL Q N0, N1, N2 (I/O EXECUTION CYCLE) 00 tPHL DATA FROM CPU TO BUS STATE CODES 71 tH tPLH, tPHL HIGH ORDER ADDRESS BYTE tPLH 0 tPHL TPB MEMORY ADDRESS 6 tPLH tPLH DATA LATCHED IN CPU tH tSU DATA FROM BUS TO CPU DMA SAMPLED (S1, S2, S3) DMA REQUEST INTERRUPT REQUEST tSU tH INTERRUPT SAMPLED (S1, S2) tSU tH FLAG LINES SAMPLED (IN S1) tSU EF 1-4 tH tSU WAIT ANY NEGATIVE TRANSITION tW CLEAR FIGURE 2. TIMING WAVEFORM NOTES: 8. This timing diagram is used to show signal relationships only and does not represent any specific machine cycle. 9. All measurements are referenced to 50% point of the waveforms. 10. Shaded areas indicate “Don’t Care” or undefined state. Multiple transitions may occur during this period. 8 FN1441.3 October 17, 2008 CDP1802AC/3 Machine Cycle Timing Waveforms 0 1 2 3 4 5 6 7 (Propagation Delays Not Shown) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 CLOCK TPA TPB MACHINE CYCLE CYCLE n HIGH ADD MA CYCLE (n + 1) LOW ADDRESS HIGH ADD CYCLE (n + 2) LOW ADDRESS HIGH ADD LOW ADDRESS FIGURE 3. GENERAL TIMING WAVEFORMS INSTRUCTION FETCH (S0) MEMORY READ CYCLE EXECUTE (S1) NON MEMORY CYCLE FETCH (S0) EXECUTE MEMORY READ CYCLE MRD MWR (HIGH) MEMORY OUTPUT ALLOWABLE MEMORY ACCESS VALID OUTPUT “DON’T CARE” OR INTERNAL DELAYS VALID OUTPUT HIGH IMPEDANCE STATE FIGURE 4. NON-MEMORY CYCLE TIMING WAVEFORMS INSTRUCTION FETCH (S0) MEMORY READ CYCLE EXECUTE (S1) FETCH (S0) MEMORY WRITE CYCLE MEMORY READ CYCLE EXECUTE MRD MWR MEMORY OUTPUT ALLOWABLE MEMORY ACCESS CPU OUTPUT TO MEMORY OFF VALID OUTPUT VALID OUTPUT VALID DATA “DON’T CARE” OR INTERNAL DELAYS OFF VALID HIGH IMPEDANCE STATE FIGURE 5. MEMORY WRITE CYCLE TIMING WAVEFORMS 9 FN1441.3 October 17, 2008 CDP1802AC/3 Machine Cycle Timing Waveforms INSTRUCTION FETCH (S0) MEMORY READ CYCLE (Propagation Delays Not Shown) (Continued) EXECUTE (S1) MEMORY READ CYCLE FETCH (S0) EXECUTE MEMORY READ CYCLE MRD MWR (HIGH) MEMORY OUTPUT ALLOWABLE MEMORY ACCESS VALID OUTPUT “DON’T CARE” OR INTERNAL DELAYS VALID OUTPUT VALID OUTPUT HIGH IMPEDANCE STATE FIGURE 6. MEMORY READ CYCLE TIMING WAVEFORMS INSTRUCTION FETCH (S0) MEMORY READ CYCLE EXECUTE (S1) MEMORY READ CYCLE EXECUTE (S1) FETCH (S0) MEMORY READ CYCLE MRD MWR (HIGH) MEMORY OUTPUT ALLOWABLE MEMORY ACCESS VALID OUTPUT “DON’T CARE” OR INTERNAL DELAYS VALID OUTPUT VALID OUTPUT HIGH IMPEDANCE STATE FIGURE 7. LONG BRANCH OR LONG SKIP CYCLE TIMING WAVEFORMS 10 FN1441.3 October 17, 2008 CDP1802AC/3 Machine Cycle Timing Waveforms 0 1 2 (Propagation Delays Not Shown) 4 3 5 6 7 0 1 (Continued) 2 3 4 5 6 7 0 CLOCK TPA TPB MACHINE CYCLE INSTRUCTION CYCLE n CYCLE (n + 1) FETCH (S0) EXECUTE (S1) MRD N0 - N2 N=9-F MWR MEMORY OUTPUT VALID OUTPUT ALLOWABLE MEMORY ACCESS DATA BUS (NOTE) VALID DATA FROM INPUT DEVICE MEMORY READ CYCLE NOTE: USER GENERATED SIGNAL MEMORY WRITE CYCLE HIGH IMPEDANCE STATE “DON’T CARE” OR INTERNAL DELAYS FIGURE 8. INPUT CYCLE TIMING WAVEFORMS 0 1 2 4 3 5 6 7 0 1 2 3 4 5 6 7 0 CLOCK TPA TPB MACHINE CYCLE INSTRUCTION CYCLE n CYCLE (n + 1) FETCH (S0) EXECUTE (S1) MRD N=1-9 ALLOWABLE MEMORY ACCESS N0 - N2 DATA BUS ALLOWABLE MEMORY ACCESS VALID OUTPUT VALID DATA FROM MEMORY DATA STROBE (MRD ² TPB ² N) MEMORY READ CYCLE (NOTE) NOTE: USER GENERATED SIGNAL MEMORY READ CYCLE “DON’T CARE” OR INTERNAL DELAYS HIGH IMPEDANCE STATE FIGURE 9. OUTPUT CYCLE TIMING WAVEFORMS 11 FN1441.3 October 17, 2008 CDP1802AC/3 Machine Cycle Timing Waveforms 0 1 2 3 4 5 6 (Propagation Delays Not Shown) 7 0 1 2 3 4 5 (Continued) 6 7 0 1 2 3 4 5 6 7 CLOCK TPA TPB MACHINE CYCLE CYCLE n INSTRUCTION CYCLE (n+1) FETCH (S0) CYCLE (n+2) EXECUTE (S1) DMA (S2) DMA-IN MRD MWR MEMORY OUTPUT VALID OUTPUT VALID DATA FROM INPUT DEVICE DATA BUS (NOTE) MEMORY READ CYCLE MEMORY READ, WRITE OR NON-MEMORY CYCLE NOTE: USER GENERATED SIGNAL MEMORY WRITE CYCLE HIGH IMPEDANCE STATE “DON’T CARE” OR INTERNAL DELAYS FIGURE 10. DMA IN CYCLE TIMING WAVEFORMS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 CLOCK TPA TPB MACHINE CYCLE INSTRUCTION CYCLE n CYCLE (n + 1) CYCLE (n + 2) FETCH (S0) EXECUTE (S1) DMA (S2) DMA OUT (NOTE) MRD MWR MEMORY OUTPUT DATA STROBE (S2 ² TPB) (NOTE) VALID OUTPUT MEMORY READ CYCLE NOTE: USER GENERATED SIGNAL MEMORY READ, WRITE OR NON-MEMORY CYCLE “DON’T CARE” OR INTERNAL DELAYS VALID DATA FROM MEMORY MEMORY READ CYCLE HIGH IMPEDANCE STATE FIGURE 11. DMA OUT CYCLE TIMING WAVEFORMS 12 FN1441.3 October 17, 2008 CDP1802AC/3 Machine Cycle Timing Waveforms 0 1 2 3 4 5 (Propagation Delays Not Shown) 6 7 0 1 2 3 4 (Continued) 5 6 7 0 1 2 3 4 5 6 CLOCK TPA TPB MACHINE CYCLE INSTRUCTION CYCLE n CYCLE (n + 1) CYCLE (n + 2) FETCH (S0) EXECUTE (S1) INTERRUPT (S3) MRD MWR INTERRUPT (NOTE) (INTERNAL) IE MEMORY OUTPUT VALID OUTPUT MEMORY READ, WRITE OR NON-MEMORY CYCLE MEMORY READ CYCLE NOTE: USER GENERATED SIGNAL NON-MEMORY CYCLE HIGH IMPEDANCE STATE “DON’T CARE” OR INTERNAL DELAYS FIGURE 12. INTERRUPT CYCLE TIMING WAVEFORMS 6 5 4 VDD = 5V 3 2 1 0 25 35 45 55 65 75 85 95 105 115 125 AMBIENT TEMPERATURE (TA) (°C) FIGURE 13. TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF TEMPERATURE 13 LOAD CAPACITANCE (CL) = 50pF 7 6 TA = +25°C 5 4 PO LA TE D 7 8 3 TR A LOAD CAPACITANCE (CL) = 50pF 2 TA = +125°C EX 8 SYSTEM MAXIMUM CLOCK FREQUENCY (fCL) (MHz) SYSTEM MAXIMUM CLOCK FREQUENCY (fCL) (MHz) Performance Curves 1 0 2 3 4 5 6 7 8 9 SUPPLY VOLTAGE (VDD) (V) 10 11 12 FIGURE 14. TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE FN1441.3 October 17, 2008 CDP1802AC/3 Performance Curves (Continued) 0 AMBIENT TEMPERATURE (TA) = +25°C 350 OUTPUT HIGH (SOURCE) CURRENT (IOH -mA) TRANSITION TIME (tTHL, t TLH) (ns) 400 300 250 200 150 tTLH 100 tTHL 50 00 25 50 75 100 125 150 LOAD CAPACITANCE (CL) (pF) 175 2 3 4 AMBIENT TEMPERATURE = -40°C TO +85°C 5 6 -10 200 -9 -2 -8 -7 -6 -5 -4 -3 DRAIN TO SOURCE VOLTAGE (VDS) (V) -1 0 FIGURE 16. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 15. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE 1000 35 AMBIENT TEMPERATURE (TA) = +25°C IDLE = “00” at M (0000) BRANCH = “3707” at M (8107) AMBIENT TEMPERATURE = -40°C TO +85°C TYPICAL POWER DISSIPATION (PD) (mW) OUTPUT LOW (SINK) CURRENT (IOL) (mA) GATE TO SOURCE VOLTAGE (VGS) = -5V 1 30 25 20 15 10 GATE TO SOURCE VOLTAGE (VGS) = 5V 5 0 0 1 2 3 4 5 6 7 8 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 9 D V CC 1 “ CH AN BR = VD ” V CC =5 V D = VD =+ 5V ” LE “ID 0.1 1M CLOCK INPUT FREQUENCY (f CL) (Hz) 10M FIGURE 18. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY FOR BRANCH INSTRUCTION AND IDLE INSTRUCTION AMBIENT TEMPERATURE (TA) = +25°C 125 (ΔtPLH, ΔtPHL) (ns) Δ PROPAGATION DELAY TIME 10 0.1 0.01 10 FIGURE 17. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 150 100 100 C = D VD = 5V VC 75 50 L Δt P 25 H V CC = V DD = 5V Δt PHL ANY OUTPUT EXCEPT XTAL 0 0 50 100 150 200 Δ LOAD CAPACITANCE (Δ CL) (pF) FIGURE 19. TYPICAL CHANGE IN PROPAGATION DELAY AS A FUNCTION OF A CHANGE IN LOAD CAPACITANCE 14 FN1441.3 October 17, 2008 CDP1802AC/3 Signal Descriptions Bus 0 to Bus 7 (Data Bus) 4. acknowledging an interrupt request. The levels of state code are tabulated in Table 1. All states are valid at TPA. H = VCC, L = VSS. 8-bit bidirectional DATA BUS lines. These lines are used for transferring data between the memory, the microprocessor, and I/O devices. TABLE 1. LEVELS OF STATE CODE STATE CODE LINES STATE TYPE SC1 SC0 S0 (Fetch) L L S1 (Execute) L H S2 (DMA) H L S3 (Interrupt) H H N0 to N2 (I/O Control Lines) Activated by an I/O instruction to signal the I/O control logic of a data transfer between memory and I/O interface. These lines can be used to issue command codes or device selection codes to the I/O devices (independently or combined with the memory byte on the data bus when an I/O instruction is being executed). The N bits are low at all times except when an I/O instruction is being executed. During this time their state is the same as the corresponding bits in the N register. The direction of data flow is defined in the I/O instruction by bit N3 (internally) and is indicated by the level of the MRD signal. MRD = VCC: Data from I/O to CPU and Memory MRD = VSS: Data from Memory to I/O EF1 to EF4 (4 Flags) These inputs enable the I/O controllers to transfer status information to the processor. The levels can be tested by the conditional branch instructions. They can be used in conjunction with the INTERRUPT request line to establish interrupt priorities. These flags can also be used by I/O devices to “call the attention” of the processor, in which case the program must routinely test the status of these flag(s). The flag(s) are sampled at the beginning of every S1 cycle. TPA, TPB (2 Timing Pulses) Positive pulses that occur once in each machine cycle (TPB follows TPA). They are used by I/O controllers to interpret codes and to time interaction with the data bus. The trailing edge of TPA is used by the memory system to latch the higher-order byte of the 16-bit memory address. TPA is suppressed in IDLE when the CPU is in the load mode. MA0 to MA7 (8 Memory Address Lines) In each cycle, the higher-order byte of a 16-bit CPU memory address appears on the memory address lines MA0-7 first. Those bits required by the memory system can be strobed into external address latches by timing pulse TPA. The low order byte of the 16-bit address appears on the address lines after the termination of TPA. Latching of all 8 higher-order address bits would permit a memory system of 64k bytes. MWR (Write Pulse) A negative pulse appearing in a memory-write cycle, after the address lines have stabilized. INTERRUPT, DMA-lN, DMA-OUT (3 I/O Requests) MRD (Read Level) These inputs are sampled by the CPU during the interval between the leading edge of TPB and the leading edge of TPA. A low level on MRD indicates a memory read cycle. It can be used to control three-state outputs from the addressed memory which may have a common data input and output bus. If a memory does not have a three-state high-impedance output, MRD is useful for driving memory/bus separator gates. It is also used to indicate the direction of data transfer during an I/O instruction. For additional information see Table 4. Interrupt Action - X and P are stored in T after executing current instruction; designator X is set to 2; designator P is set to 1; interrupt enable is reset to 0 (inhibit); and instruction execution is resumed. The interrupt action requires one machine cycle (S3). DMA Action - Finish executing current instruction; R(0) points to memory area for data transfer; data is loaded into or read out of memory; and increment R(0). Q NOTE: In the event of concurrent DMA and Interrupt requests, DMA-lN has priority followed by DMA-OUT and then Interrupt. Single bit output from the CPU which can be set or reset under program control. During SEQ or REQ instruction execution, Q is set or reset between the trailing edge of TPA and the leading edge of TPB. SC0, SC1 (2 State Code Lines) CLOCK These outputs indicate that the CPU is: Input for externally generated single-phase clock. The clock is counted down internally to 8-clock pulses per machine cycle. 1. Fetching an instruction 2. Executing an instruction 3. Processing a DMA request, 15 FN1441.3 October 17, 2008 CDP1802AC/3 XTAL Connection to be used with clock input terminal, for an external crystal, if the on-chip oscillator is utilized. The crystal is connected between terminals 1 and 39 (CLOCK and XTAL) in parallel with a resistance (10MΩ typ). Frequency trimming capacitors may be required at terminals 1 and 39. For additional information, see Application Note AN6565. loaded into the register and the lower order 4 bits into the N register. The content of the program counter is automatically incremented by one so that R(P) is now “pointing” to the next byte in the memory. The X designator selects one of the 16 registers R(X) to “point” to the memory for an operand (or data) in certain ALU or I/O operations. The N designator can perform the following five functions depending on the type of instruction fetched: WAIT, CLEAR (2 Control Lines) Provide four control modes as listed in Table 2: 1. Designate one of the 16 registers in R to be acted upon during register operations. TABLE 2. TRUTH TABLE CLEAR WAIT MODE L L LOAD L H RESET H L PAUSE H H RUN VDD, VSS, VCC (Power Levels) The internal voltage supply VDD is isolated from the Input/Output voltage supply VCC so that the processor may operate at maximum speed while interfacing with peripheral devices operating at lower voltage. VCC must be less than or equal to VDD. All outputs swing from VSS to VCC. The recommended input voltage swing is VSS to VCC. Architecture The “CPU Block Diagram” is shown on page 3. The principal feature of this system is a register array (R) consisting of sixteen 16-bit scratchpad registers. Individual registers in the array (R) are designated (selected) by a 4-bit binary code from one of the 4-bit registers labeled N, P and X. The contents of any register can be directed to any one of the following three paths: 1. The external memory (multiplexed, higher-order byte first, on to 8 memory address lines). 2. The D register (either of the two bytes can be gated to D). 3. The increment/decrement circuit where it is increased or decreased by one and stored back in the selected 16-bit register. The three paths, depending on the nature of the instruction, may operate independently or in various combinations in the same machine cycle. 2. Indicate to the I/O devices a command code or device selection code for peripherals. 3. Indicate the specific operation to be executed during the ALU instructions, types of test to be performed during the Branch instruction, or the specific operation required in a class of miscellaneous instructions (70 - 73 and 78 - 7B). 4. Indicate the value to be loaded into P to designate a new register to be used as the program counter R(P). 5. Indicate the value to be loaded into X to designate a new register to be used as data pointer R(X). The registers in R can be assigned by a programmer in three different ways: as program counters, as data pointers, or as scratchpad locations (data registers) to hold two bytes of data. Program Counters Any register can be the main program counter; the address of the selected register is held in the P designator. Other registers in R can be used as subroutine program counters. By single instruction the contents of the P register can be changed to effect a “call” to a subroutine. When interrupts are being serviced, register R(1) is used as the program counter for the user's interrupt servicing routine. After reset, and during a DMA operation, R(0) is used as the program counter. At all other times the register designated as program counter is at the discretion of the user. Data Pointers The registers in R may be used as data pointers to indicate a location in memory. The register designated by X (i.e., R(X)) points to memory for the following instructions (see Table 4). 1. ALU operations F1 - F5, F7, 74, 75, 77 2. Output instructions 61 through 67 3. Input instructions 69 through 6F 4. Certain miscellaneous instructions - 70 - 73, 78, 60, F0 With two exceptions, CPU instruction consists of two 8-clock-pulse machine cycles. The first cycle is the fetch cycle, and the second and third if necessary, are execute cycles. During the fetch cycle the four bits in the P designator select one of the 16 registers R(P) as the current program counter. The selected register R(P) contains the address of the memory location from which the instruction is to be fetched. When the instruction is read out from the memory, the higher order 4 bits of the instruction byte are 16 The register designated by N (i.e., R(N)) points to memory for the “load D from memory” instructions 0N and 4N and the “Store D” instruction 5N. The register designated by P (i.e., the program counter) is used as the data pointer for ALU instructions F8 - FD, FF, 7C, 7D, 7F. During these instruction executions, the operation is referred to as “data immediate”. Another important use of R as a data pointer supports the built-in Direct-Memory-Access (DMA) function. When a FN1441.3 October 17, 2008 CDP1802AC/3 DMA-IN or DMA-Out request is received, one machine cycle is “stolen”. This operation occurs at the end of the execute machine cycle in the current instruction. Register R(0) is always used as the data pointer during the DMA operation. The data is read from (DMA-Out) or written into (DMA-IN) the memory location pointed to by the R(0) register. At the end of the transfer, R(0) is incremented by one so that the processor is ready to act upon the next DMA byte transfer request. This feature in the 1800-series architecture saves a substantial amount of logic when fast exchanges of blocks of data are required, such as with magnetic discs or during CRT-display-refresh cycles. Data Registers When registers in R are used to store bytes of data, four instructions are provided which allow D to receive from or write into either the higher-order or lower-order byte portions of the register designated by N. By this mechanism (together with loading by data immediate) program pointer and data pointer designations are initialized. Also, this technique allows scratchpad registers in R to be used to hold general data. By employing increment or decrement instructions, such registers may be used as loop counters. CPU Register Summary D 8 Bits Data Register (Accumulator) DF 1-Bit Data Flag (ALU Carry) B 8 Bits Auxiliary Holding Register R 16 Bits 1 of 16 Scratchpad Registers P 4 Bits Designates which register is Program Counter X 4 Bits Designates which register is Data Pointer N 4 Bits Holds Low-Order Instruction Digit I 4 Bits Holds High-Order Instruction Digit T 8 Bits Holds old X, P after Interrupt (X is high nibble) lE 1-Bit Interrupt Enable Q 1-Bit Output Flip-Flop CDP1802 Control Modes The WAIT and CLEAR lines provide four control modes as listed in Table 3: TABLE 3. CONTROL MODES CLEAR WAIT MODE L L LOAD L H RESET The Q Flip-Flop H L PAUSE An internal flip-flop, Q, can be set or reset by instruction and can be sensed by conditional branch instructions. The output of Q is also available as a microprocessor output. H H RUN The functions of the modes are defined as follows: LOAD Interrupt Servicing Register R(1) is always used as the program counter whenever interrupt servicing is initiated. When an interrupt request occurs and the interrupt is allowed by the program (again, nothing takes place until the completion of the current instruction), the contents of the X and P registers are stored in the temporary register T, and X and P are set to new values; hex digit 2 in X and hex digit 1 in P. Interrupt Enable is automatically deactivated to inhibit further interrupts. The user's interrupt routine is now in control; the contents of T may be saved by means of a single instruction (78) in the memory location pointed to by R(X). At the conclusion of the interrupt, the user's routine may restore the pre-interrupted value of X and P with a single instruction (70 or 71). The Interrupt Enable flip-flop can be activated to permit further interrupts or can be disabled to prevent them. 17 Holds the CPU in the IDLE execution state and allows an I/O device to load the memory without the need for a “bootstrap” loader. It modifies the IDLE condition so that DMA-lN operation does not force execution of the next instruction. RESET Registers l, N, Q are reset, lE is set and 0’s (VSS) are placed on the data bus. TPA and TPB are suppressed while reset is held and the CPU is placed in S1. The first machine cycle after termination of reset is an initialization cycle which requires 9 clock pulses. During this cycle the CPU remains in S1 and register X, P, and R(0) are reset. Interrupt and DMA servicing are suppressed during the initialization cycle. The next cycle is an S0, S1, or an S2 but never an S3. With the use of a 71 instruction followed by 00 at memory locations 0000 and 0001, this feature may be used to reset IE, so as to preclude interrupts until ready for them. Power-up reset can be realized FN1441.3 October 17, 2008 CDP1802AC/3 RUN-MODE STATE TRANSITIONS by connecting an RC network directly to the CLEAR pin, since it has a Schmitt triggered input; see Figure 20. The CPU state transitions when in the RUN and RESET modes are shown in Figure 21. Each machine cycle requires the same period of time, 8-clock pulses, except the initialization cycle, which requires 9-clock pulses. The execution of an instruction requires either two or three machine cycles, S0 followed by a single S1 cycle or two S1 cycles. S2 is the response to a DMA request and S3 is the interrupt response. Table 5 shows the conditions on Data Bus and Memory Address lines during all machine states. VCC CDP1802 RS THE RC TIME CONSTANT SHOULD BE GREATER THAN THE OSCILLATOR START-UP TIME (TYPICALLY 20ms) CLEAR 3 C FIGURE 20. RESET DIAGRAM INSTRUCTION SET PAUSE The CPU instruction summary is given in Table 4. Hexadecimal notation is used to refer to the 4-bit binary codes. Stops the internal CPU timing generator on the first negative high-to-low transition of the input clock. The oscillator continues to operate, but subsequent clock transitions are ignored. In all registers bits are numbered from the least significant bit (LSB) to the most significant bit (MSB) starting with 0. RUN R(W): Register designated by W, where: May be initiated from the Pause or Reset mode functions. If initiated from Pause, the CPU resumes operation on the first negative high-to-low transition of the input clock. When initiated from the Reset operation, the first machine cycle following Reset is always the initialization cycle. The initialization cycle is then followed by a DMA (S2) cycle or fetch (S0) from location 0000 in memory. W = N or X, or P R(W).0: Lower order byte of R(W) R(W).1: Higher order byte of R(W) OPERATION NOTATION M(R(N)) → D; R(N) + 1 → R(N) This notation means: The memory byte pointed to by R(N) is loaded into D, and R(N) is incremented by 1. . IDLE • DMA • INT FORCE S1 S1 RESET (LONG BRANCH, LONG SKIP, NOP, ETC.) DMA S1 EXECUTE S1 INIT DMA INT • DMA DMA • IDLE • INT DMA DMA S2 DMA DMA DMA • INT S0 FETCH S3 INT DMA PRIORITY: FORCE S0, S1 DMA IN DMA OUT INT INT • DMA FIGURE 21. STATE TRANSITION DIAGRAM 18 FN1441.3 October 17, 2008 CDP1802AC/3 TABLE 4. INSTRUCTION SUMMARY (See Notes 11 through 16) MNEMONIC OP CODE LOAD VIA N LDN 0N M(R(N)) → D; FOR N not 0 LOAD ADVANCE LDA 4N M(R(N)) → D; R(N) + 1 → R(N) LOAD VIA X LDX F0 M(R(X)) → D LDXA 72 M(R(X)) → D; R(X) + 1 → R(X) LOAD IMMEDIATE LDl F8 M(R(P)) → D; R(P) + 1 → R(P) STORE VIA N STR 5N D → M(R(N)) STXD 73 D → M(R(X)); R(X) - 1 → R(X) INCREMENT REG N INC 1N R(N) + 1 → R(N) DECREMENT REG N DEC 2N R(N) - 1 → R(N) INCREMENT REG X IRX 60 R(X) + 1 → R(X) GET LOW REG N GLO 8N R(N).0 → D PUT LOW REG N PLO AN D → R(N).0 GET HIGH REG N GHl 9N R(N).1 → D PUT HIGH REG N PHI BN D → R(N).1 OR OR F1 M(R(X)) OR D → D OR IMMEDIATE ORl F9 M(R(P)) OR D → D; R(P) + 1 → R(P) EXCLUSIVE OR XOR F3 M(R(X)) XOR D → D EXCLUSIVE OR IMMEDIATE XRI FB M(R(P)) XOR D → D; R(P) + 1 → R(P) AND AND F2 M(R(X)) AND D → D AND IMMEDIATE ANl FA M(R(P)) AND D → D; R(P) + 1 → R(P) SHIFT RIGHT SHR F6 SHIFT D RIGHT, LSB(D) → DF, 0 → MSB(D) INSTRUCTION OPERATION MEMORY REFERENCE LOAD VIA X AND ADVANCE STORE VIA X AND DECREMENT REGISTER OPERATIONS LOGIC OPERATIONS (Note 11) SHIFT RIGHT WITH CARRY SHRC 76 SHIFT D RIGHT, LSB(D) → DF, DF → MSB(D) (Note 12) RING SHIFT RIGHT RSHR 76 SHIFT D RIGHT, LSB(D) → DF, DF → MSB(D) (Note 12) SHIFT LEFT SHL FE SHIFT D LEFT, MSB(D) → DF, 0 → LSB(D) SHIFT LEFT WITH CARRY SHLC 7E SHIFT D LEFT, MSB(D) → DF, DF → LSB(D) (Note 12) RING SHIFT LEFT RSHL 7E SHIFT D LEFT, MSB(D) → DF, DF → LSB(D) (Note 12) ARITHMETIC OPERATIONS (Note 11) ADD ADD F4 M(R(X)) + D → DF, D ADD IMMEDIATE ADl FC M(R(P)) + D → DF, D; R(P) + 1 → R(P) ADD WITH CARRY ADC 74 M(R(X)) + D + DF → DF, D ADD WITH CARRY, IMMEDIATE ADCl 7C M(R(P)) + D + DF → DF, D; R(P) + 1 → R(P) SUBTRACT D SD F5 M(R(X)) - D → DF, D SUBTRACT D IMMEDIATE SDl FD M(R(P)) - D → DF, D; R(P) + 1 → R(P) SUBTRACT D WITH BORROW SDB 75 M(R(X)) - D - (NOT DF) → DF, D 19 FN1441.3 October 17, 2008 CDP1802AC/3 TABLE 4. INSTRUCTION SUMMARY (See Notes 11 through 16) (Continued) MNEMONIC OP CODE SDBl 7D M(R(P)) - D - (Not DF) → DF, D; R(P) + 1 → R(P) SUBTRACT MEMORY SM F7 D-M(R(X)) → DF, D SUBTRACT MEMORY IMMEDIATE SMl FF D-M(R(P)) → DF, D; R(P) + 1 → R(P) SUBTRACT MEMORY WITH BORROW SMB 77 D-M(R(X))-(NOT DF) → DF, D SUBTRACT MEMORY WITH BORROW, IMMEDIATE SMBl 7F D-M(R(P))-(NOT DF) → DF, D; R(P) + 1 → R(P) BR 30 M(R(P)) → R(P).0 INSTRUCTION SUBTRACT D WITH BORROW, IMMEDIATE OPERATION BRANCH INSTRUCTIONS - SHORT BRANCH SHORT BRANCH NO SHORT BRANCH (See SKP) NBR 38 R(P) + 1 → R(P) (Note 12) BZ 32 IF D = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) SHORT BRANCH IF D NOT 0 BNZ 3A IF D NOT 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) SHORT BRANCH IF DF = 1 BDF SHORT BRANCH IF POS OR ZERO BPZ SHORT BRANCH IF EQUAL OR GREATER BGE SHORT BRANCH IF DF = 0 BNF SHORT BRANCH IF MINUS BM SHORT BRANCH IF LESS BL SHORT BRANCH IF Q = 1 BQ 31 IF Q = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) SHORT BRANCH IF Q = 0 BNQ 39 IF Q = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) SHORT BRANCH IF EF1 = 1 (EF1 = VSS) B1 34 IF EF1 =1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) SHORT BRANCH IF EF1 = 0 (EF1 = VCC) BN1 3C IF EF1 = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) SHORT BRANCH IF EF2 = 1 (EF2 = VSS) B2 35 IF EF2 = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) SHORT BRANCH IF EF2 = 0 (EF2 = VCC) BN2 3D IF EF2 = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) SHORT BRANCH IF EF3 = 1 (EF3 = VSS) B3 36 IF EF3 = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) SHORT BRANCH IF EF3 = 0 (EF3 = VCC) BN3 3E IF EF3 = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) SHORT BRANCH IF EF4 = 1 (EF4 = VSS) B4 37 IF EF4 = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) SHORT BRANCH IF EF4 = 0 (EF4 = VCC) BN4 3F IF EF4 = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) LBR C0 M(R(P)) → R(P). 1, M(R(P) + 1) → R(P).0 SHORT BRANCH IF D = 0 33 IF DF = 1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) (Note 12) 3B IF DF = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) (Note 12) BRANCH INSTRUCTIONS - LONG BRANCH LONG BRANCH NO LONG BRANCH (See LSKP) NLBR C8 R(P) = 2 → R(P) (Note 12) LBZ C2 lF D = 0, M(R(P)) → R(P).1, M(R(P) +1) → R(P).0, ELSE R(P) + 2 → R(P) LONG BRANCH IF D NOT 0 LBNZ CA IF D Not 0, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0, ELSE R(P) + 2 → R(P) LONG BRANCH IF DF = 1 LBDF C3 lF DF = 1, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0, ELSE R(P) + 2 → R(P) LONG BRANCH IF DF = 0 LBNF CB IF DF = 0, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0, ELSE R(P) + 2 → R(P) LONG BRANCH IF Q = 1 LBQ C1 IF Q = 1, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0, ELSE R(P) + 2 → R(P) LONG BRANCH IF D = 0 20 FN1441.3 October 17, 2008 CDP1802AC/3 TABLE 4. INSTRUCTION SUMMARY (See Notes 11 through 16) (Continued) INSTRUCTION LONG BRANCH lF Q = 0 MNEMONIC OP CODE LBNQ C9 OPERATION lF Q = 0, M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0 EISE R(P) + 2 → R(P) SKIP INSTRUCTIONS SHORT SKIP (See NBR) SKP 38 R(P) + 1 → R(P) (Note 12) LONG SKIP (See NLBR) LSKP C8 R(P) + 2 → R(P) (Note 12) LSZ CE IF D = 0, R(P) + 2 → R(P), ELSE CONTINUE LONG SKIP IF D NOT 0 LSNZ C6 IF D Not 0, R(P) + 2 → R(P), ELSE CONTINUE LONG SKIP IF DF = 1 LSDF CF IF DF = 1, R(P) + 2 → R(P), ELSE CONTINUE LONG SKIP IF DF = 0 LSNF C7 IF DF = 0, R(P) + 2 → R(P), ELSE CONTINUE LONG SKIP lF Q = 1 LSQ CD IF Q = 1, R(P) + 2 → R(P), ELSE CONTINUE LONG SKIP IF Q = 0 LSNQ C5 IF Q = 0, R(P) + 2 → R(P), ELSE CONTINUE LONG SKIP IF lE = 1 LSlE CC IF IE = 1, R(P) + 2 → R(P), ELSE CONTINUE LONG SKIP IF D = 0 CONTROL INSTRUCTIONS IDLE lDL 00 WAIT FOR DMA OR INTERRUPT; M(R(0)) → BUS (Note 13) NO OPERATION NOP C4 CONTINUE SET P SEP DN N→P SET X SEX EN N→X SET Q SEQ 7B 1→Q RESET Q REQ 7A 0→Q SAVE SAV 78 T → M(R(X)) MARK 79 (X, P) → T; (X, P) → M(R(2)), THEN P → X; R(2) - 1 → R(2) RETURN RET 70 M(R(X)) → (X, P); R(X) + 1 → R(X), 1 → lE DISABLE DlS 71 M(R(X)) → (X, P); R(X) + 1 → R(X), 0 → lE OUTPUT 1 OUT 1 61 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 1 OUTPUT 2 OUT 2 62 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 2 OUTPUT 3 OUT 3 63 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 3 OUTPUT 4 OUT 4 64 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 4 OUTPUT 5 OUT 5 65 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 5 OUTPUT 6 OUT 6 66 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 6 OUTPUT 7 OUT 7 67 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 7 INPUT 1 INP 1 69 BUS → M(R(X)); BUS → D; N LINES = 1 INPUT 2 INP 2 6A BUS → M(R(X)); BUS → D; N LINES = 2 INPUT 3 INP 3 6B BUS → M(R(X)); BUS → D; N LINES = 3 INPUT 4 INP 4 6C BUS → M(R(X)); BUS → D; N LINES = 4 INPUT 5 INP 5 6D BUS → M(R(X)); BUS → D; N LINES = 5 PUSH X, P TO STACK INPUT - OUTPUT BYTE TRANSFER 21 FN1441.3 October 17, 2008 CDP1802AC/3 TABLE 4. INSTRUCTION SUMMARY (See Notes 11 through 16) (Continued) MNEMONIC OP CODE INPUT 6 INP 6 6E BUS → M(R(X)); BUS → D; N LINES = 6 INPUT 7 INP 7 6F BUS → M(R(X)); BUS → D; N LINES = 7 INSTRUCTION OPERATION NOTES: (For Table 4) 11. The arithmetic operations and the shift instructions are the only instructions that can alter the DF. After an add instruction: DF = 1 denotes a carry has occurred DF = 0 Denotes a carry has not occurred After a subtract instruction: DF = 1 denotes no borrow. D is a true positive number DF = 0 denotes a borrow. D is two’s complement The syntax “-(not DF)” denotes the subtraction of the borrow. 12. This instruction is associated with more than one mnemonic. Each mnemonic is individually listed. 13. An idle instruction initiates a repeating S1 cycle. The processor will continue to idle until an I/O request (INTERRUPT, DMA-lN, or DMA- OUT) is activated. When the request is acknowledged, the idle cycle is terminated and the I/O request is serviced, and then normal operation is resumed. 14. Long-Branch, Long-Skip and No Op instructions require three cycles to complete (1 fetch + 2 execute). Long-Branch instructions are three bytes long. The first byte specifies the condition to be tested; and the second and third byte, the branching address. The long-branch instructions can: a. Branch unconditionally b. Test for D = 0 or D ≠ 0 c. Test for DF = 0 or DF = 1 d. Test for Q = 0 or Q = 1 e. Effect an unconditional no branch If the tested condition is met, then branching takes place; the branching address bytes are loaded in the high-and-low order bytes of the current program counter, respectively. This operation effects a branch to any memory location. If the tested condition is not met, the branching address bytes are skipped over, and the next instruction in sequence is fetched and executed. This operation is taken for the case of unconditional no branch (NLBR). 15. The short-branch instructions are two bytes long. The first byte specifies the condition to be tested, and the second specifies the branching address. The short branch instruction can: a. Branch unconditionally b. Test for D = 0 or D ≠ 0 c. Test for DF = 0 or DF = 1 d. Test for Q = 0 or Q = 1 e. Test the status (1 or 0) of the four EF flags f. Effect an unconditional no branch If the tested condition is met, then branching takes place; the branching address byte is loaded into the low-order byte position of the current program counter. This effects a branch within the current 256-byte page of the memory, i.e., the page which holds the branching address. If the tested condition is not met, the branching address byte is skipped over, and the next instruction in sequence is fetched and executed. This same action is taken in the case of unconditional no branch (NBR). 16. The skip instructions are one byte long. There is one Unconditional Short-Skip (SKP) and eight Long-Skip instructions. The Unconditional Short-Skip instruction takes 2 cycles to complete (1 fetch + 1 execute). Its action is to skip over the byte following it. Then the next instruction in sequence is fetched and executed. This SKP instruction is identical to the unconditional no-branch instruction (NBR) except that the skipped-over byte is not considered part of the program. The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute). They can: a. Skip unconditionally b. Test for D = 0 or D ≠ 0 c. Test for DF = 0 or DF = 1 d. Test for Q = 0 or Q = 1 e. Test for IE = 1 If the tested condition is met, then Long Skip takes place; the current program counter is incremented twice. Thus two bytes are skipped over, and the next instruction in sequence is fetched and executed. If the tested condition is not met, then no action is taken. Execution is continued by fetching the next instruction in sequence. 22 FN1441.3 October 17, 2008 CDP1802AC/3 TABLE 5. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES STATE I N S1 RESET Initialize, Not Programmer Accessible FETCH S0 S1 DATA BUS MEMORY ADDRESS MRD MWR N LINES NOTES 0 → I, N, Q, X, P; 1 → lE 00 XXXX 1 1 0 17 0000 → R 00 XXXX 1 1 0 18 MRP → l, N; RP + 1 → RP MRP RP 0 1 0 19 SYMBOL OPERATION 0 0 lDL IDLE MR0 RO 0 1 0 20, Fig. 6 0 1-F LDN MRN → D MRN RN 0 1 0 Fig. 6 1 0-F INC RN + 1 → RN Float RN 1 1 0 Fig. 4 2 0-F DEC RN - 1 → RN Float RN 1 1 0 Fig. 4 3 0-F Short Branch Taken: MRP → RP.0 Not Taken; RP + 1 → RP MRP RP 0 1 0 Fig. 6 4 0-F LDA MRN → D; RN + 1 → RN MRN RN 0 1 0 Fig. 6 5 0-F STR D → MRN D RN 1 0 0 Fig. 5 6 0 IRX RX + 1 → RX MRX RX 0 1 0 Fig. 5 6 1 OUT 1 MRX → BUS; RX + 1 → RX MRX RX 0 1 1 Fig. 9 2 OUT 2 2 Fig. 9 3 OUT 3 3 Fig. 9 4 OUT 4 4 Fig. 9 5 OUT 5 5 Fig. 9 6 OUT 6 6 Fig. 9 7 OUT 7 7 Fig. 9 9 INP 1 1 Fig. 8 A INP 2 2 Fig. 8 B INP 3 3 Fig. 8 C INP 4 4 Fig. 8 D INP5 5 Fig. 8 E INP6 6 Fig. 8 F INP7 7 Fig. 8 0 RET MRX → (X, P); RX + 1 → RX; 1 → lE MRX RX 0 1 0 Fig. 6 1 DlS MRX → (X, P); RX + 1 → RX; 0 → lE MRX RX 0 1 0 Fig. 6 2 LDXA MRX → D; RX + 1 → RX MRX RX 0 1 0 Fig. 6 3 STXD D → MRX; RX - 1 → RX D RX 1 0 0 Fig. 5 4 ADC MRX + D + DF → DF, D MRX RX 0 1 0 Fig. 6 5 SDB MRX - D - DFN → DF, D MRX RX 0 1 0 Fig. 6 6 SHRC LSB(D) → DF; DF → MSB(D) Float RX 1 1 0 Fig. 4 7 SMB D - MRX - DFN → DF, D MRX RX 0 1 0 Fig. 6 8 SAV T → MRX T RX 1 0 0 Fig. 5 7 23 BUS → MRX, D Data from I/O Device RX 1 0 FN1441.3 October 17, 2008 CDP1802AC/3 TABLE 5. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) DATA BUS MEMORY ADDRESS MRD MWR N LINES NOTES T R2 1 0 0 Fig. 5 0→Q Float RP 1 1 0 Fig. 4 SEQ 1→Q Float RP 1 1 0 Fig. 4 C ADCl MRP + D + DF → DF, D; RP + 1 MRP RP 0 1 0 Fig. 6 D SDBl MRP - D - DFN → DF, D; RP + 1 MRP RP 0 1 0 Fig. 6 E SHLC MSB(D) → DF; DF → LSB(D) Float RP 1 1 0 Fig. 4 F SMBl D - MRP - DFN → DF, D; RP + 1 MRP RP 0 1 0 Fig. 6 8 0-F GLO RN.0 → D RN.0 RN 1 1 0 Fig. 4 9 0-F GHl RN.1 → D RN.1 RN 1 1 0 Fig. 4 A 0-F PLO D → RN.0 D RN 1 1 0 Fig. 4 B 0-F PHI D → RN.1 D RN 1 1 0 Fig. 4 C 0 - 3, 8-B Long Branch MRP RP 0 1 0 Fig. 7 M(RP + 1) RP + 1 0 1 0 Fig. 7 STATE I N SYMBOL S1 7 9 MARK A REQ B S1#1 OPERATION (X, P) → T, MR2; P → X; R2 - 1 → R2 Taken: MRP → B; RP + 1 → RP Taken: B → RP.1; MRP → RP.0 #2 S1#1 Not Taken: RP + 1 → RP MRP RP 0 1 0 Fig. 7 #2 Not Taken: RP + 1 → RP M(RP + 1) RP + 1 0 1 0 Fig. 7 Taken: RP + 1 → RP MRP RP 0 1 0 Fig. 7 Taken: RP + 1 → RP M(RP + 1) RP + 1 0 1 0 Fig. 7 Not Taken: No Operation MRP RP 0 1 0 Fig. 7 Not Taken: No Operation MRP RP 0 1 0 Fig. 7 No Operation MRP RP 0 1 0 Fig. 7 No Operation MRP RP 0 1 0 Fig. 7 S1#1 #2 S1#1 #2 S1#1 5 6 7 C D E F Long Skip 4 NOP #2 S1 S1 D 0-F SEP N→P NN RN 1 1 0 Fig. 4 E 0-F SEX N→X NN RN 1 1 0 Fig. 4 F 0 LDX MRX → D MRX RX 0 1 0 Fig. 6 1 2 3 4 5 7 OR AND XOR ADD SD SM MRX OR D → D MRX AND D → D MRX XOR D → D MRX + D → DF, D MRX - D → DF, D D - MRX → DF, D MRX RX 0 1 0 Fig. 6 6 SHR LSB(D) → DF; 0 → MSB(D) Float RX 1 1 0 Fig. 4 24 FN1441.3 October 17, 2008 CDP1802AC/3 TABLE 5. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) DATA BUS MEMORY ADDRESS MRD MWR N LINES NOTES MRP RP 0 1 0 Fig. 6 MSB(D) → DF; 0 → LSB(D) Float RP 1 1 0 Fig. 4 DMA IN BUS → MR0; R0 + 1 → R0 Data from I/O Device R0 1 0 0 22, Fig. 10 DMAOUT MR0 → BUS; R0 + 1 → R0 MR0 R0 0 1 0 22, Fig. 11 STATE I N SYMBOL S1 F 8 LDl MRP → D; RP + 1 → RP 9 ORl MRP OR D → D; RP + 1 → RP A ANl MRP AND D → D; RP + 1 → RP B XRl MRP XOR D → D; RP + 1 → RP C ADl MRP + D → DF, D; RP + 1 → RP D SDl MRP - D → DF, D; RP + 1 → RP F SMl D - MRP → DF, D; RP +1 → RP E SHL S2 OPERATION S3 INTERRUPT X, P → T; 0 → lE, 1 → P; 2→X Float RN 1 1 0 Fig. 12 S1 LOAD IDLE (CLEAR, WAlT = 0) M(R0 - 1) R0 - 1 0 1 0 21, Fig. 6 NOTES: 17. lE = 1, TPA, TPB suppressed, state = S1. 18. BUS = 0 for entire cycle. 19. Next state always S1. 20. Wait for DMA or INTERRUPT. 21. Suppress TPA, wait for DMA. 22. IN REQUEST has priority over OUT REQUEST. 23. See “Timing Waveforms” beginning on page 7 and Figures 3 through 12 for “Machine Cyle Timing Waveforms beginning on page 9. Operating and Handling Considerations INPUT SIGNALS All inputs and outputs of Intersil CMOS devices have a network for electrostatic protection during handling. To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS. Input currents must not exceed 10mA even when the power supply is off. Operating UNUSED INPUTS OPERATING VOLTAGE A connection must be provided at every input terminal. All unused input terminals must be connected to either VDD or VSS, whichever is appropriate. Handling During operation near the maximum supply voltage limit care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply ripple, or ground noise; any of these conditions must not cause VDD - VSS to exceed the absolute maximum rating. 25 OUTPUT SHORT CIRCUITS Shorting of outputs to VDD or VSS may damage CMOS devices by exceeding the maximum device dissipation. FN1441.3 October 17, 2008 CDP1802AC/3 Burn-In Circuit VDD VDD NC VDD NC 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 NC VDD ALL RESISTORS ARE 47kΩ ±20% TYPE CDP1802AC VDD TEMPERATURE TIME 7V +125°C 160 Hours FIGURE 22. BIAS/STATIC BURN-IN CIRCUIT 26 FN1441.3 October 17, 2008 CDP1802AC/3 Ceramic Dual-In-Line Metal Seal Packages (SBDIP) D40.6 MIL-STD-1835 CDIP2-T40 (D-5, CONFIGURATION C) LEAD FINISH c1 -A- 40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE -DBASE METAL E b1 M (b) M -Bbbb S C A - B S (c) SECTION A-A D S D BASE PLANE Q S2 -C- SEATING PLANE A L S1 eA A A b2 b e eA/2 c aaa M C A - B S D S ccc M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. INCHES SYMBOL MIN MILLIMETERS MAX MIN MAX NOTES A - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 2.096 - 53.24 4 E 0.510 0.620 15.75 4 e 12.95 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.070 0.38 1.78 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N 40 40 8 Rev. 0 4/94 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 27 FN1441.3 October 17, 2008