Adjustable Output 1-/2-/3-Phase Synchronous Buck Controller ADP3182 FEATURES GENERAL DESCRIPTION Selectable 1-, 2-, or 3-phase operation at up to 1 MHz per phase ±2% worst-case differential sensing error over temperature Externally adjustable 0.8 V to >5 V output from a 12 V supply Logic-level PWM outputs for interface to external high power drivers Active current balancing between all output phases Built-in power good/crowbar functions Programmable short-circuit protection with programmable latch-off delay The ADP3182 is a highly efficient multiphase, synchronous, buck-switching regulator controller optimized for converting a 12 V main supply into a high current, low voltage supply for use in point-of-load (POL) applications. It uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 1-, 2-, or 3-phase operation, allowing for the construction of up to three complementary buckswitching stages. The ADP3182 also provides accurate and reliable short-circuit protection and adjustable current limiting. APPLICATIONS Auxiliary supplies DDR memory supplies Point-of-load modules ADP3182 is specified over the commercial temperature range of 0°C to +85°C and is available in a 20-lead QSOP package. FUNCTIONAL BLOCK DIAGRAM VCC 1 UVLO SHUTDOWN & BIAS EN 6 RAMPADJ RT 9 8 OSCILLATOR SET GND 14 CMP 950mV FB CURRENT BALANCING CIRCUIT CMP 20 PWM1 RESET 19 PWM2 2 / 3-PHASE DRIVER LOGIC 650mV CMP DELAY 18 PWM3 RESET CROWBAR PWRGD 5 EN RESET 1.05V CURRENT LIMIT FB ILIMIT 10 17 SW1 16 SW2 EN 15 SW3 DELAY 7 SOFT START 12 CSSUM CURRENT LIMIT CIRCUIT 11 CSREF 13 CSCOMP 3 FB COMP 4 2 FBRTN 04938-001 800mV REFERENCE ADP3182 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADP3182 TABLE OF CONTENTS Specifications..................................................................................... 3 Output Enable and UVLO ........................................................ 12 Test Circuits....................................................................................... 5 Applications..................................................................................... 14 Absolute Maximum Ratings............................................................ 6 Setting the Clock Frequency..................................................... 14 ESD Caution.................................................................................. 6 Soft Start and Current Limit Latch-Off Delay Time ............. 14 Pin Configuration and Function Description .............................. 7 Inductor Selection ...................................................................... 14 Typical Performance Characteristics ............................................. 8 Output Current Sense................................................................ 15 Theory of Operation ........................................................................ 9 Output Voltage............................................................................ 16 Start-Up Sequence........................................................................ 9 Power MOSFETs......................................................................... 16 Master Clock Frequency.............................................................. 9 Ramp Resistor Selection............................................................ 17 Output Voltage Differential Sensing .......................................... 9 Current Limit Setpoint .............................................................. 17 Output Current Sensing .............................................................. 9 Feedback Loop Compensation Design.................................... 17 Current Control Mode and Thermal Balance ........................ 10 Input Capacitor Selection and Input Current di/dt ............... 18 Voltage Control Mode................................................................ 10 Inductor DCR Temperature Correction ................................. 18 Soft Start ...................................................................................... 10 Layout and Component Placement ......................................... 19 Current Limit, Short-Circuit, and Latch-off Protection ....... 10 Outline Dimensions ....................................................................... 20 Power Good Monitoring ........................................................... 11 Ordering Guide .......................................................................... 20 Output Crowbar ......................................................................... 11 REVISION HISTORY 10/04—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADP3182 SPECIFICATIONS VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table 1. Parameter OSCILLATOR Frequency Range2 Frequency Variation Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range VOLTAGE ERROR AMPLIFIER Output Voltage Range2 Accuracy Line Regulation Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current CURRENT BALANCE CIRCUIT Common-Mode Range Input Resistance Input Current Input Current Matching CURRENT LIMIT COMPARATOR Output Voltage Normal Mode In Shutdown Mode Output Current, Normal Mode Maximum Output Current2 Current Limit Threshold Voltage Current Limit Setting Ratio DELAY Normal Mode Voltage DELAY Overcurrent Threshold Latch-Off Delay Time SOFT START Output Current, Soft Start Mode Soft Start Delay Time Symbol fOSC fPHASE VRT VRAMPADJ IRAMPADJ VCOMP VFB ∆VFB IFB IFBRTN IO(ERR) GBW(ERR) VOS(CSA) IBIAS(CSSUM) GBW(CSA) Conditions TA = 25°C, RT = 348 kΩ, 3-phase TA = 25°C, RT = 174 kΩ, 3-phase TA = 25°C, RT = 100 kΩ, 3-phase RT = 100 kΩ to GND RAMPADJ − FB Referenced to FBRTN VCC = 10 V to 14 V FB = 800 mV Min 0.25 155 1.9 −50 0 0.7 784 CCSCOMP = 10 pF CSSUM and CSREF 800 0.05 100 500 20 25 −5.5 −50 Max Unit 3 245 MHz kHz kHz kHz V mV µA 2.1 +50 100 3.1 816 V mV % +4 140 µA µA µA MHz V/µs +5.5 +50 mV nA MHz V/µs V V µA 10 10 0 0.05 ICSCOMP VSW(X)CM RSW(X) ISW(X) 200 400 600 2.0 −4 FB forced to VOUT − 3% COMP = FB CCOMP = 10 pF CSSUM − CSREF, Figure 2 Typ VCC − 2.5 VCC − 2.5 500 ∆ISW(X) SW(X) = 0 V SW(X) = 0 V SW(X) = 0 V VILIMIT(NM) VILIMIT(SD) IILIMIT(NM) EN > 2 V, RILIMIT = 250 kΩ EN < 0.8 V, IILIMIT = −100 µA EN > 2 V, RILIMIT = 250 kΩ −600 20 4 −7 30 7 2.9 3 VCSREF − VCSCOMP, RILIMIT = 250 kΩ VCL/IILIMIT VDELAY(NM) VDELAY(OC) tDELAY RDELAY = 250 kΩ RDELAY = 250 kΩ RDELAY = 250 kΩ, CDELAY = 12 nF 2.9 1.7 IDELAY(SS) tDELAY(SS) During start-up, DELAY < 2.4 V 15 Rev. 0 | Page 3 of 20 mV kΩ µA % 3.1 400 V mV 125 10.4 3 1.8 1.5 145 µA µA mV 20 500 25 12 60 105 VCL RDELAY = 250 kΩ, CDELAY = 12 nF +200 40 10 +7 3.1 1.9 mV/µA V V ms µA µs ADP3182 Parameter ENABLE INPUT Input Low Voltage Input High Voltage Input Current POWER GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Low Voltage Power Good Delay Time Crowbar Trip Point Crowbar Reset Point Crowbar Delay Time PWM OUTPUTS Output Low Voltage Output High Voltage SUPPLY DC Supply Current UVLO Threshold Voltage UVLO Hysteresis 1 2 Symbol Conditions VIL(EN) VIH(EN) IIN(EN) Min Typ 2.0 −1 VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) Relative to FBRTN Relative to FBRTN IPWRGD(SINK) = 4 mA 600 880 VCROWBAR 0.975 550 tCROWBAR Relative to FBRTN Relative to FBRTN Overvoltage to PWM going low VOL(PWM) VOH(PWM) IPWM(SINK) = −400 µA IPWM(SOURCE) = 400 µA VUVLO VCC rising Unit 0.8 V V µA +1 660 940 225 200 1.05 650 400 720 1000 400 1.1 750 mV mV mV ns V mV ns 160 5 500 4.0 mV V 6.5 0.7 5 6.9 0.9 10 7.3 1.1 mA V V All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not tested in production. Rev. 0 | Page 4 of 20 Max ADP3182 TEST CIRCUITS ADP3182 1 12V 13 39kΩ VCC CSCOMP 100nF 12 CSSUM 1kΩ CSREF 0.8V VOS = 14 CSCOMP –0.8V 40 GND Figure 2. Current Sense Amplifier VOS Rev. 0 | Page 5 of 20 04938-002 11 ADP3182 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC FBRTN EN, DELAY, ILIMIT, RT, PWM1 to PWM3, COMP SW1 to SW3 All Other Inputs and Outputs Storage Temperature Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (θJA) Lead Temperature Soldering (10 s) Infrared (15 s) Rating −0.3 V to +15 V −0.3 V to +0.3 V −0.3 V to 5.5 V −5 V to +25 V −0.3 V to VCC + 0.3 V −65°C to +150°C 0°C to 85°C 125°C 100°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND. 300°C 260°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 20 ADP3182 VCC 1 20 PWM1 FBRTN 2 19 PWM2 FB 3 18 PWM3 17 SW1 16 SW2 15 SW3 DELAY 7 14 GND COMP 4 PWRGD 5 EN 6 ADP3182 TOP VIEW (Not to Scale) RT 8 13 CSCOMP RAMPADJ 9 12 CSSUM ILIMIT 10 11 CSREF 04938-003 PIN CONFIGURATION AND FUNCTION DESCRIPTION Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 Mnemonic VCC FBRTN FB 4 5 COMP PWRGD 6 7 EN DELAY 8 RT 9 RAMPADJ 10 ILIMIT 11 CSREF 12 CSSUM 13 CSCOMP 14 15 to 17 GND SW3 to SW1 18 to 20 PWM3 to PMW1 Description Supply Voltage for the Device. Feedback Return. Voltage error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor divider between the output and FBRTN connected to this pin sets the output voltage point. This pin is also the reference point for the power good and crowbar comparators. Error Amplifier Output and Compensation Point. Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating range. Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Soft Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected between this pin and GND sets the soft start, ramp-up time and the overcurrent latch-off delay time. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Current Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current limit threshold of the converter. This pin is actively pulled low when the ADP3182’s EN input is low, or when VCC is below its UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low. Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier. This pin should be connected to the common point of the output inductors. Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determines the gain of the current sense amplifier. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3418. Connecting the PWM3 output to GND causes that phase to turn off, allowing the ADP3182 to operate as a 1- or 2-phase controller. Rev. 0 | Page 7 of 20 ADP3182 TYPICAL PERFORMANCE CHARACTERISTICS 5.4 3 SUPPLY CURRENT (mA) 5.3 2 1 5.2 5.1 5.0 4.9 0 0 50 100 150 200 250 RT VALUE (kΩ) 300 4.7 0 0.5 1.0 1.5 2.0 OSCILLATOR FREQUENCY (MHz) 2.5 Figure 5. Supply Current vs. Oscillator Frequency Figure 4. Master Clock Frequency vs. RT Rev. 0 | Page 8 of 20 3.0 04938-005 4.8 04938-004 MASTER CLOCK FREQUENCY (MHz) TA = 25ºC 3-PHASE OPERATION ADP3182 THEORY OF OPERATION The ADP3182 combines a multimode, fixed frequency PWM control with multiphase logic outputs for use in 1-, 2-, and 3-phase, synchronous, buck, point-of-load supply power converters. Multiphase operation is important for producing the high currents and low voltages demanded by auxiliary supplies in desktop computers, workstations, and servers. Handling the high currents in a single-phase converter would place high thermal demands on the components in the system, such as the inductors and MOSFETs. The multimode control of the ADP3182 ensures a stable, high performance topology for • Balancing currents and thermals between phases • High speed response at the lowest possible switching frequency and output decoupling • Minimizing thermal switching losses due to lower frequency operation • Tight regulation and accuracy • Reduced output ripple due to multiphase cancellation • PC board layout noise immunity • Ease of use and design due to independent component selection • Flexibility in operation for tailoring design to low cost or high performance cycle is possible. Also, more than one output can be on at the same time for overlapping phases. MASTER CLOCK FREQUENCY The clock frequency of the ADP3182 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 4. To determine the frequency per phase, the clock is divided by the number of phases in use. If PWM3 is grounded, then divide the master clock by 2 for the frequency of the remaining two phases. It is important to note that if only one phase is used, the clock will switch as if two phases were operating. This means that the oscillator frequency must be set at twice the expected value to program the desired PWM frequency. OUTPUT VOLTAGE DIFFERENTIAL SENSING START-UP SEQUENCE During start-up, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3182 operates as a 3-phase PWM controller. Grounding the PWM3 pin programs 1/2-phase operation. When the ADP3182 is enabled, the controller outputs a voltage on PWM3 that is approximately 675 mV. An internal comparator checks the pin’s voltage vs. a threshold of 300 mV. If the pin is grounded, it is below the threshold and the phase is disabled. The output resistance of the PWM pin is approximately 5 kΩ during this detection time. Any external pull-down resistance connected to the PWM pin should be more than 25 kΩ to ensure proper operation. PWM1 and PWM2 are disabled during the phase detection interval, which occurs during the first two clock cycles of the internal oscillator. After this time, if the PWM output is not grounded, the 5 kΩ resistance is removed, and the PWM output switches between 0 V and 5 V. If the PWM output is grounded, it remains off. The PWM outputs are logic-level devices intended for driving external gate drivers such as the ADP3418. Because each phase is monitored independently, operation approaching 100% duty The ADP3182 uses a differential-sensing, low offset voltage error amplifier. This maintains a worst-case specification of ±2% differential-sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB and FBRTN pins. FB should be connected through a resistor to the regulation point, usually the local bypass capacitor for the load. FBRTN should be connected directly to the remote sense ground point. The internal precision reference is referenced to FBRTN, which has a minimal current of 100 µA to allow accurate remote sensing. The internal error amplifier compares the output of the reference to the FB pin to regulate the output voltage. OUTPUT CURRENT SENSING The ADP3182 provides a dedicated current sense amplifier (CSA) to monitor the total output current for current limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the lowside MOSFET. This amplifier can be configured several ways depending on the objectives of the system: • Output inductor DCR sensing without a thermistor for lowest cost • Output inductor DCR sensing with a thermistor for improved accuracy for tracking inductor temperature • Sense resistors for highest accuracy measurements The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The Rev. 0 | Page 9 of 20 ADP3182 gain of the amplifier is programmable by adjusting the feedback resistor. The current information is then given as the difference of CSREF − CSCOMP. This difference in signal is used as a differential input for the current limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. In addition, the sensing gain is determined by external resistors so that the gain can be made extremely accurate. CURRENT CONTROL MODE AND THERMAL BALANCE The ADP3182 has individual inputs for each phase that are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system, which has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for the current limit described previously. SOFT START The power-on, ramp-up time of the output voltage is set with a capacitor and resistor in parallel from the DELAY pin to ground. The RC time constant also determines the current limit latchoff time as explained in the following section. In UVLO or when EN is logic low, the DELAY pin is held at ground. After the UVLO threshold is reached and EN is logic high, the DELAY capacitor is charged with an internal 20 µA current source. The output voltage follows the ramping voltage on the DELAY pin, limiting the inrush. The soft start time depends on the value of CDLY, with a secondary effect from RDLY. If either EN is taken low or VCC drops below UVLO, the DELAY capacitor is reset to ground to prepare for another soft start cycle. Figure 6 shows a typical soft start sequence for the ADP3182. To increase the current in any given phase, increase RSW for that phase (set RSW = 0 for the hottest phase and do not change it during balancing). Increasing RSW to only 500 Ω substantially increases the phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase. VOLTAGE CONTROL MODE A high gain-bandwidth voltage mode error amplifier is used for the voltage-mode control loop. The control input voltage to the positive input is derived from the internal 800 mV reference. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. 04938-006 The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed-forward control to compensate for changes in the supply voltage. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. External resistors can be placed in series with individual phases to create, if desired, an intentional current imbalance such as when one phase may have better cooling and can support higher currents. Resistors RSW1 through RSW3 (see the typical application circuit in Figure 9) can be used for adjusting thermal balance. Add placeholders for these resistors during the initial layout so that adjustments can be made after completing thermal characterization of the design. Figure 6. Typical Start-Up Waveforms Channel 1: CSREF, Channel 2: DELAY, Channel 3: PWRGD, Channel 4: COMP CURRENT LIMIT, SHORT-CIRCUIT, AND LATCH-OFF PROTECTION The ADP3182 compares a programmable current limit setpoint to the voltage from the output of the current sense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During normal operation, the voltage on ILIMIT is 3 V. The current through the external resistor is internally scaled to produce a current limit threshold of 10.4 mV/µA. If the difference in voltage between CSREF and CSCOMP rises above the current limit threshold, the internal current limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. The negative input (FB) is tied to the center point of a resistor divider from the output sense location. The main loop compensation is incorporated into the feedback network between FB and COMP. Rev. 0 | Page 10 of 20 ADP3182 After the limit is reached, the 3 V pull-up on the DELAY pin is disconnected, and the external delay capacitor is discharged through the external resistor. A comparator monitors the DELAY voltage and shuts off the controller when the voltage drops below 1.8 V. The current limit latch-off delay time is therefore set by the RC time constant discharging from 3 V to 1.8 V. Typical overcurrent latch-off waveforms are shown in Figure 7. 04938-007 Because the controller continues to cycle the phases during the latch-off delay time, the controller returns to normal operation if the short is removed before the 1.8 V threshold is reached. The recovery characteristic depends on the state of PWRGD. If the output voltage is within the PWRGD window, the controller resumes normal operation. However, if a short circuit has caused the output voltage to drop below the PWRGD threshold, a soft start cycle is initiated. Figure 7. Overcurrent Latch-Off Waveforms Channel 1: CSREF, Channel 2: COMP, Channel 3: Phase 1 Switch Node, Channel 4: DELAY The latch-off function can be reset by either removing and reapplying VCC to the ADP3182, or by pulling the EN pin low for a short time. To disable the short-circuit latch-off function, the external resistor to ground should be left open, and a highvalue (>1 MΩ) resistor should be connected from DELAY to VCC. This prevents the DELAY capacitor from discharging, so the 1.8 V threshold is never reached. The resistor has an impact on the soft start time because the current through it adds to the internal 20 µA current source. An inherent per phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage. POWER GOOD MONITORING The power good comparator monitors the output voltage via the FB pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified in the electrical table. PWRGD goes low if the output voltage is outside this specified range or the EN pin is pulled low. Figure 8 shows the PWRGD output response when the input power is removed from the regulator. 04938-008 During start-up when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit controls the internal COMP voltage to the PWM comparators to 2 V. This limits the voltage drop across the low-side MOSFETs through the current balance circuitry. Figure 8. Shutdown Waveforms Channel 1: CSREF, Channel 2: DELAY, Channel 3: PWRGD, Channel 4: COMP OUTPUT CROWBAR As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 650 mV. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action limits the current of the input supply or blows the fuse to protect the microprocessor from being destroyed. Rev. 0 | Page 11 of 20 ADP3182 OUTPUT ENABLE AND UVLO For the ADP3182 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold, and the EN pin must be higher than its logic threshold. If UVLO is less than the threshold or the EN pin is logic low, the ADP3182 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and holds the ILIMIT pin at ground. In the application circuit, the ILIMIT pin should be connected to the OD pins of the ADP3418 drivers. The ILIMIT being grounded disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs were not disabled, a negative voltage could be generated during output due to the high current discharge of the output capacitors through the inductors. Rev. 0 | Page 12 of 20 ADP3182 L1 1µH VIN 12V VIN RTN + C1 2700µF 16V + C5 4.7µF C2 2700µF D2 16V 1N4148WS C4 U2 ADP3418 100nF D1 1N4148WS 1 BST 2 IN Q1 NTD40N02 DRVH 8 L2 600nH/1.4mΩ SW 7 3 OD PGND 6 4 VCC DRVL 5 C6 4.7nF R1 2.2Ω C3 1µF Q2 NTD110N02 D3 1N4148WS 2 IN PGND 6 DRVL 5 C17 C21 VOUT 1.8V 55A VOUT RTN L3 600nH/1.4mΩ SW 7 4 VCC + 4.7µF × 10 6.3V MLCC Q3 NTD40N02 DRVH 8 3 OD + C9 4.7µF C8 U3 ADP3418 100nF 1 BST 1200µF/6.3V × 5 15mΩ ESR (EACH) C10 4.7nF C7 1µF R2 2.2Ω Q4 NTD110N02 C13 4.7µF D4 1N4148WS C12 U4 ADP3418 100nF 1 BST 2 IN Q5 NTD40N02 DRVH 8 L4 600nH/1.4mΩ SW 7 3 OD PGND 6 4 VCC DRVL 5 C14 4.7nF C11 1µF R3 2.2Ω Q6 NTD110N02 R4 10Ω C15 1µF + C16 33µF RB1 1.00kΩ RB2 1.24kΩ RA 6.04kΩ CFB 100pF CA 1.2nF POWER GOOD ENABLE RLIM 287kΩ RDLY 470kΩ 1 VCC PWM1 20 2 FBRTN PWM2 19 3 FB PWM3 18 4 COMP SW1 17 5 PWRGD SW2 16 6 EN SW3 15 7 DELAY GND 14 8 RT RT 258kΩ RSW1 * RSW2 * CSCOMP 13 9 RAMPADJ CSSUM 12 10 ILIMIT CSREF 11 RSW3 * RPH2 RCS 140kΩ 100kΩ RPH3 140kΩ RPH1 140kΩ CCS 5.6nF 04938-009 CDLY 39nF U1 ADP3182 RR 332kΩ Figure 9. 1.8 V, 55 A Application Circuit Rev. 0 | Page 13 of 20 ADP3182 APPLICATIONS The value for CDLY can be approximated using The design parameters for the typical high current point-ofload dc/dc buck converter shown in Figure 9 are as follows: • Input voltage (VIN) = 12 V • VID setting voltage (VOUT) = 1.8 V • Duty cycle (D) = 0.15 • Output current IO = 55 A • Maximum output current (ILIM) = 110 A • Number of phases (n) = 3 • Switching frequency per phase (fSW) = 250 kHz ⎛ VOUT CDLY = ⎜ 20 μA − ⎜ 2 × RDLY ⎝ Once CDLY is chosen, RDLY can be calculated for the current limit latch-off time using R DLY = The ADP3182 uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and the input and output capacitors. With n = 3 for three phases, a clock frequency of 750 kHz sets the switching frequency (fSW) of each phase to 250 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Equation 1 shows that to achieve a 750 kHz oscillator frequency, the correct value for RT is 256 kΩ. Alternatively, the value for RT can be calculated using 1 − 27 kΩ n × f SW × 4.7 pF RT = 1 − 27 kΩ = 256 kΩ 3 × 250 kHz × 4.7 pF (2) where: tSS is the desired soft start time. Assuming an RDLY of 390 kΩ and a desired soft start time of 3 ms, CDLY is 36 nF. The closest standard value for CDLY is 39 nF. SETTING THE CLOCK FREQUENCY RT = ⎞ t SS ⎟× ⎟ V OUT ⎠ (1) where 4.7 pF and 27 kΩ are internal IC component values. For good initial accuracy and frequency stability, a 1% resistor is recommended. The closest standard 1% value for this design is 258 kΩ. SOFT START AND CURRENT LIMIT LATCH-OFF DELAY TIME Because the soft start and current limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The first step is to set CDLY for the soft start ramp. This ramp is generated with a 20 µA internal current source. The value of RDLY has a second-order impact on the soft start time because it sinks part of the current source to ground. However, as long as RDLY is kept greater than 200 kΩ, this effect is minor. 1.96 × t DELAY C DLY (3) If the result for RDLY is less than 200 kΩ, a smaller soft start time should be considered by recalculating the equation for CDLY, or a longer latch-off time should be used. RDLY should never be less than 200 kΩ. In this example, a delay time of 9 ms results in RDLY = 452 kΩ. The closest standard 5% value is 470 kΩ. INDUCTOR SELECTION The amount of inductance determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs, but allows using smaller inductors and, for a specified peak- peak transient deviation, less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger inductors and more output capacitance for the same peak-peak transient deviation. In any multiphase converter, a practical value for the peak-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the inductance, oscillator frequency, and peak-peak ripple current in the inductor. Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage. IR = L≥ VOUT × (1 − D ) f SW × L VOUT × R x × (1 − (n × D )) f SW × VRIPPLE where: RX is ESR of output bulk capacitors. Rev. 0 | Page 14 of 20 (4) (5) ADP3182 Solving Equation 5 for a 20 mV p-p output ripple and an RX of 3 mΩ voltage yields L≥ 1.8 V × 3 mΩ × (1 − 3 × 0.15) 250 kHz × 20 mV = 594 nH If the resulting ripple voltage is too low, the level of inductance can be decreased until the desired ripple value is met. This allows optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 600 nH inductor is a good starting point that produces a calculated ripple current of 6.6 A. The inductor should not saturate at the peak current of 21.6 A and should be able to handle the sum of the power dissipation caused by the average current of 18.3 A in the winding and core loss. Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. A large DCR can cause excessive power losses, whereas too small a value can lead to increased measurement error. For this design, a DCR of 1.4 mΩ was chosen. Designing an Inductor Once the inductance and DCR are known, the next step is to either design an inductor or find a standard inductor that comes as close as possible to meeting the overall design goals. The first decision in designing the inductor is to choose the core material. Several possibilities for providing low core loss at high frequencies include the powder cores (e.g., Kool-Mµ® from Magnetics, Inc., or from Micrometals) and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided, especially when the inductor value is relatively low and the ripple current is high, due to their high core loss. The best choice for a core geometry is a closed-loop type such as a potentiometer core, a PQ, U, or E core, or a toroid core. A good compromise between price and performance is a core with a toroidal shape. Many useful references for magnetics design are available for quickly designing a power inductor, such as Selecting a Standard Inductor The following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request. • Coilcraft (847) 639-6400 www.coilcraft.com • Coiltronics (561) 752-5000 www.coiltronics.com • Sumida Electric Company (510) 668-0660 www.sumida.com • Vishay Intertechnology (402) 563-6866 www.vishay.com OUTPUT CURRENT SENSE The output current can be measured by summing the voltage across each inductor and passing the signal through a low-pass filter. The CS amplifier is configured with resistors RPH(X) (for summing the voltage), and RCS and CCS (for the low-pass filter). The output current IO is set by the following equations: IO = R PH ( x ) C CS ≥ RCS × VDRP RL (6) L R L × RCS (7) where: RL is the DCR of the output inductors. VDRP is the voltage drop from CSCOMP to CSREF. When load current reaches its limit, VDRP is at its maximum (VDRPMAX). VDRPMAX can be in the range of 100 to 200 mV. In this example, it is 110 mV. One has the flexibility of choosing either RCS or RPH(X). It is recommended to select RCS equal to 100 kΩ, and then solve for RPH(X) by rearranging Equation 6. • Magnetic Designer Software Intusoft (www.intusoft.com) R PH ( x ) = R L × RCS × • Designing Magnetic Components for High-Frequency DCDC Converters, by William T. McLyman, Kg Magnetics, Inc., ISBN 1883107008 R PH ( x ) = 1.4 mΩ × 100 kΩ × Rev. 0 | Page 15 of 20 I LIM VDRPMAX 110A = 140 kΩ 110 mV ADP3182 RDS(SF) (per MOSFET) < 7.5 mΩ. This RDS(SF) is also at a junction temperature of about 120°C, so one must account for this when making this selection. This example uses a lower-side MOSFET with 4.8 mΩ at 120°C. The closest standard 1% value for RPH(X) is 140 kΩ. Next, use Equation 7 to solve for CCS. C CS ≥ 600 nH 1.4 mΩ × 100 kΩ ≥ 4.29 nF Choose the closest standard value that is greater than the result given by Equation 7. This example uses a CCS value of 5.6 nF. OUTPUT VOLTAGE ADP3182 has an internal FBRTN voltage reference VREF of 800 mV. The output voltage can be set up using a voltage divider made up of resistors RB1 and RB2: VOUT = R B1 + R B 2 × VREF R B1 (8) Rearranging Equation 8 to solve for RB2 using the ADP3182 with an internal FB voltage of 800 mV and assuming a 1%, 1 kΩ resistor for RB1 yields ⎛ 1. 8 V ⎞ ⎞ ⎛V R B 2 = ⎜⎜ OUT − 1⎟⎟ × R B1 = ⎜ − 1⎟ × 1 kΩ = 1.25 kΩ ⎜ 0. 8 V ⎟ ⎠ ⎝ VREF ⎝ ⎠ The closest standard 1% resistor value for RB2 is 1.24 kΩ. POWER MOSFETS For this example, one high-side, N-channel power MOSFET and two low-side, N-channel power MOSFETs per phase have been selected. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3418) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With VGATE ~10 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are recommended. The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3182, currents are balanced between phases, thus the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and the average total output current (IO): ⎡⎛ I PSF = (1 − D ) × ⎢⎜⎜ O ⎢⎣⎝ nSF 2 ⎞ 1 ⎛ n IR ⎞ ⎟ + ⎜ ⎟ ⎟ 12 × ⎜ n ⎟ ⎠ ⎝ SF ⎠ 2 ⎤ ⎥ × RDS ( SF ) ⎥⎦ Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of feedback to input must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3418). The output impedance of the driver is approximately 2 Ω, and the typical MOSFET input gate resistances are about 1 Ω to 2 Ω; therefore, one should adhere to a total gate capacitance of less than 6000 pF. Because there are two MOSFETs in parallel, the input capacitance for each synchronous MOSFET should be limited to 3000 pF. The high-side (main) MOSFET must handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount of time for the main MOSFET to turn on and off, and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET: PS ( MF ) = 2 × f SW × nMF × RG × nMF × CISS n (10) where: nMF is the total number of main MOSFETs. RG is the total gate resistance (2 Ω for the ADP3418 and about 1 Ω for typical high speed switching MOSFETs, making RG = 3 Ω). CISS is the input capacitance of the main MOSFET. Note that adding more main MOSFETs (nMF) does not help the switching loss per MOSFET because the additional gate capacitance slows switching. The most efficient way to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the following equation: PC ( MF ) (9) Knowing the maximum output current and the maximum allowed power dissipation, one can determine the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an ambient temperature of 50°C, a safe limit for PSF is 1 W to 1.5 W at 120°C junction temperature. Therefore, for this example, VCC × I O ⎡⎛ I = D × ⎢⎜⎜ O ⎢⎣⎝ n MF 2 ⎞ 1 ⎛ n × IR ⎟ + ×⎜ ⎟ 12 ⎜⎝ n MF ⎠ ⎞ ⎟ ⎟ ⎠ 2 ⎤ ⎥ × R DS( MF ) ⎥⎦ (11) where: RDS(MF) is the on resistance of the MOSFET. Typically, for main MOSFETs, the highest speed (low CISS) device is preferred, but faster devices usually have higher on resistance. Select a device that meets the total power dissipation Rev. 0 | Page 16 of 20 ADP3182 The internal ramp voltage magnitude can be calculated by using (about 1.5 W for a single D-PAK) when combining the switching and conduction losses. For this example, an NTD40N03L was selected as the main MOSFET (three total; nMF = 3), with a CISS = 584 pF (max) and RDS(MF) = 19 mΩ (max at TJ = 120°C), and an NTD110N02L was selected as the synchronous MOSFET (three total; nSF = 3), with CISS = 2710 pF (max) and RDS(SF) = 4.8 mΩ (max at TJ = 120°C). The synchronous MOSFET CISS is less than 3000 pF, satisfying that requirement. Solving for the power dissipation per MOSFET at IO = 55 A and IR = 6.6 A yields 894 mW for each synchronous MOSFET and 1.16 W for each main MOSFET. These numbers comply with the guideline to limit the power dissipation to around 1 W per MOSFET. One last thing to consider is the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following equation: PDRV ⎤ ⎡ f = ⎢ SW × (nMF × QGMF + nSF × QGSF ) + ICC ⎥ × VCC n 2 × ⎦⎥ ⎣⎢ (12) where: QGMF is the total gate charge for each main MOSFET. QGSF is the total gate charge for each synchronous MOSFET. RAMP RESISTOR SELECTION The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. The following expression is used to determine the optimum value: AR × L 3 × A D × R DS(ON )( SF ) × C R (13) RR = 0.2 × 600 nH 3 × 5 × 4.8 mΩ × 5 pF = 333 kΩ where: AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain. RDS(ON)(SF) is the total low-side MOSFET on resistance. CR is the internal ramp capacitor value. The closest standard 1% resistor value is 332 kΩ. A R × (1 − D ) × VOUT R R × C R × f SW (14) VR = 0.2 × (1 − 0.15) × 1.8 V 332 kΩ × 5 pF × 250 kHz = 737 m V The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response improve, but thermal balance degrades. Likewise, if the ramp is made smaller, thermal balance improves but transient response and stability degrade. The factor of three in the denominator of Equation 13 sets a ramp size with optimal balance for good stability, transient response, and thermal balance. CURRENT LIMIT SETPOINT To select the current limit setpoint, first find the resistor value for RLIM. The current limit threshold for the ADP3182 is set with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/µA (ALIM). RLIM can be found using R LIM = Also shown is the standby dissipation factor (ICC × VCC) for the driver. For the ADP3418, the maximum dissipation should be less than 400 mW. In this example, with ICC = 7 mA, QGMF = 9 nC, and QGSF = 46 nC, there is 165 mW in each driver, which is below the 400 mW dissipation limit. See the ADP3418 data sheet for more details. RR = VR = A LIM × V LIM (15) V DRPMAX For values of RLIM greater than 500 kΩ, the current limit may be lower than expected and therefore necessitate some adjustment of RLIM. Here, ILIM is the average current limit for the output of the supply. In this example, using the VDRPMAX value of 110 mV from Equations 6 and 7 and choosing a peak current limit of 110 A for ILIM results in RLIM = 284 kΩ, for which 287 kΩ is chosen as the nearest 1% value. The limit of the per phase current limit described earlier is determined by I PHLIM ≅ VCOMP ( MAX ) − VR − V BIAS A D × R DS( MAX ) + IR 2 (16) FEEDBACK LOOP COMPENSATION DESIGN Optimized compensation of the ADP3182 allows the best possible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc. With the multimode feedback structure of the ADP3182, the feedback compensation must be set so that the converter’s output impedance, working in parallel with the output decoupling, will meet this goal. One will need to compensate for the several poles and zeros created by the output inductor and decoupling capacitors (output filter). Rev. 0 | Page 17 of 20 ADP3182 A type three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equations 20 to 22 are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects. C X × RX n× RX × V 4 × R B2 R × R L + A D × R DS VOUT RA = ⎛ L ×V A D × R DS 4 × R B2 R ×⎜ − ⎜ n×CX × RX R × VOUT 2 × f SW × R X ⎝ X C FB = 1 2 × n × f SW × R A (17) ⎞ ⎟ ⎟ ⎠ (18) (19) With the inductor’s DCR being used as the sense element and copper wire being the source of the DCR, one needs to compensate for temperature changes in the inductor’s winding if a highly accurate safety current limit setpoint is desired. Fortunately, copper has a well-known temperature coefficient (TC) of 0.39%/°C. If RCS is designed to have an opposite and equal percentage of change in resistance to that of the wire, it cancels the temperature variation of the inductor’s DCR. Due to the nonlinear nature of NTC thermistors, resistors RCS1 and RCS2 are needed. See Figure 10 for instructions on how to linearize the NTC and produce the desired temperature tracking. PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR OR LOW-SIDE MOSFET If CX is 6000 µF (five 1200 µF capacitors in parallel) with an equivalent ESR of 3 mΩ, the equations above give the following compensation values: CA = 1.33 nF RPH1 RCS1 CSCOMP CFB = 110 pF 18 CCS1 Using the nearest standard value for each of these components yields CA = 1.2 nF, RA = 6.04 kΩ, and CFB = 100 pF. CSSUM 17 INPUT CAPACITOR SELECTION AND INPUT CURRENT di/dt RPH3 CCS2 RCS2 KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES CSREF 16 In continuous inductor current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n × VOUT/VIN and an amplitude of one-nth the maximum output current. To prevent large voltage transients, a low ESR input capacitor, sized for the maximum rms current, must be used. The maximum rms capacitor current is given by Figure 10. Temperature Compensation Circuit Values The following procedures and expressions yield values to use for RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given RCS value. 1. Select an NTC based on type and value. Because we do not have a value yet, start with a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%. 2. Based on the type of NTC, find its relative resistance value at two temperatures. The temperatures that work well are 50°C and 90°C. These resistance values are called A (RTH(50°C)/RTH(25°C)) and B (RTH(90°C)/RTH(25°C)). Note that the NTC’s relative value is always 1 at 25°C. 3. Find the relative value of RCS required for each of these temperatures. This is based on the percentage of change needed, which in this example is initially 0.39%/°C. These are called r1 (1/(1 + TC × (T1 − 25))) and r2 (1/(1 + TC × (T2 − 25))), where TC = 0.0039 for copper. T1 = 50°C and T2 = 90°C are chosen. From this, one can calculate that r1 = 0.9112 and r2 = 0.7978. 4. Compute the relative values for RCS1, RCS2, and RTH using ( A − B ) × r1 × r2 − A × (1 − B ) × r2 + B × (1 − A ) × r1 (21) rCS2 = A × (1 − B ) × r1 − B × (1 − A ) × r2 − ( A − B ) 1 −1 N×D (20) I CRMS RPH2 TO VOUT SENSE ADP3182 RA = 6.05 kΩ I CRMS = D × I O × TO SWITCH NODES RTH 1 = 0.15 × 55 A × − 1 = 9 .1 A 3 × 0.15 Note that manufacturers often base capacitor ripple current rating on only 2,000 hours of life. Therefore, it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may be placed in parallel to meet size or height requirements in the design. In this example, the input capacitor bank is formed by two 2,700 µF, 16 V aluminum electrolytic capacitors and three 4.7 µF ceramic capacitors. To reduce the input current di/dt to a level below the recommended maximum of 0.1 A/µs, an additional small inductor (L > 370 nH @ 10 A) can be inserted between the converter and the supply bus. That inductor also acts as a filter between the converter and the primary power source. 04938-010 CA = INDUCTOR DCR TEMPERATURE CORRECTION Rev. 0 | Page 18 of 20 ADP3182 rCS1 = rTH = 5. 1 1 1 − 1 − rCS2 rCS1 (22) (23) Calculate RTH = rTH × RCS, then select the closest value of thermistor available. Also, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: k= 6. (1 − A) A 1 − 1 − rCS2 r1 − rCS2 RTH ( ACTUAL ) (24) RTH (CALCULATED) Calculate values for RCS1 and RCS2 using RCS1 = RCS × k × rCS1 (25) RCS2 = RCS × ((1 − k ) + (k × rCS2 )) (26) LAYOUT AND COMPONENT PLACEMENT The following guidelines are recommended for optimal performance of a switching regulator in a PC system. General Recommendations For good results, a PCB with at least four layers is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 mΩ at room temperature. When high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3182) must cross through power circuitry, a signal ground plane should be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making the signal ground a bit noisier. An analog ground plane should be used around and under the ADP3182 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground, but it should not be tied to any other power circuitry to prevent power currents from flowing in it. The components around the ADP3182 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB and CSSUM pins. The output capacitors should be connected as close as possible to the load or connector. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop, described in the following section. Power Circuitry Recommendations To minimize radiated switching noise energy (i.e., EMI) and conduction losses in the board, the switching power path should be routed on the PCB to encompass the shortest possible length. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power-converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. When a power-dissipating component, for example, a power MOSFET, is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias that extend to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. To optimize thermal dissipation, make a mirror image of the pads in use to heat sink the MOSFETs on the opposite side of the PCB. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers, extending fully under all the power components. Signal Circuitry Recommendations The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Therefore, the FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller. Rev. 0 | Page 19 of 20 ADP3182 OUTLINE DIMENSIONS 0.341 BSC 20 11 0.154 BSC 1 0.236 BSC 10 PIN 1 0.065 0.049 0.010 0.004 0.069 0.053 0.025 BSC 0.012 0.008 SEATING PLANE COPLANARITY 0.004 0.010 0.006 8° 0° 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137AD Figure 11. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in inches ORDERING GUIDE Model ADP3182JRQZ-RL1 1 Temperature Range 0°C to 85°C Package Description Shrink SOIC 13” Reel Z = Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04938–0–10/04(0) Rev. 0 | Page 20 of 20 Package Option RQ-20 Quantity per Reel 2500