ACTIVE-SEMI ACT8846 Advanced pmu for multi-core application processor Datasheet

ACT8846
Rev 7.0, 06-Dec-2017
Advanced PMU for Multi-core Application Processors
FEATURES
GENERAL DESCRIPTION
INTEGRATED POWER SUPPLIES
The ACT8846 is a complete, cost effective, and
highly-efficient ActivePMUTM power management
solution optimized for the power, voltage
sequencing and control requirements of Rockchip
RK31x8 application processor family.
 Four DC/DC Step-Down (Buck) Regulators
 2 x 2.8A, 2 x 1.5A
 Five Low-Noise LDOs
 2 x 150mA, 3 x 350mA
The ACT8846 features four fixed-frequency,
current-mode, synchronous PWM step-down
converters that achieve peak efficiencies of up to
97%. These regulators operate with a fixed
frequency of 2.25MHz, minimizing noise in sensitive
applications and allowing the use of small external
components. These buck regulators supply up to
2.8A of output current and can fully satisfy the
power and control requirements of the multi-core
application processor. Dynamic Voltage Scaling
(DVS) is supported either by dedicated control pins,
or through I2C interface to optimize the energy-pertask performance for the processor. This device
also include eight low-noise LDOs (up to 350mA
per LDO), one always-on LDO and an integrated
backup battery charger to provide a complete
power system for the processor.
 Three Low-Input Voltage LDOs
 1 x 150mA, 2 x 350mA
 One Low IQ Keep-Alive LDO
 Backup Battery Charger
SYSTEM CONTROL AND INTERFACE
 Four General Purpose I/O with PWM Drivers
 I2C Serial Interface
 Interrupt Controller
SYSTEM MANAGEMENT
 Reset Interface and Sequencing Controller
 Power on Reset
 Soft / Hard Reset
 Watchdog Supervision
 Multiple Sleep Modes
The power sequence and reset controller provides
power-on reset, SW-initiated reset, and power cycle
reset for the processor. It also features the
watchdog supervisory function. Multiple sleep
modes with autonomous sleep and wake-up
sequence control are supported.
 Thermal Management Subsystem
The
thermal
management
and
protection
subsystem allows the host processor to manage the
power dissipation of the PMU and the overall
system dynamically. The PMU provides a thermal
warning to the host processor when the
temperature reaches a certain threshold such that
the system can turn off some of the non-essential
functions, reduce the clock frequency and etc to
manage the system temperature.
APPLICATIONS





Tablet PC
Mobile Internet Devices (MID)
E-books
Personal Navigation Devices
The ACT8846 is available in a compact, Pb-Free
and RoHS-compliant TQFN66-48 package.
Smart Phones
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
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Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
FUNCTIONAL BLOCK DIAGRAM
VP1
REG1
SW1
To Battery
OUT1
FB1
GP14
ACT8846
VP2
To Battery
VIO
REG2
SW2
nRSTO
OUT2
OUT2
INL2
GP2
nPBIN
PUSH BUTTON
VP3
To Battery
VIO
nPBSTAT
SW3
REG3
OUT3
OUT3
VIO
GP3
nIRQ
VP4
To Battery
SW4
OUT4
REG4
PWRHLD
OUT4
PWREN
GP14
To Battery
System
Control
VSELR2
SCL
INL1
REG5
LDO
OUT5
REG6
LDO
OUT6
REG7
LDO
OUT7
OUT5
OUT6
SDA
OUT7
REFBP
Reference
INL2
REG8
LDO
OUT8
REG9
LDO
OUT9
To Battery
OUT8
GPIO1
GPIO2
GPIO3
OUT9
INL3
GPIO4
To Battery
GPIO5
GPIO6
REG10
LDO
OUT10
REG11
LDO
OUT11
REG12
LDO
OUT12
REG13
OUT13
RTC LDO
GA
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ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
OUT10
OUT11
OUT12
OUT13
EP
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Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
ORDERING INFORMATION
PART NUMBER
VOUT1
VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 VOUT13
ACT8846QM460-T
Adjustable 1.0V 1.0V
3.0V
1.0V
1.2V
1.8V
3.3V
3.3V
3.3V
1.8V
2.8V
1.8V
ACT8846QM468-T
Adjustable 1.0V 1.0V
3.0V
1.0V
1.2V
1.8V
3.3V
3.3V
3.3V
1.8V
2.8V
1.8V
ACT8846QM490-T
Adjustable 3.3V 1.1V
2.0V
3.3V
1.0V
3.3V
3.3V
3.3V
1.0V
1.8V
1.8V
1.8V
1.0V
3.0V
1.0V
1.2V
1.8V
3.3V
3.3V
3.3V
1.8V
2.8V
1.8V
ACT8846QM468-T15 Adjustable 1.0V
ACT8846QM106-T
1.2V
0.95V 3.3V
1.8V
1.8V
1.8V
3.3V
1.2V
2.8V
1.5V
2.8V
1.8V
OFF
ACT8846QM107-T
1.8V
0.9V 1.2V
3.0V
3.3V
1.8V
1.8V
3.3V
3.3V
3.3V
2.5V
3.3V
1.8V
PACKAGE
PINS
TEMPERATURE RANGE
TQFN66-48
48
-40°C to +85°C
: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means
semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
: Push button 10s shut down function is supported in ACT8846QM468-T and ACT8846QM490-T and ACT8846QM468-T15.
ACT8846QM_ _ _-T
Product Number
Package Code
Pin Count
Option Code
Tape and Reel
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ACT8846
Rev 7.0 06-Dec-2017
PIN CONFIGURATION
OUT13
GPIO4
OUT7
OUT6
INL1
OUT5
GPIO3
GPIO2
GPIO1
OUT3
VP3
VP3
TOP VIEW
SW3
GPIO5
SW3
GPIO6
GP3
nIRQ
OUT10
nRSTO
ACTIVE
8846QM
DATE CODE
OUT11
INL3
OUT12
VSELR2
PWRHLD
nPBIN
VP1
FB1
nPBSTAT
SW1
GP2
GP14
SW2
SW4
EP
SCL
SDA
OUT8
OUT4
GA
OUT9
INL2
REFBP
OUT2
PWREN
VP2
VP4
VP2
SW2
Thin - QFN (TQFN66-48)
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I2CTM is a trademark of NXP.
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ACT8846
Rev 7.0 06-Dec-2017
PIN DESCRIPTIONS
PIN
NAME
1, 2
SW3
Switch Node for REG3.
3
GP3
Power Ground for REG3. Connect GP14, GP2, GP3, and GA together at a single
point as close to the IC as possible.
4
OUT10
REG10 output. Bypass it to ground with a 2.2µF capacitor.
5
OUT11
REG11 output. Bypass it to ground with a 2.2µF capacitor.
6
INL3
7
OUT12
8
VSELR2
9
nPBSTAT
10
GP2
Power ground for REG2. Connect GP14, GP2, GP3, and GA together at a single
point as close to the IC as possible.
11, 12
SW2
Switch Node for REG2.
13, 14
VP2
Power input for REG2. Bypass to GP2 with a high quality ceramic capacitor placed as
close to the IC as possible.
15
OUT2
16
PWREN
Power Enable Input for REG3. PWREN is functional only when PWRHLD is driven
high. Drive PWREN to a logic high to turn on the REG3. Drive PWREN to a logic low
to turn off the REG3.
17
REFBP
Reference Bypass. Connect a 0.047μF ceramic capacitor from REFBP to GA. This
pin is discharged to GA in shutdown.
18
INL2
Power Input for REG8, REG9.
19
OUT9
REG9 output. Bypass it to ground with a 2.2µF capacitor.
20
GA
21
OUT4
Output voltage sense for REG4.
22
OUT8
REG8 output. Bypass it to ground with a 2.2µF capacitor.
23
SDA
Data Input for I2C Serial Interface. Data is read on the rising edge of SCL.
24
SCL
Clock Input for I2C Serial Interface.
25
VP4
Power input for REG4. Bypass to GP14 with a high quality ceramic capacitor placed
as close to the IC as possible.
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DESCRIPTION
Power input for REG10, REG11 and REG12.
REG12 output. Bypass it to ground with a 2.2µF capacitor.
Output Voltage Selection for REG2. Drive to logic low to select default output voltage.
Drive to logic high to select secondary output voltage.
Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low
whenever the nPBIN is pushed, and is high-Z otherwise.
Output Voltage Sense for REG2.
Analog Ground.
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
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Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
PIN DESCRIPTIONS CONT’D
PIN
NAME
DESCRIPTION
26
SW4
Switch Node for REG4.
27
GP14
Power Ground for REG1 and REG4. Connect GP14, GP2, GP3, and GA together at a
single point as close to the IC as possible.
28
SW1
Switch Node for REG1.
29
FB1
Output Feedback Sense for REG1. For the adjustable output voltage options, connect
this pin to the center of the output feedback resistor divider for voltage setting,
connect this pin to the output directly to regulate the output voltage at 1.2V.
30
VP1
Power Input for REG1. Bypass to GP14 with a high quality ceramic capacitor placed
as close to the IC as possible.
31
nPBIN
Master Enable Input. Drive nPBIN to GA through a 50kΩ resistor for 32ms to enable
the IC. Drive nPBIN to GA through a 50kΩ resistor for 10 seconds to disable the IC.
Drive nPBIN directly to GA to assert a Manual-Reset condition.
32
PWRHLD
33
nRSTO
34
nIRQ
35
GPIO6
General Purpose I/O #6. Configured as PWM LED driver output for up to 6mA current
with programmable frequency and duty cycle. See the PWM LED Drive section for
more information.
36
GPIO5
General Purpose I/O #5. Configured as PWM LED driver output for up to 6mA current
with programmable frequency and duty cycle. See the PWM LED Driver section for
more information.
37
OUT13
REG13 output. Bypass it to ground with a 0.47µF capacitor.
38
OUT7
REG7 output. Bypass it to ground with a 2.2µF capacitor.
39
GPIO4
General Purpose I/O #4. Configured as PWM LED driver output for up to 6mA current
with programmable frequency and duty cycle. See the PWM LED Driver section for
more information.
40
OUT6
REG6 output. Bypass it to ground with a 2.2µF capacitor.
41
INL1
Power Input for REG5, REG6, REG7.
42
OUT5
REG5 output. Bypass it to ground with a 2.2µF capacitor.
43
GPIO3
General Purpose I/O #3. Configured as PWM LED driver output for up to 6mA current
with programmable frequency and duty cycle. See the PWM LED Drier section for
more information.
44
GPIO2
General Purpose I/O #2. Configured as VSELR4 for Voltage Selection of REG4. Drive
to logic low to select default output voltage. Drive to logic high to select secondary
output voltage.
45
GPIO1
General Purpose I/O #1. Configured as VSELR3 for Voltage Selection of REG3. Drive
to logic low to select default output voltage. Drive to logic high to select secondary
output voltage.
46
OUT3
Output Voltage Sense for REG3.
47,48
VP3
Power input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as
close to the IC as possible.
EP
EP
Exposed Pad. Must be soldered to ground on PCB.
Power Hold Input, enable input for REG1, REG2, REG4, REG5, REG6, REG8 and
REG10. PWRHLD is internally pulled down to GA through a 900kΩ resistor.
Open-Drain Reset Output.
Open-Drain Interrupt Output.
: Only for ACT8846QM468.
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I2CTM is a trademark of NXP.
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Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
UNIT
-0.3 to 6
V
-0.3 to + 0.3
V
OUT5, OUT6, OUT7, OUT13 TO GA
-0.3 to INL1 + 0.3
V
OUT8, OUT9, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, VSELR2, nPBIN,
-0.3 to INL2 + 0.3
V
OUT10, OUT11, OUT12 to GA
-0.3 to INL3 + 0.3
V
Junction to Ambient Thermal Resistance
21
°C/W
Operating Ambient Temperature Range
-40 to 85
°C
Operating Junction Temperature
-40 to 125
°C
Storage Temperature
-55 to 150
°C
300
°C
INL1, INL2, INL3 to GA; VP1, SW1, FB1 to GP14; VP2, SW2, OUT2 to GP2; VP3,
SW3, OUT3 to GP3; VP4, SW4, OUT4 to GP14
GP14, GP2, GP3 to GA
Lead Temperature (Soldering, 10 sec)
: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
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Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VINL2 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
SCL, SDA Input Low
VINL2 = 3.1V to 5.5V, TA = -40ºC to 85ºC
SCL, SDA Input High
VINL2 = 3.1V to 5.5V, TA = -40ºC to 85ºC
TYP
MAX
UNIT
0.35
V
1.55
V
SDA Leakage Current
1
µA
SCL Leakage Current
1
µA
0.35
V
SDA Output Low
IOL = 5mA
SCL Clock Period, tSCL
1.5
µs
SDA Data Setup Time, tSU
100
ns
SDA Data Hold Time, tHD
300
ns
Start Setup Time, tST
For Start Condition
100
ns
Stop Setup Time, tSP
For Stop Condition
100
ns
Figure 1:
I2C Compatible Serial Bus Timing
tSCL
SCL
tST
tHD
tSU
tSP
SDA
Start
condition
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I2CTM is a trademark of NXP.
Stop
condition
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ACT8846
Rev 7.0 06-Dec-2017
GLOBAL REGISTER MAP
BITS
BLOCK ADDRESS
SYS
0x00
SYS
0x01
REG1
REG2
REG2
0x12
0x20
0x21
REG2
0x22
REG3
0x30
REG3
REG3
REG4
REG4
REG4
0x31
0x32
0x40
0x41
0x42
REG5
0x50
REG5
0x51
REG6
REG6
REG7
0x58
0x59
0x60
REG7
0x61
REG8
0x68
REG8
0x69
D7
NAME
D6
nBATLEVMSK nBATSTAT
D5
D4
D3
D2
D1
D0
VBATDAT
Reserved
BATLEV[3]
BATLEV[2]
BATLEV[1]
BATLEV[0]
DEFAULT
0
R
R
R
0
1
0
0
Reserved
NAME
nTMSK
TSTAT
Reserved
Reserved
Reserved
Reserved
Reserved
DEFAULT
0
R
0
0
0
0
0
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
PHASE
nFLTMSK
OK
DEFAULT
1
1
0
0
1
0
0
R
NAME
Reserved
Reserved
VSET0[5]
VSET0[4]
VSET0[3]
VSET0[2]
VSET0[1]
VSET0[0]
DEFAULT
0
0
0
1
0
0
0
0
NAME
Reserved
Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
DEFAULT
0
0
0
1
0
0
0
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
PHASE
nFLTMSK
OK
DEFAULT
1
1
0
0
1
0
0
R
VSET0[0]
NAME
Reserved
Reserved
VSET0[5]
VSET0[4]
VSET0[3]
VSET0[2]
VSET0[1]
DEFAULT
0
0
0
1
0
0
0
0
NAME
Reserved
Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
DEFAULT
0
0
0
1
0
0
0
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
PHASE
nFLTMSK
OK
DEFAULT
1
1
0
1
1
1
0
R
NAME
Reserved
Reserved
VSET0[5]
VSET0[4]
VSET0[3]
VSET0[2]
VSET0[1]
VSET0[0]
DEFAULT
0
0
1
1
0
1
1
0
NAME
Reserved
Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
DEFAULT
0
0
1
1
0
1
1
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
PHASE
nFLTMSK
OK
DEFAULT
1
1
0
0
1
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULT
0
1
0
1
0
0
0
0
OK
NAME
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
DEFAULT
1
1
0
0
1
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULT
0
1
0
1
1
0
0
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
DEFAULT
0
1
0
0
1
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULT
0
1
1
0
0
1
0
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
DEFAULT
0
1
0
0
1
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]

0
1
1
1
1
0
0
1
NAME
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
DEFAULT
0
1
0
0
1
1
0
R
DEFAULT
: Default values of ACT8846QM468-T.
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I2CTM is a trademark of NXP.
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ACT8846
Rev 7.0 06-Dec-2017
GLOBAL REGISTER MAP CONT’D
BITS
BLOCK ADDRESS
REG9
REG9
REG10
REG10
REG11
REG11
REG12
REG12
REG13
PB
PB
PB
PB
PB
0x70
0x71
0x80
0x81
0x90
0x91
0xA0
0xA1
0xB1
0xC0
0xC1
0xC2
0xC3
0xC5
GPIO6
0xE3
GPIO5
0xE4
GPIO3
0xF4
GPIO4
0xF5
NAME
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULT
0
1
1
1
1
0
0
1
NAME
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
DEFAULT
0
1
0
0
1
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULT
0
1
1
1
1
0
0
1
NAME
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
DEFAULT
0
1
0
0
1
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULT
0
1
1
0
0
1
0
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
DEFAULT
1
1
0
0
1
1
0
R
NAME
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
DEFAULT
0
1
1
1
0
1
0
0
NAME
ON
Reserved
Reserved
Reserved
Reserved
DIS
nFLTMSK
OK
DEFAULT
0
1
0
0
1
1
0
R
NAME
ON
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DEFAULT
1
0
0
0
0
0
0
0
NAME
PBAMSK
PBDMSK
Reserved
Reserved
Reserved
Reserved
WDSREN
WDPCEN
0
0
0
0
0
0
0
DEFAULT
NAME
INTADR [7] INTADR [6] INTADR [5] INTADR [4]
0
INTADR [3]
INTADR [2] INTADR [1] INTADR [0]
DEFAULT
R
R
R
R
R
R
R
R
NAME
PBASTAT
PBDSTAT
PBDAT
Reserved
Reserved
Reserved
Reserved
Reserved
DEFAULT
R
R
R
R
R
R
R
R
NAME
Reserved
Reserved
Reserved
OFFSYS
OFFSYSCLR
Reserved
Reserved
SIPC
DEFAULT
0
0
0
0
0
0
0
0
NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCSTAT
SRSTAT
DEFAULT
0
0
0
0
0
0
R
R
NAME
PWM6EN
FRE6[2]
FRE6[1]
FRE6[0]
DUTY6[3]
DUTY6[2]
DUTY6[1]
DUTY6[0]
DEFAULT
0
0
0
0
0
0
0
0
DUTY5[0]
NAME
PWM5EN
FRE5[2]
FRE5[1]
FRE5[0]
DUTY5[3]
DUTY5[2]
DUTY5[1]
DEFAULT
0
0
0
0
0
0
0
0
NAME
PWM3EN
FRE3[2]
FRE3[1]
FRE3[0]
DUTY3[3]
DUTY3[2]
DUTY3[1]
DUTY3[0]
DEFAULT
1
1
0
1
0
1
1
1
NAME
PWM4EN
FRE4[2]
FRE4[1]
FRE4[0]
DUTY4[3]
DUTY4[2]
DUTY4[1]
DUTY4[0]
DEFAULT
0
0
0
0
0
0
0
0
: Default values of ACT8846QM468-T.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 10 -
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Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
REGISTER AND BIT DESCRIPTIONS
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
Battery Voltage Level Interrupt Mask. Set this bit to 1 to unmask
the interrupt. See the Programmable Battery Voltage Monitor
section for more information
SYS
0x00
[7]
nBATLEVMSK
R/W
SYS
0x00
[6]
nBATSTAT
R
Battery Voltage Status. Value is 1 when BATLEV interrupt is
generated, value is 0 otherwise.
SYS
0x00
[5]
VBATDAT
R
Battery Voltage Monitor real time status. Value is 1 when VBAT <
BATLEV, value is 0 otherwise.
SYS
0x00
[4]
-
R/W
Reserved.
SYS
0x00
[3:0]
BATLEV
R/W
Battery Voltage Detect Threshold. Defines the BATLEV voltage
threshold. See the Programmable Battary Voltage Monitor
section for more information.
SYS
0x01
[7]
nTMSK
R/W
Thermal Interrupt Mask. Set this bit to 1 to unmask the interrupt.
SYS
0x01
[6]
TSTAT
R
Thermal Interrupt Status. Value is 1 when a thermal interrupt is
generated, value is 0 otherwise.
SYS
0x01
[5:0]
-
R/W
Reserved.
REG1
0x12
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG1
0x12
[6:3]
-
R
REG1
0x12
[2]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG1
0x12
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG1
0x12
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG2
0x20
[7:6]
-
R
Reserved.
REG2
0x20
[5:0]
VSET0
R/W
REG2
0x21
[7:6]
-
R
REG2
0x21
[5:0]
VSET1
R/W
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Programming section for more
information.
REG2
0x22
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG2
0x22
[6:3]
-
R
REG2
0x22
[2]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG2
0x22
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG2
0x22
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG3
0x30
[7:6]
-
R
Reserved.
REG3
0x30
[5:0]
VSET0
R/W
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven
low. See the Output Voltage Programming section for more
information
Reserved.
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven
low. See the Output Voltage Programming section for more
information
- 11 -
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Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
REG3
0x31
[7:6]
-
R
Reserved.
REG3
0x31
[5:0]
VSET1
R/W
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Programming section for more
information.
REG3
0x32
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG3
0x32
[6:3]
-
R
REG3
0x32
[2]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG3
0x32
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG3
0x32
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG4
0x40
[7:6]
-
R
Reserved.
REG4
0x40
[5:0]
VSET0
R/W
REG4
0x41
[7:6]
-
R
REG4
0x41
[5:0]
VSET1
R/W
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Programming section for more
information.
REG4
0x42
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG4
0x42
[6:3]
-
R
REG4
0x42
[2]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG4
0x42
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG4
0x42
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG5
0x50
[7:6]
-
R
Reserved.
REG5
0x50
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG5
0x51
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG5
0x51
[6:3]
-
R
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven
low. See the Output Voltage Programming section for more
information
Reserved.
Reserved.
Reserved.
REG5
0x51
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG5
0x51
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG5
0x51
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG6
0x58
[7:6]
-
R
Reserved.
REG6
0x58
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG6
0x59
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 12 -
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Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
REG6
0x59
[6:3]
NAME
ACCESS
-
R
DESCRIPTION
Reserved.
REG6
0x59
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG6
0x59
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG6
0x59
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG7
0x60
[7:6]
-
R
Reserved.
REG7
0x60
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG7
0x61
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG7
0x61
[6:3]
-
R
Reserved.
REG7
0x61
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG7
0x61
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG7
0x61
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG8
0x68
[7:6]
-
R
Reserved.
REG8
0x68
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG8
0x69
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG8
0x69
[6:3]
-
R
Reserved.
REG8
0x69
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG8
0x69
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG8
0x69
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG9
0x70
[7:6]
-
R
Reserved.
REG9
0x70
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG9
0x71
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG9
0x71
[6:3]
-
R
REG9
0x71
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG9
0x71
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG9
0x71
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG10
0x80
[7:6]
-
R
Reserved.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
Reserved.
- 13 -
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Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
REG10
0x80
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG10
0x81
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG10
0x81
[6:3]
-
R
REG10
0x81
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG10
0x81
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG10
0x81
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG11
0x90
[7:6]
-
R
Reserved.
REG11
0x90
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG11
0x91
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG11
0x91
[6:3]
-
R
Reserved.
Reserved.
REG11
0x91
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG11
0x91
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG11
0x91
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG12
0xA0
[7:6]
-
R
Reserved.
REG12
0xA0
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage Programming
section for more information.
REG12
0xA1
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG12
0xA1
[6:3]
-
R
REG12
0xA1
[2]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown. Set
bit to 1 to enable output voltage discharge in shutdown, clear bit
to 0 to disable this function.
REG12
0xA1
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG12
0xA1
[0]
OK
R
REG13
0xB1
[7]
ON
R/W
REG13
0xB1
[6:0]
-
R
PB
0xC0
7
nPBAMSK
R/W
nPBIN Assertion Interrupt Control. Set this bit to 1 to generate
an interrupt when nPBIN is asserted.
PB
0xC0
6
nPBDMSK
R/W
nPBIN De-assertion Interrupt Control. Set this bit to 1 to
generate an interrupt when nPBIN is de-asserted.
PB
0xC0
[5:2]
-
R
PB
0xC0
Innovative PowerTM
1
WDSREN
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
R/W
Reserved.
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
Reserved.
Reserved.
Watchdog Soft-Reset Enable. Set this bit to 1 to enable
watchdog function. When the watchdog timer expires, the PMU
commences a soft-reset routine. This bit is automatically reset to
0 when entering sleep mode.
- 14 -
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Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
PB
0xC0
[5:2]
-
R
Reserved.
PB
0xC0
1
WDSREN
R/W
Watchdog Soft-Reset Enable. Set this bit to 1 to enable
watchdog function. When the watchdog timer expires, the PMU
commences a soft-reset routine. This bit is automatically reset to
0 when entering sleep mode.
Watchdog Power-Cycle Enable. Set this bit to 1 to enable
watchdog function. When watchdog timer expires, the PMU
commence a power cycle. This bit is automatically reset to 0
when entering sleep mode.
PB
0xC0
0
WDPCEN
R/W
PB
0xC1
[7:0]
INTADR
R
Interrupt Address. It holds the address of the block that triggers
the interrupt. This byte defaults to 0xFF and is automatically set
to 0xFF after being read. Bit 7 is the MSB while Bit 0 is the LSB.
PB
0xC2
7
PBASTAT
R
nPBIN Assertion Interrupt Status. The value of this bit is 1 if the
nPBIN Assertion Interrupt is triggered.
PB
0xC2
6
PBDSTAT
R
nPBIN De-assertion Interrupt Status. The value of this bit is 1 if
the nPBIN De-assertion Interrupt is triggered.
PB
0xC2
5
PBASTAT
R
nPBIN Status bit. This bit contains the real-time status of the
nPBIN pin. The value of this bit is 1 if nPBIN is asserted, and is 0
if nPBIN is de-asserted.
PB
0xC2
[4:0]
-
R
Reserved.
PB
0xC3
[7:5]
-
R
Reserved.
PB
0xC3
[4]
OFFSYS
R/W
Global Off Control. Set OFFSYSCLR[ ] to 1 first, then set this bit
to 1 to turn off all outputs.
PB
0xC3
[3]
OFFSYSCLR
R/W
Global Off Control State Clear bit. Set bit to 1, then set OFFSYS
[ ] to 1 to turn off all outputs.
PB
0xC3
[2:1]
-
R
PB
0xC3
0
SIPC
R/W
PB
0xC5
[7:2]
-
R
PB
0xC5
1
PCSTAT
R/W
Power-cycle Flag. The value of this bit is 1 after a power cycle.
This bit is automatically cleared to 0 after read.
PB
0xC5
0
SRSTAT
R/W
Soft-reset Flag. The value of this bit is 1 after a soft-reset. This
bit is automatically cleared to 0 after read.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
Reserved.
Software Initiated Power Cycle. When this bit is set, the PMU
commences a power cycle after 8ms delay.
Reserved.
- 15 -
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Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
REGISTER AND BIT DESCRIPTIONS CONT’D
BLOCK ADDRESS BIT
NAME
ACCESS
DESCRIPTION
GPIO6
0xE3
[7]
PWM6EN
R/W
PWM Function Enable. Set 1 to enable PWM function of GPIO6.
GPIO6
0xE3
[6:4]
FRE6
R/W
PWM Frequency Selection Bits for GPIO6. See the Table 6 for
code to frequency cross.
GPIO6
0xE3
[3:0]
DUTY6
R/W
Duty Cycle Selection Bits for GPIO6. See the Table 7 for code to
duty cross.
GPIO5
0xE4
[7]
PWM5EN
R/W
PWM Function Enable. Set 1 to enable PWM function of GPIO5.
GPIO5
0xE4
[6:4]
FRE5
R/W
PWM Frequency Selection Bits for GPIO5. See the Table 6 for
code to frequency cross.
GPIO5
0xE4
[3:0]
DUTY5
R/W
Duty Cycle Selection Bits for GPIO5. See the Table 7 for code to
duty cross.
GPIO3
0xF4
[7]
PWM3EN
R/W
PWM Function Enable. Set 1 to enable PWM function of GPIO3.
GPIO3
0xF4
[6:4]
FRE3
R/W
PWM Frequency Selection Bits for GPIO3. See the Table 6 for
code to frequency cross.
GPIO3
0xF4
[3:0]
DUTY3
R/W
Duty Cycle Selection Bits for GPIO3. See the Table 7 for code to
duty cross.
GPIO4
0xF5
[7]
PWM4EN
R/W
PWM Function Enable. Set 1 to enable PWM function of GPIO4.
GPIO4
0xF5
[6:4]
FRE4
R/W
PWM Frequency Selection Bits for GPIO4. See the Table 6 for
code to frequency cross.
GPIO4
0xF5
[3:0]
DUTY4
R/W
Duty Cycle Selection Bits for GPIO4. See the Table 7 for code to
duty cross.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 16 -
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Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
SYSTEM CONTROL ELECTRICAL CHARACTERISTICS
(VINL2 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Input Voltage Range
MIN
TYP
3.0
5.5
V
3.0
V
VINL2 Rising, BATLEV[3:0]=0001
UVLO Hysteresis
VINL2 Hysteresis
200
Operating Supply Current
All Regulators Enabled but no load
0.6
1.2
mA
Shutdown Supply Current
All Regulators Disabled except REG13
10
20
µA
2.25
2.5
MHz
Logic High Input Voltage
2.0
2.8
UNIT
UVLO Threshold Voltage
Oscillator Frequency
2.6
MAX
1.4

V
Logic Low Input Voltage
Leakage Current
V[nIRQ] = V[nRSTO] = 4.2V
Low Level Output Voltage
nIRQ, nRSTO, ISINK = 5mA
nRSTO Delay
Thermal Shutdown Temperature
mV
Thermal Shutdown Hysteresis
V
1
µA
0.3
V
100
ms
160
°C
20
°C

Temperature rising
0.4
: PWRHLD, PWREN, VSELR2, GPIO1, GPIO2 are logic inputs.
: Typical value shown. Actual value may vary from (T-1ms) x 85% to T x 115%, where T = 100ms.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 17 -
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Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = VVP4 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
Operating Voltage Range
MIN
TYP
2.7
UVLO Threshold
Input Voltage Rising
UVLO Hysteresis
Input Voltage Falling
100
Standby Supply Current
VOUT = 103%, Regulator Enabled
72
Shutdown Current
VVP = 5.5V, Regulator Disabled
0
Output Voltage Accuracy
2.5
VOUT ≥ 1.0V, IOUT = 10mA
-1%
VOUT < 1.0V, IOUT = 10mA
-10
2.6
VNOM

MAX
UNIT
5.5
V
2.7
V
mV
100
µA
2
µA
1%
V
10
mV
Line Regulation
VVP = Max (VNOM +1V, 3.2V) to 5.5V
0.15
%/V
Load Regulation REG1/4
IOUT = 10mA to IMAX
1.70
%/A
Load Regulation REG2/3
IOUT = 10mA to IMAX
1.00
%/A
Power Good Threshold
VOUT Rising
93
%VNOM
Power Good Hysteresis
VOUT Falling
2
%VNOM
Switching Frequency

VOUT ≥ 20% of VNOM
2
VOUT = 0V
2.25
2.5
MHz
550
kHz
Soft-Start Period
400
µs
Minimum On-Time
75
ns
REG1 AND REG4
Maximum Output Current
1.5
Current Limit
1.8
A
2.2
2.7
A
PMOS On-Resistance
ISW = -100mA
0.11
Ω
NMOS On-Resistance
ISW = 100mA
0.08
Ω
SW Leakage Current
VVP = 5.5V, VSW = 0 or 5.5V
0
2
µA
Input Capacitor
4.7
µF
Output Capacitor
33
µF
Power Inductor
1.0
2.2
3.3
µH
REG2 AND REG3
Maximum Output Current
2.8
Current Limit
3.5
A
4.2
A
PMOS On-Resistance
ISW = -100mA
0.07
Ω
NMOS On-Resistance
ISW = 100mA
0.08
Ω
SW Leakage Current
VVP = 5.5V, VSW = 0 or 5.5V
0
2
µA
Input Capacitor
10
µF
Output Capacitor
44
µF
Power Inductor
0.5
1
2.2
µH
: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
: IMAX Maximum Output Current.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 18 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
LOW-NOISE LDO ELECTRICAL CHARACTERISTICS
(VINL1 = VINL2 = 3.6V, COUT5 = COUT6 = COUT7 = COUT8 = COUT9 = 2.2µF, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Operating Voltage Range
Output Voltage Accuracy
MIN
TYP
2.5
VOUT ≥ 1.0V, IOUT = 10mA
-1
VOUT < 1.0V, IOUT = 10mA
-10
VNOM

MAX
UNIT
5.5
V
1
%
10
mV
Line Regulation
VINL = Max (VOUT + 0.5V, 3.6V) to 5.5V
0.5
mV
Load Regulation
IOUT = 1mA to IMAX
0.1
V/A
f = 1kHz, IOUT = 20mA, VOUT = 1.2V
75
f = 10kHz, IOUT = 20mA, VOUT = 1.2V
65
Regulator Enabled
25
Regulator Disabled
0
Power Supply Rejection Ratio
Supply Current per Output
dB
2
µA
Soft-Start Period
VOUT = 3.0V
140
µs
Power Good Threshold
VOUT Rising
92
%
Power Good Hysteresis
VOUT Falling
3.5
%
Output Noise
IOUT = 20mA, f = 10Hz to 100kHz, VOUT =
1.2V
30
µVRMS
Discharge Resistance
LDO Disabled, DIS[ ] = 1
1.5
kΩ
LDO rated at 150mA (REG5 & REG6)
Dropout Voltage
IOUT = 80mA, VOUT > 3.1V
Maximum Output Current

Current Limit
140
280
150
VOUT = 95% of regulation voltage
mA
180
Recommend Output Capacitor
mV
mA
2.2
µF
LDO rated at 350mA (REG7, REG8 & REG9)
Dropout Voltage
IOUT = 160mA, VOUT > 3.1V
Maximum Output Current

Current Limit
VOUT = 95% of regulation voltage
140
280
mV
350
mA
400
mA
Recommend Output Capacitor
2.2
µF
: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
: IMAX Maximum Output Current.
: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage (for 3.1V output voltage or higher).
: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage.
Under heavy overload conditions the output current limit folds back by 50% (typ.)
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 19 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
LOW-INPUT VOLTAGE LDO ELECTRICAL CHARACTERISTICS
(VINL3 = 3.6V, COUT10 = COUT11 = COUT12 = 2.2µF, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Operating Voltage Range
Output Voltage Accuracy
MIN
TYP
1.7
VOUT ≥ 1.0V, IOUT = 10mA
-1
VOUT < 1.0V, IOUT = 10mA
-10
VNOM

MAX
UNIT
5.5
V
1
%
10
mV
Line Regulation
VINL = Max (VOUT + 0.5V, 3.6V) to 5.5V
0.5
mV
Load Regulation
IOUT = 1mA to IMAX
0.1
V/A
f = 1kHz, IOUT = 20mA, VOUT = 1.2V
50
f = 10kHz, IOUT = 20mA, VOUT = 1.2V
40
Regulator Enabled
22
Regulator Disabled
0
Power Supply Rejection Ratio
Supply Current per Output
dB
2
µA
Soft-Start Period
VOUT = 3.0V
100
µs
Power Good Threshold
VOUT Rising
92
%
Power Good Hysteresis
VOUT Falling
3.5
%
Output Noise
IOUT = 20mA, f = 10Hz to 100kHz, VOUT =
1.2V
30
µVRMS
Discharge Resistance
LDO Disabled, DIS[ ] = 1
1.5
kΩ
IOUT = 80mA, VOUT > 3.1V
100
LDO rated at 150mA (REG10)
Dropout Voltage
Maximum Output Current
Current Limit
VOUT = 95% of regulation voltage
200
mV
150
mA
180
mA
Recommend Output Capacitor
2.2
µF
LDO rated at 350mA (REG11 & REG12)
Dropout Voltage
IOUT = 160mA, VOUT > 3.1V
Maximum Output Current

Current Limit
100
350
VOUT = 95% of regulation voltage
mV
mA
400
Recommend Output Capacitor
200
mA
2.2
µF
: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
: IMAX Maximum Output Current.
: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage (for 3.1V output voltage or higher).
: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage.
Under heavy overload conditions the output current limit folds back by 50% (typ)
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 20 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
LOW-POWER(ALWAYS-ON) LDO ELECTRICAL CHARACTERISTICS
(VINL1 = 3.6V, COUT13 = 1µF, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5.5
V
REG13 — VNOM = 1.8V
Operating Voltage Range
2.5
Output Voltage Accuracy
-3
Line Regulation
VINL1 = Max (VOUT + 0.2V, 2.5V) to 5.5V
VNOM

3
13
Supply Current from VINL1
5
Maximum Output current
Recommend Output Capacitor
%
mV
µA
50
mA
0.47
µF
PWM LED DRIVER ELECTRICAL CHARACTERISTICS
(VINL2 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Output Current
100% Duty Cycle
Output Low Voltage
Feed in with 6mA
Leakage Current
Sinking from 5.5V source
PWM Frequency
FRE[2:0] = 000
PWM Duty Adjustment
DUTY[3:0] = 0000 to 1111
MIN
TYP
MAX
UNIT
6
10
16
mA
0.35
V
1
µA
0.25
6.26
Hz
100
%
: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 21 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C, unless otherwise specified.)
Frequency vs. Temperature
VREF vs. Temperature
2.340
Frequency (MHz)
VREF (V)
1.200
ACT8846-002
2.360
ACT8846-001
1.204
1.196
1.192
1.188
2.320
2.300
2.280
2.260
2.240
2.220
2.200
1.184
-40
-20
0
20
40
60
80
100
120
2.180
-40
140
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
Startup of VIN/OUT13
Startup of nPBIN/OUT5/nRSTO
ACT8846-004
ACT8846-003
CH1
CH1
CH2
CH2
CH3
CH1: VnPBIN, 2V/div
CH2: VOUT5, 500mV/div
CH3: VnRSTO, 1V/div
TIME: 20ms/div
CH1: VVIN, 2V/div
CH2: VOUT13, 1V/div
TIME: 500µs/div
Startup of OUT4/OUT5/OUT11/OUT3/
OUT1/OUT2
ACT8846-005
CH1
CH2
CH3
CH4
CH5
CH6
CH1: VOUT4, 2V/div
CH2: VOUT5, 1V/div
CH3: VOUT11, 2V/div
CH4: VOUT3, 1V/div
CH5: VOUT1, 1V/div
CH6: VOUT2, 1V/div
TIME: 2ms/div
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 22 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
Shutdown of PWRHLD/OUT3/OUT2/OUT1
Sleep of PWREN/OUT3
ACT8846-007
ACT8846-006
CH1
CH1
CH2
CH2
CH3
CH4
CH1: VPWRHLD, 2V/div
CH2: VOUT3, 1V/div
CH3: VOUT2, 1V/div
CH4: VOUT1, 1V/div
TIME: 1ms/div
CH1: VPWREN, 2V/div
CH2: VOUT3, 1VV/div
TIME: 1ms/div
Shutdown of PWRHLD/OUT4/OUT5/OUT11
nPBIN and nPBSTAT
ACT8846-009
ACT8846-008
CH1
CH1
CH2
CH2
CH3
CH4
CH1: VnPBIN, 2V/div
CH2: VnPBSTAT, 2V/div
TIME: 10ms/div
CH1: VPWRHLD, 2V/div
CH2: VOUT4, 2V/div
CH3: VOUT5, 1V/div
CH4: VOUT11, 2V/div
TIME: 1ms/div
Shutdown of PWRHOLD and nRSTO
ACT8846-010
CH1
CH2
CH1: VPWRHOLD, 2V/div
CH2: VnRSTO, 2V/div
TIME: 2ms/div
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 23 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG2 Efficiency vs. Output Current
REG1 Efficiency vs. Output Current
VIN = 3.6V
VIN = 5.0V
60
VIN = 5.0V
VIN = 4.0V
40
20
VIN = 4.0V
60
40
20
0
0
0
1
10
1000
100
0
10000
1
REG3 Efficiency vs. Output Current
1000
10000
VOUT = 1.1V
VIN = 3.6V
80
Efficiency (%)
VIN = 5.0V
100
ACT8846-014
VIN = 3.6V
80
Efficiency (%)
100
REG4 Efficiency vs. Output Current
ACT8846-013
VOUT = 1.1V
10
Output Current (mA)
Output Current (mA)
100
VIN = 3.6V
80
Efficiency (%)
Efficiency (%)
80
VOUT = 1.2V
ACT8846-012
VOUT = 1.2V
ACT8846-011
100
100
60
VIN = 4.0V
40
20
VIN = 5.0V
60
VIN = 4.0V
40
20
0
0
0
1
10
100
1000
10000
0
Output Current (mA)
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
1
10
100
1000
10000
Output Current (mA)
- 24 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG5 VOUT vs. IOUT
VOUT10 @ 150mA vs. Temperature
1.186
1.182
1.120
VOUT (V)
Dropout Voltage (V)
1.160
ACT8846-016
ACT8846-015
1.200
1.080
1.178
1.174
1.040
1.000
1.170
0
40
80
120
160
200
-40
-20
0
20
Output Current (mA)
60
80
100
120
140
Temperature (°C)
REG10 @ 10mA vs. Temperature
REG5/6 Dropout Voltage vs. IOUT
350
300
ACT8846-018
1.205
ACT8846-017
400
1.200
250
VOUT (V)
Dropout Voltage (mV)
40
200
150
100
1.195
1.190
1.185
50
1.180
0
0
50
100
150
200
250
-40
-20
0
20
Output Current (mA)
REG6 VOUT vs. IOUT
60
80
100
120
140
REG7/8/9 Dropout Voltage vs. IOUT
400
Dropout Voltage (mV)
1.160
ACT8846-020
ACT8846-019
1.200
Dropout Voltage (V)
40
Temperature (°C)
1.120
1.080
1.040
1.000
300
200
100
0
0
40
80
120
160
200
0
Output Current (mA)
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
50
100
150
200
250
300
350
400
Output Current (mA)
- 25 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG10 Dropout Voltage vs. IOUT
REG8 VOUT vs. IOUT
Dropout Voltage (mV)
Output Voltage (V)
1.860
1.820
1.780
1.740
ACT8846-022
250
ACT8846-021
1.900
200
150
100
50
0
1.700
0
50
100
150
200
250
300
0
350
50
Output Current (mA)
REG11 Dropout Voltage vs. IOUT
Dropout Voltage (mV)
200
150
100
50
ACT8846-024
ACT8846-023
Dropout Voltage (mV)
200
250
0
200
150
100
50
0
0
100
200
300
0
400
100
200
300
400
Output Current (mA)
Output Current (mA)
REG5 Output Voltage vs. Output Current
1.220
Output Voltage (V)
1.000
REG6 Output Voltage vs. Output Current
ACT8846-026
1.240
ACT8846-025
1.020
Output Voltage (V)
150
REG12 Dropout Voltage vs. IOUT
250
1.040
100
Output Current (mA)
0.980
0.960
0.940
0.920
1.200
1.180
1.160
1.140
1.120
0.900
1.100
0
40
80
120
160
0
200
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
80
120
160
200
Output Current (mA)
Output Current (mA)
Innovative PowerTM
40
- 26 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG7 Output Voltage vs. Output Current
REG8 Output Voltage vs. Output Current
1.800
3.320
Output Voltage (V)
Output Voltage (V)
1.820
ACT8846-028
3.340
ACT8846-027
1.840
1.780
1.760
1.740
1.720
3.300
3.280
3.260
3.240
3.220
1.700
0
50
100
150
200
250
300
3.200
0
350
50
100
Output Current (mA)
250
300
350
REG10 Output Voltage vs. Output Current
REG9 Output Voltage vs. Output Current
3.320
Output Voltage (V)
3.300
ACT8846-030
3.340
ACT8846-029
3.320
Output Voltage (V)
200
Output Current (mA)
3.340
3.280
3.260
3.240
3.300
3.280
3.260
3.240
3.220
3.220
3.200
3.200
0
50
100
150
200
250
300
0
350
40
120
160
200
REG12 Output Voltage vs. Output Current
REG11 Output Voltage vs. Output Current
1.800
2.820
Output Voltage (V)
1.820
ACT8846-032
2.840
ACT8846-031
1.840
1.780
1.760
1.740
2.800
2.780
2.760
2.740
2.720
1.720
1.700
0
80
Output Current (mA)
Output Current (mA)
Output Voltage (V)
150
2.700
50
100
150
200
250
300
0
350
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
100
150
200
250
300
350
Output Current (mA)
Output Current (mA)
Innovative PowerTM
50
- 27 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
SYSTEM CONTROL INFORMATION
Interfacing with the Rockchip RK31x8 processors
The ACT8846 is optimized for the Rockchip
RK31x8 processors, supporting both the power
domains as well as the signal interface. The
following paragraphs describe how to design
ACT8846 with the RK31x8 processors.
between these devices benefits by doing so, both
the ACT8846 pin names and the RK31x8
processors pin names are provided. When this is
done, the RK31x8 pin names are located after the
ACT8846 pin names, and are italicized and located
inside parentheses. For example, PWREN (GPIOX)
refers to the logic signal applied to the ACT8846's
PWREN input, identifying that it is driven from the
RK31x8's GPIOX output.
While the ACT8846 supports many possible
configurations for powering these processors, one
of the most common configurations is detailed in
this datasheet. In general, this document refers to
the ACT8846 pin names and functions. However, in
cases where the description of interconnections
Table 1:
ACT8846 and Rockchip RK31x8 Power Domains
ACT8846
REGULATOR
POWER DOMAIN
DEFAULT
MAX
POWER UP
VOLTAGE CURRENT
ORDER
ON/OFF @
SLEEP
TYPE
REG1
VCC_DDR
Adjustable
1.5A
5
ON
DC/DC Step Down
REG2
VDD_LOG
1.0V
2.8A
5
ON
DC/DC Step Down
REG3
VDD_ARM
1.0V
2.8A
4
OFF
DC/DC Step Down
REG4
VCC_IO
3.0V
1.5A
1
ON
DC/DC Step Down
REG5
VDD_10
1.0V
150mA
2
ON
Low-Noise LDO
REG6
VDD_JETTA1V2
1.2V
150mA
/
OFF
Low-Noise LDO
REG7
VCC18_CIF
1.8V
350mA
/
OFF
Low-Noise LDO
REG8
VCCA_33
3.3V
350mA
/
OFF
Low-Noise LDO
REG9
VCC_TP
3.3V
350mA
/
OFF
Low-Noise LDO
REG10
VCC_JETTA3V3
3.3V
150mA
/
OFF
Low Input-Voltage LDO
REG11
VCC18_IO
1.8V
350mA
3
ON
Low Input-Voltage LDO
REG12
VCC28_CIF
2.8V
350mA
/
OFF
Low Input-Voltage LDO
REG13
VDD_RTC
1.8V
50mA
0
ON
Always-ON LDO
Table 2:
ACT8846 and Rockchip RK31x8 Power Mode
Power Mode
ALL ON
SHUTDOWN
ALL OFF
Innovative PowerTM
Control State
Power Domain State
PWRHLD is asserted, PWREN is
All Regulators ON
asserted
PWRHLD is de-asserted, PWREN is REG13 is ON, all other regulade-asserted, VINL2 > 2.6V
tors are off.
PWRHLD is de-asserted, PWREN is
All regulators off.
de-asserted, VINL2 < 2.2V
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 28 -
Quiescent Current
0.6mA
10µA
5µA
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
Table 3:
ACT8846 and RK31x8 Signal Interface
ACT8846
DIRECTION
ROCKCHIP RK31X8
PWREN
GPIO6_B1
SCL
I2C1_SCL
SDA
I2C1_SDA
VSELR2
GPIO0_D7
GPIO1/VSELR3
GPIO0_D6
nRSTO
NPOR
nIRQ
GPIO6_A4
nPBSTAT
GPIO6_A2
PWRHLD
GPIO6_B0
Note: Typical connections shown, actual connections may vary.
WDSREN[ ] for properly shutdown sequence.
Control Signals
Enable Inputs
The ACT8846 features a variety of control inputs,
which are used to enable and disable outputs
depending upon the desired mode of operation.
PWRHLD is a logic inputs, while nPBIN is a unique,
multi-function input.
Long Press / Power-cycle:
If the Manual Reset button is asserted for more
than 4s/10s, ACT8846 commences a power
cycle routine in which case all regulators are turned
off and then turned back on. A status bit, PCSTAT[
], is set after the power cycle. The PCSTAT[ ] bit is
automatically cleared to 0 after read.
nPBIN Multi-Function Input
The ACT8846 features the nPBIN multi-function
pin, which combines system enable/disable control
with a hardware reset function. Select either of the
two pin functions by asserting this pin, either
through a direct connection to GA as Manual Reset
input, or through a 50kΩ resistor to GA for 32ms to
enable the IC, or through a 50kΩ resistor to GA for
10s to disable the IC, as shown in Figure 2.
Manual Reset Function
The second major function of the nPBIN input is to
provide a manual-reset input for the processor. To
manually-reset the processor, drive nPBIN directly
to GA through a low impedance (less than 2.5kΩ).
An internal timer detects the duration of the MR
event:
nPBSTAT Output
nPBSTAT is an open-drain output that reflects the
state of the nPBIN input; nPBSTAT is asserted low
whenever nPBIN is asserted, and is high-Z
otherwise. This output is typically used as an
interrupt signal to the processor, to initiate a
software-programmable routine such as operating
mode selection or to open a menu. Connect
nPBSTAT to an appropriate supply voltage through
a 10kΩ or greater resistor.
Figure 2:
nPBIN Input
INL2
Short Press / Soft-Reset:
50kΩ
If the Manual Reset button is asserted for less than
4s/10s, ACT8846 commences a soft-reset
operation where nRSTO immediately asserts low,
then remains asserted low until the nPBIN input is
de-asserted and the reset time-out period expires.
A status bit, SRSTAT[ ] , is set after a soft-reset
event. The SRSTAT[ ] bit is automatically cleared to
0 after read. After Short Press, set WDSREN[ ] to 1
about 1s after nRSTO de-assert then clear
nPBIN
Manual
Reset
Detect
PushButton
Detect
Manual
Reset
Push-Button
VIO
nPBSTAT
To CPU
ACT8846
: Only for ACT8846QM468 and ACT8846QM490-T.
: Soft-Reset function is disabled in ACT8846QM460 , ACT8846QM468 and ACT8846QM490.
: Only for ACT8846QM460.
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ACT8846
Rev 7.0 06-Dec-2017
nRSTO Output
nRSTO is an open-drain output which asserts low
upon startup or when manual reset is asserted via
the nPBIN input. When asserted on startup, nRSTO
remains low until reset time-out period expires.
When asserted due to manual-reset, nRSTO
immediately asserts low, then remains asserted low
until the nPBIN input is de-asserted and the reset
time-out period expires.
Connect a 10kΩ or greater pull-up resistor from
nRSTO to an appropriate voltage supply.
nIRQ Output
nIRQ is an open-drain output that asserts low any
time an interrupt is generated. Connect a 10kΩ or
greater pull-up resistor from nIRQ to an appropriate
voltage supply. nIRQ is typically used to drive the
interrupt input of the system processor.
Many of the ACT8846's functions support interruptgeneration as a result of various conditions. These
are typically masked by default, but may be
unmasked via the I2C interface. For more
information about the available fault conditions,
refer to the appropriate sections of this datasheet.
Push-Button Control
The ACT8846 is designed to initiate a system
enable sequence when the nPBIN multi-function
input is asserted for 32ms. Once this occurs, a
power-on sequence commences, as described
below. The power-on sequence must complete and
the microprocessor must take control (by asserting
PWRHLD) before nPBIN is de-asserted. If the
microprocessor is unable to complete its power-up
routine successfully before the user releases the
push-button, the ACT8846 automatically shuts the
system down. This provides protection against
accidental or momentary assertions of the pushbutton. If desired, longer “push-and-hold” times can
be implemented by simply adding an additional time
delay before asserting PWRHLD.
completed, the system remains enabled after the
push-button is released as long as PWRHLD is
asserted high. If the processor does not assert
PWRHLD before the user releases the push-button,
the boot-up sequence is terminated and all
regulators are disabled. This provides protection
against "false-enable", when the push-button is
accidentally depressed, and also ensures that the
system remains enabled only if the processor
successfully completes the boot-up sequence.
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. After system is turned on, the
processor may shut down the system by setting
OFFSYSCLR[ ] to 1 then setting OFFSYS[ ] to 1, or
by pulling PWRHLD to logic low. The user could
force shut down ACT8846 anytime by pressing the
power on push-button for 10 seconds even when
software crashes.
SLEEP Mode Sequence
The ACT8846 supports RK31x8 processor’s
SLEEP mode operation. Once a successful powerup routine has been completed, SLEEP mode may
be initiated through a variety of software-controlled
mechanisms.
SLEEP mode is typically initiated when the user
presses the push-button during normal operation.
Pressing the push-button asserts the nPBIN input,
which asserts the nPBSTAT output, which
interrupts the processor. In response to this
interrupt the processor should disable REG6,
REG7, REG8, REG9, REG10 and REG12 via I2C,
then de-assert PWREN(GPIO6_B1), disabling
REG3. PWRHLD should remain asserted during
SLEEP mode so that REG1, REG2, REG4, REG5,
and REG11 remain enabled.
The ACT8846 wakes up from SLEEP mode when
either the push-button and/or PWREN (GPIO6_B1)
is asserted. In either case, REG3 is enable which
allow the system to resume normal operation.
Control Sequences
The ACT8846 features a variety of control
sequences that are optimized for supporting system
enable and disable, as well as SLEEP mode of the
Rockchip RK31x8 processors.
Enabling/Disabling Sequence
A typical enable sequence is initiated whenever the
nPBIN is asserted low for 32ms via 50KΩ
resistance. The power control diagram is shown in
Figure 3. During the boot sequence, the
microprocessor must assert PWRHLD (GPIO6_B0)
to ensure that the system remains powered after
nPBIN is released. Once the power-up routine is
: Only for ACT8846QM468.
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ACT8846
Rev 7.0 06-Dec-2017
Watch-Dog Supervision
The ACT8846 features a watchdog supervisory
function. An internal watchdog timer of 4s is
unmasked by setting either WDSREN[ ] or
WDPCEN [ ] bit to one. Once enabled, the
watchdog timer is reset whenever there is I2C
activity for the PMU. In the case where the system
software stops responding and that there is no I2C
transactions for 4s, the watchdog timer expires. As
a result, the PMU either perform a soft-reset or
power cycle, depending on whether WDSREN [ ] or
WDPCEN [ ] is set.
ACT8846 supports software-initiated power cycle.
Once the SIPC[ ] bit is set, the PMU waits for 8ms
and then initiate a power cycle to restart the entire
system.
Software-Initiated Power Cycle
Figure 3:
ACT8846QM460 and ACT8846QM468 Power Control Sequence
Sleep/Wakeup
Sequence
Power on Sequence
Power off
Sequence
UVLO
Main Battery
OUT13
nPBIN
2ms
93% of VOUT4
OUT4
2ms
93% of VOUT5
OUT5
OUT11
2ms
93% of VOUT11
2ms
93% of VOUT3
OUT3
2ms
OUT1, OUT2
PWREN
100ms
nRSTO
PWRHLD
: Watch-Dog is not supported in ACT8846QM468 and ACT8846QM490-T .
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ACT8846
Rev 7.0 06-Dec-2017
Figure 3A:
ACT8846QM490 Power Control Sequence for RK3288
Power on Sequence
Power off
Sequence
UVLO
Main Battery
OUT13
nPBIN
2ms
93% of VOUT4
OUT4
1ms
93% of VOUT10
OUT10
OUT1
1ms
93% of VOUT1
1ms
93% of VOUT3
OUT3
1ms
93% of VOUT11
OUT11
1ms
93% of VOUT9
OUT9
1ms
93% of VOUT5
OUT2 OUT5
PWREN
100ms
nRSTO
PWRHLD
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ACT8846
Rev 7.0 06-Dec-2017
FUNCTIONAL DESCRIPTION
I2C Interface
Thermal Protection
The ACT8846 features an I2C interface that allows
advanced programming capability to enhance overall
system performance. To ensure compatibility with a
wide range of system processors, the I2C interface
supports clock speeds of up to 400kHz (“Fast-Mode”
operation) and uses standard I2C commands. I2C
write-byte commands are used to program the
ACT8846, and I2C read-byte commands are used to
read the ACT8846’s internal registers. The ACT8846
always operates as a slave device, and is addressed
using a 7-bit slave address followed by an eighth bit,
which indicates whether the transaction is a readoperation or a write-operation, [1011010x].
SDA is a bi-directional data line and SCL is a clock
input. The master device initiates a transaction by
issuing a START condition, defined by SDA
transitioning from high to low while SCL is high. Data
is transferred in 8-bit packets, beginning with the
MSB, and is clocked-in on the rising edge of SCL.
Each packet of data is followed by an “Acknowledge”
(ACK) bit, used to confirm that the data was
transmitted successfully.
2
For more information regarding the I C 2-wire serial
interface, go to the NXP website: http://www.nxp.com.
Housekeeping Functions
Programmable battery Voltage Monitor
The ACT8846 features a programmable batteryvoltage monitor, which monitors the voltage at INL2
(which should be connected directly to the battery)
and compares it to a programmable threshold
voltage. The VBATMON comparator is designed to
be immune to noise resulting from switching, load
transients, etc. The BATMON comparator is disable
by default; to enable it, set the BATLEV[3:0] register
to one of the value in Table 4. Note that there is a
200mV hysteresis between the rising and falling
threshold for the comparator. The VBATDAT [-] bit
reflects the output of the BATMON comparator. The
value of VBATDAT[ ] is 1 when VINL2 < BATLEV;
value is 0 otherwise.
The VBATMON comparator can generate an
interrupt when VINL2 is lower than BATLEV[ ] voltage.
The interrupt is masked by default by can be
unmasked by setting VBATMSK[ ] = 1.
BATLEV[3:0]
BATLEV Falling
Threshold
0000
2.5
0001
2.6
0010
2.7
0011
2.8
0100
2.9
0101
3.0
0110
3.1
0111
3.2
1000
3.3
1001
3.4
1010
3.5
1011
3.6
1100
3.7
1101
3.8
1110
3.9
1111
4.0
The ACT8846 integrates thermal shutdown
protection circuitry to prevent damage resulting
from excessive thermal stress, as may be
encountered under fault conditions.
Thermal Interrupt
If the thermal interrupt is unmasked (by setting
nTMSK[ ] to 1), ACT8846 can generate an interrupt
when the die temperature reaches 120°C (typ).
Thermal Protection
If the ACT8846 die temperature exceeds 160°C, the
thermal protection circuitry disables all regulators
and prevents the regulators from being enabled until
the IC temperature drops by 20°C (typ).
Table 4:
BATLEV Falling Threshold
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ACT8846
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STEP-DOWN DC/DC REGULATORS
General Description
REG1, REG2, REG3, and REG4 are fixed-frequency,
current-mode,
synchronous
PWM
step-down
converters that achieves peak efficiencies of up to
97%. These regulators operate with a fixed frequency
of 2.25MHz, minimizing noise in sensitive
applications and allowing the use of small external
components. Additionally, REG1, REG2, REG3, and
REG4 are available with a variety of standard and
custom output voltages, and may be softwarecontrolled via the I2C interface for systems that
require advanced power management functions.
100% Duty Cycle Operation
REG1, REG2, REG3, and REG4 are capable of
operating at up to 100% duty cycle. During 100%
duty cycle operation, the high-side power MOSFETs
are held on continuously, providing a direct
connection from the input to the output (through the
inductor), ensuring the lowest possible dropout
voltage in battery powered applications.
Operating Mode
By default, REG1, REG2, REG3, and REG4 operate
in fixed-frequency PWM mode at medium to heavy
loads, then transition to a proprietary power-saving
mode at light loads in order to save power.
Synchronous Rectification
REG1, REG2, REG3, and REG4 each feature
integrated synchronous rectifiers, maximizing
efficiency and minimizing the total solution size and
cost by eliminating the need for external rectifiers.
Soft-Start
REG1, REG2, REG3, and REG4 include internal 400
us soft-start ramps which limit the rate of change of
the output voltage, minimizing input inrush current
and ensuring that the output powers up in a
monotonic manner that is independent of loading on
the outputs. This circuitry is effective any time the
regulator is enabled, as well as after responding to a
short-circuit or other fault condition.
induced upon the voltage source. A 10μF ceramic
capacitor is recommended for each regulator in most
applications.
Output Capacitor Selection
REG1, REG2, REG3, and REG4 were designed to
take advantage of the benefits of ceramic capacitors,
namely small size and very-low ESR. REG1, REG2,
REG3 and REG4 are designed to operate with 33uF
or 44uF output capacitor over most of their output
voltage ranges, although more capacitance may be
desired depending on the duty cycle and load step
requirements.
Two of the most common dielectrics are Y5V and
X5R. Whereas Y5V dielectrics are inexpensive and
can provide high capacitance in small packages, their
capacitance varies greatly over their voltage and
temperature ranges and are not recommended for
DC/DC applications. X5R and X7R dielectrics are
more suitable for output capacitor applications, as
their characteristics are more stable over their
operating ranges, and are highly recommended.
Inductor Selection
REG1, REG2, REG3, and REG4 utilize current-mode
control and a proprietary internal compensation
scheme to simultaneously simplify external
component selection and optimize transient
performance over their full operating range. These
devices were optimized for operation with 2.2μH or
1μH inductors. Choose an inductor with a low DCresistance, and avoid inductor saturation by choosing
inductors with DC ratings that exceed the maximum
output current by at least 30%.
Configuration Options
Output Voltage Programming
Figure 4:
OUT1 Output Voltage Programming
Compensation
REG1, REG2, REG3, and REG4 utilize current-mode
control and a proprietary internal compensation
scheme to simultaneously simplify external
component selection and optimize transient
performance over their full operating range. No
compensation design is required; simply follow a few
simple guide lines described below when choosing
external components.
OUT1
ACT8846
CFF
RFB1
FB1
RFB2
Input Capacitor Selection
The input capacitor reduces peak currents and noise
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Figure 4 shows the feedback network necessary to
set the output voltage for REG1 when using the
adjustable output voltage option. Connect the FB1
pin to the output directly to regulate the output
voltage at 1.2V. Select components as follows: Set
RFB2 = 51kΩ, then
calculate RFB1 using the
following equation:
RFB1
V

 RFB 2  OUT 1  1 
V
 FB1

(1)
where VFB1 is 1.2V. Finally choose CFF using the
following equation:
CFF 
1  10 6
RFB1
(2)
By default, REG2, REG3 and REG4 power up and
regulate to their default output voltages. For REG2,
REG3 and REG4, the output voltage is selectable by
setting corresponding VSELR# pin that when
VSELR# is low, output voltage is programmed by
VSET0[ ] bits, and when VSELR# is high, output
voltage is programmed by VSET1[ ] bits. Also, once
the system is enabled, each regulator's output
voltage may be independently programmed to a
different value. Program the output voltages via the
I2C serial interface by writing to the regulator's
VSET0[ ] register if VSELR# is low or VSET1[ ]
register if VSELR# is high as shown in Table 5.
Enable / Disable Control
During normal operation, each buck may be enabled
or disabled via the I2C interface by writing to that
regulator's ON[ ] bit.
OK[ ] and Output Fault Interrupt
If a DC/DC's nFLTMSK[-] bit is set to 1, the ACT8846
will interrupt the processor if that DC/DC's output
voltage falls below the power-OK threshold. In this
case, nIRQ will assert low and remain asserted until
either the regulator is turned off or back in regulation,
and the OK[ ] bit has been read via I2C.
PCB Layout Considerations
High switching frequencies and large peak currents
make PC board layout an important part of step-down
DC/DC converter design. A good design minimizes
excessive EMI on the feedback paths and voltage
gradients in the ground plane, both of which can
result in instability or regulation errors.
Step-down DC/DCs exhibit discontinuous input
current, so the buck input capacitors must be placed
as close as possible to the IC. Connect the
capacitors directly to the corresponding VPx input pin
and Gx power ground pin. Avoid the use of vias. Best
performance is achieved by direct input capacitor
connection to the IC and by routing the SWx trace on
the top layer, directly under the input capacitor. The
inductor, input filter capacitor, and output filter
capacitor should be connected as close together as
possible, with short, direct, and wide traces. The
ground nodes for each regulator's power loop should
be connected at a single point in a star-ground
configuration, and this point should be connected to
the backside ground plane with multiple via. The
output node for each regulator should be connected
to its corresponding OUTx pin through the shortest
possible route, while keeping sufficient distance from
switching nodes to prevent noise injection. Finally,
the exposed pad should be directly connected to the
backside ground plane using multiple via to achieve
low electrical and thermal resistance.
Each DC/DC features a power-OK status bit that can
be read by the system microprocessor via the I2C
interface. If an output voltage is lower than the powerOK threshold, typically 7% below the programmed
regulation voltage, that regulator's OK[ ] bit will be 0.
Table 5:
REGx/VSET[ ] Output Voltage Setting
REGx/VSET[2:0]
REGx/VSET[5:3]
000
001
010
011
100
101
110
111
000
0.600
0.800
1.000
1.200
1.600
2.000
2.400
3.200
001
0.625
0.825
1.025
1.250
1.650
2.050
2.500
3.300
010
0.650
0.850
1.050
1.300
1.700
2.100
2.600
3.400
011
0.675
0.875
1.075
1.350
1.750
2.150
2.700
3.500
100
0.700
0.900
1.100
1.400
1.800
2.200
2.800
3.600
101
0.725
0.925
1.125
1.450
1.850
2.250
2.900
3.700
110
0.750
0.950
1.150
1.500
1.900
2.300
3.000
3.800
111
0.775
0.975
1.175
1.550
1.950
2.350
3.100
3.900
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ACT8846
Rev 7.0 06-Dec-2017
LOW-NOISE, LOW-DROPOUT LINEAR REGULATORS
General Description
ACT8846 features eight low-noise, low-dropout
linear regulators (LDOs) that supply up to 350mA.
Three of these LDOs (REG10, REG11, and
REG12) supports extended input voltage range
down to 1.7V. Each LDO has been optimized to
achieve low noise and high-PSRR.
Output Current Limit
Each LDO contains current-limit circuitry featuring a
current-limit fold-back function. During normal and
moderate overload conditions, the regulators can
support more than their rated output currents.
During extreme overload conditions, however, the
current limit is reduced by approximately 30%,
reducing power dissipation within the IC.
Compensation
The LDOs are internally compensated and require
very little design effort, simply select input and
output capacitors according to the guidelines below.
Input Capacitor Selection
Each LDO requires a small ceramic input capacitor
to supply current to support fast transients at the
input of the LDO. Bypassing each INL pin to GA
with 1μF. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
Output Capacitor Selection
Each LDO requires a small 2.2μF ceramic output
capacitor for stability . For best performance, each
output capacitor should be connected directly
between the output and GA pins, as close to the
output as possible, and with a short, direct
connection. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
Configuration Options
Output Voltage Programming
By default, each LDO powers up and regulates to
its default output voltage. Once the system is
enabled, each output voltage may be independently
programmed to a different value by writing to the
regulator's VSET[-] register via the I2C serial
interface as shown in Table 5.
Each of the LDOs features an optional output
discharge function, which discharges the output to
ground through a 1.5kΩ resistance when the LDO is
disabled. This feature may be enabled or disabled
by setting DIS[-]; set DIS[-] to 1 to enable this
function, clear DIS[-] to 0 to disable it.
OK[ ] and Output Fault Interrupt
Each LDO features a power-OK status bit that
be read by the system microprocessor via
interface. If an output voltage is lower than
power-OK threshold, typically 11% below
programmed regulation voltage, the value of
regulator's OK[-] bit will be 0.
can
the
the
the
that
If a LDO's nFLTMSK[-] bit is set to 1, the ACT8846
will interrupt the processor if that LDO's output
voltage falls below the power-OK threshold. In this
case, nIRQ will assert low and remain asserted until
either the regulator is turned off or back in
regulation, and the OK[-] bit has been read via I2C.
PCB Layout Considerations
The ACT8846’s LDOs provide good DC, AC, and
noise performance over a wide range of operating
conditions, and are relatively insensitive to layout
considerations. When designing a PCB, however,
careful layout is necessary to prevent other circuitry
from degrading LDO performance.
A good design places input and output capacitors
as close to the LDO inputs and output as possible,
and utilizes a star-ground configuration for all
regulators to prevent noise-coupling through
ground. Output traces should be routed to avoid
close proximity to noisy nodes, particularly the SW
nodes of the DC/DCs.
REFBP is a noise-filtered reference, and internally
has a direct connection to the linear regulator
controller. Any noise injected onto REFBP will
directly affect the outputs of the linear regulators,
and therefore special care should be taken to
ensure that no noise is injected to the outputs via
REFBP. As with the LDO output capacitors, the
REFBP bypass capacitor should be placed as close
to the IC as possible, with short, direct connections
to the star-ground. Avoid the use of via whenever
possible. Noisy nodes, such as from the DC/DCs,
should be routed as far away from REFBP as
possible.
Enable / Disable Control
During normal operation, each LDO may be
enabled or disabled via the I2C interface by writing
to that LDO's ON[ ] bit.
Output Discharge
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ALWAYS-ON LDO (REG13)
General Description
REG13 is an always-on, low-dropout linear
regulator (LDO) that is optimized for RTC and
backup-battery applications. REG13 features lowquiescent supply current, current-limit protection,
and reverse-current protection, and is ideally suited
for always-on power supply applications, such as
for a real-time clock, or as a backup-battery or
super-cap charger.
Reverse-Current Protection
REG13 features internal circuitry that limits the
reverse supply current to less than 1µA when the
input voltage falls below the output voltage, as can
be encountered in backup-battery charging
applications. REG13's internal circuitry monitors the
input and the output, and disconnects internal
circuitry and parasitic diodes when the input voltage
falls below the output voltage, greatly minimizing
backup battery discharge.
Typical Application
Voltage Regulators
REG13 is ideally suited for always-on voltageregulation applications, such as for real-time clock
and memory keep-alive applications. This regulator
requires only a small ceramic capacitor with a
minimum capacitance of 0.47μF for stability. For
best performance, the output capacitor should be
connected directly between the output and GA, with
a short and direct connection.
Figure 5:
Typical Application of RTC LDO
Backup Battery Charging
ACT8846
OUT13
RTC
Supper cap or
Back- up battery
REG13 features a constant current-limit, which
protects the IC under output short-circuit conditions
as well as provides a constant charge current, when
operating as a backup battery charger.
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ACT8846
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PWM LED DRIVERS
The GPIO3, the GPIO4, the GPIO5, and the GPIO6
are configured as PWM LED drivers, which could
support up to 6mA current with programmable
frequency and duty cycle. Set PWM#EN[ ] bit to “1”
to enable PWM function of GPIO#.
DUTY#[ ] PWM Frequency Setting
PWM Frequence Selection
Each LED driver may be independently
programmed to a different frequency by writing to
the GPIO’s FRE[2:0] register via the I2C serial
interface as shown in Table 6.
Table 6:
FRE#[ ] PWM Frequency Setting
FRE#[2:0]
PWM Frequency [Hz]
000
0.25
001
0.5
010
1
011
2
100
128
101
256
PWM Duty Cycle Selection
Each LED driver may be independently
programmed to a different duty cycle by writing to
the GPIO’s DUTY[3:0] register via the I2C serial
interface as shown in Table 7.
DUTY#[3:0]
PWM Duty Cycle [%]
0000
6.25
0001
12.5
0010
18.75
0011
25
0100
31.25
0101
37.5
0110
43.75
0111
50
1000
56.25
1001
62.5
1010
68.75
1011
75
1100
81.25
1101
87.5
1110
93.75
1111
100
Table 7:
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ACT8846
Rev 7.0 06-Dec-2017
CMI OPTIONS
CMI 106: ACT8846QM106
Rail
VSET0
Voltage
(V)
VSET1
Voltage (V)
Sequencing
Input Trigger
OUT1
1.2
1.2
OUT2
OUT2
0.95
0.95
Vin UVLO
OUT3
3.3
3.3
OUT1
OUT4
1.8
1.8
Vin UVLO
OUT5
1.8
n/a
Vin UVLO
OUT6
1.8
n/a
OUT1
OUT7
3.3
n/a
Vin UVLO
2
StartUp
Delay
(us)
SoftStart
(us)
2000
400
0
400
2000
400
0
400
0
140
2000
140
0
140
OUT8
1.2
n/a
IC
0
140
OUT9
2.8
n/a
I 2C
0
140
2
OUT10
1.5
n/a
IC
0
100
OUT11
2.8
n/a
I 2C
0
100
2
OUT12
1.8
n/a
IC
0
100
OUT13
1.8
n/a
I 2C
0
100
Hardware Configuration
PWRHLD and PWREN must be connected together in CMI 106.
Startup
The ACT8846QM106-T has two startup sequences. The first is pushbutton startup. Asserting nPBIN low
starts the startup sequence. nPBIN must stay low until after PWRHLD and PWREN are asserted high by
an external source, usually a uP. If nPBIN goes high before PWRHLD goes high, the IC shuts down all
outputs. The second startup sequence is with the PWREN and PWRHLD pins. After input power is applied, asserting PWREN high starts the startup sequence. Note that nPBIN should stay high in this appli-
CMI 106 Startup with PWRHLD
UVLO
VIN
PWRHLD and PWREN
nPBIN
OUT2/4/5/7
2ms
OUT1
2ms
40ms
OUT3/6
nRSTO
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 39 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
CMI 106: ACT8846QM106 continued.
CMI 106 Startup with nPBIN
UVLO
VIN
PWRHLD and PWREN
nPBIN
32ms
OUT2/4/5/7
2ms
OUT1
2ms
40ms
OUT3/6
nRSTO
Shutdown
The IC can be turned off by pulling nPBIN low through a 50kohm resistor to GA or by deasserting
PWREN and PWRHLD pins low. The IC can also be turned off via I2C.
PWREN
Asserting PWREN high enables the IC. In pushbutton applications, if PWREN is not asserted high before
the nPBIN pin goes high, the IC shuts down. Note that PWREN and PWRHLD must be connected together.
nPBIN
nPBIN retains the short and long press functionality described earlier in the datasheet.
NRSTO
nRSTO is gated by OUT6 and OUT7 and has a 40ms delay.
DVS
DVS functionality is only available via I2C.
VSELR/GPIO1/GPIO2
The VSELR/GPIO1/GPIO2 pins are not functional and should be permanently pulled high or low.
GPIO1/2/3/4/5/6
These outputs are off by default but can be enabled via I 2C. GPIO3 frequency and duty cycle are 256Hz
and 50%. GPIO4/5/6 frequency and duty cycle are 0.25Hz and 6.25%.
Watchdog
All watchdog functionality is disabled by default.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 40 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
CMI 107: ACT8846QM107
CMI107 is optimized to power the Cortex A7 processor.
Sequencing
Rail
VSET0
Voltage
(V)
VSET1
Voltage (V)
OUT1
1.8
1.8
OUT2
0.9
0.9
OUT3
1.2
1.2
OUT4
3.0
3.0
OUT5
3.3
n/a
Sequencing
Input Trigger
StartUp
Delay
(us)
SoftStart
(us)
OUT7
0
400
GPIO1
500
400
OUT11
500
400
I 2C
0
400
0
140
2
IC
2
OUT6
1.8
n/a
IC
0
140
OUT7
1.8
n/a
OUT2
500
140
OUT8
3.3
n/a
OUT3
500
140
OUT9
3.3
n/a
OUT8
1000
140
OUT10
3.3
n/a
OUT8
500
100
OUT11
2.5
n/a
OUT1
500
100
OUT12
3.3
n/a
I 2C
0
100
OUT13
1.8
n/a
Always On
0
100
Hardware Configuration
PWRHLD and PWREN must be connected together in CMI 107.
GPIO1 must be directly connected to OUT13 in CMI 107.
Startup
The ACT8846QM107-T has two startup sequences. The first is pushbutton startup. Asserting nPBIN low
starts the startup sequence. nPBIN must stay low until after PWRHLD and PWREN are asserted high by
an external source, usually a uP. If nPBIN goes high before PWRHLD goes high, the IC shuts down all
outputs. The second startup sequence is with the PWREN and PWRHLD pins. After input power is applied, asserting PWREN high starts the startup sequence. Note that nPBIN should stay high in this application. In both startup conditions, OUT4/5/6/12 are off by default, but can be enabled via I 2C
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 41 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
CMI 107: ACT8846QM107 continued
CMI 107 Startup with PWRHLD
VIN
PWRHLD and PWREN
nPBIN
OUT13 / GPIO1
0.5ms
OUT2
0.5ms
OUT7
OUT1
0.5ms
OUT11
0.5ms
OUT3
0.5ms
OUT8
1ms
OUT10
0.5ms
OUT9
40ms
nRSTO
Shutdown
The IC can be turned off by pulling nPBIN low through a 50kohm resistor to GA or by deasserting PWREN
and PWRHLD pins low. The IC can also be turned off via I2C.
PWREN
Asserting PWREN high enables the IC. In pushbutton applications, if PWREN is not asserted high before
the nPBIN pin goes high, the IC shuts down. Note that PWREN and PWRHLD must be connected together.
nPBIN
nPBIN retains the short and long press functionality described earlier in the datasheet.
NRSTO
nRSTO is gated by OUT9 and has a 40ms delay.
DVS
DVS functionality is only available via I2C.
VSELR/GPIO1/GPIO2
The VSELR/GPIO1/GPIO2 pins are not functional and should be permanently pulled high or low.
GPIO1/2/3/4/5/6
These outputs are off by default but can be enabled via I 2C. GPIO3 frequency and duty cycle are 256Hz
and 50%. GPIO4/5/6 frequency and duty cycle are 0.25Hz and 6.25%.
Watchdog
All watchdog functionality is disabled by default.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 42 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
ERRATA INFO
Errata Name:
ACT8846 creates I2C BUS contention.
Description:
ACT8846 incorrectly detects its I2C slave
address and pulls SDA low to acknowledge the
address. This occurs under several conditions.
1. The IC is on a multi-slave I2C bus and the
other slaves use multi-byte read or write
commands, and the read/write data contains a
string of bits that match the ACT8846 I2C
address.
2. The host addresses a device with a 10 bit I2C
address that contains a string of bits that match
the ACT8846 I2C address.
Work Around:
This issue has several work arounds.
1. Do not put I2C devices that use multi-byte
read or write commands on the ACT8846 I2C
bus.
2. Disable the ACT8846 I2C communication after
power up and before using any multi-byte read
or write commands. This allows the user to do a
one-time reconfiguration of the ACT8846 after
power up. Disabling ACT8846 I2C
communication reconfigures SDA and SCL highimpedance digital inputs. Because the specific
commands to disable the I2C bus are CMI
specific, please contact the factory for specific
instructions.
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 43 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.
ACT8846
Rev 7.0 06-Dec-2017
TQFN66-48 PACKAGE OUTLINE AND DIMENSIONS
D
D/2
SYMBOL
A
A1
E/2
E
DIMENSION IN
MILLIMETERS
DIMENSION IN
INCHES
MIN
MAX
MIN
MAX
0.700
0.800
0.032
0.036
0.200 REF
0.008 REF
A2
0.000
0.050
0.000
0.002
b
0.150
0.250
0.006
0.010
D
6.00
0.24
E
6.00
0.24
D2
4.15
4.40
0.166
0.176
E2
4.15
4.40
0.166
0.176
e
L
R
0.400 BSC
0.300
0.500
0.300
0.016 BSC
0.012
0.020
0.012
A
A1
A2
D2
b
L
e
E2
R
Innovative PowerTM
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
- 44 -
www.active-semi.com
Copyright © 2016-2017 Active-Semi, Inc.