ON LC898123F40XC Optical image stabilization (ois) / auto focus (af) controller & driver Datasheet

LC898123F40XC
Optical Image Stabilization (OIS) /
Auto Focus (AF) Controller & Driver
with 40kB Flash Memory
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1. Overview
LC898123F40XC is a system solution integrating an ultra-low-power
32-bit DSP, Flash Memory, and analog peripherals for OIS (Optical Image
Stabilization) /AF (Auto Focus) control, H-bridge, and linear drivers.
Available in a tiny 3.22mm x 2.30mm chipscale package, this device’s
40kB Flash memory enables high level commands and user data for greater
system flexibility.
2. Features
WLCSP35, 3.22x2.3
 On-chip ultra-low-power 32-bit DSP


 Motor Driver

Built-in software digital servo filter
Built-in software Gyro filter
 Flash Memory


40 KByte Flash memory to store data and DSP
software

 Peripherals









Built-in Hall op amp with internal 5, 10, 13,
20, 40, and 60 adjustable gain
4-channel, 14-bit A/D converter for Hall input
3-channel, 3-bit D/A converter for Hall offset
setting
3-channel, 8-bit D/A converter for Hall bias
setting
Built-in 1-MHz 2-wire serial interface with clock
stretch function
Digital Gyro interface for various types of gyro
(SPI Bus)
Built-in 41-MHz oscillator
Built-in LDO (Low Drop-Out regulator)
 Power supply voltage




 Package




OIS
2-channel constant current linear driver
(Ifull = 200 mA)
2-channel H-bridge PWM driver
(Iomax = 220 mA)
OP-AF (unidirection)
1-channel constant current linear driver
(Ifull = 150 mA)
OP-AF (bidirection)
1-channel constant current linear driver
(Ifull = 150 mA)
CL-AF
1-channel constant current linear driver
(Ifull = 150 mA)
1-channel H-bridge PWM driver
(Iomax 150 mA)
WLP35 (35-bump chipscale)
3.22 mm  2.30 mm , 0.45 mm thick
0.4 mm bump pitch
Pb-Free and Halogen Free
AD/DA/VGA/LDO/OSC:
AVDD30 = 2.6 to 3.3 V
Digital I/O (except Gyro I/F):
AVDD30 = 2.6 to 3.3 V
Driver:
VM = Constant current: 1.75 to 3.3 V
H Bridge PWM: 2.6 to 3.3 V
Core Logic / Gyro interface I/O generated by
internal LDO:
DVDD15 = 1.55 V output (typ)
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
August 2016 - Rev. 1
1
Publication Order Number :
LC898123F40XC/D
LC898123F40XC
3. Block Diagram
LPDSP32
DAC
Work RAM: DMA0
Program ROM
HLXBO
Work RAM: DMA1
FLASH
Work RAM: DMB
HLYBO
FLASH I/F
HLAFBO
SCL
SCL
SDA
SDA
I2C
(master)
SCL
WPB
SDA
EIRQ1
I2C
(slave)
SCL
SDA
SCL2
(TXD)
UART
RXD
I2C
(slave)
Hall
X
OPINPX
OPINMX
DAC Ctrl
SDA2
(RXD)
TXD
Hall
Y
OPINPY
HOST
CPU
(master)
Timer
OPINMY
DGSSB
Port
SPI
(master/slave)
(D-Gyro I/F)
DGSCLK
DGDATA
Digital
Gyro
(slave)
DGDIN
Hall
AF
OPINPAF
OPINMAF
OUT1
OUT2
OUT3
PWM/Current
Linear Ctrl
ADC Ctrl
H-Bridge
Driver
OUT4
OUT5
OUT6
ADC
MON1
AIN0
VM
PGND
System Ctrl
AIN1
AIN2
MON2
AIN3
PLL
EXCLK
POR
OSC/PLL
AVDD30
AVSS
Clock Divider
LDO
LDOPO(DVDD15
)
DVSS
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2
LC898123F40XC
4. Application Diagram
Camera Module
Lens
Hall
Sensor
Position
OIS / AF
Actuator
VCM
LC898123F40XC
EEPROM
I2C
SPI
Digital
Gyro
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3
Image
Sensor
AP / ISP
LC898123F40XC
5. Package Dimensions
unit : mm
WLCSP35, 3.22x2.3
CASE 567LJ
ISSUE O
E
A B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
PIN A1
REFERENCE
DIM
A
A1
b
D
E
e
D
MILLIMETERS
MIN
MAX
0.45
0.03
0.13
0.15
0.25
3.22 BSC
2.30 BSC
0.40 BSC
0.10 C
2X
0.10 C
2X
TOP VIEW
A
0.10 C
A1
0.08 C
C
SIDE VIEW
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
A1
e
35X
b
0.05 C A B
0.03 C
PACKAGE
OUTLINE
G
F
e
E
0.40
PITCH
D
35X
C
0.20
B
0.40
PITCH
A
DIMENSIONS: MILLIMETERS
1
2
3
4
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
5
BOTTOM VIEW
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4
LC898123F40XC
6. Pin Assign
OUT4
OUT3
OUT2
OUT1
VM
MON1
SDA2
(RXD)
WPB
PGND
OUT6
MON2
SCL2
(TXD)
DVSS
EXCLK
OUT5
DVDD15
EIRQ1
AVSS
SDA
SCL
AVDD30
HLAFBO
AVSS
HLYBO
HLXBO
DGDATA
DGSSB
OPINMAF
OPINMY
OPINMX
DGSCLK
DGDIN
OPINPAF
OPINPY
OPINPX
1
2
3
4
5
G
F
E
D
C
B
A
BOTTOM VIEW
Driver output
Analog VDD
Driver VDD
Analog GND
Driver GND
Digital GND
Logic Core VDD (Output)
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5
LC898123F40XC
7. Pin Descriptions
Pin
Num
Pin
I/O
Atr
I/O
Pwr (V)
Primary Function
(just after Reset)
Digital Gyro I/F Clock Input
Digital Gyro I/F Clock Output
A1
DGSCLK
B
1.55
A2
DGDIN
B
1.55
Digital Gyro Data Input (4 Wired)
A3
A4
A5
OPINPAF
OPINPY
OPINPX
I
I
I
2.8
2.8
2.8
AF Hall Opamp Input Plus
OIS Hall Y Opamp Input Plus
OIS Hall X Opamp Input Plus
B1
DGDATA
B
1.55
GPIO Input
B2
DGSSB
B
1.55
B3
B4
B5
C1
C2
C3
C4
C5
D1
OPINMAF
OPINMY
OPINMX
AVDD30
HLAFBO
AVSS
HLYBO
HLXBO
DVDD15
I
I
I
P
O
P
O
O
P
2.8
2.8
2.8

2.8
2.8
2.8
-
D2
EIRQ1
B
2.8
Digital Gyro I/F Chip Select Input
Digital Gyro I/F Chip Select Output
AF Hall OpAmp Input Minus
OIS Hall Y Opamp Input Minus
OIS Hall X Opamp Input Minus
Analog Power (2.6 to 3.3 V)
AF Hall Bias Output
Analog GND
OIS Hall Y Bias Output
OIS Hall X Bias Output
Internal LDO Power Output
External IRQ1
External Clock Input
D3
D4
D5
AVSS
SDA
SCL
P
B
B

2.8
2.8
Analog GND
I2C Data
I2C Clock
E1
MON2
B
2.8
(Debugger Data Input)
E2
SCL2
(TXD)
B
2.8
I2C Clock for 2nd I2C
E3
DVSS
P

E4
EXCLK
B
2.8
E5
OUT5
O
2.8
Logic GND
External Clock Input
External IRQ1
AF Driver Output (H-Bridge, Linear)
F1
MON1
B
2.8
(Debugger Data Output)
F2
SDA2
(RXD)
B
2.8
I2C Data for 2nd I2C
F3
F4
F5
G1
G2
G3
G4
G5
WPB
PGND
OUT6
OUT4
OUT3
OUT2
OUT1
VM
I
P
O
O
O
O
O
P
2.8

2.8
2.8
2.8
2.8
2.8

Write Protect for Flash
Driver GND
AF Driver Output (H-Bridge, Linear)
OIS Driver Output
OIS Driver Output
OIS Driver Output
OIS Driver Output
Driver Power (2.6 to 3.3 V)
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Sub Functions
Digital Gyro Clock Output
Internal Signal Monitor
I2C Data I/O for DAC Monitor
Internal Signal Monitor



Digital Gyro I/F Data Output (4 Wired)
Digital Gyro I/F Data I/O (3 Wired)
Internal Signal Monitor
Digital Gyro I/F Chip Select Output
Internal Signal Monitor









I2C Data I/O for DAC Monitor
UART Data Output (TXD)
SPI I/F Chip Select Output
Internal Signal Monitor
Servo Monitor Analog Input



I2C Data I/O for DAC Monitor
UART Data Input (RXD)
Servo Monitor Analog Out
Internal Signal Monitor
I2C Data I/O for DAC Monitor
UART Data Output
Internal Signal Monitor

I2C Data I/O for DAC Monitor
Internal Signal Monitor

I2C Data I/O for DAC Monitor
UART Data Output (TXD)
Servo Monitor Analog Out
Internal Signal Monitor
I2C Data I/O for DAC Monitor
UART Data Input
Internal Signal Monitor








Init
Z
Z



Z
Z









D

Z
Z
Z
Z

D

L
Z
D







LC898123F40XC
8. Electrical Characteristics
Absolute Maximum Rating at AVSS = 0 V, DVSS = 0 V, PGND = 0 V
Parameter
Symbol
VAD30 max
VM max
Ta  25C
Ta  25C
0.3 to +4.6
0.3 to +4.6
VAI30
Ta  25C
0.3 to VAI30+0.3
V
(DGDATA, DGSSB, DGSCLK, DGDIN)
VLDO18
Ta = 30 to +85C
0.3 to +1.872
V
Storage temperature
Operating temperature
Tstg
Topr
Output continuous current
Iomax
Power supply voltage
Input voltage
(Except
DGDATA, DGSSB, DGSCLK, DGDIN)
Input voltage
Conditions
Ratings
55 to +125
30 to +85
210
157.5
OUT1 to 4
OUT5, OUT6
Unit
V
V
C
C
mA
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Allowable Operating Ratings at Ta = 30 to +85C, AVSS = 0 V, DVSS = 0 V, PGND = 0 V
3.0V Power Supply (AVDD30)
Parameter
Power supply voltage
Input voltage range
Symbol
VAD30
VIN
Min
2.6
0
Typ
2.8
Symbol
Min
2.6
1.75
0
Typ
2.8
2.8

Max
3.3
VAD30
Unit
V
V
Max
3.3
3.3
VM30
Unit
V
V
V
3.0V Power Supply (VM)
Parameter
Power supply voltage (H-Bridge PWM)
Power supply voltage (Constant current)
Input voltage range
VM30
VINM

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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LC898123F40XC
DC Characteristics : Input/Output level at AVSS = 0 V, DVSS = 0 V, PGND = 0 V,VDD = 2.6 to 3.6 V, Ta = 30 to +85C
Parameter
High-level input
voltage
Low-level input
voltage
High-level input
voltage
Low-level input
voltage
High-level input
voltage
Low-level input
voltage
High-level input
voltage
Low-level input
voltage
High-level input
voltage
Low-level input
voltage
Symbol
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
Conditions
Min
Typ
Max
1.36
CMOS
schmitt
V
0.39
1.26
CMOS
schmitt
Unit
V
V
0.35
Applicable Pin
SCL2(TXD), SDA2(RXD),
EXCLK
DGDIN, DGSSB,
DGSCLK, DGDATA
1.40
CMOS
schmitt
SCL, SDA
0.40
V
1.48
CMOS
schmitt
EIRQ1, WPB
0.37
1.40
CMOS
supported
MON1, MON2
0.51
AVDD30
0.4
V
1.32
V
High-level output
voltage
VOH
IOH = 2 mA
High-level output
voltage
VOH
IOH = 0.1 mA
Low-level output
voltage
VOL
IOL = 2 mA
0.2
V
Low-level output
voltage
VOL
IOL = 2 mA
0.4
V
Analog input
voltage
VAI
AVSS
AVDD30
V
PullUp resistor
Rup
50
200
kΩ
PullUp resistor
Rup
180
800
kΩ
PullDown resistor
Rdn
50
220
kΩ
PullDown resistor
Rdn
120
500
kΩ
SCL2(TXD), SDA2(RXD),
EXCLK, EIRQ1, MON1,
MON2
DGDIN, DGSSB,
DGSCLK, DGDATA
SCL2(TXD), SDA2(RXD),
DGDIN, DGSSB,
DGSCLK, DGDATA,
EXCLK, SDA, SCL
MON1,MON2,EIRQ1
OPINPX, OPINPY,
OPINPAF, OPINMX,
OPINMY, OPINMAF
MON1, MON2, EIRQ1,
SCL2(TXD), SD2(RXD)
DGDATA, DGDIN,
DGSSB, DGSCLK
MON1, MON2, EIRQ1,
SCL2(TXD), SDA2(RXD),
EXCLK, WPB
DGDATA, DGDIN,
DGSSB, DGSCLK
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
Driver output at Ta = 30 to +85C, AVSS = 0 V, DVSS = 0 V, PGND = 0 V
Parameter
Output Current
OUT1 to OUT4
Output Current
OUT5, OUT6
Symbol
Ifull
Condition
Min
Typ
Max
Unit
Full code
200
mA
Full Code
OP-AF (bidirection / unidirection)
CL-AF
150
mA
Non-volatile Memory Characteristics
Parameter
Endurance
Data retention
Symbol
EN
RT
Condition
Min
10
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8
Typ
Max
1000
Unit
Cycles
Years
LC898123F40XC
9. AC Characteristics
9-1 Power Sequence
Item
Symbol
Rise time
tR
Wait time
tW
Bottom Voltage
Min
Typ
Max
Units
3
ms
100
Vbot
ms
0.2
V
Injection order between AVDD30 and VM is below.
tVMrd
tAVfd
2.6V
2.6V
AVDD30
VM ≦ AVDD30 + 0.5V
(VM ≦ 3.3V)
VM
tVMrd ≧ 0ms
tAVfd ≧0ms
WPB
WPB must be open or pulled down normally. When Flash is erased or programmed, WPB must be held High.
SDA, SCL, EXCLK, and WPB will tolerate 3 V input at the time of power off.
Power must remain applied to the device during flash access in order to prevent unintentional rewriting of the flash
memory.
Data in flash memory may be rewritten unintentionally if the specified power sequencing techniques are not kept.
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LC898123F40XC
9-2 Two Wire Serial Interface Timing
The device’s communication protocol is compatible with I2C (Fast mode Plus). This circuit has clock stretch function.
SD
SCL
Item
SCL clock frequency
START condition
hold time
SCL clock
Low period
SCL clock
High period
Setup time for repetition START
condition
Symbol
Min
Typ
Max
Units
1000
kHz
Fscl
SCL
tHD,STA
SCL
SDA
0.26
s
tLOW
SCL
0.5
s
tHIGH
SCL
0.26
s
0.26
s
tSU,STA
Data hold time
tHD,DAT
Data setup time
tSU,DAT
SDA, SCL
rising time
SDA, SCL
falling time
Pin name
tr
tf
STOP condition setup time
tSU,STO
Bus free time between STOP
and START
tBUF
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
0 (*1)
0.9
50
s
ns
120
ns
120
ns
0.26
s
0.5
s
(*1) Although the I2C specification defines a condition that 300 ns of hold time is required internally,
LC898123F40XC is designed for a condition with typ. 40 ns of hold time. If SDA signal is unstable
around falling point of SCL signal, please implement an appropriate countermeasure on board, such
as inserting a resistor.
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LC898123F40XC
ORDERING INFORMATION
Device
LC898123F40XC-VH
Package
Shipping (Qty / Packing)
WLCSP35, 3.22x2.3
(Pb-Free / Halogen Free)
4000 / Tape & Reel
† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
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