MC10173 Quad 2-Input Multiplexer/ Latch The MC10173 is a quad two channel multiplexer with latch. It incorporates common clock and common data select inputs. The select input determines which data input is enabled. A high (H) level enables data inputs D00, D10, D20, and D30 and a low (L) level enables data inputs D01, D11, D21, D31. Any change on the data input will be reflected at the outputs while the clock is low. The outputs are latched on the positive transition of the clock. While the clock is in the high state, a change in the information present at the data inputs will not affect the output information. • PD = 275 mW typ/pkg (No Load) • tpd = 2.5 ns typ • tr, tf = 2.0 ns typ (20%–80%) http://onsemi.com MARKING DIAGRAMS 16 CDIP–16 L SUFFIX CASE 620 MC10173L AWLYYWW 1 16 PDIP–16 P SUFFIX CASE 648 LOGIC DIAGRAM MC10173P AWLYYWW 1 SELECT 9 1 1 Q0 D00 6 PLCC–20 FN SUFFIX CASE 775 10173 AWLYYWW D01 5 A WL YY WW 2 Q1 D10 4 = Assembly Location = Wafer Lot = Year = Work Week D11 3 DIP PIN ASSIGNMENT 15 Q2 D20 13 D21 12 14 Q3 D30 11 D31 10 VCC = PIN 16 VEE = PIN 8 CLOCK 7 Q0 1 16 VCC Q1 2 15 Q2 D11 3 14 Q3 D10 4 13 D20 D01 5 12 D21 D00 6 11 D30 CLOCK 7 10 D31 VEE 8 9 SELECT TRUTH TABLE SELECT CLOCK Q0n+1 H L X L L H D00 D01 Q0n Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). ORDERING INFORMATION Device Semiconductor Components Industries, LLC, 2002 January, 2002 – Rev. 7 1 Package Shipping MC10173L CDIP–16 25 Units / Rail MC10173P PDIP–16 25 Units / Rail MC10173FN PLCC–20 46 Units / Rail Publication Order Number: MC10173/D MC10173 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Symbol Pin Under Test Max Unit Power Supply Drain Current IE 8 73 66 73 mAdc IinH 5 6 7 9 470 470 400 400 295 295 250 250 295 295 250 250 µAdc IinL All 0.5 Input Current –30°C Min +25°C Max Min Typ +85°C Max 0.5 Min µAdc 0.3 Output Voltage Logic 1 VOH 1 2 –1.060 –1.060 –0.890 –0.890 –0.960 –0.960 –0.810 –0.810 –0.890 –0.890 –0.700 –0.700 Vdc Output Voltage Logic 0 VOL 1 2 –1.890 –1.890 –1.675 –1.675 –1.850 –1.850 –1.650 –1.650 –1.825 –1.825 –1.615 –1.615 Vdc Threshold Voltage Logic 1 VOHA 1 2 –1.080 –1.080 Threshold Voltage Logic 0 VOLA 1 2 –0.980 –0.980 –0.910 –0.910 –1.655 –1.655 –1.630 –1.630 Vdc –1.595 –1.595 Switching Times (50Ω Load) Propagation Delay Vdc ns Data Input t6+1+ t6–1– t5+1+ t5–1– 1 1 1 1 0.8 0.8 0.8 0.8 3.7 3.7 3.7 3.7 1.0 1.0 1.0 1.0 2.5 2.5 2.5 2.5 3.5 3.5 3.5 3.5 1.1 1.1 1.1 1.1 5.3 5.3 5.3 5.3 Clock Input t7–1+ t7–1– 1 1 1.6 1.6 7.2 7.2 1.6 1.6 4.5 4.5 6.8 6.8 1.4 1.4 6.8 6.8 Select Input t9+1+ t9+1– t9–1+ t9–1– 1 1 1 1 1.1 1.1 1.1 1.1 6.2 6.2 6.2 6.2 1.3 1.3 1.3 1.3 3.5 3.5 3.5 3.5 5.7 5.7 5.7 5.7 1.2 1.2 1.2 1.2 6.7 6.7 6.7 6.7 Setup TIme Data Input Select Input tsetup tsetup 1 1 2.0 3.0 2.0 3.0 1.5 2.5 2.0 3.0 Hold TIme Data Input Select Input thold thold 1 1 2.5 1.5 2.5 1.5 0.0 –0.5 2.5 1.5 Rise Time (20 to 80%) t+ 1 1.2 4.0 1.5 2.0 3.5 1.4 4.0 Fall Time (20 to 80%) t– 1 1.2 4.0 1.5 2.0 3.5 1.4 4.0 * VILmin applied to each input pin, one at a time. http://onsemi.com 2 MC10173 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic Power Supply Drain Current @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Symbol Pin Under Test IE 8 Input Current 5 6 7 9 IinL All TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VEE (VCC) Gnd 8 16 8 8 8 8 16 16 16 16 * 8 16 VILmin VIHAmin VILAmax 5 6 7 9 Output Voltage Logic 1 VOH 1 2 6, 9 5 7 7 8 8 16 16 Output Voltage Logic 0 VOL 1 2 9 7 7 8 8 16 16 Threshold Voltage Logic 1 VOHA 1 2 9 7 7 8 8 16 16 Threshold Voltage Logic 0 VOLA 1 2 9 7 7 6 5 8 8 16 16 +1.11V +0.31V Pulse In Pulse Out –3.2 V +2.0 V 9 9 7 7 7 7 6 6 5 5 1 1 1 1 8 8 8 8 16 16 16 16 5, 7 5, 7 1 1 8 8 16 16 9 9 9 9 1 1 1 1 8 8 8 8 16 16 16 16 Switching Times Propagation Delay (50Ω Load) 6 5 Data Input t6+1+ t6–1– t5+1+ t5–1– 1 1 1 1 Clock Input t7–1+ t7–1– 1 1 Select Input t9+1+ t9+1– t9–1+ t9–1– 1 1 1 1 6 5 5 6 Data Input Select Input tsetup tsetup 1 1 6 5, 7 7, 9 1 1 8 8 16 16 Data Input Select Input thold thold 1 1 6 5, 7 7, 9 1 1 8 8 16 16 Rise Time (20 to 80%) t+ 1 5 7 1 8 16 Fall Time (20 to 80%) t– 1 7 1 8 16 Setup TIme Hold TIme 7 7 7 7 * VILmin applied to each input pin, one at a time. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. http://onsemi.com 3 MC10173 PACKAGE DIMENSIONS PLCC–20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) B Y BRK –N– M T L-M 0.007 (0.180) U M N S T L-M S G1 0.010 (0.250) S N S D –L– –M– Z W 20 D 1 X V S T L-M S N S VIEW D–D A 0.007 (0.180) M T L-M S N S R 0.007 (0.180) M T L-M S N S Z 0.007 (0.180) H M T L-M S N S K1 K C E F 0.004 (0.100) G J –T– VIEW S G1 0.010 (0.250) S T L-M S N S 0.007 (0.180) M T L-M S VIEW S SEATING PLANE NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 4 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2 10 0.310 0.330 0.040 --- MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2 10 7.88 8.38 1.02 --- N S MC10173 PACKAGE DIMENSIONS –A– 16 9 1 8 –B– CDIP–16 L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE T C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M S T A M http://onsemi.com 5 INCHES MIN MAX 0.750 0.785 0.240 0.295 --0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0 15 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 MC10173 Notes http://onsemi.com 6 MC10173 Notes http://onsemi.com 7 MC10173 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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