OKI ML60851C Usb device controller Datasheet

PEDL60851C-02
1Semiconductor
ML60851C
This version: Dec. 1999
Preliminary
USB Device Controller
GENERAL DESCRIPTION
The ML60851C is a general purpose Universal Serial Bus (USB) device controller. The ML60851C provides a
USB interface, control/status block, application interface, and FIFOs. The FIFO interface and two types of
transfer have been optimized for BulkOut devices such as printers and BulkIn devices such as digital still cameras
and image scanners. In addition, Mass Storage devices are also applicable to this device.
FEATURES
• USB 1.0 compliant
• Built-in USB transceiver circuit
• Full-speed (12 Mb/sec) support
• Supports printer device class, image device class, and Mass Storage device class
• Supports three types of transfer; control transfer, bulk transfer, and interrupt transfer
• Built-in FIFOs for control transfer
Two 8-byte FIFOs (one for receive FIFO and the other for transmit FIFO)
• Built-in FIFOs for bulk transfer (available for either receive FIFO or transmit FIFO)
One 64-byte FIFO
Two 64-byte FIFOs
• Built-in FIFO for interrupt transfer
One 8-byte FIFO
• Supports one control endpoint, two bulk endpoint addresses, and one interrupt endpoint address
• Two 64-byte FIFOs enable fast BulkOut transfer and BulkIn transfer
• Supports 8 bit/16 bit DMA transfer
• VCC is 3.0 V to 3.6 V
• Supporting dual power supply enables 5 V application interface
• Built-in 48 MHz oscillator circuit
• Package options:
44-pin plastic QFP (QFP44-P-910-0.80-2K)
(Product name: ML60851CGA)
44-pin plastic TQFP (TQFP44-P-1010-0.80-K)
(Product name: ML60851CTB)
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USB Bus
48 MHz
D-
D+
XOUT
XIN
Transceiver
USB
Oscillator
Engine
Protocol
DPLL
ML60851C
Status/Control
DACK
,
(Local MCU)
Module
Interface
,
Application
Application
D15:D0
A7:A0
PEDL60851C-02
1Semiconductor
ML60851C
BLOCK DIAGRAM
Endpoint FIFO/
8-byte Setup Register
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PEDL60851C-02
1Semiconductor
ML60851C
PIN CONFIGURATION (TOP VIEW)
AD0
AD1
AD2
AD3
VCC5
GND
AD4
AD5
AD6
AD7
DREQ
44
43
42
41
40
39
38
37
36
35
34
;;
D+
1
33
DACK
D-
2
32
A0
VCC3
3
31
A1
TEST1
4
30
A2
TEST2
5
29
A3
ADSEL
RESET
11
23
ALE
D8
D9
D10
D11
VCC5
GND
D12
D13
D14
22
24
21
10
20
A7
WR
19
25
18
9
17
A6
RD
16
26
15
8
14
A5
CS
13
A4
27
12
28
D15
6
7
INTR
XIN
XOUT
AD0
AD1
AD2
AD3
VCC5
VSS
AD4
AD5
AD6
AD7
DREQ
44
42
41
40
39
38
37
36
35
34
;
29
A3
6
28
A4
21
22
D9
D8
ALE
20
23
D10
ADSEL
11
19
24
D11
A7
10
18
A6
25
VCC5
26
9
17
A5
VSS
27
16
7
8
D12
RESET
A2
5
15
WR
30
D13
CS
RD
A1
4
14
XOUT
31
D14
XIN
A0
3
12
TEST2
DACK
32
13
TEST1
33
D15
VCC3
1
2
INTR
D+
D-
43
44-Pin Plastic QFP
44-Pin Plastic TQFP
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PEDL60851C-02
1Semiconductor
ML60851C
PIN DESCRIPTION
Pin
1,2
6, 7
4, 5
13 to 16,
19 to 22
35 to 38,
41 to 44
25 to 32
Symbol
D+, DXIN, XOUT
TEST14, 2
Type
I/O
—
I
Description
USB data
Pins for external crystal oscillator
Test pins (normally “L”)
Data bus (MSB)
D15 to D18
I/O
AD7 to AD0
I/O
A7 to A0
I
8
CS
I
Address inputs
Chip select signal input pin. LOW active
9
RD
I
Read signal input pin. LOW active
10
WR
I
Write signal input pin. LOW active
12
INTR
O
Interrupt request signal output pin
34
O
DMA request output pin
33
23
24
DREQ
DACK
ALE
ADSEL
I
I
I
11
RESET
I
DMA acknowledge signal input pin
Address latch enable signal input pin
Address input mode select input pin. “H”: address/data multiplex
System reset signal input pin. LOW active.
Data bus (LSB)/address inputs
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PEDL60851C-02
1Semiconductor
ML60851C
INTERNAL REGISTERS
Addresses and Names of Registers
Addresses
Read
Write
A5:A0
A7, A6
A7, A6
00h
01b
—
Register
Symbol
EP0RXFIFO
Page
Register name
Endpoint 0 Receive FIFO Data
7
01h
01b
—
EP1RXFIFO
Endpoint 1 Receive FIFO Data
7
02h
01b
—
EP2RXFIFO
Endpoint 2 Receive FIFO Data
8
03h
01b
—
00h
—
11b
EP0TXFIFO
Endpoint 0 Transmit FIFO Data
9
01h
—
11b
EP1TXFIFO
Endpoint 1 Transmit FIFO Data
9
02h
—
11b
EP2TXFIFO
Endpoint 2 Transmit FIFO Data
10
03h
—
11b
EP3TXFIFO
Endpoint 3 Transmit FIFO Data
10
00h
11b
01b
DVCADR
Device Address Register
11
01h
11b
01b
DVCSTAT
Device Status Register
11
02h
11b
—
PKTERR
Packet Error Register
13
03h
11b
—
FIFOSTAT1
FIFO Status Register 1
13
04h
11b
—
FIFOSTAT2
FIFO Status Register 2
14
08h
11b
01b
PKTRDY
Endpoint Packet-Ready Register
15
09h
11b
—
EP0RXCNT
Endpoint 0 Receive-Byte Count Register
19
0Ah
11b
—
EP1RXCNT
Endpoint 1 Receive-Byte Count Register
19
EP2RXCNT
Endpoint 2 Receive-Byte Count Register
20
0Bh
11b
—
0Ch
11b
—
0Dh
11b
—
Reserved
Reserved
REVISION
Revision Register
21
0Eh
—
01b
CLRFIFO
Transmit FIFO Clear Register
21
0Fh
—
01b
SYSCON
System Control Register
22
10h
11b
—
bmRequestType
bmRequestType Setup Register
23
11h
11b
—
bRequest
bRequest Setup Register
23
12h
11b
—
wValueLSB
wValueLSB Setup Register
24
13h
11b
—
wValueMSB
wValueMSB Setup Register
24
14h
11b
—
wIndexLSB
wIndexLSB Setup Register
24
15h
11b
—
wIndexMSB
wIndexMSB Setup Register
24
16h
11b
—
wLengthLSB
wLengthLSB Setup Register
25
17h
11b
—
wLengthMSB
wLengthMSB Setup Register
25
1Ah
11b
01b
POLSEL
Assertion Select Register
26
1Bh
11b
01b
INTENBL
Interrupt Enable Register
27
1Ch
11b
—
INTSTAT
Interrupt Status Register
28
1Dh
11b
01b
DMACON
DMA Control Register
30
1Eh
11b
01b
DMAINTVL
DMA Interval Register
31
1Fh
—
—
Reserved
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PEDL60851C-02
1Semiconductor
ML60851C
Addresses and Names of Registers (Continued)
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
Addresses
11b
11b
11b
—
11b
11b
11b
—
—
—
—
—
—
—
—
—
11b
11b
11b
11b
11b
11b
11b
—
11b
11b
11b
—
—
—
—
—
—
—
01b
—
01b
01b
01b
—
—
—
—
—
—
—
—
—
—
—
01b
01b
01b
01b
01b
—
01b
01b
01b
—
—
—
—
—
Symbol
EP0RXCON
EP0RXTGL
EP0RXPLD
EP1CON
EP1TGL
EP1PLD
EP0TXCON
EP0TXTGL
EP0TXPLD
EP0STAT
EP2CON
EP2TGL
EP2PLD
EP3CON
EP3TGL
EP3PLD
Register name
Endpoint 0 Receive Control Register
Endpoint 0 Receive Data Toggle Register
Endpoint 0 Receive Payload Register
Reserved
Endpoint 1 Control Register
Endpoint 1 Data Toggle Register
Endpoint 1 Payload Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Endpoint 0 Transmit Control Register
Endpoint 0 Transmit Data Toggle Register
Endpoint 0 Transmit Payload Register
Endpoint 0 Status Register
Endpoint 2 Control Register
Endpoint 2 Data Toggle Register
Endpoint 2 Payload Register
Reserved
Endpoint 3 Control Register
Endpoint 3 Data Toggle Register
Endpoint 3 Payload Register
Reserved
Reserved
Reserved
Reserved
Reserved
Page
32
32
33
34
35
35
36
36
37
38
40
41
41
42
43
43
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PEDL60851C-02
1Semiconductor
ML60851C
FUNCTIONS OF REGISTERS
End Point 0 Receive FIFO (EP0RXFIFO)
Read address
40h
Write address
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
x
x
x
x
x
x
x
x
After a bus reset
x
x
x
x
x
x
x
x
Definition
EP0 Receive data (R)
The receive data from the host computer in the data state during a control Write transfer is stored in EP0RXFIFO.
The EP0 receive data can be read out by the local MPU through reading the address 40h when the ML60851C
issues an EP0 receive packet ready interrupt request. It is possible to read successively the data in the packet by
reading continuously.
The EP2RXFIFO is cleared under the following conditions:
1. When the local MPU resets the EP0 receive packet ready bit (A “1” is written in PKTRDY(0)).
2. When a setup packet is received.
3. When the local MCU writes a “0” in the stall bit (EP0STAT(2)).
End Point 1 Receive FIFO (EP1RXFIFO)
Read address
41h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
x
x
x
x
x
x
x
x
After a bus reset
x
x
x
x
x
x
x
x
Definition
EP1 Receive data (R)
It is possible to read out the EP1 receive data by reading the address 41h. When EP1 is set for bulk reception
(BULK OUT), The local MCU should read EP1RXFIFO when the ML60851C issues an EP2 packet ready
interrupt request. It is possible to read successively the data in the packet by reading continuously. When the data
transfer direction of EP1 is set as “Transmit”, all accesses to this address will be invalid.
The EP1RXFIFO is cleared under the following conditions:
1. When an OUT token is received for EP1.
2. When the EP1 receive packet ready bit is reset. (A “1” is written in PKTRDY(1).)
3. When the local MCU writes a “0” in the stall bit (EP1CON(1)).
Even when a DMA read with a 16-bit width is made from EP1RXFIFO, the address is A7:A0 = 41h.
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PEDL60851C-02
1Semiconductor
ML60851C
End Point 2 Receive FIFO (EP2RXFIFO)
Read address
42h
—
Write address
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
x
x
x
x
x
x
x
x
After a bus reset
x
x
x
x
x
x
x
x
Definition
EP2 Receive data (R)
It is possible to read out the EP2 receive data by reading the address 42h. When EP2 is set for bulk reception (Bulk
OUT), the local MCU should read EP2RXFIFO when the ML60851C issues an EP2 packet ready interrupt request.
It is possible to read successively the data in the packet by reading continuously. When the data transfer direction
of EP2 is set as ‘Transmit’, all accesses to this address will be invalid.
The EP2RXFIFO is cleared under the following conditions:
1. When an OUT token is received for EP2.
2. When the EP2 receive packet ready bit is reset. (A “1” is written in PKTRDY(2).)
3. When the local MCU writes a “0” in the stall bit (EP2CON(1)).
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PEDL60851C-02
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ML60851C
End Point 0 Transmit FIFO (EP0TXFIFO)
Read address
—
Write address
C0h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
x
x
x
x
x
x
x
x
After a bus reset
x
x
x
x
x
x
x
x
Definition
EP0 Transmit data (W)
The EP0 transmit data can be written in by writing to the address C0h. The receive data from the host in the data
stage during a control read transfer is stored in EP0TXFIFO. When the ML60851C issues an EP0 transmit packet
ready interrupt request, the local MCU writes the transmit data to the address C0h. It is possible to write the packet
data successively by writing continuously.
The EP0 TXFIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP0.
2. When a setup packet is received.
End Point 1 Transmit FIFO (EP1TXFIFO)
Read address
—
Write address
C1h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
x
x
x
x
x
x
x
x
After a bus reset
x
x
x
x
x
x
x
x
Definition
EP1 Transmit data (W)
The EP1 transmit data can be written in by writing to the address C1h. When EP1 has been set for bulk
transmission (BULK IN), The local MCU should write the transmit data in EP1TXFIFO when the ML60851C
issues an EP1 packet ready interrupt request. It is possible to write the packet data successively by writing
continuously. When the data transfer direction of EP1 is set as ‘Receive’, all accesses to this address will be
invalid.
The EP1 transmit FIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP1.
2. When the local MCU writes a “1” in the EP1FIFO clear bit (CLRFIFO(1)).
Even when a DMA write with a 16-bit width is made in EP1TXFIFO, the address is A7:A0 = 41h.
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PEDL60851C-02
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ML60851C
End Point 2 Transmit FIFO (EP2TXFIFO)
Read address
—
Write address
C2h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
x
x
x
x
x
x
x
x
After a bus reset
x
x
x
x
x
x
x
x
Definition
EP2 Transmit data (W)
The EP2 transmit data can be written in by writing to the address C2h. When EP2 has been set for bulk
transmission (BULK IN), The local MCU should write the transmit data in EP1TXFIFO when the ML60851C
issues an EP2 packet ready interrupt request. It is possible to write the packet data successively by writing
continuously. When the data transfer direction of EP2 is set as “Receive”, all accesses to this address will be
invalid.
The EP2 TXFIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP2.
2. When the local MCU writes a “1” in the EP2FIFO clear bit (CLRFIFO(2)).
End Point 3 Transmit FIFO (EP3TXFIFO)
Read address
—
Write address
C3h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
x
x
x
x
x
x
x
x
After a bus reset
x
x
x
x
x
x
x
x
Definition
EP3 Transmit data (W)
The EP3 transmit data can be written in by writing to the address C3h. Make the local MCU write the transmit data
in EP3TXFIFO when the ML60851C issues an EP3 packet ready interrupt request. It is possible to write the
packet data successively by writing continuously.
The EP3 TXFIFO is cleared under the following conditions:
1. When an ACK is received from the host for the data transmission from EP3.
2. When the local MCU writes a “1” in the EP3FIFO clear bit (CLRFIFO(3)).
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PEDL60851C-02
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ML60851C
Device Address Register (DVCADR)
Read address
C0h
Write address
40h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
Device address (R/W)
The local MCU writes in this register the device address given by the SET_ADDRESS command from the host.
Thereafter, the ML60851C responds only to the token specifying this address among all the tokens from the host
computer. The default value is the address D6:D0 = 00h.
Note 1:
Note 2:
It is possible to carry out addressing using a 7-bit address because up to 127 devices can be
connected according to the USB standard.
The bit D7 is fixed at “0”, and even if a “1” is written in the bit D7, it will be invalid.
Device State Register (DVCSTAT)
Read address
C1h
Write address
41h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
1
After a bus reset
0
0
0
0
0
0
0
1
Definition
0
0
Default state (R/W)
Address state (R/W)
Configuration state (R/W)
Suspend state (R)
Remote wake-up (R/W)
USB bus reset status clear (W)
This is a register for displaying the status of the device. The functions of the different bits are described below:
The bits D7 and D6 are fixed at “0” and even if a “1” is written in these bits, the write operation will be invalid.
Default state:
This bit is asserted in the initial state. The default state is valid from the time the power is switched ON and
the hardware resetting is complete. There is no need to write a “0” in this bit.
Address state:
When a SET_ADDRESS request arrives, the local MCU writes the device address in the device address
register. If necessary, by writing a “1” in this bit also at that time, it is possible to give an indication that the
ML60851C has entered the address state. Since the content of this bit does not affect the operation of the
ML60851C, there is no need to write in this bit if it will not be read out.
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PEDL60851C-02
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ML60851C
Configuration state:
When the local MPU asserts the configuration bits EP1CON, EP2CON, or EP3CON in response to a
SET_CONFIGURATION request from the host computer when this IC is in the address state, by writing a
“1” in this bit also, if necessary, at that time, it is possible to give an indication that the ML60851C has
entered the configuration state. Since the content of this bit does not affect the operation of the ML60851C,
there is no need to write in this bit if it will not be read out.
Remarks:
When all these three states are “1”, it means that this IC is normally operating. However, since these bits do
not affect the operation of the ML60851C, there is no need to write in these bits if they will not be read out.
Suspend state:
When the idle condition continues for more than 3ms in the USB bus, the ML60851C automatically asserts
this bit thereby indicating that it is going into the suspend state. At the same time, bit D6 of the interrupt
status register INTSTAT is asserted and the INTR pin is asserted. With this, the local MCU can suppress
the current consumption.
This bit is deasserted when the EOP of any type of packet is received.
Remote wake-up:
The ML60851C is in the suspend state, the remote wake-up function is activated when the local MCU
asserts this bit. When this bit is written while 5ms have not yet elapsed in the idle condition, the remote
wake-up signal is output after waiting for the idle condition to continue for the full 5ms period. Further,
when this bit is written after the idle condition has persisted for 5ms or more, the remote wake-up signal is
output immediately after this bit is written. This bit is deasserted automatically when the suspend state is
released by receiving the resume instruction over the USB bus.
USB bus reset status clear:
When the ML60851C is in the USB bus reset interrupt state (bit D5 of the interrupt status register, that is the
USB bus reset interrupt status bit is “1” and the INTR pin is asserted), it is possible to clear the interrupt
status by writing a “1” in this bit. (This makes the USB bus reset interrupt status bit “0” and deassertes
INTR.) Although this bit can be read out, the read out value will always be “0”.
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ML60851C
Packet Error Register (PKTERR)
Read address
C2h
Write address
—
After a hardware reset
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
Definition
0
0
0
0
Bit stuff error (R)
Data CRC error (R)
Address CRC error (R)
PID Error (R)
Each bit is asserted when the corresponding error occurs and is deasserted when SOP is received.
This register is used to report the error information. This register is useful for the tests during development, or for
preparing the error frequency measurement report. This register is not particularly required for the specification of
commercial a product.
FIFO Status Register 1 (FIFOSTAT1)
Read address
C3h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
1
0
1
0
After a bus reset
0
0
0
0
1
0
1
0
Definition
0
0
0
0
Receive FIFO0 Full (R)
Receive FIFO0 Empty (R)
FIFO1 Full (R)
FIFO1 Empty (R)
This register reports the statuses of the EP0RXFIFO and the FIFO for EP1. Normally, there is no need to read this
register because it is sufficient to read the packet ready status before reading out or writing in a FIFO.
Receive FIFO0 Full:
This bit becomes “1” when 8-bytes of data are stored in the EP0RXFIFO. This bit is
not set to “1” when a packet less than 8 bytes long (a short packet) is stored in.
Receive FIFO0 Empty: This bit will be “1” when the EP0RXFIFO0 is empty.
FIFO1 Full:
This bit becomes “1” when 64 bytes of data is stored in the FIFO for EP1. This is true
during both transmission and reception. This bit does not become “1” in the case of a
short packet. The FIFO for EP1 has a two-layer structure and can store up to 128
bytes of data. This bit indicates the status of the FIFO in which data being written at
that time. In other words, this bit indicates the status of the FIFO into which the host
computer is writing data when EP1 is receiving data, and of the FIFO into which the
local MCU is writing data when EP1 is transmitting data.
FIFO1 Empty:
This bit becomes “1” when the FIFO for EP1 is empty. This is true during both
transmission and reception. The FIFO for EP1 has a two-layer structure and can store
up to 128 bytes of data. This bit indicates the status of the FIFO which is being read
out at that time.
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ML60851C
FIFO0 Status Register 2 (FIFOSTAT2)
Read address
C4h
Write address
—
After a hardware reset
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
After a bus reset
0
0
Definition
0
0
Transmit FIFO0 Full (R)
Transmit FIFO0 Empty (R)
FIFO2 Full (R)
FIFO2 Empty (R)
FIFO3 Full (R)
FIFO3 Empty (R)
This register reports the statuses of the EP0TXFIFO, the FIFO for EP2, and the FIFO for EP3. Normally, there is
no need to read this register because it is sufficient to read the packet ready status before reading out or writing in
a FIFO.
Transmit FIFO0 Full:
This bit becomes “1” when 8-bytes of data is stored in the EP0TXFIFO. This bit is
not set to “1” when a packet less than 8 bytes (a short packet) is written in.
Transmit FIFO0 Empty: This bit will be “1” when the EP0 transmit FIFO0 is empty.
FIFO2 Full:
This bit becomes “1” when 64 bytes of data is either stored or written in the FIFO for
EP2. This bit does not become “1” in the case of a short packet.
FIFO2 Empty:
This bit becomes “1” when the FIFO of EP2 is empty.
FIFO3 Full:
This bit becomes “1” when 64 bytes are written in the FIFO for EP3. This bit does not
become “1” in the case of a short packet.
FIFO3 Empty:
This bit becomes “1” when the FIFO for EP3 is empty.
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ML60851C
End Point Packet Ready Register (PKTRDY)
This register indicates whether or not the preparations for reading out or writing in a packet data have been
completed. In addition, this register is also used for controlling the handshake packet (ACK/NAK)
Read address
C8h
Write address
48h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
0
EP0 Receive packet ready (R/Reset)
EP1 Receive packet ready (R/Reset)
EP2 Receive packet ready (R/Reset)
EP0 Transmit packet ready (R/Set)
EP1 Transmit packet ready (R/Set)
EP2 Transmit packet ready (R/Set)
EP3 Transmit packet ready (R/Set)
This is the register for indicating that the local MCU can request a read/write of the FIFO for each EP. The logical
sums (AND) of each of these bits and the corresponding bits of INTENBL become the bits of INTSTAT.
The ML60851C asserts a receive packet ready bit (set to “0”) and generates an interrupt cause. The local MCU
resets the receive packet ready bit after completion of the interrupt servicing (such as taking out data from the
corresponding receive FIFO, etc.,).
The ML60851C deasserts a transmit packet ready bit and generates an interrupt cause. The local MCU sets the
receive packet ready bit after completion of the interrupt servicing (such as writing data in the corresponding
transmit FIFO, etc.,).
The bit D3 is fixed at “0”, and even if a “1” is written in this bit, that write operation will be invalid.
The operations of the different bits of PKTRDY are described in detail below.
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ML60851C
EP0 Receive packet ready bit (D0)
This bit can be read by the local MCU. Further, this bit can be set to “0” by writing “1” to the D0 bit.
The conditions of asserting and deasserting this bit are the following.
Bit name
EP0 Receive packet ready (D0)
Asserting condition
1. When data is received in EP0
and storing of one packet of
receive data in EP0RXFIFO is
completed.
2. When a setup packet is received
during a control Read or a control
Write transfer.
Action when asserted
EP0 is locked (that is, an NAK is
returned automatically when a data
packet is received from the host
computer).
(In the case of the asserting
condition 1, the local MCU can read
EP0RXFIFO.)
Bit name
EP0 Receive packet ready (D0)
Deasserting condition
1. When the local MCU resets
(writes a “1” in) this bit.
2. When the local MCU resets the
setup ready bit during a control
Write transfer.
Action when deasserted
Reception is possible in EP0.
R/Reset: Reading possible/ Reset when a “1” is written
R/Set:
Reading possible/ Set when a “1” is written
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ML60851C
EP1 Receive Packet Ready Bit (D1)
This bit can be read by the local MCU. Further, this bit can be set to “0” by writing “1” to the D1 bit.
The conditions of asserting and deasserting this bit are the following. EP1 has a two-layer FIFO, and even the
packet ready bits are present independently for layer A and layer B. The switching between these two layers is
done automatically by the ML60851C.
Bit name
EP1 Receive packet ready (D1)
Asserting condition
When an error-free packet is
received in either layer A or layer B.
Action when asserted
The local MCU can read the
EP1RXFIFO. EP1 is locked when
both layer A and layer B have
received a packet data.
Bit name
EP1 Receive packet ready (D1)
Deasserting condition
When the local MCU resets (writes a
“1”) in the bits of both layer A and
layer B.
Action when deasserted
Reception is possible in EP1 when at
least one of the bits of layer A and
layer B has been reset.
See the explanation of the operation of the two-layer FIFO given in the Section on ‘Functional Description’.
EP2 Receive Packet Ready Bit (D2)
This bit can be read by the local MCU. Further, this bit can be set to “0” by writing “1” to the D2 bit.
The conditions of asserting and deasserting this bit are the following.
Bit name
EP2 Receive packet ready (D2)
Asserting condition
When an error-free packet is
received.
Action when asserted
EP2 is locked.
Bit name
EP2 Receive packet ready (D2)
Deasserting condition
When the local MCU resets (writes a
“1” in) this bit.
Action when deasserted
Data reception is possible in EP2.
EP0 Transmit Packet Ready Bit (D4)
This bit can be read by the local MCU. Further, this bit can be set to “1” by writing “1” to the D4 bit.
The conditions of asserting and deasserting this bit are the following.
Bit name
EP0 Transmit packet ready (D4)
Asserting condition
When the local MCU sets this bit.
Action when asserted
Data transmission is possible from
EP0.
Bit name
EP0 Transmit packet ready (D4)
Deasserting condition
1. When an ACK is received from the
host computer in response to the
data transmission from EP0.
2. When a setup packet is received.
Action when deasserted
EP0 is locked. In other words, an
NAK is returned automatically when
an IN token is received from the host
computer.
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ML60851C
EP1 Transmit Packet Ready Bit (D5)
This bit can be read by the local MCU. Further, this bit can be set to “1” by writing “1” to the D5 bit.
The conditions of asserting and deasserting this bit are the following. EP1 has a two-layer FIFO, and even the
packet ready bits are present independently for layer A and layer B. The switching between these two layers is
performed automatically by the ML60851C.
Bit name
EP1 Transmit packet ready (D5)
Asserting condition
When the local MCU has set the bits
of both layer A and layer B.
Action when asserted
Data transmission is possible from
EP1 when the bit for at least one of
layer A and layer B has been
asserted.
Bit name
EP1 Transmit packet ready (D5)
Deasserting condition
When an ACK is received from the
host computer for the data
transmission from either layer A or
layer B.
Action when deasserted
EP1 is locked when both layer A and
layer B have not prepared the
transmit data.
See the explanation of the operation of the two-layer FIFO given in the Section on ‘Functional Description’.
EP2 Transmit Packet Ready Bit (D6)
This bit can be read by the local MCU. Further, this bit can be set to “1” by writing “1” to the D6 bit.
The conditions of asserting and negating this bit are the following.
Bit name
EP2 Transmit packet ready (D6)
Asserting condition
When the local MCU has set this bit.
Action when asserted
Data transmission is possible from
EP2.
Bit name
EP2 Transmit packet ready (D6)
Deasserting condition
When an ACK is received from the
host computer in response to the
data transmission from EP2.
Action when deasserted
EP2 is locked.
EP3 Transmit Packet Ready Bit (D7)
This bit can be read by the local MCU. Further, this bit can be set to “1” by writing “1” to the D7 bit.
The conditions of asserting and deasserting this bit are the following.
Bit name
EP3 Transmit packet ready (D7)
Asserting condition
When the local MCU has set this bit.
Action when asserted
Data transmission is possible from
EP3.
Bit name
EP2 Transmit packet ready (D7)
Deasserting condition
When an ACK is received from the
host computer in response to the
data transmission from EP3.
Action when deasserted
EP3 is locked.
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ML60851C
End Point 0 Receive Byte Count Register (EP0RXCNT)
Read address
C9h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
0
After a hardware reset
Byte count of EP0 (R)
The ML60851C automatically counts the number of bytes in the packet being received by EP0 and stored it in this
register. Although the counting is performed up to the maximum packet size entered in the payload register in the
case of a full packet, the count will be less than this value in the case of a short packet. The local MCU refers to
this value and reads the data of one packet from the EP0RXFIFO.
The EP0 receive byte count register is cleared under the following conditions:
1. When the local MCU resets the EP0 receive packet ready bit (by writing a “1” in PKTRDY(0)).
2. When a setup packet is received.
3. When the local MCU writes a “0” in the stall bit (EP0STAT(2)).
End Point 1 Receive Byte Count Register (EP1RXCNT)
Read address
CAh
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
0
Byte count of EP1 (R)
The ML60851C automatically counts the number of bytes in the packet being received by EP1 and stored it in this
register. Although the counting is performed up to the maximum packet size entered in the payload register in the
case of a full packet, the count will be less than this value in the case of a short packet. The local MCU refers to
this value and reads the data of one packet from the EP1 receive FIFO.
This register is invalid when the EP1 transfer direction is set as ‘Transmit’.
The EP1 receive byte count register is cleared under the following conditions:
1. When an OUT token is received for EP1.
2. When the EP1 receive packet ready bit is reset (by writing a “1” in PKTRDY(1)).
3. When the local MCU writes a “0” in the stall bit (EP1CON(1)).
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ML60851C
End Point 2 Receive Byte Count Register (EP2RXCNT)
Read address
CBh
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
0
After a hardware reset
Byte Count of EP2 (R)
The ML60851C automatically counts the number of bytes in the packet being received by EP2 and stored it in this
register. Although the counting is performed up to the maximum packet size entered in the payload register in the
case of a full packet, the count will be less than this value in the case of a short packet. The local MCU refers to
this value and reads the data of one packet from the EP2RXFIFO.
This register is invalid when the EP2 transfer direction is set as ‘Transmit’.
The EP2 receive byte count register is cleared under the following conditions:
1. When an OUT token is received for EP2.
2. When the EP2 receive packet ready bit is reset (by writing a “1” in PKTRDY(2)).
3. When the local MCU writes a “0” in the stall bit (EP2CON(1)).
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ML60851C
Revision Register (REVISION)
Read address
CDh
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
D0
After a hardware reset
D5
D4
D3
D2
D1
Cannot be read (indeterminate)
After a bus reset
Cannot be read (indeterminate)
After a hardware reset
After a bus reset
Revision No. of Chip
Definition
Transmit FIFO Clear Register (CLRFIFO)
Read address
—
Write address
4Eh
D7
Definition
0
D6
0
0
0
EP1 Transmit FIFO Clear
EP2 Transmit FIFO Clear
EP3 Transmit FIFO Clear
EP1 to EP3 FIFO Clear: When each EP has been set for transmission, by writing a “1” in these bits, the
corresponding FIFOs are cleared at the Write pulse and also the corresponding EP
Packet Ready bits are reset.
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ML60851C
System Control Register (SYSCON)
Read address
—
Write address
4Fh
After a hardware reset
D7
D5
D4
D3
D2
D1
Cannot be read (indeterminate)
After a bus reset
Cannot be read (indeterminate)
Definition
D6
0
0
D0
0
Software Reset
Oscillation Stop Command
Software Reset:
When a “1” is written in this bit, a system reset is executed at the Write pulse. This is
functionally equivalent to a hardware reset.
Oscillation Stop command: The Oscillation circuit of the ML60851C stops and goes into the standby state when
1010b is written in D7 to D4 (that is, when A0h is written in this register).
Once the IC goes into the standby state, to start communication with the USB bus
thereafter, it is necessary to carry out again disconnecting, connecting, and
enumeration.
Even when the Oscillation has stopped, although it is possible to read on write the
registers, it is impossible to read or write the FIFO.
The oscillation can be started again by asserting the RESET pin. The oscillation can
be restarted even by a software reset.
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ML60851C
bmRequest Type Setup Register
Read address
D0h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
Type
Receiving side
0 = Device
1 = Interface
2 = End point
3 = Others
4 to 31 = Reserved
0 = Standard
1 = Class
2 = Vendor
3 = Reserved
0 = From the host computer to the device
1 = From the device to the host computer
Data Transfer Direction
The format of the device request conforms to Section 9.3 of the USB standards. The eight bytes of setup data sent
by the host computer during the setup stage of control transfer are stored automatically in eight registers including
this register.
bRequest Setup Register
Read address
D1h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
Request Code
The request code indicating the contents of the device request is stored automatically in this register during the
setup stage of control transfer.
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ML60851C
wValue LSB Setup Register
Read address
D2h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
wValue LSB
A parameter of device request is stored in this register during the setup stage of control transfer.
wValue MSB Setup Register
Read address
D3h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
wValue MSB
A parameter of device request is stored in this register during the setup stage of control transfer.
wIndex LSB Setup Register
Read address
D4h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
wIndex LSB
A parameter of device request is stored in this register during the setup stage of control transfer.
wIndex MSB Setup Register
Read address
D5h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
wIndex MSB
A parameter of device request is stored in this register during the setup stage of control transfer.
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ML60851C
wLength LSB Setup Register
Read address
D6h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
wLength LSB
A parameter of device request is stored in this register during the setup stage of control transfer.
wLength MSB Setup Register
Read address
D7h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
wLength MSB
A parameter of device request is stored in this register during the setup stage of control transfer.
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ML60851C
Polarity Selection Register (POLSEL)
Read address
DAh
Write address
5Ah
After a hardware reset
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
After a bus reset
Definition
The previous value is retained
0
0
0
Polarity of INTR
0 = Active Low
1 = Active High
Polarity of DREQ
0 = Active Low
1 = Active High
Polarity of DACK
0 =Active High
1 =Active Low
The local MCU can set the operating conditions of the ML60851C. The bits D7 to D3 are fixed at “0” and even if
“1”s are written in them, they are ignored.
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ML60851C
Interrupt Enable Register (INTENBL)
Read address
DBh
Write address
5Bh
After a hardware reset
After a bus reset
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
The previous value is retained
Definition
Setup ready Interrupt Enable
EP1
Packet Ready
Interrupt Enable
EP2
Packet Ready
Interrupt Enable
EP0
Receive Packet
Ready Interrupt Enable
EP0
Transmit Packet
Ready Interrupt Enable
USB Bus Reset Interrupt Enable
Suspend State Interrupt Enable
EP3 Packet Ready Interrupt Enable
The interrupts that can be accepted are set in this register. It is possible to change the setting of interrupt enable or
disable dynamically depending on the operating conditions. There is a correspondence between this register the
interrupt status register described next in terms of the bit numbers and the corresponding interrupt factors.
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ML60851C
Interrupt Status Register (INTSTAT)
Read address
DCh
Write address
—
After a hardware reset
After a bus reset
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
See
below
See
below
0
See
below
0
0
See
below
Definition
Setup Ready Interrupt Status
EP1 Packet Ready Interrupt
Status
EP2 Packet Ready Interrupt
Status
EP0 Receive Packet Ready
Interrupt Status
EP0 Transmit Packet Ready
Interrupt Status
USB Bus Reset Interrupt Status
Suspend State Interrupt Status
EP3 Packet Ready Interrupt Status
Setup Ready Interrupt Status: When bit D0 of the interrupt enable register (INTENBL) is “1”, the content of bit
D0 of the EP0 status register (EP0STAT) is copied here.
This bit is “0” when D0 of INTENBL is “0”. In other words, when the eight bytes of setup
data are received in the setup stage of control transfer and are correctly stored in the setup
registers, this bit is set to “1” and the INTR pin is asserted.
EP1 Packet Ready Interrupt Status: When bit D1 of the interrupt enable register (INTENBL) is “1”, the negation of
the content of bit D1 or of bit D5 of the end point packet ready register (PKTRDY) is copied
here. This bit is “0” when bit D1 of INTENBL is “0”. The value at the time of a bus reset is
determined based on the value of INTENBL and the EP transfer direction at that time, and
also based on the value of the packet ready bit for that EP.
(If the EP1 transfer direction has been set as “Receive”, the negation of D1 is stored here, and
the negation of D5 is stored if the transfer direction has been set as “Transmit”.)
During data reception, the packet ready interrupt is generated when one packet of receive
data is correctly stored in one of the two FIFO layers of EP1. During transmission, the packet
ready interrupt is generated when data transmission has been completed from (and writing
becomes possible again) one of the two FIFO layers of EP1.
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ML60851C
EP2 Packet Ready Interrupt Status: When bit D2 of the interrupt enable register (INTENBL) is “1”, the negation
of bit D2 or bit D6 of the end point packet ready register (PKTRDY) is copied here. This bit
is “0” when bit D2 of INTENBL is “0”. The value at the time of a bus reset is determined
based on the value of INTENBL and the EP transfer direction at that time, and also based on
the value of the packet ready bit for that EP.
(If the EP2 transfer direction has been set as “Receive”, the negation of D2 is stored here, and
the negation of D6 is stored if the transfer direction is has been set as “Transmit”.)
During data reception, the packet ready interrupt is generated when one packet of receive
data is correctly stored in the FIFO of EP2. During transmission, the packet ready interrupt is
generated when data transmission has been completed from (and writing becomes possible
again) the FIFO of EP2.
EP0 Receive Packet Ready Interrupt Status: When bit D3 of the interrupt enable register (INTENBL) is “1”, the
content of bit D0 of the end point packet ready register (PKTRDY) is copied here. This bit is
“0” when bit D3 of INTENBL is “0”.
In other words, when one data packet is received in the data stage of control transfer and is
correctly stored in the EP0RXFIFO, this bit is set to “1” and the INTR pin is asserted.
EP0 Transmit Packet Ready Interrupt Status: When bit D4 of the interrupt enable register (INTENBL) is “1”, the
negation of the content of bit D4 of the end point packet ready register (PKTRDY) is copied
here. This bit is “0” when bit D4 of INTENBL is “0”. The value at the time of a bus reset is
determined based on the value of INTENBL and the EP transfer direction at that time, and
also based on the value of the packet ready bit of that EP.
In other words, when the transmission from the EP0RXFIFO is completed (and writing is
possible again in the FIFO) in the data stage of control transfer, this bit is set to “1” and the
INTR pin is asserted.
USB Bus Reset Interrupt Status: When bit D5 of the interrupt enable register (INTENBL) is “1”, this bit becomes
“1” during a bus reset. This bit is “0” when bit D5 of INTENBL is “0”. The value at the time
of a bus reset is determined based on the value of INTENBL and the EP transfer direction at
that time, and also based on the value of the packet ready bit of that EP.
Write a “1” in bit D5 of the device status register to return this bit to “0”.
Suspend State Interrupt Status: When bit D6 of the interrupt enable register (INTENBL) is “1”, the content of bit
D3 of the device state register (DVCSTAT) is copied here. This bit is “0” when bit D6 of
INTENBL is “0”.
EP3 Packet Ready Interrupt Status: When bit D7 of the interrupt enable register (INTENBL) is “1”, the negation
of bit D7 of the end point packet ready register (PKTRDY) is copied here. This bit is “0”
when bit D7 of INTENBL is “0”. The value at the time of a bus reset will be determined
based on the value of INTENBL and the EP transfer direction at that time, and also based on
the value of the packet ready bit of that EP.
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ML60851C
DMA Control Register (DMACON)
Read address
DDh
Write address
5Dh
After a hardware reset
After a bus reset
Definition
D7
D6
0
0
D5
D4
D3
D2
D1
0
0
0
0
0
The previous value is retained
0
0
D0
0
DMA Enable
0 = DMA Inhibited
1 = DMA Transfer of EP1 is
enabled
DMA Address Mode
0 = Single address mode
1 = Dual address mode
Byte Count
0 = The byte count is not inserted.
1 = The byte count data is inserted in the
leading byte or the leading word of the
transfer data. (Note 1)
DMA Transfer Data Width
0 = Byte wide (8 bits)
1 = Word wide (16 bits) (Note 2)
DMA Transfer Mode
0 = Single transfer mode
1 = Demand transfer mode
Halting DMA Transfer
0 = Normal operation
1 = The DREQ pin is deasserted.
Note 1: In the 16-bit mode, the upper byte of the leading word is 00h.
Note 2: The allocation is made in the little-endian sequence of the upper byte followed by the LSB. In
other words, the lower byte corresponds to AD0 to AD7 and the MSB corresponds to D8 to D15.
In the 16-bit mode, when the packet size is an odd number of bytes, the upper byte of the last
word is 00h.
Note 3: Make sure that all bits other than D7, that is, bits D4 to D0, are set completely during initialization
(at the latest, before the token packet for EP1 arrives) and are not modified thereafter.
When wanting to temporarily halt the DMA transfer in the middle, write a “1” in D7. When the
transfer is restarted by writing a “0” in D7, it is possible to restart the transfer from the byte (or
word) next to the one a the time the transfer was halted.
Note 4: The bits D6 and D5 are fixed at “0”. Even if a “1” is written in them, it will be invalid.
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ML60851C
DMA Interval Register (DMAINTVL)
Read address
DEh
Write address
5Eh
After a hardware reset
After a bus reset
Definition
D7
D6
0
0
D5
D4
D3
D2
D1
0
0
0
0
0
The previous value is retained
Interval time
D0
0
This register is used for specifying the interval of the single DMA transfer mode, that is, the interval from the
completion of the previous byte (or word) DMA transfer until DREQ is asserted again. The time per bit is 84ns
(12MHz, one period).
Interval time = (DREQ enable time) + 84 x n (ns)
See DMA timings (1), (2), (5), and (6) for details of the DREQ enable time.
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PEDL60851C-02
1Semiconductor
ML60851C
End Point 0 Receive Control Register (EP0RXCON)
Read address
E0h
Write address
—
After a hardware reset
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
1
After a bus reset
0
0
0
0
0
0
0
Definition
0
0
0
0
0
0
0
Configuration Bit (R)
Transfer Type
00 = Control transfer
End Point Address
Configuration Bit:
The configuration bit of EP0 becomes “1” at the time of an USB bus reset. The packets sent
by the host computer to EP0 are received when this bit is “1”. This IC does not respond to
any transactions with this EP when this bit is “0”.
The transfer mode of EP0 is a control transfer and the end point address is fixed at 0h. Therefore, the values of D6
to D2 are fixed and other values written in them are invalid.
End Point 0 Receive Data Toggle Register (EP0RXTGL)
Read address
E1h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
x
After a bus reset
0
0
0
0
0
0
0
x
Definition
0
0
0
0
0
0
0
Data Sequence Toggle Bit (R)
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PEDL60851C-02
1Semiconductor
ML60851C
End Point 0 Receive Payload Register (EP0RXPLD)
Read address
E2h
Write address
62h
After a hardware reset
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
0
0
0
After a bus reset
0
0
0
0
1
0
0
0
Definition
0
0
0
0
1
0
0
0
Maximum packet size
Maximum packet size:
Since the FIFO capacity for EP0 in the ML60851C is 8 bytes, write 08h in the
bMaxPacketSize0 byte of the device descriptor. The maximum packet size is fixed at 8
bytes in this register EP0RXPLD.
When a packet longer than 8 bytes is received, the stall bit of the EP0 status register is
asserted and the stall status is returned to the host computer.
The content of this register is fixed at 08h. This value will not change even if any other value is written in this
register.
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PEDL60851C-02
1Semiconductor
ML60851C
End Point 1 control Register (EP1CON)
Read address
E4h
Write address
64h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
1
1
0
x
0
After a bus reset
0
x
0
Definition
0
0
1
1
0
0
0
1
1
0
Configuration Bit (R/W)
Stall Bit (R/W)
Transfer Type
10 = Bulk Transfer
End point Address (R)
Transfer Direction (R/W)
0 = Receive, 1 = Transmit
Configuration Bit: The local MCU should write “1” in this bit during the status stage of control transfer when a
“Set Configuration” request is received from the host computer to make EP1 active.
When this bit is “1”, the exchange of data between the host computer and EP1 is enabled.
When this bit is “0”, this IC does not respond to any transactions with this EP.
Stall Bit:
When a data packet is received with a number of bytes more than the maximum packet size set
in the EP1 payload register, the ML60851C automatically sets this bit to “1”. It is also possible
for the local MCU to write a “1” in this bit. When this bit is “1”, the stall handshake is
automatically returned to the host computer in response to the packet transmitted by the host
computer to the end point. In addition, the packet ready status is not asserted and even the
INTR pin is not asserted.
The EP1 transfer mode is set as a bulk transfer and the end point address is 1h. Therefore, the bits D6 to D2 have
fixed values, and other values written in them are ignored.
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PEDL60851C-02
1Semiconductor
ML60851C
End Point 1 Data Toggle Register (EP1TGL)
Read address
E5h
Write address
65h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
0
Definition
0
0
0
0
0
0
0
Data Sequence Toggle Bit
(R/Reset)
Data Sequence Toggle Bit:
When initializing an EP, write a “1” in this bit to reset the toggle bit of the data
packet and specify PID of DATA0 (this bit also becomes “0”). Thereafter, the
synchronous operation is made automatically based on the data sequence toggling
mechanism.
The values of bits D7 to D1 are fixed at “0” and even if a “1” is written in these bits, it will be invalid.
End Point 1 Payload Register (EP1PLD)
Read address
E6h
Write address
66h
D7
D6
D5
D4
D3
D2
D1
D0
0
x
x
x
x
x
x
x
After a bus reset
0
x
x
x
x
x
x
x
Definition
0
After a hardware reset
Maximum Packet Size:
Maximum packet size (R/W)
The value of wMaxPacketSize of the end point descriptor selected by the Set_Configuration
request from the host computer should be written in this register by the local MCU.
The packet size of packets other than short packets is specified in units of a byte.
The value can be one of 40h (64 bytes), 20h (32 bytes), 10h (16 bytes), and 08h
(8 bytes).
During data reception by EP1, if a packet with more number of bytes than that
specified here is received, the receive packet ready bit is not asserted, and the stall
bit is set during EOP and the stall handshake is returned to the host computer.
On the other hand, when EP1 is being used for transmission, the transmit packet
ready bit is set automatically when the writing of data of the number of bytes set in
this register (maximum packet size) by the DMA controller is completed.
Bit D7 is fixed at “0”, and even if a “1” is written, it will be ignored.
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PEDL60851C-02
1Semiconductor
ML60851C
End Point 0 Transmit Control Register (EP0TXCON)
Read address
F0h
Write address
—
After a hardware reset
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
0
0
1
After a bus reset
0
1
0
0
0
0
0
Definition
0
1
0
0
0
0
0
Configuration Bit (R)
Transfer Type
00 = Control transfer
FIFO Number
Configuration Bit: The configuration bit of EP0 becomes “1” during an USB bus reset (both D+ and D- being “0”
for more than 2.5µs). Packets can be sent from this end point to the host computer when this bit
is “1”. This IC does not respond to any transactions with this EP when this bit is “0”.
The transfer mode of EP0 is a control transfer and the end point address is fixed at 0h. Therefore, the values of D6
to D2 are fixed and other values written in them are invalid.
End Point 0 Transmit Data Toggle Register (EP0TXTGL)
Read address
F1h
Write address
—
After a hardware reset
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
x
x
After a bus reset
0
0
0
0
0
0
0
Definition
0
0
0
0
0
0
0
Data Sequence Toggle Bit (R)
The synchronization based on the data sequence toggling mechanism is carried out automatically by the
ML60851C.
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PEDL60851C-02
1Semiconductor
ML60851C
End Point 0 Transmit Payload Register (EP0TXPLD)
Read address
F2h
Write address
72h
D7
D6
D5
D4
D3
D2
D1
D0
0
x
x
x
x
x
x
x
After a bus reset
0
x
x
x
x
x
x
x
Definition
0
After a hardware reset
Maximum packet size:
Maximum Packet Size (R/W)
This is a register that has no relationship with the operation of the ML60851C, and can
be used as a general purpose register. Bit D7 is fixed at “0”.
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PEDL60851C-02
1Semiconductor
ML60851C
End Point 0 Status Register (EP0STAT)
Read address
F3h
Write address
73h
After a hardware reset
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
x
0
0
0
0
x
0
0
After a bus reset
0
0
0
Definition
0
0
0
0
Setup Ready (R/Reset)
Stall Bit (R/W)
EP0 Stage (R)
00 = Setup stage
01 = Data stage
10 = Status stage
Setup Ready:
This bit is set automatically when a proper setup packet arrives in the 8-byte setup register, and
the EP0RXFIFO is locked. If D0 of INTENBL has been asserted, the INTR pin is also
asserted automatically when this bit is set. The local MCU should write a “1” in this bit after
the reading out the 8-byte setup data. When this is performed, the setup ready bit is reset and
the INTR pin also is deasserted. During a control write, even the packet ready bit of EP0 is
reset simultaneously, the lock condition is released, and it becomes possible to receive packets
by EP0 during the data stage.
The register value will not change even if a “0” is written in this bit.
Stall bit:
During EP0 reception (in the data stage of a control write transfer), the ML60851C
automatically sets this bit to “1” when a packet with a number bytes more than the maximum
packet size written in EP0RXPLD is received (or when EOP is missing).
Bits D7 to D5 and D1 are fixed at “0”, and other values written in them are invalid.
EP0 Stage:
Indicates the stage transition during a control transfer. The transition conditions between the
different stages are shown in the following stage transition diagram.
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PEDL60851C-02
1Semiconductor
ML60851C
Hardware Reset
USB Bus Reset
Setup Stage
Condition 1
Data Stage
Condition 2
Condition 3
Condition 1
Status Stage
Condition 2
Condition 1:
Condition 2:
Condition 3:
Reception of a setup packet of control READ transfer or control
WRITE transfer.
Reception of a setup packet of control transfer without data.
Reception of a token (IN/OUT) of a direction opposite to the data
flow in the data stage.
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PEDL60851C-02
1Semiconductor
ML60851C
End Point 2 Control Register (EP2CON)
Read address
F4h
Write address
74
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
1
0
1
0
X
0
After a bus reset
0
X
0
Definition
0
1
0
1
0
0
1
0
1
0
Configuration Bit (R/W)
Stall Bit (R/W)
Transfer Type
10 = Bulk transfer
End Point Address (R)
Transfer Direction (R/W)
0 = Receive, 1 = Transmit
Configuration Bit: The local MCU should write a “1” in this bit during the status stage of control transfer when a
“Set Configuration” request is received from the host computer to make EP2 active. When this
bit is “1”, the exchange of data between the host computer and EP2 is enabled. When this bit is
“0”, this IC does not respond to any transactions with this EP.
Stall Bit:
During EP2 reception, when a data packet is received with a number of bytes more than the
maximum packet size set in the pay load register EP2PLD, the ML60851C automatically sets
this bit to “1”. It is also possible for the local MCU to write a “1” in this bit. When this bit is
“1”, the stall handshake is automatically returned to the host computer in response to the packet
transmitted by the host computer to the end point. In addition, the packet ready status is not
asserted and the INTR pin is not asserted.
The EP2 transfer mode is set as a bulk transfer and the end point address is 2h. Therefore, the bits D6 to D2 have
fixed values, and other values written in them are ignored.
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PEDL60851C-02
1Semiconductor
ML60851C
End Point 2 Data Toggle Register (EP2TGL)
Read address
F5h
Write address
75h
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
After a hardware reset
After a bus reset
0
0
0
0
0
0
0
Definition
0
0
0
0
0
0
0
Data Sequence Toggle Bit
(R/Reset)
Data Sequence Toggle Bit:
When initializing an EP after receiving a setup packet, write a “1” in this bit to reset
the toggle bit of the data packet and specify PID of DATA0 (this bit also becomes
“0”). Thereafter, the synchronous operation is made automatically based on the data
sequence toggling mechanism.
The values of bits D7 to D1 are fixed at “0” and even if a “1” is written in these bits,
it will be invalid.
End Point 2 Payload Register (EP2PLD)
Read address
F6h
Write address
76h
D7
D6
D5
D4
D3
D2
D1
D0
0
x
x
x
x
x
x
x
After a bus reset
0
x
x
x
x
x
x
x
Definition
0
After a hardware reset
Maximum Packet Size:
Maximum packet size (R/W)
The value of wMaxPacketSize of the end point descriptor selected by the
Set_Configuration request from the host computer should be written in this register
by the local MCU. The packet size of packets other than short packets is specified in
units of a byte. The value can be one of 40h (64 bytes), 20h (32 bytes), 10h (16
bytes), and 08h (8 bytes). This register is used for EP2 reception. During data
reception by EP2, if a packet with more number of bytes than that specified here is
received, the receive packet ready bit is not asserted, and the stall bit is set during
EOP and the stall handshake is returned to the host computer.
Bit D7 is fixed at “0”, and even if a “1” is written, it will be invalid.
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PEDL60851C-02
1Semiconductor
ML60851C
End Point 3 Control Register (EP3CON)
Read address
F8h
Write address
78h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0
1
1
1
1
x
0
After a bus reset
0
x
0
Definition
0
1
1
1
1
0
1
1
1
1
Configuration Bit (R/W)
Stall Bit (R/W)
Transfer Type (R)
11b = Interrupt Transfer
End Point Address
Toggling Condition (R/W)
0 = Normal
1 = Rate feedback mode
Configuration Bit:
Stall Bit:
The local MCU should write a “1” in this bit during the status stage of control transfer
when a “Set Configuration” request is received from the host computer to make EP3
active.
When this bit is “1”, the exchange of data between the host computer and EP3 is
enabled. When this bit is “0”, this IC does not respond to any transactions with this
EP.
When this bit is “1”, the stall handshake is automatically returned to the host computer
in response to the packet transmitted to the host computer from this end point.
The EP3 transfer mode is set as an interrupt transfer and the end point address is fixed at 3h. Therefore, the bits D6
to D2 have fixed values, and other values written in them are invalid.
Toggling Condition Bit:
When this bit is “0”, toggling is performed between DATA0 and DATA1 every time
an ACK is sent from the host computer to EP3.
If this bit is set to “1”, the rate feedback mode will be set. In this case, the toggling is
performed every time the packet ready bit is asserted.
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PEDL60851C-02
1Semiconductor
ML60851C
End Point 3 Data Toggle Register (EP3TGL)
Read address
F9h
Write address
79h
After a hardware reset
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
After a bus reset
0
0
0
0
0
0
0
Definition
0
0
0
0
0
0
0
Data Sequence Toggle Bit
(R/Reset)
Data Sequence Toggle Bit: When initializing an EP, write a “1” in this bit to reset the toggle bit of the data packet
and specify PID of DATA0 (this bit also becomes “0”).
The values of bits D7 to D1 are fixed at “0” and even if a “1” is written in these bits, it will be invalid.
End Point 3 Payload Register (EP3PLD)
Read address
FAh
Write address
7Ah
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
x
x
x
x
x
x
x
After a bus reset
0
x
x
x
x
x
x
x
Definition
0
7-Bit general purpose register
This register can be used for any purpose. It is possible to retain or refer to the value written in this register without
affecting the other operations of the ML60851C. The initial values of bits other than D7 are indeterminate. Bit D7
is fixed at “0” and even if a “1” is written in this bit, it will be invalid.
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PEDL60851C-02
¡ Semiconductor
ML60851C
ABSOLUTE MAXIMUM RATINGS
Symbol
Condition
Rating
Unit
Power Supply 3
VCC3
—
–0.3 to +4.6
V
Power Supply 5
VCC5
—
–0.5 to +6.5
V
VI
—
–0.3 to VCC5 + 0.3
V
TSTG
—
–55 to +150
°C
Parameter
Input Voltage
Storage Temperature
RECOMMENDED OPERATING CONDITIONS
Symbol
Condition
Range
Unit
Power Supply 3
VCC3
—
3.0 to 3.6
V
Power Supply 5
VCC5
—
3.0 to 5.5
V
Ta
—
0 to 70
°C
FOSC
—
48
MHz
Parameter
Operating Temperature
Oscillation Frequency
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PEDL60851C-02
¡ Semiconductor
ML60851C
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VCC5 = VCC3 = 3.0 to 3.6 V, Tj = 0 to 85°C)
Parameter
High-level Input
Voltage
Low-level Input
Voltage
High-level Input
Voltage
Low-level Input
Voltage
Schmitt Trigger
Input Voltage
High-level
Output Voltage
Low-level
Output Voltage
High-level Input
Current
Low-level Input
Symbol
Condition
Min.
Typ.
Max.
Unit
VIH
—
2.0
—
VCC5 + 0.3
V
Applicable pin
Note 1
VIL
—
–0.3
—
+0.8
V
VIH
—
VCC3 ¥ 0.8
—
VCC3 + 0.3
V
VIL
—
–0.3
—
VCC3 ¥ 0.2
V
Vt+
—
—
1.6
2.0
V
Vt–
—
0.8
1.2
—
V
DVt
(Vt+) – (Vt–)
IOH = –100 mA
0.1
0.4
—
V
VCC5 – 0.2
—
—
V
IOH = –4 mA
2.4
—
—
V
IOL = 100 mA
—
—
0.2
V
IOL = 4 mA
—
—
0.4
V
VIH = VCC5
—
0.01
1
mA
XIN
VOH
VOL
IIH
RESET
D15:D8
AD7:AD0
INTR, DREQ
Note 2
IIL
VIL = 0 V
–1
–0.01
—
mA
3-state Output
IOZH
VOH = VCC5
—
0.01
1
mA
D15:D8
Leakage Current
IOZL
VOL = 0 V
–1
–0.01
—
mA
AD7:AD0
ICC
Note 3
—
55
mA
VCC3, VCC5
ICCS
Note 4
—
100
mA
VCC3, VCC5
Current
Power Supply
Current (Operating)
Power Supply
Current (Standby)
Notes: 1.
2.
3.
4.
Applied to D15:D8, AD7:AD0, A7:A0, CS, RD, WR, DACK, ALE, and ADSEL.
Applied to XIN, A7:A0, CS, RD, WR, DACK, ALE, and ADSEL.
Total currents when VCC3 and VCC5 are connected.
Total currents when VCC3 and VCC5 are connected.
The XIN pin is fixed at a high level or a low level in the suspend state.
All the output pins are open.
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PEDL60851C-02
¡ Semiconductor
ML60851C
DC Characteristics (2)
(VCC5 = 4.5 to 5.5 V, VCC3 = 3.0 to 3.6 V, Tj = 0 to 85°C)
Parameter
High-level Input
Voltage
Low-level Input
Voltage
Schmitt Trigger
Input Voltage
High-level
Output Voltage
Low-level
Output Voltage
High-level Input
Current
Low-level Input
Symbol
Condition
Min.
Typ.
Max.
Unit
VIH
—
2.2
—
VCC5 + 0.5
V
VIL
—
–0.5
—
+0.8
V
Vt+
—
—
1.7
2.2
V
Vt–
—
0.8
1.4
—
V
DVt
(Vt+) – (Vt–)
IOH = –100 mA
0.2
0.3
—
V
VCC5 – 0.2
—
—
V
IOH = –8 mA
3.7
—
—
V
IOL = 100 mA
—
—
0.2
V
IOL = 8 mA
—
—
0.4
V
VIH = VCC5
—
0.01
10
mA
Applicable pin
Note 1
VOH
VOL
IIH
RESET
D15:D8
AD7:AD0
INTR, DREQ
Note 2
IIL
VIL = 0 V
–10
–0.01
—
mA
IOZH
VOH = VCC5
—
0.01
10
mA
D15:D8
Leakage Current
IOZL
VOL = 0 V
–10
–0.01
—
mA
AD7:AD0
Power Supply
ICC3
—
—
—
50
mA
VCC3
Current (Operating)
ICC5
—
—
—
5
mA
VCC5
Current
3-state Output
Power Supply
ICCS3
Note 3
—
—
50
mA
VCC3
Current (Standby)
ICCS5
Note 3
—
—
50
mA
VCC5
Notes: 1. Applied to D15:D8, AD7:AD0, A7:A0, CS, RD, WR, DACK, ALE, and ADSEL. The DC
characteristics (1) applies to XIN.
2. Applied to A7:A0, CS, RD, WR, DACK, ALE, and ADSEL. The DC characteristics (1)
applies to XIN.
3. The XIN pin is fixed at a high level or a low level in the suspend state. All the output
pins are open.
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PEDL60851C-02
¡ Semiconductor
ML60851C
DC Characteristics (3) USB Port
(VCC3 = 3.0 to 3.6 V, Ta = 0 to 70°C)
Parameter
Differential Input
Sensitivity
Differential Common
Mode Range
Single Ended
Receiver Threshold
High-level Output
Voltage
Low-level Output
Voltage
Output Leakage
Current
Symbol
Condition
Min.
VDI
(D+) – (D–)
VCM
Includes VDI range
VSE
Typ.
Max.
Unit
0.2
—
V
0.8
2.5
V
0.8
2.0
V
Applicable pin
D+, D–
VOH
RL of 15 kW to GND
2.8
3.6
V
VOL
RL of 1.5 kW to 3.6 V
—
0.3
V
ILO
0 V < VIN < 3.3 V
–10
+10
mA
AC Characteristics USB Port
(VCC3 = 3.0 to 3.6 V, VSS = 0 V, Ta = 0 to 70°C)
Parameter
Symbol
Condition
(Notes 1. and 2.)
Min.
Typ.
Max.
Unit
Rise Time
tR
CL = 50 pF
4
20
ns
Fall Time
tF
CL = 50 pF
4
20
ns
tRFM
(tR/tF)
90
111.11
%
1.3
2
V
28
44
W
11.97
12.03
Mbps
Rise/Fall Time
Matching
Output Signal
Crossover Voltage
Driver Output
Resistance
Data Rate
VCRS
ZDRV
tDRATE
Steady State Driver
(Note 3)
Ave. Bit Rate
(12 Mbps ±0.25%)
Applicable pin
D+, D–
Notes: 1. 1.5 kW pull-up to 3.3 V on the D+ data line.
2. tR and tF are measured from 10% to 90% of the data signal.
3. Including an external resistance of 22 W ± 5% on the D+ and D– data lines.
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PEDL60851C-02
¡ Semiconductor
ML60851C
TIMING DIAGRAM
READ Timing (1)
(Address Separate, ADSEL = 0)
Min.
Max.
Unit
Note
Address Setup Time (RD)
Parameter
Symbol
t1 (RD)
Condition
21
—
ns
5
Address Setup Time (CS)
t1 (CS)
10
—
ns
5
Address (CS) Hold Time
t2
0
—
ns
2
1
Read Data Delay Time
t3
Load 20 pF
—
25
ns
Read Data Hold Time
t4
Load 20 pF
0
25
ns
Recovery Time
t5
FIFO READ
63
—
ns
3
FIFO Access Time
t6
FIFO READ
42
—
ns
4
Notes: 1. t3 is defined depending upon CS or RD which becomes active last.
2. t2 is defined depending upon CS or RD which becomes active first.
3. 3-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
4. 2-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
5. t1 is required for reading FIFO. t1 is defined when either t1(CS) or t1(RD) is satisfied.
A7:A0
t1
t2
t6
CS
t5
t3
RD
t4
AD7:AD0
DATA OUT
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¡ Semiconductor
ML60851C
READ Timing (2)
(Address/Data Multiplex, ADSEL = 1)
Parameter
Symbol
Condition
Min.
Max.
Unit
Address (CS) Setup Time
t1
10
—
ns
Address (CS) Hold Time
t2
0
—
ns
Note
Read Data Delay Time
t3
Load 20 pF
—
25
ns
Read Data Hold Time
t4
Load 20 pF
0
25
ns
Recovery Time
t5
FIFO READ
63
—
ns
1
FIFO Access Time
t6
FIFO READ
42
—
ns
2
Notes: 1. 3-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
2. 2-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
AD7:AD0
ADDRESS
t1
DATA OUT
t2
t4
CS
ALE
t3
t5
RD
t6
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¡ Semiconductor
ML60851C
WRITE Timing (1)
(Address Separate, ADSEL = 0)
Parameter
Symbol
Condition
Min.
Max.
Unit
Note
Address Setup Time
t1(a–w)
21
—
ns
1
Address Setup Time
t1 (a–c)
10
—
ns
1
Address (CS) Hold Time
t2
0
—
ns
CS Setup Time
t3
10
—
ns
Write Data Setup Time
t4
30
—
ns
Write Data Hold Time
t5
2
—
ns
Recovery Time
t6
FIFO WRITE
63
—
ns
2
FIFO Access Time
t7
FIFO WRITE
42
—
ns
3
Notes: 1.
2.
3.
4.
5.
Either t1(a–w) or t1(a–c) should be satisfied.
t1 is defined depending upon CS or WR which becomes active first.
3-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
2-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
Applied to all registers including CLRFIFO (address: 4Eh).
A7:A0
t1(a–w)
t2
t7
CS
t1(a–c)
t3
t6
WR
t4
AD7:AD0
t5
DATA IN
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PEDL60851C-02
¡ Semiconductor
ML60851C
WRITE Timing (2)
(Address/Data Multiplex, ADSEL = 1)
Parameter
Symbol
Address (CS) Setup Time
t1
Address (CS) Hold Time
t2
Write Data Setup Time
t3
Condition
Min.
Max.
Unit
10
—
ns
0
—
ns
30
—
ns
Note
Write Data Hold Time
t4
2
—
ns
Recovery Time
t5
FIFO WRITE
63
—
ns
1
FIFO Access Time
t6
FIFO WRITE
42
—
ns
2
Notes: 1. 3-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
2. 2-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
3. Applied to all registers including CLRFIFO (address: 4Eh).
AD7:AD0
ADDRESS
t1
DATA IN
t2
t4
CS
ALE
t3
t5
WR
t6
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¡ Semiconductor
ML60851C
DMA Transfer Timing (1)
ML60851C to Memory (Single Transfer, Single Address Mode)
Symbol
Condition
Min.
Max.
Unit
DREQ Disable Time
Parameter
t1
Load 20 pF
—
20
ns
DREQ Enable Time
t2
—
63
ns
0
—
ns
—
25
ns
Note
4
DACK Hold Time
t3
Read Data Delay Time
t4
Load 20 pF
Data Hold Time
t5
Load 20 pF
0
25
ns
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
Recovery Time
t6
1
Notes: 1. When in Single Address mode, CS and A7:A0 are ignored.
t1 and t4 are defined depending on DACK or RD which becomes active last.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
4. It is possible to increase t2 by setting the DMA interval register (DMAINTVL).
DREQ
t2
t3
t1
DACK
t4
t6
RD
t5
DOUT
DATA OUT
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PEDL60851C-02
¡ Semiconductor
ML60851C
DMA Transfer Timing (2)
ML60851C to Memory (Single Transfer, Dual Address Mode)
Symbol
Condition
Min.
Max.
Unit
DREQ Disable Time
Parameter
t1
Load 20 pF
—
20
ns
Note
DREQ Enable Time
t2
—
63
ns
4
Read Data Delay Time
t3
Load 20 pF
—
25
ns
1
Data Hold Time
t4
Load 20 pF
0
25
ns
Recovery Time
t5
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
Notes: 1. When in Dual Address mode, the DACK is ignored.
t1 and t3 are defined depending on CS or RD which becomes active last.
A7:A0 specifies the FIFO address.
Refer to READ Timing (1) for Address Setup Time and Address Hold Time.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
4. It is possible to increase t2 by setting the DMA interval register (DMAINTVL).
A7:A0
DREQ
CS
t2
t1
t5
t3
RD
t4
DOUT
DATA OUT
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PEDL60851C-02
¡ Semiconductor
ML60851C
DMA Transfer Timing (3)
ML60851C to Memory (Demand Transfer, Single Address Mode)
Symbol
Condition
Min.
Max.
Unit
DREQ Disable Time
Parameter
t1
Load 20 pF
—
20
ns
Note
DACK Hold Time
t2
0
—
ns
Read Data Delay Time
t3
Load 20 pF
—
25
ns
Data Hold Time
t4
Load 20 pF
0
25
ns
Recovery Time
t5
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
1
Notes: 1. When in Single Address mode, t3 is defined depending on DACK or RD which becomes
active last.
A7:A0 and CS are ignored.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
DREQ
t1
DACK
t5
t2
RD
t3
t4
Last Packet Read
DOUT
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PEDL60851C-02
¡ Semiconductor
ML60851C
DMA Transfer Timing (4)
ML60851C to Memory (Demand Transfer, Dual Address Mode)
Symbol
Condition
Min.
Max.
Unit
DREQ Disable Time
Parameter
t1
Load 20 pF
—
20
ns
CS Hold Time
t2
0
—
ns
Read Data Delay Time
t3
Load 20 pF
—
25
ns
Data Hold Time
t4
Load 20 pF
0
25
ns
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
Recovery Time
t5
Note
1
Notes: 1. When in Dual Address mode, the DACK is ignored.
t3 is defined depending on CS or RD which becomes active last.
A7:A0 specifies the FIFO address.
Refer to READ Timing (1) for Address Setup Time and Address Hold Time.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
A7:A0
DREQ
t1
CS
t5
t2
RD
t4
t3
Last Packet Read
DOUT
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PEDL60851C-02
¡ Semiconductor
ML60851C
DMA Transfer Timing (5)
Memory to ML60851C (Single Transfer, Single Address Mode)
Parameter
DREQ Disable Time
Symbol
Condition
Min.
Max.
Unit
t1
Load 20 pF
—
20
ns
—
63
ns
4
42
—
ns
1
DREQ Enable Time
t2
FIFO Access Time
t3
DACK Hold Time
t4
0
—
ns
Write Data Setup Time
t5
30
—
ns
Write Data Hold Time
t6
Recovery Time
Notes: 1.
2.
3.
4.
FIFO WRITE
t7
Note
2
—
ns
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
When in Single Address mode, CS and A7:A0 are ignored.
3-clock time of oscillation clock (clock period: 21 ns).
5-clock time of oscillation clock (clock period: 21 ns).
It is possible to increase t2 by setting the DMA interval register (DMAINTVL).
DREQ
t1
t4
t2
DACK
t3
t7
WR
t5
t6
DIN
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PEDL60851C-02
¡ Semiconductor
ML60851C
DMA Transfer Timing (6)
Memory to ML60851C (Single Transfer, Dual Address Mode)
Parameter
Symbol
Condition
Min.
Max.
Unit
DREQ Disable Time
t1
Load 20 pF
—
20
ns
DREQ Enable Time
t2
—
63
ns
4
FIFO Access Time
t3
42
—
ns
1
FIFO WRITE
Note
Write Data Setup Time
t4
30
—
ns
Write Data Hold Time
t5
2
—
ns
Recovery Time
t6
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
Notes: 1. When in Dual Address mode, the DACK is ignored.
t1 and t3 are defined depending on CS or WR which becomes active last.
Refer to WRITE Timing (1) for Address Setup Time and Address Hold Time.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
4. It is possible to increase t2 by setting the DMA interval register (DMAINTVL).
A7:A0
DREQ
t1
t2
CS
t6
t3
WR
t5
t4
DIN
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PEDL60851C-02
¡ Semiconductor
ML60851C
DMA Transfer Timing (7)
Memory to ML60851C (Demand Transfer, Single Address Mode)
Symbol
Condition
Min.
Max.
Unit
DREQ Disable Time
Parameter
t1
Load 20 pF
—
20
ns
FIFO Access Time
t2
FIFO WRITE
42
—
ns
DACK Hold Time
t3
0
—
ns
Note
1
Write Data Setup Time
t4
30
—
ns
Write Data Hold Time
t5
2
—
ns
Recovery Time
t6
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
Notes: 1. When in Single Address mode, A7:A0 and CS are ignored.
t2 is defined depending on DACK or WR which becomes active last.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
DREQ
t1
DACK
t2
t6
t3
WR
t4
t5
(Note)
Last Packet Write
DIN
(Note) The last Write to reach the byte size (maximum packet size) specified by the EP1 Payload
Register.
To terminate DMA transfer before reaching the maximum packet size, set EP1 Packet Ready
by writing "1" to the EP1 Endpoint Packet Ready bit.
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PEDL60851C-02
¡ Semiconductor
ML60851C
DMA Transfer Timing (8)
Memory to ML60851C (Demand Transfer, Dual Address Mode)
Parameter
Symbol
Condition
Min.
Max.
Unit
DREQ Disable Time
t1
Load 20 pF
—
20
ns
FIFO Access Time
t2
FIFO WRITE
42
—
ns
CS Hold Time
t3
0
—
ns
Write Data Setup Time
t4
30
—
ns
Write Data Hold Time
t5
Recovery Time
t6
Note
1
2
—
ns
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
Notes: 1. When in Dual Address mode, the DACK is ignored.
A7:A0 specifies the FIFO address.
Refer to WRITE Timing (1) for Address Setup Time and Address Hold Time.
t2 is defined depending on CS or WR which becomes active last.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
A7:A0
DREQ
t1
CS
t2
t6
t3
WR
t4
(Note)
t5
Last Packet Write
DIN
(Note) Refer to the previous page.
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PEDL60851C-02
¡ Semiconductor
ML60851C
FUNCTIONAL DESCRIPTIONS
Pin Functional Description
USB Interface
Signal
Type Assertion
Description
USB data (Plus). This signal and the D– signal are the transmitted or received
data from/to USB Bus. The table below shows values and results for these signals.
D+
I/O
—
D+
D–
Result
0
0
Single end 0
0
1
Differential "0"
1
0
Differential "1"
1
1
Undefined
USB Data (Minus). This signal and the D+ signal are the transmitted or
D–
I/O
—
received data from/to USB Bus. The table above shows values and results for
these signals.
Crystal Oscillator Interface
Signal
XIN
XOUT
Type Assertion
I
O
—
—
Description
For internal oscillation, connect a crystal to XIN and XOUT.
For external oscillation, supply an external 48 MHz clock signal to XIN.
Set XOUT to be open.
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¡ Semiconductor
ML60851C
Application Interface
Signal
Type Assertion
D15:D8
I/O
—
AD7:AD0
I/O
—
Description
Upper byte (MSB) of data bus. This data bus is used by applications to access
register files and FIFO data.
Lower byte (LSB) of data bus when ADSEL is LOW.
Address and lower byte of data bus are multiplexed when ADSEL is HIGH.
Address when ADSEL is LOW. This address signal is used by application to
A7:A0
I
—
access register files and FIFO data.
This signal is ignored (all lows or all highs) when ADSEL is HIGH.
CS
I
LOW
RD
I
LOW
WR
I
LOW
INTR
O
LOW
(Note 1)
LOW
DREQ
O
DACK
I
ALE
I
—
ADSEL
I
—
Chip Select. When this signal is asserted LOW, the ML60851C is selected
and ready to read or write data.
Read Strobe. When this signal is asserted LOW, the Read instruction is
executed.
Write Strobe. When this signal is asserted LOW, the Write instruction is
executed.
Interrupt Request. When this signal is asserted, the ML60851C makes an
interrupt request to the application.
DMA Request. This signal requests the Endpoint FIFO to make a DMA transfer.
(Note 1)
HIGH
(Note 1)
DMA Acknowledge Signal. This signal, when asserted, enables accessing
FIFOs, without address bus setting.
When ADSEL is HIGH, the address and CS on AD7:AD0 is latched at the
trailing edge of this signal. This signal is ignored when ADSEL is LOW.
When ADSEL is LOW, the address is input on A7:A0 and data is input on
D15:D8 and AD7:AD0. When ADSEL is HIGH, the lower bytes (LSB) of
address and data are multiplexed on AD7:AD0.
RESET
I
LOW
System Reset. When this signal is asserted LOW, the ML60851C is reset.
When the ML60851C is powered on, this signal must be asserted for 1 ms or more.
Note: 1. Initial value immediately after resetting. Its assertion can be changed by programming.
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¡ Semiconductor
ML60851C
Functional Description
The ML60851C USB device controller contains the Protocol Engine, DPLL, Timer, Status/Control,
FIFO Control, Application Interface, and Remote Wakeup blocks.
• Protocol Engine
The Protocol Engine handles the USB communication protocol. It performs control of packet
transmission/reception, generation/detection of synchronous patterns, CRC generation/checking,
NRZI data modulation, bit stuffing, and packet ID (PID) generation/checking.
• DPLL (Digital Phase Locked Loop)
The DPLL extracts clock and data from the USB differential received data (D+ and D–).
• Timer
The Timer block monitors idle time on the USB bus.
• Status/Control
The Status Control block moniors the transaction status and transmits control events to the
application through an interrupt request.
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¡ Semiconductor
ML60851C
• FIFO Control
The FIFO Control block controls all FIFO operations for transmitting and receiving USB packets.
The FIFO configuration is described below.
Endpoint FIFO/8-Byte Setup Register Configuration
For Control Transfer
8-Byte
Endpoint Address 0
Setup Register
Setup Ready
8-Byte
Endpoint Address 0
EP0 Receive FIFO
FIFO Rx
Packet Ready
8-Byte
Endpoint Address 0
EP0 Transmit FIFO
FIFO Tx
Packet Ready
For Bulk Transfer
64-Byte
FIFO
Packet Ready
EP1 FIFO (128 bytes)
DMA Request
(Selectable for transmitter
or receiver)
64-Byte
Endpoint Address 1
FIFO
EP2 FIFO (64 bytes)
64-Byte
Endpoint Address 2
(Selectable for transmitter
FIFO
or receiver)
Packet Ready
8-Byte
Endpoint Address 3
EP3 FIFO (8 bytes)
FIFO
Packet Ready
FIFO type
Endpoint address
Program size
Function
Reception
0
8 Bytes
Transfer control
Transmission
0
8 Bytes
Transfer control
Reception/Transmission
1
64 Bytes (2 levels)
Bulk-In and bulk-Out
Reception/Transmission
2
64 Bytes
Bulk-Out and bulk-In
Transmission
3
8 Bytes
Interrupt
Every FIFO has a flag that indicates a full or empty FIFO and the capability of re-transmitting and
re-receiving data. Endpoint addresses 1 and 2 can be used for either of reception and transmission
by writing the register.
The FIFO at endpoint address 1 can be used for DMA transfer.
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¡ Semiconductor
ML60851C
• Interrupt
Interrupt factors include Packet Ready for a transmit/receive FIFO, Setup Ready for 8-byte setup
data, and Suspend. Generation of each interrupt request can be enabled or disabled by the
Interrupt Enable register.
• DMA
8-bit and 16-bit demand transfer DMA and single transfer DMA are enabled for bulk-transfer FIFO
at endpoint address 1.
In Demand Transfer mode, DREQ is asserted when a valid packet arrives at the FIFO. When the
external DMA contoller has completed transferring all byte data of a received packet, DREQ is
deasserted. Accordingly, other devices cannot access the local bus during DMA transfer.
In Single Tranfer mode, each time transfer of one byte data is completed, DREQ is deasserted.
While DREQ is deasserted, other devices can access the local bus.
• Remote Wakeup
This functional block supports the remote wakeup function.
• USB Transfers
The ML60851C supports the two transfer types (Control Transfer and Bulk Transfer) of four
transfer types (Control, Isochronous, Interrupt, and Bulk) defined by the USB Specifications.
- The Control Transfer is required for transfer of configuration, commands, and status information
between the host and devices.
- The Bulk Transfer enables transfer of a large amount of data when the bus bandwidth is enough.
• USB Transceiver
The ML60851C contains an Oki's USB transceiver which converts internal unidirectional signals
into USB-compatible signals.
This enables the designer's application module to interface to the physical layer of the USB.
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PEDL60851C-02
¡ Semiconductor
ML60851C
EXAMPLE OF OSCILLATOR CIRCUIT
• Oscillation Circuit Example 1
ML60851C
XIN
Rf
C2
XOUT
C3
L1
Crystal: HC-49U (KINSEKI, LTD)
C2 = 5 pF
C3 = 1000 pF
Rf = 1 MW
L1 = 2.2 mH
Note: The example shown above is not guaranteed for circuit operation.
• Oscillation Circuit Example 2
CSTCW4800MX41xxx
ML60851C
XIN
Rf
XOUT
Ceramic oscillator: CSTCM4800MXxxx (MURATA MFG.)
(C-built-in type)
Note: The example shown above is not guaranteed for circuit operation.
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PEDL60851C-02
¡ Semiconductor
ML60851C
PACKAGE DIMENSIONS
(Unit : mm)
QFP44-P-910-0.80-2K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Epoxy resin
42 alloy
Solder plating
5 mm or more
Package weight (g)
0.41 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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PEDL60851C-02
¡ Semiconductor
ML60851C
(Unit : mm)
TQFP44-P-1010-0.80-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.28 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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