TI MPA4609IPFBR Quad, differential i/o, 2x1 multiplexed high gain preamp Datasheet

MPA4609
MP
A46
09
SBOS252D – AUGUST 2002 – REVISED MARCH 2005
Quad, Differential I/O, 2X1 Multiplexed
High Gain Preamp
FEATURES
DESCRIPTION
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The MPA4609 is one of the lowest noise, fixed gain, 5V
single-supply, differential amplifiers available for amplification of low-level signals in a variety of system applications.
The chip has two sets of four differential input, low-noise
amplifiers that are routed to four output stages. Two standard
logic input select lines control which set of four input preamps
are active. For applications such as tape recorders, four
heads in forward and four heads in reverse can be selected
at one time.
4 DIFFERENTIAL OUTPUT CHANNELS
2 SETS OF 4 DIFFERENTIAL INPUTS
90MHz BANDWIDTH UP TO 3.5VPP OUTPUT
GAIN OF 190V/V (No External Load)
LOW 0.65nV/√Hz INPUT NOISE VOLTAGE
50mA QUIESCENT CURRENT (5V Supply)
LOW CROSSTALK, TQFP-48 PACKAGING
TTL/CMOS CHANNEL SELECT LINE
APPLICATIONS
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TAPE PREAMP
TEST EQUIPMENT
MULTI-CHANNEL TWISTED PAIR RECEIVER
SAW FILTER POSTAMPLIFIER
HIGH GAIN QUAD ADC DRIVERS
ULTRA SOUND PRE-AMPLIFIERS
RELATED PARTS
PART NUMBER
DESCRIPTION
OPA2846
Dual, Low-Noise Op Amp
ADS5121
Octal, 10-Bit 40MSPS ADC
The quad consists of eight differential low noise (0.65nV√Hz)
voltage preamps. Two select lines control two pairs of inputs.
Each of the output stages provides a nominal 470Ω-output
impedance on each half of the differential output stages. The
overall gain of 190V/V may be attenuated by adding an
external load resistor between each set of differential outputs. For example, adding an external 940Ω resistor across
the output pins will reduce the nominal differential gain by
half to 95V/V.
Internal biasing controls the differential inputs to 2.0V and
outputs to a 2.1V common-mode operating level. The maximum no-load differential output swing is 3.5VPP centered on
the 2.1V bias level. A low input offset voltage and bias
current offset holds the maximum output differential offset to
< ±350mV for no-load conditions.
The low (3.5pF) input capacitance makes this part useable
for applications requiring wide bandwidth and multiple pickups often seen in testers, medical equipment, twisted pair
receivers, and optical systems. The single +5V supply and its
low quiescent current of 50mA make it exceptionally attractive in multi-channel, low power, high bandwidth designs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2002-2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Power Supply ...................................................................................... +7V
Internal Power Dissipation ............................................................. 750mW
Differential Input Voltage .................................................................. ±1.2V
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Input Voltage Range .............................................................. GND to +VS
Storage Temperature Range: PFB ................................ –40°C to +125°C
Junction Temperature (TJ) ............................................................ +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
ESD Rating (Human Body Model) .................................................. 3000V
(Charge Device Model) ............................................... 1500V
(Machine Model) ........................................................... 200V
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
MPA4609IPFBT
MPA4609IPFBR
Tape and Reel, 250
Tape and Reel, 2000
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
MPA4609
TQFP-48
PFB
–40°C to +85°C
MPA4609
"
"
"
"
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at
www.ti.com.
Forward
AINF+
3kΩ
VCM
470Ω
470Ω
470Ω
Output
Amp
Output
Amp
Output
Amp
Output
Amp
VCM
VCM
VCM
VCM
Read
Amp
+5V
470Ω
DOUT+ DOUT–
470Ω
COUT+ COUT–
470Ω
BOUT+ BOUT–
470Ω
MPA4609
AOUT+ AOUT–
470Ω
BLOCK DIAGRAM
Reverse
Read
Amp
3kΩ
AINR+
3kΩ
VCM
3kΩ
AINF–
AINR–
BINF+
BINR+
3kΩ
VCM
Read
Amp
Read
Amp
3kΩ
3kΩ
VCM
3kΩ
BINF–
BINR–
CINF+
CINR+
3kΩ
VCM
Read
Amp
Read
Amp
3kΩ
3kΩ
VCM
3kΩ
CINF–
CINR–
DINF+
DINR+
3kΩ
VCM
Read
Amp
Read
Amp
3kΩ
DINF–
3kΩ
VCM
3kΩ
2.1V
VCM
DINR–
Band Gap
Reference
Common-Mode
Reference
FWD/REV (Pin 3)
2
FWD/REV (Pin 34)
MPA4609
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SBOS252D
ELECTRICAL CHARACTERISTICS: VS = +5.0V
Boldface limits are tested at +25°C.
At TA = +25°C, RS = 65Ω (differential), VICM = 2.0, VOCM = 2.1V, RL > 2kΩ,unless otherwise noted.
MPA4609IPFB
TYP
DC PERFORMANCE(3)
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Forward/Reverse Gain Match
INPUT
Minimum Common-Mode Input Voltage(4)
Maximum Common-Mode Input Voltage(4)
Input Bias Resistor
Input Bias Resistor Tolerance
Input Differential Capacitance
Minimum Common-Mode Bias Voltage
Maximum Common-Mode Bias Voltage
Common-Mode Rejection Ratio (DC)
OUTPUT
Output Offset Voltage
Minimum Common-Mode Output Voltage
Maximum Common-Mode Output Voltage
Maximum Differential Output Voltage Swing
Single Ended Output Impedance
Single Ended Output Impedance Tolerance
CHANNEL SELECT (F/R)
Highest Logic Low Level
Lowest Logic High Level
Logic Low Input Bias Current (each pin)
Logic High Input Bias Current (each pin)
Channel Switching Time
Output Differential Glitch in Switching
Unselected Channel Feedthrough
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage
Minimum Operating Voltage
Maximum Quiescent Supply Current
Minimum Quiescent Supply Current
Power Supply Rejection Ratio (DC)
TEMPERATURE RANGE
Specification: I
Thermal Resistance, θJA
PFB TQFP-48
TEST
MIN/MAX LEVEL(2)
CONDITION
+25°C
+25°C
0 to +70°C
UNITS
VO = 500mVPP, no load
= 200mVPP (DC to 20MHz)
= 200mVPP (DC to 20MHz)
= 200mVPP (DC to 20MHz)
= 200mVPP (DC to 20MHz)
No Load, VO = 3VPP
±250mV Step
10MHz, 2VPP Output
F > 100kHz
F > 100kHz
F = 5MHz, CH A measured,
CH B, C, D driven RL = open
90
95
95
190
190
150
3.5
–64
0.65
3.8
80
78
115
160
220
75
65
120
140
240
4.4
4.7
0.80
5.1
0.85
5.7
MHz
V/V
V/V
V/V
V/V
V/µsec
nsec
dBc
nV/√Hz
pA/√Hz
min
min
max
min
max
typ
min
typ
max
max
B
A
A
A
A
C
B
C
B
B
dBc
typ
C
VICM = 2.0V nominal (internally set)
±0.2
±0.9
–70
Channel Pairs
–51
±0.25
±2.3
±0.95
±1
–75
±10
±11
mV
µV/°C
µA
µA
%
max
max
max
typ
max
A
B
A
C
A
Externally Applied (CMIR)
Externally Applied (CMIR)
Each Input to VCM
1.3
2.3
3000
1.4
2.3
1.5
2.2
±15
±16
1.85
2.15
25
1.75
2.25
24
V
V
Ω
%
pF
V
V
dB
min
max
typ
max
typ
min
max
min
A
A
C
A
C
A
A
A
±350
1.95
2.25
2.8
±450
1.85
2.35
2.6
±15
±16
mV
V
V
Vpp
Ω
%
max
min
max
min
typ
max
A
A
A
A
C
A
0.9
1.6
0.9
1.6
–36
–36
V
V
µA
µA
nsec
mV
dB
max
min
typ
typ
typ
typ
max
A
A
C
C
C
C
A
6.0
4.5
52
46
34
6.0
4.5
59
42
33
V
V
V
mA
mA
dB
typ
max
min
max
min
min
C
A
A
A
A
A
–40 to +85°C
°C
typ
C
60
°C/W
typ
C
PARAMETER
AC PERFORMANCE (Figure 1)
Large Signal Bandwidth,
Minimum Midband Gain [RL = 940Ω]
Maximum Midband Gain [RL = 940Ω]
Minimum Open Load Gain
Maximum Open Load Gain
Differential Slew Rate
Differential Rise/Fall Time
Total Harmonic Distortion
Input Noise Voltage (differential)
Input Noise Current (each input)
Channel-To-Channel X-talk (Input → Output)
MIN/MAX OVER TEMPERATURE(1)
VO
VO
VO
VO
Internal Reference
Internal Reference
RL = open, Common-Mode
Input to Differential Output
RL open, Inputs Open
VOCM = 2.1V, RL = open
TTL/CMOS Compatible
Logic Low = REV Channels
Logic High = FOR Channels
F/R pins = 0V
F/R pins = 5V
All Inputs, 65Ω Differential Source
All Channel Pairs,
Unselected Input (±100mV) to Output
–55
3.5
2
2
36
±40
2.1
2.1
3.5
470
1.0
1.5
70
1
50
±15
–50
5
VS = +5V
VS = +5V
RL = open, Power Supply (±250mV)
to Differential Output
49
49
50
Junction-to-Ambient
NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature
+15°C at high temperature limit specifications.
(2) Test Levels:
(A) 100% DC tested at +25°C. Over-temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation.
(C) Typical value only for information.
(3) Current is considered positive out-of-node. VCM is the input and output common-mode voltage.
(4) Tested < 3dB below minimum specified CMRR at CMIR limits.
MPA4609
SBOS252D
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3
BinR+
NC
GND
BinF–
BinF+
NC
NC
AinF+
AinF–
GND
NC
AinR+
PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
BinR–
1
36 AinR–
NC
2
35 NC
F/R
3
34 F/R
Bout+
4
33 Aout+
Bout–
5
32 Aout–
NC
6
NC
7
30 NC
Dout–
8
29 Cout–
Dout+
9
28 Cout+
31 NC
MPA4609IPFB
VCC 10
27 VCC
NC 11
26 NC
17
18
19
20
GND
DinF–
DinF+
NC
NC
CinF+
21
22
23
24
CinR+
16
NC
15
GND
14
CinF–
13
NC
25 CinR–
DinR+
DinR– 12
PIN DESCRIPTIONS
PIN
NAME
TYPE
1
BinR–
A(1)
2
NC
3
F/R
D
DESCRIPTION
PIN
NAME
TYPE
A
B –Channel Reverse Inverting Input
25
CinR–
Internally Not Connected - may be grounded
26
NC
Forward or Reverse Channel Select Line
Ch. B and Ch. D
27
VCC
P
Supply Voltage (+5V nominal)
28
Cout+
A
C –Channel Non-Inverting Output
29
Cout–
A
30
NC
4
Bout+
A
B –Channel Non-Inverting Output
5
Bout–
A
B –Channel Inverting Output
6
NC
Internally Not Connected - may be grounded
7
NC
Internally Not Connected - may be grounded
8
Dout–
9
Dout+
A
D –Channel Non-Inverting Output
10
VCC
P
Supply Voltage (+5V nominal)
11
NC
12
DinR–
13
DinR+
A
D –Channel Inverting Output
Internally Not Connected - may be grounded
A
A
DESCRIPTION
D –Channel Reverse Inverting Input
D –Channel Reverse Non-Inverting Input
Internally Not Connected - may be grounded
C –Channel Reverse Inverting Input
Internally Not Connected - may be grounded
C –Channel Inverting Output
Internally Not Connected - may be grounded
31
NC
32
Aout–
A
Internally Not Connected - may be grounded
A –Channel Inverting Output
33
Aout+
A
A –Channel Non-Inverting Output
34
F/R
D
35
NC
Forward or Reverse Channel Select Line
Internally Not Connected - may be grounded
36
AinR–
A
37
AinR+
A
38
NC
A –Channel Reverse Inverting Input
A –Channel Reverse Non-Inverting Input
Internally Not Connected - may be grounded
14
NC
15
GND
G
Ground
39
GND
G
Ground
16
DinF–
A
D –Channel Forward Inverting Input
40
AinF–
A
A –Channel Forward Inverting Input
17
DinF+
A
D –Channel Forward Non-Inverting Input
41
AinF+
A
18
NC
Internally Not Connected - may be grounded
42
NC
A –Channel Forward Non-Inverting Input
Internally Not Connected - may be grounded
19
NC
Internally Not Connected - may be grounded
43
NC
20
CinF+
A
C –Channel Forward Non-Inverting Input
44
BinF+
A
B –Channel Forward Non-Inverting Input
21
CinF–
A
C –Channel Forward Inverting Input
45
BinF–
A
B –Channel Forward Inverting Input
22
GND
G
G
23
NC
24
CinR+
A
Ground
46
GND
Internally Not Connected - may be grounded
47
NC
C –Channel Reverse Non-Inverting Input
48
BinR+
Internally Not Connected - may be grounded
Ground
Internally Not Connected - may be grounded
A
B –Channel Reverse Non-Inverting Input
NOTE: (1) Pin Types: A (analog), D (digital), G (ground), P (power supply).
4
MPA4609
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SBOS252D
TYPICAL CHARACTERISTICS: VS = +5V
TA = +25°C, RS = 65Ω (differential), VICM = 2.0V, VOCM = 2.1V, RL > 2kΩ, unless otherwise noted.
FREQUENCY RESPONSE
TYPICAL GAIN DISTRIBUTION
46.6
600
G = 190V/V Typical
45.6
303 Parts with 8 Gain
Measurements
on Each Part.
Total Count 2424
Mean = 182V/V
Standard Deviation = 7V/V
500
VO = 100mVPP → 3VPP
400
Count
Gain (dB)
44.6
43.6
42.6
300
200
41.6
100
See Figure 1
40.6
Frequency (MHz)
200
500
150
450
Large Signal
1.0
100
0.5
50
0
0
Small Signal
→ Right Scale
–50
–1.0
–100
–1.5
–150
220
214
208
202
303 Parts
with 4 Channel Pairs
on Each Part
Total Count 1212
Mean = 0
Standard Deviation = 0.19dB
400
350
Count
← Left Scale
Output Voltage (mV)
Output Voltage (V)
196
TYPICAL FORWARD/REVERSE CHANNEL
GAIN MISMATCH
2.0
–0.5
190
Gain (V/V)
DIFFERENTIAL PULSE RESPONSE
1.5
184
178
172
100
160
10
166
0
1
300
250
200
150
100
50
See Figure 1
–200
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Time (5ns/div)
–0.2
–0.1
0
0.1
0.2
0
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–2.0
Gain Mismatch (dB)
FORWARD/REVERSE CHANNEL FEEDTHROUGH
0
IN = 3.8pA/√Hz Each Input
Reverse Input Selected
Forward Input Driven
–10
Feedthrough (dB)
Input Differential Voltage Noise (nV/√Hz)
Input Current Noise (pA/√Hz)
INPUT VOLTAGE AND CURRENT NOISE DENSITY
10
1
Differential EN = 0.65nV/√Hz
–20
–30
–40
Forward Input Selected
Reverse Input Driven
–50
–60
See Figure 1
0.1
0.004 0.01
–70
0.1
1
10
40
1
Frequency (MHz)
MPA4609
SBOS252D
10
100
Frequency (MHz)
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5
TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
TA = +25°C, RS = 65Ω (differential), VICM = 2.0V, VOCM = 2.1V, RL > 2kΩ, unless otherwise noted.
5MHz HARMONIC DISTORTION vs OUTPUT VOLTAGE
20MHz HARMONIC DISTORTION vs OUTPUT VOLTAGE
–50
–60
3rd-Harmonic
–65
2nd-Harmonic
–70
–75
–80
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–55
–55
–60
2nd-Harmonic
–65
3rd-Harmonic
–70
–75
See Figure 1
See Figure 1
–85
–80
0.5
1.0
1.5
2.0
2.5
3.0
0.5
Intercept Point (+dBm)
Harmonic Distortion (dBc)
38
–65
–70
–75
2nd-Harmonic
36
34
32
30
26
470Ω
500Ω
PO
20
0.5
1
10
0
20
5
10
15
20
25
30
35
40
45
50
Frequency (MHz)
Frequency (MHz)
FORWARD/REVERSE SWITCHING TIME
FORWARD/REVERSE SWITCHING GLITCH
3.5
20
Forward/Reverse Select Line
Both Forward/Reverse Inputs with
68Ω Across Inputs, No Signal
135kHz Forward/Reverse
Select Squarewave
15
2.5
2.0
10
Differential Output Voltage
For. Channel Input = +5.8mV
0.5
VOUT (mV)
Output and Channel Select Voltage (V)
PI
22
See Figure 1
–85
5
0
0
–5
Reverse Channel Input
= –5.8mV
–1.5
–10
Time (100ns/div)
6
470Ω
28
24
–80
–1.0
3.0
40
3rd-Harmonic
–0.5
2.5
2-TONE, 3RD-ORDER INTERMODULATION
INTERCEPT 500Ω LOAD
–60
1.0
2.0
HARMONIC DISTORTION vs FREQUENCY
VO = 2VPP
1.5
1.5
Output Voltage (VPP)
–55
3.0
1.0
Output Voltage (VPP)
Time (1µs/div)
MPA4609
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SBOS252D
TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
TA = +25°C, RS = 65Ω (differential), VICM = 2.0V, VOCM = 2.1V, RL > 2kΩ, unless otherwise noted.
COMMON-MODE REJECTION RATIO AND
POWER-SUPPLY REJECTION RATIO
vs FREQUENCY
ALL HOSTILE CROSSTALK
60
–30
Three Input Channels Driven
Undriven Channel Measured
at Output
–40
Crosstalk (dB)
PSRR
50
Forward
CMRR and PSRR to
Differential Output (dB)
–35
–45
–50
Reverse
–55
40
CMRR
30
20
10
–60
0
–65
1
10
0.1
100
1
10
100
Frequency (MHz)
Frequency (MHz)
OVERDRIVE RECOVERY
OVERDRIVE RECOVERY TIME
vs OVERDRIVE LEVEL
20
4
190 * VIN
Overdrive Recovery Time (ns)
VOUT and VOUT (V)
3
2
1
Differential
Output
Voltage
0
–1
–2
18
16
14
12
10
–3
8
–4
0
Time (500ns/div)
10
20
30
40
50
60
70
80
Input Overdrive Level (mV)
TYPICAL OPEN LOAD GAIN vs TEMPERATURE
200
198
195
196
190
194
185
Gain (V/V)
Gain (V/V)
GAIN vs SUPPLY VOLTAGE
200
192
190
188
180
175
170
186
165
184
160
182
155
180
150
4.5
5.0
5.5
See Figure 1
–55
6.0
–35
–15
5
25
45
65
85
105
125
Ambient Temperature (°C)
Supply Voltage (V)
MPA4609
SBOS252D
5 Units, 1 Channel/Each
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7
TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
TA = +25°C, RS = 65Ω (differential), VICM = 2.0V, VOCM = 2.1V, RL > 2kΩ, unless otherwise noted.
INPUT AND OUTPUT COMMON-MODE VOLTAGE
vs TEMPERATURE
2.15
5 Units
58
56
2.11
Supply Current (mA)
VCM (Input and Output) (V)
2.13
TYPICAL SUPPLY CURRENT vs TEMPERATURE
60
5 Units, 1 Channel/Each
Output Lines
2.09
2.07
2.05
2.03
Input Lines
2.01
54
52
50
48
46
1.99
44
1.97
42
1.95
40
–55
–35
–15
5
25
45
65
85
105
125
See Figure 1
–55
–35
–15
Ambient Temperature (°C)
TYPICAL OUTPUT OFFSET
VOLTAGE DISTRIBUTION
25
Output Common-Mode Voltage (V)
Mean = 27mV
Standard Deviation = 48mV
400
350
300
303 Parts
with 8 Output Offset
Measurements on Each
Total Count 2424
250
200
45
65
85
105
125
OUTPUT COMMON-MODE LOOP RECOVERY
2.6
450
Count
5
Ambient Temperature (°C)
150
100
50
Output
Common-mode
Voltage
2.5
2.4
2.3
2.2
Input 2X Overdrive Signal
Differential Input 0 → 40mV
2.1
2.0
1.9
1.8
0
–200
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
20
40
60
80
100
120
140
160
180
200
Time (5ns/div)
Output Offset Voltage (mV)
COMMON-MODE VO vs INPUT VCM
FORWARD/REVERSE CHANNEL SELECT CURRENT
2.15
80
Current considered positive
out of device pin.
70
2.13
Output VCM (V)
Current (µA)
60
50
Current for 1 of 2 control pins.
Double this for total current
sinking requirements of source
logic if pins 3 and 34 tied together.
40
30
20
2.11
2.09
2.07
10
2.05
0
0
1
2
3
4
1.3
5
8
1.5
1.7
1.9
2.1
2.3
Input VCM (V)
Channel Select Pin Voltage
MPA4609
www.ti.com
SBOS252D
APPLICATIONS INFORMATION
DIFFERENTIAL FIXED GAIN AMPLIFIER OPERATION
The MPA4609 consists of four pairs of two-channel, lownoise, differential input stages that can be selected using a
pair of digital control pins. These two pins, F/R, are intended
to switch 4 differential preamps from the forward tape head
to the reverse tape head in a tape preamp application. This
multiplexing capability can be used in other applications as
well. Where a high gain, quad differential output is required,
one set of inputs can be used for signal transmission while
the other set can be applied as a reference signal input or as
a simple look-away during high overdrive conditions on the
signal input. Channel switching is a fast 50ns.
Figure 1 shows the internal configuration for 1 of 4 channels
along with a simplified external configuration used for test.
Since the MPA4609 is such a high gain device, the input
signal is typically attenuated for test purposes at the input
through a resistive divider network that matches the source
and provides a 65Ω differential source impedance looking
out of the inputs. Those are not shown in Figure 1, but some
input signal interface components were typically present
when the Typical Characteristics curves were taken.
All input pins are DC-biased from an internal 2.1V bandgap
reference through 3kΩ resistors. In application, the total AC
source impedance is dominated by the low source impedance of the head, giving a minimal gain for the input current
noise terms. For a low output DC offset, very low input
+5V
2.2µF
+
voltage offset and bias current offset terms are required. The
±0.8mV maximum input offset voltage along with the ±0.25µA
typical input bias current offset give a low total output DC
differential offset voltage. AC loading for the source is minimal given the low 3.5pF differential input capacitance looking
into each of the 8 inputs.
Channel select is provided in the 1st stage of the amplifier.
The unselected input stage is biased down. The output stage
includes a common-mode control loop referenced to the 2.1V
internal bandgap reference. Output swings specified in the
Specifications and Characteristics are at the internal nodes
(V′O) prior to the series 470Ω resistors provided in each
output leg. These resistors provide an easy way to adjust the
overall differential gain by including an external RL. However,
it is the internal output swing (V′O) that matters in setting the
limits to performance.
The 2.1V I/O DC bias voltage is intended to retain maximum
differential output voltage swing when the nominal +5V single
supply drops as low as +4.5V. Each output can swing ±0.75V
around this bias giving a maximum 3VPP differential signal at
V′O. This 3VPP available swing is adequate to support most
differential ADC input ranges. The series 470Ω output resistors also provide an easy means to bandlimit at the input of
the ADC with a single capacitor. Input signals that require DC
coupling can override the input common-mode reference
over the specified 1.4 to 2.3V input common-mode range
limits at 25°C.
VS
0.1µF
MPA4609
1 of 4 Channel Pairs
1:1
RS = 65Ω
3kΩ
VI
2.1V
VCM
Forward
G = 190V/V
3kΩ
470Ω
Channel
Select
F/R
VCM
2.1V
VO′ 470Ω
RL
VO
1:1
RS = 65Ω
3kΩ
VI
2.1V
VCM
Reverse
G = 190V/V
3kΩ
FIGURE 1. Typical Test Circuit for 1 of 4 Channel Pairs.
MPA4609
SBOS252D
www.ti.com
9
CHANNEL SELECT
TWISTED PAIR RECEIVER
Two pins are provided to switch between input channels. Pin
3 controls channels B and D while pin 34 controls channels
A and C. These are normally tied together for tape preamp
applications but can be operated separately if the application
requires it. The channel select is a voltage control that
switches at approximately 1.25V. Voltages less than 0.9V
are guaranteed to select the REV channel while voltages >
1.6V will select the FOR channel. This allows a direct
interface to 3.3V (or lower) logic outputs. Virtually no pin
current is required in the logic high state while a low 70µA/
pin out of the pin is required in the logic low state. Left
unconnected, the channel select defaults to the forward
selection.
The extremely high gain and low input noise of the MPA4609
can provide a very capable, multi-channel, twisted pair receiver. This would be particularly useful for narrowband
higher frequency carriers that suffer from significant cable
loss. For broadband carriers, a high-pass filter should be
included to reduce the low frequency receiver power. Since
the MPA4609 provides a gain constant over frequency, the
lower frequency region, that does not have as much loss in
the twisted pair as the higher frequencies, can easily overdrive the output without the high-pass filter present.
The channels switch in approximately 50ns typically. With no
input present, there is minimal output glitching when switched.
CONNECTING TO LOW IMPEDANCE MR
HEADS FOR TAPE RECORDERS
The MPA4609 is designed to detect and amplify the voltage
signal from a Magneto Resistive (MR) head with minimal
SNR degradation from the SNR intrinsic to the head. A
typical MR head interface is shown in Figure 2. Not considering any postfiltering, the amplifier’s 0.65nV/√Hz input noise
voltage and 90MHz bandwidth combine to produce a very
low 7.7µVRMS input referred noise floor. Even with a conservative 20dB S/N margin, input signals as low as 77µVPP may
be detected. With a maximum differential output of 3VPP and
a 190V/V gain, a maximum input of 15.7mVPP may be
applied. This wide range of inputs translates into 46dB input
dynamic range. Since the MR head is biased through external voltages, it is often required to connect the signal through
series blocking capacitors as shown in Figure 2. The highpass pole created by these capacitors (CB) and the source
resistance are selected to pass the lowest frequencies required by the system.
HIGH PERFORMANCE QUAD ADC DRIVER
The high gain, wide bandwidth, capability of the MPA4609
can provide a very cost effective input stage to quad high
performance ADCs. Figure 3 shows an example implementation where a 2nd-order passive low-pass filter has been
included in the interface to bandlimit the noise. The filter in
this example is set to approximately 18MHz cutoff with a
Butterworth (maximally flat) response including the internal
470Ω output resistors in the design. The distortion performance of the MPA4609 will support up to 10-bit converters
through approximately 10MHz maximum input analog frequency. For a 2VPP output, the THD shown in the Typical
Characteristic Curves is ≤ 63dBc through 10MHz. The 18MHz
Butterworth filter limits the noise power bandwidth for
the amplifier output noise to approximately 20MHz. With a
0.65nV/√Hz input voltage noise and 190V/V nominal gain,
this 124nV/√Hz output noise integrates to approximately
555µVRMS at the differential input of the converter. This RMS
noise is approximately 1/2 of an LSB for a 2VPP full-scale
input range.
+5V
470Ω
+VB
Input
RBIAS
CB
5.9µH
470Ω
CB
MR
Element
1/4
MPA4609
5.9µH
67pF
Quad
8→ 10 Bit
ADC
1 of 4
Channels
18MHz, 2nd-Order
Butterworth Filter
Preamp
RBIAS
FIGURE 3. Quad, ADC Input Driver.
FIGURE 2. Typical MR Head Interface.
10
MPA4609
www.ti.com
SBOS252D
The example here does not take advantage of the two sets
of multiplexed inputs on each of the four channels. The
second input could be used for simple input multiplexing; for
instance, where the source signal is fed through two different
filters, then selected at the MPA4609, or as a test signal
input. Another good application of this second input is to
provide an attenuated version of the input present on one
stage where additional input dynamic range is required. The
example of Figure 4 shows the configuration for the input
stages were an added 20dB attenuation is taken in the lower
channel. The total differential input impedance of this circuit
is 200Ω where each input presents a 400Ω differential load.
The shunt resistor has been adjusted up slightly to account
for the internal 6kΩ differential load across the inputs as part
of the common-mode bias setup.
PHOTODIODE DIFFERENTIAL AMPLIFIER
The high gain and low noise with a differential input can be
applied to photodiode detector applications where a photovoltaic mode is required and a reference dark current detector can be used. Figure 5 shows an example for this, where
two matched diodes operate with a 0V bias and generate a
small signal through a grounded sense resistor. One diode is
not exposed to the light signal, having only dark current,
while the other diode has both dark current plus signal
current. This mode is sometimes used for very large area
detectors where the diode dark current and parasitic capacitance are relatively large.
If the converter full-scale input range is a differential 2VPP,
the maximum input signal that can be passed through the
upper stage of Figure 4 is 2VPP/(153V/V) = 13mVPP. As the
converter detects an over-range condition, it can switch to
the lower stage of Figure 4 where a maximum input of
2VPP/(15.3V/V) = 130mVPP would be supported. While this
lower channel certainly suffers from a higher equivalent input
referred noise, it would only be used when the input signal is
relatively high, keeping the output SNR almost constant.
1kΩ
3kΩ
2.1V
MPA4609
1 of 4
Output Stage
3kΩ
1kΩ
FIGURE 5. Photo-Diode Differential Amplifier.
20Ω
–0.9dB
1 of 4 Channels
43.7dB
Gain
3kΩ
383Ω
Input
VCM
45.6dB
3kΩ
20Ω
Channel
Select
F/R
182Ω –20.9dB
Output Stage
23.7dB
Gain
3kΩ
36.5Ω
VCM
45.6dB
3kΩ
182Ω
FIGURE 4. Switched Attenuator to Increase ADC Dynamic Range.
MPA4609
SBOS252D
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11
SONAR AND PIEZOELECTRIC SENSORS
High-frequency sonar and piezoelectric sensors will benefit
from the low voltage noise of the MPA4609, providing excellent channel density where an array of sensors is used. For
sonar, it is also useful to use the second input available
on each channel of the MPA4609 as a look-away during
the high signals that may be present just after the transmitted
pulse. While the MPA4609 recovers very well to overdrives
(< 20ns), using this look-away feature to an open input
channel will minimize large output voltage steps. In
AC-coupled channels, large output overdrives require large
charge and discharge currents through the blocking capacitor giving a potentially long recovery tail on the output side of
the blocking capacitors. Each channel pair of the MPA4609
has relatively well-matched DC output offset (±200mV maximum difference). It is only the charging current required by
this output offset difference that would need to be accounted
for if the approach of Figure 6 where used under high input
overdrive conditions.
Figure 6 shows an example piezoelectric amplifier where a
Time Gain Control (TGC) amplifier follows the output to
provide for an increasing gain with time. Depending on the
propagation speed and attenuation of the medium, this gain
would ramped up to compensate for the increasing losses
with distance.
A piezoelectric sensor is modeled as a charge source with a
shunt capacitor and resistor, or as a voltage source with a
series capacitor and resistor. The 50Ω input resistors limit the
current under high overdrive conditions that would flow into
the Schottky clamp diodes. These diodes limit the maximum
input to approximately ±0.4V—still well beyond the maximum
useable input signal of ±20mV. Should very high overdrives
occur, the MPA4609 allows the designer to switch to a
dummy input, holding the output stage in range during this
period. When the piezoelectric signal drops to < 20mV, the
channel select may be switched back to this channel and the
output detected.
The VCA610 is a differential input to ground referenced
single-ended output voltage controlled gain amplifier. A constant bandwidth vs gain of 30MHz provides adequate bandwidth for this application.
The MPA4609 outputs are AC-coupled to grounded termination resistors. This removes the DC differential offset (as high
as ±250mV) prior to the input to the VCA610. The inputs to
the dummy channel are left open to provide the same DC
source impedance to its input bias currents as the signal
channel. This is intended to help match the DC output offset
voltage as the channels are switched, minimizing settling
tails through the output blocking capacitors.
As an example, use the VCA610 to adjust the gain over a
40dB range from –20dB to +20dB while the input to the
MPA4609 goes from 20mVPP maximum input to 200µVPP.
The net gain through the MPA4609, including the input
resistive attenuation and the divider at the input of the
VCA610, will be 42.3dB nominally. At maximum input of
20mVPP, this gives a 2.6VPP input to the VCA610. If it is
operated at minimum gain at this point, then its –20dB gain
will give an output of 260mVPP. As the input signal decreases
down to 200µVPP, the gain of the VCA610 is increased to
+20dB. With the input to the MPA4609 at 200µVPP, the input
to the VCA610 will see 26mVPP input. Then, with a gain of
20dB, this is brought back up to 260mVPP. The VCA610
could be used to continue adding another 20dB of gain,
allowing the MPA4609 input to decrease to 20uVPP while still
1 of 4 Channels
50Ω
3kΩ
Piezoelectric
Transducer
2.1V
3kΩ
50Ω
45.6dB
Gain
+5V
Forward
470Ω
Channel
Select
F/R
5kΩ
–40dB → +40dB
TGC
VCM
2.1V
VCA610
470Ω
VO
5kΩ
3kΩ
2.1V
–5V VC
45.6dB
Gain
0 → –2V
Gain Control
3kΩ
FIGURE 6. Sonar Amplifier with Time Gain Control.
12
MPA4609
www.ti.com
SBOS252D
resistors is adequate to shut off one or the other transistor.
A low voltage on the F/R pin will steer IB to the Q7 emmitter,
shutting off the bias for Q5 and turning off the forward input
transistor pair (Q1 and Q2). Conversely, zero current out of
Q16 leaves the bias to Q12 operating turning on the Reverse
channel inputs.
producing a 260mVPP at the VCA610 output—over 80dB of
gain with > 20MHz bandwidth.
One limiting factor to this approach is the input bias current
noise times the 3kΩ bias resistors to the common-mode
voltage at the input. That current, plus the 3kΩ resistor noise,
combine to produce a 12nV/√Hz total differential input noise.
If the overall system noise power bandwidth is limited to
2MHz, this gives an input referred noise of 17µVRMS. While
a 200µVPP input will certainly still be detectable, the 20uVPP
at maximum VCA610 gain of 40dB may be below the noise
floor. Using an external common-mode voltage for the
MPA4609 with lower resistors can improve this performance.
Both inputs are biased through 3kΩ resistors to the internal
VCM, a 2.1V bandgap reference with minimal temperature
drift. The specified input common-mode voltage is slightly
reduced from this 2.1V by the input transistor base currents
through the 3kΩ resistors. Each input stage transistor collector is also bootstrapped through a second set of transistors
(Q3, Q4 and Q10, Q11) that cascode the signal current
through to the 2nd stage. These cascode transistors also
have a base voltage provided from VCM increased by 1 diode
drop. This holds the nominal base-collector voltage of the
input transistors (Q1,Q2, and Q8, Q9) at 0V. This arrangement improves the off channel isolation and PSRR giving
improved attenuation from an input signal present at the
inputs of a de-selected input to the output current from these
cascode transistors. This does, however, limit the available
positive going common-mode input voltage to only 300mV
above VCM. Higher input common-mode voltages (when the
source is overriding the internally set common-mode input
voltage) will start to forward bias the base-collector junction
for the input transistors (Q1, Q2, and Q8, Q9). There is more
room going negatively to override the input common-mode
voltage, where the limit is the saturation of Q5 or Q12.
OPERATING INFORMATION
INPUT STAGE AND CHANNEL SWITCHING
Each channel pair of the MPA4609 provides two very low
noise, bipolar, differential input stages that are selected by
controlling their tail current sources with their output collectors connected together. Figure 7 shows a simplified schematic for one channel pair with the channel select circuitry
shown.
The active input channel is selected by controlling which
stage is biased by their tail current sources (Q5 or Q12). The
F/R pin controls a simple differential stage (Q15 and Q16)
that steers small currents to the emmitters of Q7 and Q14.
Given a fixed-base string bias voltage for those two current
mirror transistors, a small current through their emmitter
+VS
+VS
Next
IL
Q3
IL
+VS
Q4
+VS
Q10
Stage
Q11
VB = +VS –1.1V
+
Q1
VCM
Q2
Q8
3kΩ
VF
Q7
VCM
–
Q9
3kΩ
Q14
VCM
VR
VCM
3kΩ
3kΩ
–
+VS
Q5
+
+VS
Q13
Q6
37µA
Q12
37µA
Q15
Q16
IB
F/R
FIGURE 7. Input Stage Schematic (1 of 4 channels).
MPA4609
SBOS252D
www.ti.com
13
OUTPUT STAGE OPERATION
The output stage is a unity-gain differential I/O buffer including a common-mode control loop to hold the output commonmode voltage at the internal bandgap reference (VCM). Figure
8 illustrates each of the four output stages, showing a
common-mode feedback point picked off prior to the 470Ω
series output resistors.
An alternative method would be to connect a resistor to
ground on each output. This will attenuate both the differential gain while also level-shifting the common-mode voltage
by the same attenuation. Figure 10 shows this approach
where the VCM and VI is attenuated by 1/2, but in this case
also requires a 2.1V/(940Ω) = 2.2mA bias current from each
output and drops the common-mode voltage at the load to
1.05VDC.
Internal
470Ω
Internal
470Ω
470Ω
R
VI
VCM
1/4
MPA4609
R
VO = VCM + VI
VI
R
VCM
1/4
MPA4609
VO =
470Ω
VCM
2
+
VI
2
R
470Ω
470Ω
FIGURE 8. Output Stage Buffer.
The common-mode loop will serve to set these internal
nodes to VCM, regardless of what is happening on either the
input stage or output loading. Under output voltage overdrive
conditions, the output limit is set asymmetrically around VCM,
causing the common-mode control loop to servo out of
position while the overdrive is present. When removed, the
output common-mode voltage will recover as shown in the
Typical Characteristic curves. It is important to consider that
not only will the outputs clip in overdrive (with a fast 50ns
recovery) for the differential voltage, but there will be a
relatively slow tail in the common-mode voltage recovery
after the overdrive is removed.
Some applications for the MPA4609 require the signal gain
to be attenuated. This is most easily achieved by placing a
resistor across the two outputs to attenuate the differential
signal, with no common-mode loading on the output. Figure
9 shows an example where a 940Ω resistor between the
outputs attenuates the differential gain for the MPA4609 to
95V/V nominally.
Internal
FIGURE 10. Grounded Load Attenuation.
The internal output stage resistors may be used to implement
a simple low-pass filter as part of the signal path. For
instance, if a simple 50MHz low pass pole were desired,
often to limit noise power bandwidth, two capacitors to
ground (one on each output) equal to 6.8pF would be
needed. This can also be implemented as a single capacitor
across the outputs of 1/2 this value, or 3.4pF. These low
values also indicate the strong effect that layout parasitic
capacitance can have on the overall signal bandwidth. With
a 470Ω internal output impedance, very little external parasitic capacitance can limit the signal bandwidth. If external
gain attenuation resistors are used, the source impedance
becomes the parallel combination of the 470Ω and these
external resistors. For instance, Figure 11 shows the gain of
95V/V condition of Figure 9 with an added differential capacitance to set the frequency response for the differential output
signal to 50MHz. Since the source impedance on each side
is now effectively 470Ω || 470Ω = 235Ω, the single-ended
capacitor required would double to 13.6pF from that calculated above, and then drop to 6.8pF if implemented as a
capacitor across the outputs.
470Ω
Internal
R
VI
VCM
1/4
MPA4609
940Ω VO = VCM +
470Ω
VI
2
R
R
470Ω
VI
VCM
1/4
MPA4609
940Ω
6.8pF VO = VCM +
VI
2
R
470Ω
FIGURE 9. Differential Gain Attenuation..
FIGURE 11. Bandlimited Output Stage.
14
MPA4609
www.ti.com
SBOS252D
HARMONIC DISTORTION
0
Figure 12 shows an example RLC filter design where a highpass pole at 100kHz is included, and the converter commonmode input voltage is used to reference the filter output. This
filter is designed to provide a –3dB frequency at 30MHz with
exceptional flatness through 20MHz.
The design methodology for this type of filter can be found in
TI application note SBAA108. The simulated frequency response for this filter is shown in Figure 13.
Looking at this response, there is a slight (1dB) attenuation
in the passband due to the resistor divider loss. The filter was
designed with a slight peaking, which does show up and
extends the bandwidth slightly. Of most interest is the attenuation for the 3rd-harmonic at 10MHz and 20MHz fundamental frequencies. The MPA4609 shows –65dBc for a 2VPP
output at 10MHz. This harmonic, falling at 30MHz, will be
attenuated 2.5dB at the filter output to give –67.5dB SFDR.
As the input frequency moves up to 20MHz, the MPA4609
shows –53dBc 3rd-harmonic distortion. This term falls at
60MHz where the filter is giving about 11.5dB attenuation.
Hence, the filter output will show an SFDR of –64.5dBc at
20MHz—only slightly different than the 10MHz result.
The Typical Characteristics also show a high 3rd-order, twotone, intermodulation intercept. For measurement purposes,
a relatively low 500Ω load across the outputs was used. The
intercept for lighter loads, such as ADC inputs, will be higher
+5
470Ω
320pF
–2
–3
–4
Gain (dB)
Being a differential I/O device, the MPA4609 shows lower
2nd-harmonic distortion than 3rd-harmonic distortion. This
dominant 3rd-order term holds at very low levels through
frequencies that are a significant portion of the available
–3dB bandwidth due to the open loop design. Since the
differential output distortion is dominated by the 3rd-order
harmonic, passive postfiltering can be very effective at improving the SFDR at the filter output. For instance, the
Typical Characteristics show the 3rd-order harmonic distortion increasing rapidly above the 10MHz fundamental from a
low –65dBc for a 2VPP output. If the maximum desired input
frequency is 20MHz, a 2nd-order low pass filter placed with
a F–3dB at 30MHz will hold the distortion out of the filter at the
10MHz level. As the fundamental frequency rises above
10MHz, the dominant 3rd-order distortion term is extending
beyond the 30MHz cutoff of the filter. The rolloff of a 2ndorder filter exceeds the rate of increase for the 3rd-harmonic
in going from 10MHz to 20MHz. At 20MHz input, the
3rd-harmonic occurs at 60MHz—well into the cutoff region of
the filter.
–1
–5
–6
–7
–8
–9
–10
–11
–12
0.01
0.1
1
10
100
Frequency (MHz)
FIGURE 13. Simulated Frequency Response for Differential
Filter.
than for this 500Ω load. Since this is not a 50Ω environment,
more typically used in intercept plots, the 37dBm intercept
shown in the Typical Characteristics will need some interpretation. This plot was actually the Intercept for the differential
voltage swings for two closely-spaced tones at the output
prior to the 470Ω series output resistors. To predict the
intermodulation SFDR, calculate the single-tone power at
this internal point as if it were driving 50Ω, then use the
familiar intercept equation to predict how far down (dBc) the
3rd-order spurious levels will be.
For instance, if a 2VPP 2-tone envelope is needed at the
internal output nodes (V′O in Figure 1), consider each 1VPP
tone to be the 4dBm that would be strictly correct for a 50Ω
load across these internal nodes. Then, the 3rd-order spurious levels will be 2 • (IM3 – 4dBm) below the power level of
the two carriers. With a 37dBm intercept (IM3), this predicts
the 3rd-order intermodulation terms to be 2 • (37 – 4) = 66dBc
below the carrier. This is very consistent with the 3rdharmonic distortion, which is also 66dBc below a 2VPP output
for frequencies up to 10MHz. The output interface will
not change the relative levels of the carrier vs. 3rd-order
intermodulation spurious levels. Similarly, at lower
output swings, the SFDR improves significantly as shown in
both the harmonic distortion vs. output swing and the
intercept plots. At 1VPP output, (at V′O), the 3rd-harmonic
distortion is –78dBc down. For an equal power 2-tone envelope, each tone is at 0.5VPP differential or –2dBm for
the analysis here. With a 37dBm intercept, this calculates
to a 3rd-intermodulation order, spurious-free-range of
2 • (37 – (–2)) = –78dBc.
2.1µH
VIN
Internal
4.5kΩ
1/4
MPA4609
7.5pF
VCM
4.5kΩ
470Ω
320pF
10-Bit
60MSPS
ADC
ADS826
2.1µH
VIN
Internal
FIGURE 12. 3rd-Order Filter to Improve Harmonic Distortion.
MPA4609
SBOS252D
www.ti.com
15
Given the excellent CMRR rejection for the MPA4609, the
common-mode noise source, while present, will be neglected
from the noise analysis. Combining RS in parallel with
RB (RS || RB = RT) will give the total input referred differential
noise expression of Equation 2.
TOTAL OUTPUT NOISE CALCULATION
The total output noise can be very low, given the 0.65nV/√Hz
input voltage noise. To take full advantage of this low voltage
noise, careful attention to the source impedance and PSRR
are needed. Figure 14 shows a general analysis circuit for
the differential output noise for the MPA4609.
(2)
2
en = eni
+ 2 (R Tib ) + 2 (4kTR T )
2
This circuit includes a common-mode reference voltage
noise source. This can normally be neglected if:
(4kT = 1.6E – 20J at 290°k )
1. There is no real ground (AC or DC) at the midpoint of the
source resistor—if RS is simply connected across the
inputs, the common-mode bias noise remains commonmode, and will only appear at the output as the CMRR
rolls off with frequency. The Typical Characteristics show
the CMRR remains > 20dB through 40MHz. This rejection
is defined to the output differential signal. For commonmode noise as high as 100nV/√Hz, this will appear as a
differential output noise of < 10nV/√Hz through 40MHz.
To input refer this portion of the output noise, divide by the
minimum differential gain of 160V/V to get an input referred contribution equal to 0.06nV/√Hz that can certainly
be neglected.
Using the typical values for noise and resistors (RT = 32.2Ω)
will give a total input-referred differential voltage noise shown
in Equations 3a → 3c.
(3a)
en =
=
(0.65nV)2 + 2 (32.2Ω • 3.8pA)2 + 2 (1.6E – 20 • 32.2Ω)
(3b)
(0.65nV)2 + (0.17nV)2 + (1.02nV)2
(3c)
= 1.22nV / Hz
The individual noise terms shown in Equation 3b show that
the dominant noise term is the resistor noise of the source.
The low input voltage and current noise terms for the MPA4609
increase the total input noise voltage only slightly over the
Johnson noise of the resistor itself.
2. If the source does have an AC or DC centerpoint ground,
the common-mode noise will remain a common-mode
input noise source as long as the voltage divider formed
by the 3kΩ bias resistor and the source impedance on
each side is well-balanced. Low-source impedances, normally required for an overall low noise path, will also
attenuate the available common-mode input noise across
the inputs. For instance, using 1/2 of the 65Ω test condition source impedance to a centerpoint AC ground
will attenuate the common-mode noise by 32.5Ω/3.03kΩ
= 0.0011 (60dB). Even for a common-mode noise voltage
as high as 100nV/√Hz, this will get to the inputs as a
0.1nV/√Hz term. Then, even for divider imbalances as
high as 10%, this will give only 0.01nV/√Hz differential
noise contribution.
Taking this total input-referred differential voltage noise to
the output, and integrating over a noise-power bandwidth set
only by the 1-pole rolloff of the MPA4609 itself, will give the
a total output RMS noise shown in Equations 4a → 4c.
e ORMS = en • Gain • Bandwidth • 1.54
(4a)
e ORMS = 1.22nV / Hz • 190V / V • 90MHz • 1.54
(4b)
e ORMS = 2.7mVRMS
(4c)
eN
*
√4kTRS
√4kTRS
*
*
IB
*
√4kTRB
RS
RB
3kΩ
RS
RB
3kΩ
*
*
*
ECM
*
eO
VCM
√4kTRB
IB
FIGURE 14. Output Noise Analysis Circuit.
16
MPA4609
www.ti.com
SBOS252D
More narrowly restricting the noise-power bandwidth will
reduce this integrated noise. For instance, using the 30MHz,
2nd-order filter of Figure 12 will reduce the noise-power
bandwidth to approximately 1.11 • F–3dB = 33.3MHz. This
will give a differential RMS output noise given by Equations
5a → 5b.
e ORMS = 1.22nV / Hz • 190V / V • 30MHz • 1.1
e ORMS = 1.34mVRMS
(5a)
(5b)
A more complete noise analysis description can be found in
TI application note SBOA066, Noise Analysis for High Speed
Op Amps.
One added contribution to apparent output noise can be
power supply noise coming through to the output. The
MPA4609 provides good PSRR (defined as going from the
supply to the differential output voltage). The Typical Characteristics show a PSRR holding above 20dB through 30MHz.
To estimate the contribution of power-supply noise, consider
an example of 10mV of system clocking related noise at
30MHz. This will come through to the output as approximately a 1mV differential signal given the 20dB PSRR at
30MHz. To input-refer this, divide by the 190V/V gain to get
an equivalent input-referred term of 5.2µV.
High-frequency glitches on the supply can have significant
harmonic content well above this 30MHz frequency. If the
system can be expected to have large, high-frequency, clock
noise on the supplies, a PI filter into the MPA4609 supply
pins can be used to reduce their amplitude adequately to limit
their contribution to the output signal. An example design is
shown in Figure 15.
Ferrite Bead
+VS
+5V
+
6.8µF
1000pF
10
Example Ferrite Bead
27
Surface Mount (402)
Vishay
ILBB-0402 120Ω
MPA4609
46
39
15
Figure 7 shows a simplified channel select circuit as part of
the input stage schematic. The channel select includes an
internal level shift through two diodes to compare into a
differential stage biased with three diodes above ground. Full
switching of the differential stage occurs at approximately
two diodes above ground (plus a slight IR drop) to give the
nominal 1.25V switching point. The reverse channel will be
selected when the F/R pin voltage is < 0.9V while the forward
channel will be selected when the control pin voltage is
> 1.6V. Leaving the F/R pin unconnected will default to the
high state with the Forward channels selected. This low
switching threshold, with minimal current requirements, allows very low-voltage CMOS logic to be directly interfaced to
the F/R pin.
When the F/R pin is at ground, each channel select circuit
sends approximately 35µA out of the F/R pin. Since there are
two channels on each of the two select pins (pins 3 and 34),
this give the specified total sinking current when each F/R pin
is low of 70µA in each pin. As the control logic goes high, this
bias current is diverted through two diodes connected across
the differential stage—intended to clamp the maximum differential voltage across this stage. This gives a zero current
requirement at the control pins in the logic high state.
THERMAL ANALYSIS
Neither heatsinking nor airflow will be required for most
applications of the MPA4609. Exceptional performance over
temperature is maintained using carefully designed temperature coefficients for the quiescent currents in each stage. The
common-mode reference shows very little change over temperature. The limit to operation will then be either the maximum system defined junction temperature or the specified
absolute maximum of junction temperature of 150°C.
Operating junction temperature (TJ) is given by TA + PD • θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. PDL will be very low due to the
internal 470Ω output resistors. To get a worst-case output
stage power estimate, consider the outputs to be grounded—
giving an average output current on each side set by VCM/
470Ω = 4.5mA. Putting 4.5mA in each of the eight output
stages (two for each of the four differential pairs) times the
total internal voltage drop of VS gives an absolute worst- case
output stage power dissipation = 180mW total for all channels.
0.1µF
1000pF
CHANNEL SELECT OPERATION
22
FIGURE 15. Power Supply PI Filter for Improved PSRR.
For instance, at 30MHz the two-1000pF capacitors show a
2.65Ω impedance (the 0.1µF capacitor has gone self-resonant at 10MHz typically) while the ferrite bead shows approximately 80Ω (from the manufacturers data sheet for the
part number shown) to give a 30dB attenuation at 30MHz. By
90MHz, the capacitive impedance is dropped to 0.9Ω while
the ferrite bead has increased to 130Ω to give a 43dB
attenuation in supply noise.
Continuing this worst-case example, compute the maximum
TJ using this maximum output stage power and the maximum
quiescent power. Operating at the maximum specified ambient temperature of +85°C, the maximum internal power is
(6)
given in Equation 6:
MPA4609
SBOS252D
www.ti.com
PD = 5V • 52mA + 180mW = 440mW
Maximum TJ = +85°C + (0.44W • 60°C/W) = 111.4°C.
17
wirewound type resistors in a high-frequency application.
Since the output pins are the most sensitive to parasitic
capacitance, always position the series output blocking
capacitor, if any, as close as possible to the output pin.
Keep resistor values as low as possible, consistent with
load driving considerations.
All actual applications will operate at a lower junction temperature than the 111.4°C computed above. Compute your
actual output stage power to get an accurate estimate of
maximum junction temperature, or use the results shown
here as an absolute maximum.
The “I” suffix indicates operation from –40°C to +85°C
ambient. As the Typical Characteristic curves show, D.C.
performance is stable over a very wide temperature range.
However, since the intended application is only for a commercial 0°C to +70°C range, min/max specifications are
provided only over this range.
BOARD LAYOUT
Achieving optimum performance with a high-frequency amplifier like the MPA4609 requires careful attention to board
layout parasitics and external component types. Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output
and input pins can cause unintentional bandlimiting of the
signal. To reduce unwanted capacitance, create a window
around the signal I/O pins in all of the ground and power
planes around those pins. Otherwise, ground and power
planes should be unbroken elsewhere on the board. Also,
since the outputs are differential, maintain adequate output trace separation to keep the parasitic differential
output capacitance low.
d) Socketing a high-speed part like the MPA4609 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the
MPA4609 onto the board.
INPUT AND ESD PROTECTION
The MPA4609 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are not reflected in the Absolute
Maximum Ratings table as this device is only intended for
+5V (±10%) supply operation. Internal breakdowns are typically > 12V, but an Absolute Maximum Rating of +7V is
+V CC
External
Pin
Internal
Circuitry
b) Minimize the distance (< 0.25") from the power supply
pins to high frequency 0.1µF and 1000pF decoupling
capacitors. At the device pins, the ground and power
plane layout should not be in close proximity to the signal
I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling
capacitors. The power-supply connections should always
be decoupled with these capacitors. Larger (2.2µF to
6.8µF) decoupling capacitors, effective at lower frequency,
should also be used on the supply pins. These may be
placed somewhat farther from the device and may be
shared among several devices in the same area of the PC
board.
FIGURE 16. Internal ESD Protection.
c) Careful selection and placement of external components will preserve the high frequency performance
of the MPA4609. Use resistors that have low reactance
at high frequencies. Surface mount resistors work best
and allow a tighter overall layout. Metal film and carbon
composition axially-leaded resistors can also provide good
high-frequency performance. Again, keep their leads and
PC board trace length as short as possible. Never use
These diodes provide moderate protection to input overdrive
voltages beyond the supply and ground as well. The protection diodes can typically support 30mA continuous current.
Where large common-mode or differential mode transients
are possible, current limiting series resistors may be added
on the differential inputs. Keep this resistor value as low as
possible since high values degrade both noise performance
and frequency response.
18
–V CC
shown to limit application at supplies far higher than the
MPA4609 design and characterization point.
All device I/O pins are protected with internal ESD protection
diodes to the power supply and ground as shown in Figure
16.
MPA4609
www.ti.com
SBOS252D
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MPA4609IPFBR
ACTIVE
TQFP
PFB
48
2000
TBD
CU NIPDAU
Level-2-220C-1 YEAR
MPA4609IPFBT
ACTIVE
TQFP
PFB
48
250
TBD
CU NIPDAU
Level-2-220C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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