ON NL17SZ74 Single d flip flop Datasheet

NL17SZ74
Single D Flip Flop
The NL17SZ74 is a high performance, full function Edge triggered
D Flip Flop, with all the features of a standard logic device such as the
74LCX74.
Features
•
•
•
•
•
•
•
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Extremely High Speed: tPD 2.6 ns (typical) at VCC = 5.0 V
Designed for 1.65 V to 5.5 V VCC Operation
5.0 V Tolerant Inputs − Interface Capability with 5.0 V TTL Logic
LVTTL Compatible
LVCMOS Compatible
US8
US SUFFIX
CASE 493
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current (10 mA) Substantially Reduces
System Power Requirements
Replacement for NC7SZ74
MARKING DIAGRAM
•
• Tiny Ultra Small Package Only 2.1 X 3.0 mm
• High ESD Ratings: 4000 V Human Body Model
MH M
G
High ESD Ratings: 200 V Machine Model
Chip Complexity: FET = 64
•
• NLV Prefix for Automotive and Other Applications Requiring
•
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MH
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
PINOUT DIAGRAM
TRUTH TABLE
Inputs
Outputs
PR
CLR
CP
D
Q
Q
Operating Mode
L
H
L
H
L
L
X
X
X
X
X
X
H
L
H
L
H
H
Asynchronous Set
Asynchronous Clear
Undetermined
H
H
H
H
↑
↑
h
l
H
L
L
H
Load and Read Register
H
H
↑
X
NC
NC
Hold
1
CP
D
Q
GND
2
3
4
8
7
6
5
VCC
PR
CLR
Q
LOGIC DIAGRAM
PR
H
h
= High Voltage Level
= High Voltage Level One Setup Time Prior to the Low−to−High
Clock Transition
L
= Low Voltage Level
l
= Low Voltage Level One Setup Time Prior to the Low−to−High
Clock Transition
NC
= No Change
X
= High or Low Voltage Level and Transitions are Acceptable
↑
= Low−to−High Transition
↑
= Not a Low−to−High Transition
For ICC reasons, DO NOT FLOAT Inputs
7
D
2
5
Q
CP
1
3
Q
6
CLR
VCC = 8, GND = 4
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 11
1
Publication Order Number:
NL17SZ74/D
NL17SZ74
MAXIMUM RATINGS
Symbol
Value
Units
DC Supply Voltage
−0.5 to +7.0
V
VI
DC Input Voltage
−0.5 to +7.0
V
VO
DC Output Voltage − Output in High or Low State (Note 1)
−0.5 to VCC +0.5
V
IIK
DC Input Diode Current
VI < GND
−50
mA
IOK
DC Output Diode Current
VO < GND
−50
mA
VCC
Parameter
IO
DC Output Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction Temperature Under Bias
+150
°C
qJA
Thermal Resistance (Note 2)
250
°C/W
PD
Power Dissipation in Still Air at 85°C
250
mW
MSL
FR
VESD
ILATCHUP
Moisture Sensitivity
Level 1
Flammability Rating, Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
V
>4000
>200
N/A
±100
Latchup Performance Above VCC and Below GND at 125°C (Note 6)
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm X 1 inch, 2 ounce copper trace with no air flow.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Max
Supply Voltage
Operating
Data Retention Only
1.65
1.5
5.5
5.5
VI
Input Voltage (Note 7)
0
5.5
VO
Output Voltage (HIGH or LOW State)
0
5.5
V
TA
Operating Free−Air Temperature
−55
+125
°C
Dt/DV
Input Transition Rise or Fall Rate
VCC = 2.5 V ±0.2 V
VCC = 3.0 V ±0.3 V
VCC = 5.0 V ±0.5 V
0
0
0
20
10
5.0
VCC
Parameter
Units
V
V
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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2
NL17SZ74
ORDERING INFORMATION
Package
Shipping†
NL17SZ74USG
US8
(Pb−Free)
3000 / Tape & Reel
NLV17SZ74USG*
US8
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VIH
High−Level Input Voltage
VIL
Condition
Low−Level Input Voltage
(V)
Min
1.65
0.75 VCC
0.75 VCC
2.3 to 5.5
0.7 VCC
0.7 VCC
Typ
Max
Min
Max
0.25 VCC
0.25 VCC
2.3 to 5.5
0.3 VCC
0.3 VCC
High−Level Output Voltage
VIN = VIL or VIL
IOH = 100 mA
IOH = −3 mA
IOH = −8 mA
IOH = −12 mA
IOH = −16 mA
IOH = −24 mA
IOH = −32 mA
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
VOL
Low−Level Output Voltage
VIN = VIH
IOL = 100 mA
IOL = 3 mA
IOL = 8 mA
IOL = 12 mA
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
Input Leakage Current
VIN = 5.5 V or
GND
IOFF
Power Off
Leakage Current
ICC
Quiescent Supply Current
VCC − 0.1
1.29
1.9
2.2
2.4
2.3
3.8
VCC
1.52
2.1
2.4
2.7
2.5
4.0
VCC − 0.1
1.29
1.9
2.2
2.4
2.3
3.8
V
V
0.1
0.24
0.3
0.4
0.4
0.55
0.55
0.1
0.24
0.3
0.4
0.4
0.55
0.55
V
0 to 5.5
±0.1
±1.0
mA
VIN = 5.5 V or
VOUT = 5.5 V
0
1.0
10
mA
VIN = 5.5 V or
GND
5.5
1.0
10
mA
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3
0.008
0.10
0.12
0.15
0.19
0.30
0.30
Units
V
1.65
VOH
IIN
−55_C 3 TA 3 125_C
TA = 25_C
VCC
NL17SZ74
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
TA = 25°C
Symbol
fMAX
Parameter
Maximum Clock
Frequency
(50% Duty Cycle)
(Waveform 1)
VCC (V)
1.8 ± 0.15
Test Conditions
CL = 15 pF
RD = 1 MW
S1 = Open
Min
Typ
75
TA = −55 to 125°C
Max
Min
Max
75
Units
MHz
2.5 ± 0.2
150
150
3.3 ± 0.3
200
200
5.0 ± 0.5
250
250
CL = 50 pF,
3.3 ± 0.3
175
175
RD = 500 W, S1 = Open
5.0 ± 0.5
200
200
tPLH,
Propagation Delay,
CL = 15 pF
ns
1.8 ± 0.15
2.5
6.5
12.5
2.5
13
tPHL
CP to Q or Q
RD = 1 MW
2.5 ± 0.2
1.5
3.8
7.5
1.5
8.0
(Waveform 1)
S1 = Open
3.3 ± 0.3
1.0
2.8
6.5
1.0
7.0
5.0 ± 0.5
0.8
2.2
4.5
0.8
5.0
CL = 50 pF,
3.3 ± 0.3
1.0
3.4
7.0
1.0
7.5
RD = 500 W, S1 = Open
5.0 ± 0.5
1.0
2.6
5.0
1.0
5.5
tPLH,
Propagation Delay,
CL = 15 pF
ns
1.8 ± 0.15
2.5
6.5
14
2.5
14.5
tPHL
PR or CLR to Q or Q
RD = 1 MW
2.5 ± 0.2
1.5
3.8
9.0
1.5
9.5
(Waveform 2)
S1 = Open
3.3 ± 0.3
1.0
2.8
6.5
1.0
7.0
5.0 ± 0.5
0.8
2.2
5.0
0.8
5.5
CL = 50 pF,
3.3 ± 0.3
1.0
3.4
7.0
1.0
7.5
RD = 500 W, S1 = Open
5.0 ± 0.5
1.0
2.6
5.0
1.0
5.5
tS
Setup Time, D to CP
CL = 15 pF
ns
1.8 ± 0.15
6.5
6.5
(Waveform 1)
RD = 1 MW
2.5 ± 0.2
3.5
3.5
S1 = Open
3.3 ± 0.3
2.0
2.0
5.0 ± 0.5
1.5
1.5
CL = 50 pF,
3.3 ± 0.3
2.0
2.0
RD = 500 W, S1 = Open
5.0 ± 0.5
1.5
1.5
tH
Hold Time, D to CP
CL = 15 pF
ns
1.8 ± 0.15
0.5
0.5
(Waveform 1)
RD = 1 MW
2.5 ± 0.2
0.5
0.5
S1 = Open
3.3 ± 0.3
0.5
0.5
5.0 ± 0.5
0.5
0.5
CL = 50 pF,
3.3 ± 0.3
0.5
0.5
RD = 500 W, S1 = Open
5.0 ± 0.5
0.5
0.5
tW
Pulse Width,
CL = 15 pF
ns
1.8 ± 0.15
6.0
6.0
CP, CLR, PR
RD = 1 MW
2.5 ± 0.2
4.0
4.0
(Waveform 3)
S1 = Open
3.3 ± 0.3
3.0
3.0
5.0 ± 0.5
2.0
2.0
CL = 50 pF,
3.3 ± 0.3
3.0
3.0
RD = 500 W, S1 = Open
5.0 ± 0.5
2.0
2.0
tREC
Recover Time
CL = 15 pF
ns
1.8 ± 0.15
8.0
8.0
PR; CLR to CP
RD = 1 MW
2.5 ± 0.2
4.5
4.5
(Waveform 3)
S1 = Open
3.3 ± 0.3
3.0
3.0
5.0 ± 0.5
3.0
3.0
CL = 50 pF,
3.3 ± 0.3
3.0
3.0
RD = 500 W, S1 = Open
5.0 ± 0.5
3.0
3.0
8. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 2 (per flip−flop). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
CAPACITANCE (Note 9)
Symbol
Condition
Typical
Unit
Input Capacitance
VCC = 5.5 V
7.0
pF
COUT
Output Capacitance
VCC = 5.5 V
7.0
pF
CPD
Power Dissipation Capacitance (Note 10)
Frequency = 10 MHz
VCC = 3.3 V
VCC = 5.0 V
16
21
pF
CIN
Parameter
9. TA = +25°C, f = 1 MHz
10. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at
no output loading and operating at 50% duty cycle. (See Figure 1) CPD is related to ICCD dynamic operating current by the expression:
ICCD = CPD VCC fin + ICC(static).
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4
NL17SZ74
Vcc
D
50%
0V
th
ts
Vcc
tw
CP
50%
0V
fmax
tPLH, tPHL
VOH
Q,
Q
50%
VOL
WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES
tR = tF = 3.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Vcc
PR
50%
0V
Vcc
CLR
50%
0V
tPLH
tPHL
Q
50%
50%
VOL
VOH
tPLH
Q
50%
50%
tPHL
WAVEFORM 2 − PROPAGATION DELAYS
tR = tF = 3.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Vcc
tw
PR, CLR
50%
0V
trec
Vcc
50%
CP
tw
0V
WAVEFORM 3 − RECOVERY TIME
tR = tF = 3.0 ns from 10% to 90%; f = 1 MHz; tw = 500 ns
Output Reg: VOL ≤ 0.8 V, VOH ≥ 2.0 V
Figure 1. AC Waveforms
VCC
PULSE
GENERATOR
DUT
RT
CL
Figure 2. Test Circuit
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5
RL
NL17SZ74
PACKAGE DIMENSIONS
US8
US SUFFIX
CASE 493−02
ISSUE B
−X−
A
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
MOLD FLASH. PROTRUSION AND GATE
BURR SHALL NOT EXCEED 0.140 MM
(0.0055”) PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTER−LEAD FLASH OR PROTRUSION.
INTER−LEAD FLASH AND PROTRUSION
SHALL NOT E3XCEED 0.140 (0.0055”) PER
SIDE.
5. LEAD FINISH IS SOLDER PLATING WITH
THICKNESS OF 0.0076−0.0203 MM.
(300−800 “).
6. ALL TOLERANCE UNLESS OTHERWISE
SPECIFIED ±0.0508 (0.0002 “).
J
−Y−
5
DETAIL E
B
L
1
4
R
G
P
S
U
C
−T−
SEATING
PLANE
D
H
0.10 (0.004) T
K
N
0.10 (0.004)
M
R 0.10 TYP
T X Y
V
M
F
DETAIL E
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
R
S
U
V
SOLDERING FOOTPRINT*
MILLIMETERS
MIN
MAX
1.90
2.10
2.20
2.40
0.60
0.90
0.17
0.25
0.20
0.35
0.50 BSC
0.40 REF
0.10
0.18
0.00
0.10
3.00
3.20
0_
6_
5_
10 _
0.23
0.34
0.23
0.33
0.37
0.47
0.60
0.80
0.12 BSC
INCHES
MIN
MAX
0.075
0.083
0.087
0.094
0.024
0.035
0.007
0.010
0.008
0.014
0.020 BSC
0.016 REF
0.004
0.007
0.000
0.004
0.118
0.126
0_
6_
5_
10 _
0.010
0.013
0.009
0.013
0.015
0.019
0.024
0.031
0.005 BSC
3.8
0.015
0.50
0.0197
1.8
0.07
0.30
0.012
1.0
0.0394
SCALE 8:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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