TI LMP2021MA Lmp2021/lmp2022 zero drift, low noise, emi hardened amplifier Datasheet

LMP2021, LMP2022
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SNOSAY9E – SEPTEMBER 2008 – REVISED MARGH 2013
LMP2021/LMP2022 Zero Drift, Low Noise, EMI Hardened Amplifiers
Check for Samples: LMP2021, LMP2022
FEATURES
1
(Typical Values, TA = 25°C, VS = 5V)
23
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Offset Voltage (Typical) −0.4 µV
Input Offset Voltage (Max) ±5 µV
Input Offset Voltage Drift (Typical) -0.004 µV/°C
Input Offset Voltage Drift (Max) ±0.02 µV/°C
Input Voltage Noise, AV = 1000 11 nV/√Hz
Open Loop Gain 160 dB
CMRR 139 dB
PSRR 130 dB
Supply Voltage Range 2.2V to 5.5V
Supply Current (per Amplifier) 1.1 mA
Input Bias Current ±25 pA
GBW 5 MHz
Slew Rate 2.6 V/µs
Operating Temperature Range −40°C to 125°C
5-Pin SOT-23, 8-Pin VSSOP and 8-Pin SOIC
Packages
APPLICATIONS
•
•
•
•
Precision Instrumentation Amplifiers
Battery Powered Instrumentation
Thermocouple Amplifiers
Bridge Amplifiers
DESCRIPTION
The LMP2021/LMP2022 are single and dual precision
operational amplifiers offering ultra low input offset
voltage, near zero input offset voltage drift, very low
input voltage noise and very high open loop gain.
They are part of the LMP™ precision family and are
ideal for instrumentation and sensor interfaces.
The LMP2021/LMP2022 have only 0.004 µV/°C of
input offset voltage drift, and 0.4 µV of input offset
voltage. These attributes provide great precision in
high accuracy applications.
The proprietary continuous correction circuitry
ensures impressive CMRR and PSRR, removes the
1/f noise component, and eliminates the need for
calibration in many circuits.
With only 260 nVPP (0.1 Hz to 10 Hz) of input voltage
noise and no 1/f noise component, the
LMP2021/LMP2022 are suitable for low frequency
applications such as industrial precision weigh scales.
The low input bias current of 23 pA makes these
excellent choices for high source impedance circuits
such as non-invasive medical instrumentation as well
as test and measurement equipment. The extremely
high open loop gain of 160 dB drastically reduces
gain error in high gain applications. With ultra
precision DC specifications and very low noise, the
LMP2021/LMP2022 are ideal for position sensors,
bridge sensors, pressure sensors, medical equipment
and other high accuracy applications with very low
error budgets.
The LMP2021 is offered in 5-Pin SOT-23 and 8-Pin
SOIC packages. The LMP2022 is offered in 8-Pin
VSSOP and 8-Pin SOIC packages.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LMP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
LMP2021, LMP2022
SNOSAY9E – SEPTEMBER 2008 – REVISED MARGH 2013
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TYPICAL APPLICATION
Figure 1. Bridge Amplifier
VA
VA = 5V
+
1/2
LMP2022
EMI
R1
-
0.1 PF
R4
1 k:
200:
5.1 k:
0.1%
VA
VA
470 pF
180:
R2
+
LMP2021
280:
R3
ADC161S626
-
+
VA
-
0.1 PF
5.1 k:
0.1%
1/2
LMP2022
+
VR = 1/2 VA
200:
1 k:
The LMP2021/LMP2022 support systems with up to 24 bits of accuracy.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
ESD Tolerance (3)
Human Body Model
2000V
Machine Model
200V
Charge Device Model
1000V
VIN Differential
±VS
Supply Voltage (VS = V+ – V−)
6.0V
V+ + 0.3V, V− − 0.3V
All Other Pins
Output Short-Circuit Duration to V+ or V− (4)
5s
−65°C to 150°C
Storage Temperature Range
Junction Temperature (5)
Soldering Information
(1)
(2)
(3)
(4)
(5)
2
150°C max
Infrared or Convection (20 sec)
235°C
Wave Soldering Lead Temperature (10 sec)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Human Body Model per MIL-STD-883, Method 3015.7. Machine Model, per JESD22-A115-A. Field-Induced Charge-Device Model, per
JESD22-C101-C.
Package power dissipation should be observed.
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
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SNOSAY9E – SEPTEMBER 2008 – REVISED MARGH 2013
Operating Ratings (1)
−40°C to 125°C
Temperature Range
Supply Voltage (VS = V+ – V–)
2.2V to 5.5V
Package Thermal Resistance (θJA)
(1)
5-Pin SOT-23
164 °C/W
8-Pin SOIC (LMP2021)
106 °C/W
8-Pin SOIC (LMP2022)
106 °C/W
8-Pin VSSOP
217 °C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
2.5V Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 2.5V, V− = 0V, VCM = V+/2, RL >10 kΩ to V+/2. Boldface
limits apply at the temperature extremes.
Symbol
VOS
Parameter
Conditions
Min (2)
Input Offset Voltage
(4)
Typ (3)
Max (2)
Units
–0.9
±5
±10
μV
TCVOS
Input Offset Voltage Drift
0.001
±0.02
μV/°C
IB
Input Bias Current
±23
±100
±300
pA
IOS
Input Offset Current
±57
±200
±250
pA
CMRR
Common Mode Rejection Ratio
−0.2V ≤ VCM ≤ 1.7V
0V ≤ VCM ≤ 1.5V
105
102
CMVR
Input Common-Mode Voltage Range
Large Signal CMRR ≥ 105 dB
Large Signal CMRR ≥ 102 dB
−0.2
0
EMIRR
Electro-Magnetic Interference
Rejection Ratio (5)
IN+
and
IN−
PSRR
AVOL
(1)
(2)
(3)
(4)
(5)
Power Supply Rejection Ratio
Large Signal Voltage Gain
141
dB
1.7
1.5
VRF-PEAK = 100 mVP (−20 dBVP)
f = 400 MHz
40
VRF-PEAK = 100 mVP (−20 dBVP)
f = 900 MHz
48
VRF-PEAK = 100 mVP (−20 dBVP)
f = 1800 MHz
67
VRF-PEAK = 100 mVP (−20 dBVP)
f = 2400 MHz
79
2.5V ≤ V+ ≤ 5.5V, VCM = 0
115
112
130
2.2V ≤ V+ ≤ 5.5V, VCM = 0
110
130
RL = 10 kΩ to V+/2
VOUT = 0.5V to 2V
124
119
150
RL = 2 kΩ to V+/2
VOUT = 0.5V to 2V
120
115
150
V
dB
dB
dB
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
All limits are specified by testing, statistical analysis or design.
Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and
will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production
material.
Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
The EMI Rejection Ratio is defined as EMIRR = 20Log ( VRF-PEAK/ΔVOS).
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2.5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 2.5V, V− = 0V, VCM = V+/2, RL >10 kΩ to V+/2. Boldface
limits apply at the temperature extremes.
Symbol
VOUT
Min (2)
Max (2)
RL = 10 kΩ to V /2
38
50
70
RL = 2 kΩ to V+/2
62
85
115
RL = 10 kΩ to V+/2
30
45
55
RL = 2 kΩ to V+/2
58
75
95
Conditions
+
Output Swing High
Output Swing Low
IOUT
Typ (3)
Parameter
Linear Output Current
Sourcing, VOUT = 2V
30
50
Sinking, VOUT = 0.5V
30
50
Units
mV
from either
rail
mA
IS
Supply Current
Per Amplifier
0.95
SR
Slew Rate (6)
AV = +1, CL = 20 pF, RL = 10 kΩ
VO = 2 VPP
2.5
V/μs
GBW
Gain Bandwidth Product
CL = 20 pF, RL = 10 kΩ
5
MHz
GM
Gain Margin
CL = 20 pF, RL = 10 kΩ
10
dB
ΦM
Phase Margin
CL = 20 pF, RL = 10 kΩ
60
deg
CIN
Input Capacitance
Common Mode
12
Differential Mode
12
en
Input-Referred Voltage Noise Density f = 0.1 kHz or 10 kHz, AV = 1000
Input-Referred Voltage Noise
1.10
1.37
pF
11
f = 0.1 kHz or 10 kHz, AV = 100
15
0.1 Hz to 10 Hz
260
0.01 Hz to 10 Hz
330
mA
nV/√Hz
nVPP
in
Input-Referred Current Noise
f = 1 kHz
350
fA/√Hz
tr
Recovery time
to 0.1%, RL = 10 kΩ, AV = −50,
VOUT = 1.25 VPP Step, Duration = 50 μs
50
µs
CT
Cross Talk
LMP2022, f = 1 kHz
150
dB
(6)
The number specified is the average of rising and falling slew rates and is measured at 90% to 10%.
5V Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, RL > 10 kΩ to V+/2. Boldface
limits apply at the temperature extremes.
Symbol
VOS
Parameter
Min (2)
Conditions
Input Offset Voltage
(4)
Typ (3)
Max (2)
Units
−0.4
±5
±10
μV
TCVOS
Input Offset Voltage Drift
−0.004
±0.02
μV/°C
IB
Input Bias Current
±25
±100
±300
pA
IOS
Input Offset Current
±48
±200
±250
CMRR
Common Mode Rejection Ratio
(1)
(2)
(3)
(4)
4
−0.2V ≤ VCM ≤ 4.2V
0V ≤ VCM ≤ 4.0V
120
115
139
pA
dB
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
All limits are specified by testing, statistical analysis or design.
Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and
will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production
material.
Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
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SNOSAY9E – SEPTEMBER 2008 – REVISED MARGH 2013
5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, RL > 10 kΩ to V+/2. Boldface
limits apply at the temperature extremes.
Symbol
Parameter
CMVR
Input Common-Mode Voltage Range
EMIRR
Electro-Magnetic Interference
Rejection Ratio (5)
Conditions
Large Signal CMRR ≥ 120 dB
Large Signal CMRR ≥ 115 dB
IN+
and
IN−
PSRR
AVOL
VOUT
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Swing High
Linear Output Current
Typ (3)
–0.2
0
VRF-PEAK = 100 mVP (−20 dBVP)
f = 400 MHz
58
VRF-PEAK = 100 mVP (−20 dBVP)
f = 900 MHz
64
VRF-PEAK = 100 mVP (−20 dBVP)
f = 1800 MHz
72
VRF-PEAK = 100 mVP (−20 dBVP)
f = 2400 MHz
82
2.5V ≤ V+ ≤ 5.5V, VCM = 0
115
112
130
2.2V ≤ V+ ≤ 5.5V, VCM = 0
110
130
RL = 10 kΩ to V+/2
VOUT = 0.5V to 4.5V
125
120
160
RL = 2 kΩ to V+/2
VOUT = 0.5V to 4.5V
123
118
160
Max (2)
Units
4.2
4.0
V
dB
dB
dB
RL = 10 kΩ to V+/2
83
135
170
RL = 2 kΩ to V+/2
120
160
204
RL = 10 kΩ to V /2
65
80
105
RL = 2 kΩ to V+/2
103
125
158
+
Output Swing Low
IOUT
Min (2)
Sourcing, VOUT = 4.5V
30
50
Sinking, VOUT = 0.5V
30
50
mV
from either
rail
mA
IS
Supply Current
Per Amplifier
1.1
SR
Slew Rate (6)
AV = +1, CL = 20 pF, RL = 10 kΩ
VO = 2 VPP
2.6
V/μs
GBW
Gain Bandwidth Product
CL = 20 pF, RL = 10 kΩ
5
MHz
GM
Gain Margin
CL = 20 pF, RL = 10 kΩ
10
dB
ΦM
Phase Margin
CL = 20 pF, RL = 10 kΩ
60
deg
CIN
Input Capacitance
Common Mode
12
Differential Mode
12
f = 0.1 kHz or 10 kHz, AV= 1000
11
f = 0.1 kHz or 10 kHz, AV= 100
15
0.1 Hz to 10 Hz Noise
260
0.01 Hz to 10 Hz Noise
330
en
Input-Referred Voltage Noise Density
Input-Referred Voltage Noise
1.25
1.57
mA
pF
nV/√Hz
nVPP
in
Input-Referred Current Noise
f = 1 kHz
350
fA/√Hz
tr
Input Overload Recovery time
to 0.1%, RL = 10 kΩ, AV = −50,
VOUT = 2.5 VPP Step, Duration = 50 μs
50
μs
CT
Cross Talk
LMP2022, f = 1 kHz
150
dB
(5)
(6)
The EMI Rejection Ratio is defined as EMIRR = 20Log ( VRF-PEAK/ΔVOS).
The number specified is the average of rising and falling slew rates and is measured at 90% to 10%.
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Connection Diagrams
N/C
-IN
-
V
3
-
+IN
4
-IN
Figure 2. 5-Pin SOT-23
Top View
6
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V
-
8
2
-
2
+
+IN
1
3
4
+
7
6
5
OUT A
N/C
+
-IN A
OUT
+IN A
V
V
N/C
Figure 3. 8-Pin SOIC (LMP2021)
Top View
-
1
8
A
2
3
7
B
+
+
V
+
5
1
4
6
-
OUT
5
+
V
OUT B
-IN B
+IN B
Figure 4. 8-Pin SOIC/VSSOP
(LMP2022)
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Typical Performance Characteristics
Unless otherwise noted: TA = 25°C, RL > 10 kΩ, VS= V+ – V–, VS= 5V, VCM = VS/2.
Offset Voltage Distribution
TCVOS Distribution
16
UNITS TESTED > 1700
VS = 2.5V
14
TA = 25°C
12
VCM = VS/2
10
8
6
4
PERCENTAGE (%)
PERCENTAGE (%)
14
2
UNITS TESTED > 1700
12 -40°C d TA d 125°C
VS = 2.5V
10 VCM = VS/2
8
6
4
2
0
-5
-4
-3
-2
-1
0
1
2
3
4
0
-20
5
-10
VOS (PV)
Figure 5.
Offset Voltage Distribution
UNITS TESTED = 6200
VS = 5V
VCM = VS/2
10
8
6
PERCENTAGE (%)
VCM = VS/2
12
UNITS TESTED = 6200
VS = 5V
14
TA = 25°C
14
12
-40°C d TA d 125°C
10
8
6
4
4
2
2
0
-5
-4
-3
-2
-1
0
1
2
3
4
0
-20
5
-10
0
10
VOS (PV)
TCVOS (nV/°C)
Figure 7.
Figure 8.
Offset Voltage
vs.
Supply Voltage
PSRR
vs.
Frequency
10
140
5
20
VS = 2.5V, 5V
VCM = VS/2
120
100
-PSRR
PSRR (dB)
OFFSET VOLTAGE (PV)
20
TCVOS Distribution
16
16
10
Figure 6.
18
PERCENTAGE (%)
0
TCVOS (nV/°C)
-40°C
0
25°C
85°C
80
60
+PSRR
40
-5
125°C
20
-10
2
2.5
3
3.5
4
4.5
5
5.5
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
Figure 9.
Figure 10.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, RL > 10 kΩ, VS= V+ – V–, VS= 5V, VCM = VS/2.
Input Bias Current
vs.
VCM
Input Bias Current
vs.
VCM
Figure 11.
Figure 12.
Offset Voltage
vs.
VCM
Offset Voltage
vs.
VCM
10
10
OFFSET VOLTAGE (PV)
OFFSET VOLTAGE (PV)
VS = 2.5V
5
-40°C
25°C
0
85°C
-5
125°C
-10
-0.2
0.2
0.6
1
1.4
5
-40°C
25°C
0
85°C
-5
125°C
-10
-0.2
1.8
3.8
3
Figure 14.
Supply Current
vs.
Supply Voltage (Per Amplifier)
Input Voltage Noise
vs.
Frequency
125°C
1.25
85°C
25°C
1
-40°C
0.75
2
2.5
3
3.5
4
4.5
5
5.5
INPUT VOLTAGE NOISE DENSITY (nV/ Hz)
SUPPLY CURRENT (mA)
2.2
Figure 13.
1.5
GAIN = 1000
VS = 5V
10
VS = 2.5V
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 15.
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4.6
100
SUPPLY VOLTAGE (V)
8
1.4
0.6
COMMON MODE VOLTAGE (V)
COMMON MODE VOLTAGE (V)
Figure 16.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, RL > 10 kΩ, VS= V+ – V–, VS= 5V, VCM = VS/2.
Open Loop Frequency Response
120
100
150
100
PHASE
40
180
150
60
30
20
80
120
60
90
40
PHASE
60
30
20
VS = 2.5V
VS = 5V
0 RL = 2 k:, 10 k:, 10 M:
CL = 20 pF, 50 pF, 100 pF
-20
100k
10k
100
1k
0 RL = 2 k:, 10 k:, 10 M:
CL = 20 pF, 50 pF, 100 pF
-20
100k
10k
100
1k
0
-30
10M
1M
FREQUENCY (Hz)
0
1M
Figure 18.
Open Loop Frequency Response Over Temperature
EMIRR
vs.
Frequency
120
180
160
100
150
140
60
GAIN
20 VS = 5V
RL = 10 k:
30
0 CL = 20 pF
0
100
80
VS = 5V
60
40
TA = -40°C, 25°C, 85°C, 125°C
100k
10k
1k
EMIRR (dB)
90
60
40
120
120
PHASE
PHASE (°)
GAIN (dB)
80
1M
VS = 2.5V
20
-30
10M
0
10
100
FREQUENCY (Hz)
1000
10000
FREQUENCY (MHz)
Figure 19.
Figure 20.
EMIRR
vs.
Input Power
EMIRR
vs.
Input Power
140
120
VS = 5V
VS = 2.5V
120
100
fRF = 2400 MHz
40
20
60
-10
0
fRF = 400 MHz
fRF = 900 MHz
20
fRF = 900 MHz
-20
fRF = 1800 MHz
80
40
fRF = 400 MHz
-30
EMIRR (dB)
fRF = 1800 MHz
60
0
-40
fRF = 2400 MHz
100
80
EMIRR (dB)
-30
10M
FREQUENCY (Hz)
Figure 17.
-20
100
PHASE (°)
90
60
GAIN (dB)
120
PHASE (°)
GAIN (dB)
120
GAIN
GAIN
80
Open Loop Frequency Response
180
10
20
30
0
-40
-30
-20
-10
0
10
20
RF INPUT SIGNAL PEAK (dBm)
RF INPUT SIGNAL PEAK (dBm)
Figure 21.
Figure 22.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, RL > 10 kΩ, VS= V+ – V–, VS= 5V, VCM = VS/2.
Time Domain Input Voltage Noise
Time Domain Input Voltage Noise
Figure 23.
Figure 24.
CMRR
vs.
Frequency
Slew Rate
vs.
Supply Voltage
160
VS = 2.5V
VIN = 1 VPP
AV = +1
f = 10 kHz
VCM = VS/2
140
2.8
SLEW RATE (V/Ps)
VS = 5V
120
CMRR (dB)
3
VS = 2.5V, 5V
100
80
RL = 10 k:
CL = 20 pF
FALLING EDGE
2.6
2.4
RISING EDGE
2.2
60
40
10
100
1k
10k
2
100k
2
2.5
3
3.5
4
4.5
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
Figure 25.
Figure 26.
Output Swing High
vs.
Supply Voltage
Output Swing Low
vs.
Supply Voltage
5
5.5
160
200
RL = 2 k:
RL = 2 k:
125°C
125°C
VOUT from RAIL (mV)
VOUT from RAIL (mV)
160
85°C
120
25°C
80
-40°C
120
85°C
25°C
80
-40°C
40
40
0
0
2
2.5
3
3.5
4
4.5
5
5.5
2
SUPPLY VOLTAGE (V)
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3
3.5
4
4.5
5
5.5
SUPPLY VOLTAGE (V)
Figure 27.
10
2.5
Figure 28.
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SNOSAY9E – SEPTEMBER 2008 – REVISED MARGH 2013
Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, RL > 10 kΩ, VS= V+ – V–, VS= 5V, VCM = VS/2.
Output Swing High
vs.
Supply Voltage
Output Swing Low
vs.
Supply Voltage
120
200
RL = 10 k:
RL = 10 k:
100
125°C
120
85°C
80
25°C
40
125°C
VOUT from RAIL (mV)
VOUT from RAIL (mV)
160
80
40
-40°C
-40°C
20
0
0
2
2.5
3
3.5
4
4.5
85°C
25°C
60
5
5.5
2
2.5
3
3.5
4
4.5
5
Figure 29.
Figure 30.
Overload Recovery Time
Overload Recovery Time
50 mV/DIV
INPUT
VS = 5V
50 mV/DIV
INPUT
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
AV = -50 V/V
RL = 10 k:
VS = 5V
AV = -50 V/V
RL = 10 k:
|
|
1 V/DIV
OUTPUT
1 V/DIV
OUTPUT
2 Ps/DIV
10 Ps/DIV
Figure 31.
Figure 32.
Large Signal Step Response
Small Signal Step Response
20 mV/DIV
200 mV/DIV
|
|
VS = 2.5V
AV = +1
VIN = 1 VPP
f = 10 kHz
VS = 2.5V
AV = +1
VIN = 100 mVPP
f = 10 kHz
RL = 10 k:
RL = 10 k:
CL = 20 pF
CL = 20 pF
10 Ps/DIV
10 Ps/DIV
Figure 33.
Figure 34.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, RL > 10 kΩ, VS= V+ – V–, VS= 5V, VCM = VS/2.
Small Signal Step Response
20 mV/DIV
500 mV/DIV
Large Signal Step Response
VS = 5V
AV = +1
VS = 5V
AV = +1
VIN = 2 VPP
f = 10 kHz
VIN = 100 mVPP
f = 10 kHz
RL = 10 k:
RL = 10 k:
CL = 20 pF
CL = 20 pF
10 Ps/DIV
10 Ps/DIV
Figure 35.
Figure 36.
Output Voltage
vs.
Output Current
Cross Talk Rejection Ratio
vs.
Frequency (LMP2022)
200
VS = 2.5V, 5V
+
VOUT from RAIL (V)
(V ) -0.2
+
(V ) -0.4
+
(V ) -0.6
0.4
|
125°C
85°C
-40°C
25°C
|
0.2
0
0
5
10
15
20
25
30
35
40
CROSSTALK REJECTION RATIO (dB)
+
V
VS = 2.5V
180
Channel A to B
160
140
120
60
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 37.
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Channel B to A
80
OUTPUT CURRENT (mA)
12
VS = 5V
100
Figure 38.
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APPLICATION INFORMATION
LMP2021/LMP2022
The LMP2021/LMP2022 are single and dual precision operational amplifiers with ultra low offset voltage, ultra
low offset voltage drift, and very low input voltage noise with no 1/f and extended supply voltage range. The
LMP2021/LMP2022 offer on chip EMI suppression circuitry which greatly enhances the performance of these
precision amplifiers in the presence of radio frequency signals and other disturbances.
The LMP2021/LMP2022 utilize proprietary techniques to measure and continuously correct the input offset error
voltage. The LMP2021/LMP2022 have a DC input offset voltage with a maximum value of ±5 μV and an input
offset voltage drift maximum value of 0.02 µV/°C. The input voltage noise of the LMP2021/LMP2022 is less than
11 nV/√Hz at a voltage gain of 1000 V/V and has no flicker noise component. This makes the
LMP2021/LMP2022 ideal for high accuracy, low frequency applications where lots of amplification is needed and
the input signal has a very small amplitude.
The proprietary input offset correction circuitry enables the LMP2021/LMP2022 to have superior CMRR and
PSRR performances. The combination of an open loop voltage gain of 160 dB, CMRR of 142 dB, PSRR of 130
dB, along with the ultra low input offset voltage of only −0.4 µV, input offset voltage drift of only −0.004 µV/°C,
and input voltage noise of only 260 nVPP at 0.1 Hz to 10 Hz make the LMP2021/LMP2022 great choices for high
gain transducer amplifiers, ADC buffer amplifiers, DAC I-V conversion, and other applications requiring precision
and long-term stability. Other features are rail-to-rail output, low supply current of 1.1 mA per amplifier, and a
gain-bandwidth product of 5 MHz.
The LMP2021/LMP2022 have an extended supply voltage range of 2.2V to 5.5V, making them ideal for battery
operated portable applications. The LMP2021 is offered in 5-pin SOT-23 and 8-pin SOIC packages. The
LMP2022 is offered in 8-pin VSSOP and 8-Pin SOIC packages.
EMI SUPPRESSION
The near-ubiquity of cellular, bluetooth, and Wi-Fi signals and the rapid rise of sensing systems incorporating
wireless radios make electromagnetic interference (EMI) an evermore important design consideration for
precision signal paths. Though RF signals lie outside the op amp band, RF carrier switching can modulate the
DC offset of the op amp. Also some common RF modulation schemes can induce down-converted components.
The added DC offset and the induced signals are amplified with the signal of interest and thus corrupt the
measurement. The LMP2021/LMP2022 use on chip filters to reject these unwanted RF signals at the inputs and
power supply pins; thereby preserving the integrity of the precision signal path.
Twisted pair cabling and the active front-end’s common-mode rejection provide immunity against low frequency
noise (i.e. 60 Hz or 50 Hz mains) but are ineffective against RF interference. Figure 50 displays this. Even a few
centimeters of PCB trace and wiring for sensors located close to the amplifier can pick up significant 1 GHz RF.
The integrated EMI filters of LMP2021/LMP2022 reduce or eliminate external shielding and filtering requirements,
thereby increasing system robustness. A larger EMIRR means more rejection of the RF interference. For more
information on EMIRR, please refer to AN-1698 (Literature Number SNOA497).
INPUT VOLTAGE NOISE
The input voltage noise density of the LMP2021/LMP2022 has no 1/f corner, and its value depends on the
feedback network used. This feature of the LMP2021/LMP2022 differentiates this family from other products
currently available from other vendors. In particular, the input voltage noise density decreases as the closed loop
voltage gain of the LMP2021/LMP2022 increases. The input voltage noise of the LMP2021/LMP2022 is less than
11 nV/√Hz when the closed loop voltage gain of the op amp is 1000. Higher voltage gains are required for
smaller input signals. When the input signal is smaller, a lower input voltage noise is quite advantageous and
increases the signal to noise ratio.
Figure 39 shows the input voltage noise of the LMP2021/LMP2022 as the closed loop gain increases.
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INPUT VOLTAGE NOISE DENSITY (nV/ Hz)
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24
VS = 5V
f = 100 Hz
20
16
12
8
4
0
1
10
100
1000
CLOSED LOOP GAIN (V/V)
Figure 39. Input Voltage Noise Density decreases with Gain
INPUT VOLTAGE NOISE DENSITY (nV/ Hz)
Figure 40 shows the input voltage noise density does not have the 1/f component.
100
GAIN = 100
GAIN = 10
GAIN = 51
10
GAIN = 250
GAIN = 1000
GAIN = 500
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 40. Input Voltage Noise Density with no 1/f
With smaller and smaller input signals and high precision applications with lower error budget, the reduced input
voltage noise and no 1/f noise allow more flexibility in circuit design.
ACHIEVING LOWER NOISE WITH FILTERING
The low input voltage noise of the LMP2021/LMP2022, and no 1/f noise make these suitable for many
applications with noise sensitive designs. Simple filtering can be done on the LMP2021/LMP2022 to remove high
frequency noise. Figure 41 shows a simple circuit that achieves this.
In Figure 41 CF and the corner frequency of the filter resulting from CF and RF will reduce the total noise.
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SNOSAY9E – SEPTEMBER 2008 – REVISED MARGH 2013
RIN//RF
IN
+
-
CF
RF
RIN
Figure 41. Noise Reducing Filter for Lower Gains
In order to achieve lower noise floors for even more noise stringent applications, a simple filter can be added to
the op amp’s output after the amplification stage. Figure 42 shows the schematic of a simple circuit which
achieves this objective. Low noise amplifiers such as the LMV771 can be used to create a single pole low pass
filter on the output of the LMP2021/LMP2022. The noise performance of the filtering amplifier, LMV771 in this
circuit, will not be dominant as the input signal on LMP2021/LMP2022 has already been significantly gained up
and as a result the effect of the input voltage noise of the LMV771 is effectively not noticeable.
CFILT
RIN/RF
RFILT
IN
+
RFILT
LMP2021/
LMP2022
-
RF
LMV771
+
OUT
RIN
Figure 42. Enhanced Filter to Further Reduce Noise at Higher Gains
Using the circuit in Figure 42 has the advantage of removing the non-linear filter bandwidth dependency which is
seen when the circuit in Figure 41 is used. The difference in noise performance of the circuits in Figure 41, 8
becomes apparent only at higher gains. At voltage gains of 10 V/V or less, there is no difference between the
noise performance of the two circuits.
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10
RMS NOISE (PV)
AV = 40 dB
1
2-Stage Filter
AV = 60 dB
0.1
0.01
10
100
1k
10k
3 dB FILTER BANDWIDTH (Hz)
Figure 43. RMS Input Referred Noise vs. Frequency
Figure 43 shows the total input referred noise vs. 3 dB corner of both filters of Figure 41 and Figure 42 at gains
of 100V/V and 1000V/V. For these measurements and using Figure 41's circuit, RF = 49.7 kΩ and RIN = 497Ω.
Value of CF has been changed to achieve the desired 3 dB filter corner frequency. In the case of Figure 42's
circuit, RF = 49.7 kΩ and RIN = 497Ω, RFILT = 49.7 kΩ, and CFILT has been changed to achieve the desired 3 dB
filter corner frequency. Figure 43 compares the RMS noise of these two circuits. As Figure 43 shows, the RMS
noise measured the circuit in Figure 42 has lower values and also depicts a more linear shape.
DIGITAL ACQUISITION SYSTEMS
High resolution ADC’s with 16-bits to 24-bits of resolution can be limited by the noise of the amplifier driving
them. The circuit configuration, the value of the resistors used and the source impedance seen by the amplifier
can affect the noise of the amplifier. The total noise at the output of the amplifier can be dominated by one of
several sources of noises such as: white noise or broad band noise, 1/f noise, thermal noise, and current noise.
In low frequency applications such as medical instrumentation, the source impedance is generally low enough
that the current noise coupled into it does not impact the total noise significantly. However, as the 1/f or flicker
noise is paramount to many application, the use of an auto correcting stabilized amplifier like the
LMP2021/LMP2022 reduces the total noise.
Table 1: RMS Input Noise Performance summarizes the input and output referred RMS noise values for the
LMP2021/LMP2022 compared to that of Competitor A. As described in previous sections, the outstanding noise
performance of the LMP2021/LMP2022 can be even further improved by adding a simple low pass filter following
the amplification stage.
The use of an additional filter, as shown in Figure 42 benefits applications with higher gain. For this reason, at a
gain of 10, only the results of circuit in Figure 41 are shown. The RMS input noise of the LMP2021/LMP2022 are
compared with Competitor A's input noise performance. Competitor A's RMS input noise behaves the same with
or without an additional filter.
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SNOSAY9E – SEPTEMBER 2008 – REVISED MARGH 2013
Table 1. RMS Input Noise Performance
RMS Input Noise (nV)
Amplifier
Gain
(V/V)
System Bandwidth
Requirement (Hz)
10
100
1000
(1)
LMP2021/LMP2022
Competitor A
Figure 41 Circuit
Figure 42 Circuit
100
229
See (1)
Figure 42 Figure 41 Circuit
300
1000
763
See (1)
1030
100
229
196
300
1000
763
621
1030
10
71
46
95
100
158
146
300
1000
608
462
1030
No significant difference in Noise measurements at AV = 10V/V
INPUT BIAS CURRENT
The bias current of the LMP2021/LMP2022 behaves differently than a conventional amplifier due to the dynamic
transient currents created on the input of an auto-zero circuit. The input bias current is affected by the charge
and discharge current of the input auto-zero circuit. The amount of current sunk or sourced from that stage is
dependent on the combination of input impedance (resistance and capacitance), as well as the balance and
matching of these impedances across the two inputs. This current, integrated in the auto-zero circuit, causes a
shift in the apparent "bias current". Because of this, there is an apparent "bias current vs. input impedance"
interaction. In the LMP2021/LMP2022 for an input resistive impedance of 1 GΩ, the shift in input bias current can
be up to 40 pA. This input bias shift is caused by varying the input's capacitive impedance. Since the input bias
current is dependent on the input impedance, it is difficult to estimate what the actual bias current is without
knowing the end circuit and associated capacitive strays.
Figure 44 shows the input bias current of the LMP2021/LMP2022 and that of another commercially available
amplifier from a competitor. As it can be seen, the shift in LMP2021/LMP2022 bias current is much lower than
that of other chopper style or auto zero amplifiers available from other vendors.
LMP2021/LMP2022
CG = 0, 1, 3, 5, 8, 10, 20, 50, 75, 100, 200, 500, 1000 pF
VS = 5V, VCM = VS/2, RG = 1 G:
150
IBIAS (pA)
Competitor A
175
CG = 1000 pF
150
125
125
100
100
75
CG = 1000 pF
CG = 20 pF
50
75
CG = 20 pF
50
25
25
0
0
IBIAS (pA)
175
-25
-25
-50
0
-50
CG = 0 pF
CG = 0 pF
-75
10 20 30 40 50 60 70 80 90 100
TIME (s)
10
20
30
40
50
60
70
80
-75
90 100
TIME (s)
Figure 44. Input Bias Current of LMP2021/LMP2022 is lower than Competitor A
LOWERING THE INPUT BIAS CURRENT
As mentioned in the INPUT BIAS CURRENT section, the input bias current of an auto zero amplifier such as the
LMP2021/LMP2022 varies with input impedance and feedback impedance. Once the value of a certain input
resistance, i.e. sensor resistance, is known, it is possible to optimize the input bias current for this fixed input
resistance by choosing the capacitance value that minimizes that current. Figure 45 shows the input bias current
vs. input impedance of the LMP2021/LMP2022. The value of RG or input resistance in this test is 1 GΩ. When
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this value of input resistance is used, and when a parallel capacitance of 22 pF is placed on the circuit, the
resulting input bias current is nearly 0 pA. Figure 45 can be used to extrapolate capacitor values for other sensor
resistances. For this purpose, the total impedance seen by the input of the LMP2021/LMP2022 needs to be
calculated based on Figure 45. By knowing the value of RG, one can calculate the corresponding CG which
minimizes the non-inverting input bias current, positive bias current, value.
POSITIVE BIAS CURRENT (pA)
30
18
6
-6
+
RG
-18
CG
-30
1
10
100
1000
INPUT CAPACITANCE (pF)
Figure 45. Input Bias Current vs. CG with RG = 1 GΩ
In a typical I-V converter, the output voltage will be the sum of DC offset plus bias current and the applied signal
through the feedback resistor. In a conventional input stage, the inverting input's capacitance has very little effect
on the circuit. This effect is generally on settling time and the dielectric soakage time and can be ignored. In auto
zero amplifiers, the input capacitance effect will add another term to the output. This additional term means that
the baseline reading on the output will be dependent on the input capacitance. The term input capacitance for
this purpose includes circuit strays and any input cable capacitances. There is a slight variation in the capacitive
offset as the duty cycle and amplitude of the pulses vary from part to part, depending on the correction at the
time. The lowest input current will be obtained when the impedances, both resistive and capacitive, are matched
between the inputs. By balancing the input capacitances, the effect can be minimized. A simple way to balance
the input impedance is adding a capacitance in parallel to the feedback resistance. The addition of this feedback
capacitance reduces the bias current and increases the stability of the operational amplifier. Figure 46 shows the
input bias current of the LMP2021/LMP2022 when RF is set to 1 GΩ. As it can be seen from Figure 46, choosing
the optimum value of CF will help reducing the input bias current.
NEGATIVE BIAS CURRENT (pA)
156
130
104
78
CF
52
RF
+
26
0
1
10
100
1000
FEEDBACK CAPACITANCE (pF)
Figure 46. Input Bias Current vs. CF with RF = 1 GΩ
The effect of bias current on a circuit can be estimated with the following:
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AV*IBIAS+*ZS - IBIAS−*ZF
(1)
Where AV is the closed loop gain of the system and IBIAS+ and IBIAS− denote the positive and negative bias
current, respectively. It is common to show the average of these bias currents in product datasheets. If IBIAS+ and
IBIAS− are not individually specified, use the IBIAS value provided in datasheet graphs or tables for this calculation.
For the application circuit shown in Figure 50, the LMP2022 amplifiers each have a gain of 18. With a sensor
impedance of 500Ω for the bridge, and using the above equation, the total error due to the bias current on the
outputs of the LMP2022 amplifier will be less than 200 nV.
SENSOR IMPEDANCE
The sensor resistance, or the resistance connected to the inputs of the LMP2021/LMP2022, contributes to the
total impedance seen by the auto correcting input stage.
RIN
VIN
+
VIN_DIFF
FEEDBACK
NETWORK
RIN
RON_SWITCH
VIN
VOUT
INPUT
SWITCHES
+
VIN_DIFF
COUT
Figure 47. Auto Correcting Input Stage Model
As shown in Figure 47, the sum of RIN and RON-SWITCH will form a low pass filter with COUT during correction
cycles. As RIN increases, the time constant of this filter increases, resulting in a slower output signal which could
have the effect of reducing the open loop gain, AVOL, of the LMP2021/LMP2022. In order to prevent this
reduction in AVOL in presence of high impedance sensors or other high resistances connected to the input of the
LMP2021/LMP2022, a capacitor can be placed in parallel to this input resistance. This is shown in Figure 48
CIN
RIN
VIN
+
VIN_DIFF
FEEDBACK
NETWORK
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CIN
RON_SWITCH
RIN
VIN
VOUT
INPUT
SWITCHES
+
VIN_DIFF
COUT
Figure 48. Sensor Impedance with Parallel Capacitance
CIN in Figure 48 adds a zero to the low pass filter and hence eliminating the reduction in AVOL of the
LMP2021/LMP2022. An alternative circuit to achieve this is shown in Figure 49.
RIN
VIN
+
CIN
VIN_DIFF
FEEDBACK
NETWORK
Figure 49. Alternative Sensor Impedance Circuit
TRANSIENT RESPONSE TO FAST INPUTS
On chip continuous auto zero correction circuitry eliminates the 1/f noise and significantly reduces the offset
voltage and offset voltage drift; all of which are very low frequency events. For slow changing sensor signals this
correction is transparent. For excitations which may otherwise cause the output to swing faster than 40 mV/µs,
there are additional considerations which can be viewed two perspectives: for sine waves and for steps.
For sinusoidal inputs, when the output is swinging rail-to-rail on ±2.5V supplies, the auto zero circuitry will
introduce distortions above 2.55 kHz. For smaller output swings, higher frequencies can be amplified without the
auto zero slew limitation as shown in table below. Signals above 20 kHz, are not affected, though normally,
closed loop bandwidth should be kept below 20 kHz so as to avoid aliasing from the auto zero circuit.
VOUT-PEAK (V)
fMAX-SINE WAVE (kHz)
0.32
20
1
6.3
2.5
2.5
For step-like inputs, such as those arising from disturbances to a sensing system, the auto zero slew rate
limitation manifests itself as an extended ramping and settling time, lasting ~100 µs.
DIFFERENTIAL BRIDGE SENSOR
Bridge sensors are used in a variety of applications such as pressure sensors and weigh scales. Bridge sensors
typically have a very small differential output signal. This very small signal needs to be accurately amplified
before it can be fed into an ADC. As discussed in the previous sections, the accuracy of the op amp used as the
ADC driver is essential to maintaining total system accuracy.
The high DC performance of the LMP2021/LMP2022 make these amplifiers ideal choices for use with a bridge
sensor. The LMP2021/LMP2022 have very low input offset voltage and very low input offset voltage drift. The
open loop gain of the LMP2021/LMP2022 is 160 dB.
The on chip EMI rejection filters available on the LMP2021/LMP2022 help remove the EMI interference
introduced to the signal and hence improve the overall system performance.
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The circuit in Figure 50 shows a signal path solution for a typical bridge sensor using the LMP2021/LMP2022.
Bridge sensors are created by replacing at least one, and up to all four, of the resistors in a typical bridge with a
sensor whose resistance varies in response to an external stimulus. Using four sensors has the advantage of
increasing output dynamic range. Typical output voltage of one resistive pressure sensor is 2 mV per 1V of
bridge excitation voltage. Using four sensors, the output of the bridge is 8 mV per 1V. The bridge voltage is this
system is chosen to be 1/2 of the analog supply voltage and equal to the reference voltage of the ADC161S626,
2.5V. This excitation voltage results in 2.5V * 8 mV = 20 mV of differential output signal on the bridge. This 20
mV signal must be accurately amplified by the amplifier to best match the dynamic input range of the ADC. This
is done by using one LMP2022 and one LMP2021 in front of the ADC161S626. The gaining of this 20 mV signal
is achieved in 2 stages and through an instrumentation amplifier. The LMP2022 in Figure 50 amplifies each side
of the differential output of the bridge sensor by a gain 18. Bridge sensor measurements are usually done up to
10s of Hz. Placing a 300 Hz filter on the LMP2022 helps removing the higher frequency noise from this circuit.
This filter is created by placing two capacitors in the feedback path of the LMP2022 amplifiers. Using the
LMP2022 with a gain of 18 reduces the input referred voltage noise of the op amps and the system as a result.
Also, this gain allows direct filtering of the signal on the LMP2022 without compromising noise performance. The
differential output of the two amplifiers in the LMP2022 are then fed into a LMP2021 configured as a difference
amplifier. This stage has a gain of 5, with a total system having a gain of (18*2+1)*5 = 185. The LMP2021 has an
outstanding CMRR value of 139. This impressive CMRR improves system performance by removing the
common mode signal introduced by the bridge. With an overall gain of 185, the 20 mV differential input signal is
gained up to 3.7V. This utilizes the amplifiers output swing as well as the ADC's input dynamic range.
This amplified signal is then fed into the ADC161S626. The ADC161S626 is a 16-bit, 50 kSPS to 250 kSPS 5V
ADC. In order to utilize the maximum number of bits of the ADC161S626 in this configuration, a 2.5V reference
voltage is used. This 2.5V reference is also used to power the bridge sensor and the inverting input of the ADC.
Using the same voltage source for these three points helps reducing the total system error by eliminating error
due to source variations.
With this system, the output signal of the bridge sensor which can be up to 20 mV is accurately gained to the full
scale of the ADC and then digitized for further processing. The LMP2021/LMP2022 introduced minimal error to
the system and improved the signal quality by removing common model signals and high frequency noise.
VA
VA = 5V
+
1/2
LMP2022
EMI
R1
-
0.1 PF
R4
1 k:
200:
5.1 k:
0.1%
VA
180:
-
+
LMP2021
280:
R2
VA
470 pF
ADC161S626
-
+
R3
VA
-
0.1 PF
5.1 k:
0.1%
1/2
LMP2022
+
VR = 1/2 VA
200:
1 k:
Figure 50. LMP2021/LMP2022 used with ADC161S626
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMP2021 LMP2022
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21
LMP2021, LMP2022
SNOSAY9E – SEPTEMBER 2008 – REVISED MARGH 2013
www.ti.com
REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
•
22
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMP2021 LMP2022
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMP2021MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP20
21MA
LMP2021MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP20
21MA
LMP2021MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AF5A
LMP2021MFE/NOPB
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AF5A
LMP2021MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AF5A
LMP2022MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP20
22MA
LMP2022MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP20
22MA
LMP2022MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AV5A
LMP2022MME/NOPB
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AV5A
LMP2022MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AV5A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
11-Apr-2013
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMP2021MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMP2021MF/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMP2021MFE/NOPB
SOT-23
DBV
5
250
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMP2021MFX/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMP2022MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMP2022MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP2022MME/NOPB
VSSOP
DGK
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP2022MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMP2021MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMP2021MF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMP2021MFE/NOPB
SOT-23
DBV
5
250
210.0
185.0
35.0
LMP2021MFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMP2022MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMP2022MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMP2022MME/NOPB
VSSOP
DGK
8
250
210.0
185.0
35.0
LMP2022MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
Pack Materials-Page 2
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