ON MC100LVEL56 3.3 v ecl dual differential 2:1 multiplexer Datasheet

MC100LVEL56
3.3V ECL Dual Differential
2:1 Multiplexer
Description
The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low skew
clock or other skew sensitive signals.
The device features both individual and common select inputs to
address both data path and random logic applications.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs are
left open the D input will pull down to VEE, The D input will bias
around VCC/2 forcing the Q output LOW.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB and
VCC via a 0.01ĂmF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open.
Features
•
•
•
•
•
•
•
•
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SOIC−20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
580 ps Typical Propagation Delays
Separate and Common Select
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:
VCC = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −3.8 V
Internal Input Pulldown Resistors on D(s), SEL(s), and COM_SEL
Q Output will Default LOW with Inputs Open or at VEE
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
100LVEL56
AWLYYWWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
MC100LVEL56DWG
Package
Shipping†
SOIC−20 WB
(Pb-Free)
38 Units/Tube
MC100LVEL56DWR2G SOIC−20 WB 1000/Tape & Reel
(Pb-Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 13
1
Publication Order Number:
MC100LVEL56/D
MC100LVEL56
Q0
Q0
SEL0
20
19
18
17
1
COM_SEL
VCC
Table 1. PIN DESCRIPTION
D0a* − D1a*
ECL Input Data a
SEL1
VCC
Q1
Q1
VEE
D0a* − D1a*
ECL Input Data a Invert
16
15
14
13
12
11
D0b* − D1b*
ECL Input Data b
D0b* − D1b*
ECL Input Data b Invert
SEL0* − SEL1*
ECL Indiv. Select Input
COM_SEL*
ECL Common Select Input
VBB0, VBB1
Output Reference Voltage
FUNCTION
PIN
0
1
0
Q0 − Q1
ECL True Outputs
Q0 − Q1
ECL Inverted Outputs
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
1
D0a
2
D0a
3
4
VBBO D0b
5
D0b
6
7
D1a D1a
8
VBB1
9
D1b
10
D1b
Table 2. TRUTH TABLE
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
SEL0
SEL1
COM_SEL
Q0,
Q0
Q1,
Q1
X
L
L
H
H
X
L
H
H
L
H
L
L
L
L
a
b
b
a
a
a
b
a
a
b
Figure 1. 20-Lead Package (Top View) and Logic Diagram
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 KW
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Device Model
> 2 kV
> 200 V
> 4 kV
Moisture Sensitivity, (Note 1)
Pb-Free
Level 3
Flammability Rating
Oxygen Index
UL 94 V−0 @ 0.125 in
28 to 34
Transistor Count
147
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC100LVEL56
Table 4. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6 to 0
−6 to 0
V
Iout
Output Current
Continuous
Surge
50
100
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
SOIC−20 WB
90
60
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
SOIC−20 WB
30 to 35
°C/W
Tsol
Wave Solder (Pb-Free)
2 to 3 sec @ 260°C
265
°C
VI ≤ VCC
VI ≥ VEE
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 5. LVPECL DC CHARACTERISTICS (VCC = 3.3 V; VEE = 0.0 V (Note 1))
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
20
24
20
24
20
24
mA
VOH
Output HIGH Voltage (Note 2)
2215
2295
2420
2275
2345
2420
2275
2345
2420
mV
VOL
Output LOW Voltage (Note 2)
1470
1605
1745
1490
1595
1680
1490
1595
1680
mV
VIH
Input HIGH Voltage (Single-Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1490
1825
1490
1825
1490
1825
mV
VBB
Output Voltage Reference
1.92
2.04
1.92
2.04
1.92
2.04
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
Vpp < 500 mV
Vpp ≥ 500 mV
IIH
Input HIGH Current
IIL
Input LOW Current
Dn
Dn
V
1.3
1.5
2.9
2.9
1.2
1.4
150
0.5
−600
2.9
2.9
1.2
1.4
150
0.5
−600
2.9
2.9
150
0.5
−600
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP(min)
and 1 V.
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MC100LVEL56
Table 6. LVNECL DC CHARACTERISTICS (VCC = 0.0 V; VEE = −3.3 V (Note 1))
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
20
24
Min
85°C
Typ
Max
20
24
Min
Typ
Max
Unit
20
24
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 2)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
VIH
Input HIGH Voltage (Single-Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage (Single-Ended)
−1810
−1475
−1810
−1475
−1810
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
Vpp < 500 mV
Vpp ≥ 500 mV
IIH
Input HIGH Current
IIL
Input LOW Current
Dn
Dn
V
−2.0
1.8
−0.4
0.4
−2.1
1.9
−0.4
0.4
150
0.5
−600
−2.1
1.9
−0.4
0.4
150
0.5
−600
150
mA
mA
0.5
−600
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
2. Outputs are terminated through a 50ĂW resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin
and 1 V.
Table 7. AC CHARACTERISTICS (VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 1))
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
fmax
Maximum Toggle Frequency
(See Figure 2, Fmax/JITTER)
tPLH
tPHL
Propagation Delay to Output
D
SEL
COMSEL
tSKEW
Within−Device Skew (Note 2)
tSKEW
Duty Cycle Skew (Note 3)
tJITTER
Random Clock Jitter (RMS)
VPP
Input Swing (Note 4)
150
1000
150
1000
tr
tf
Output Rise/Fall Times Q
(20% − 80%)
200
540
200
540
Min
Typ
Max
1
400
430
430
600
730
730
40
420
440
440
80
GHz
440
620
740
740
40
80
100
Unit
440
450
450
640
750
750
40
ps
80
ps
100
ps
150
1000
mV
200
540
ps
100
1.5
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. VEE can vary ±0.3 V.
2. Within-device skew is defined as identical transitions on similar paths through a device.
3. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point
of the outputs.
4. VPP(min) is minimum input swing for which AC parameters are guaranteed.
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4
1000
10
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
0
2
(JITTER)
100
0
250
JITTER (ps RMS)
OUTPUT VOLTAGE (mV amplitude)
MC100LVEL56
1
500
750
1000
1250
1500
1750
2000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Zo = 50 W
Q
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
−
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
The ECL Translator Guide
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5
MC100LVEL56
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
A1
SEATING
PLANE
c
T
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
RECOMMENDED
SOLDERING FOOTPRINT*
20X
20X
1.30
0.52
20
11
11.00
1
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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