E2E0053-59-71
¡ Semiconductor
ML63187/63189B
¡ Semiconductor
This version:
Jul. 1999
ML63187/63189B
Previous version: Mar. 1999
4-Bit Microcontroller with Built-in 1024-Dot Matrix LCD Drivers and Melody Circuit,
Operating at 0.9 V (Min.)
GENERAL DESCRIPTION
The ML63187/63189B is a CMOS 4-bit microcontroller with built-in 1024-dot matrix LCD drivers
and operates at 0.9 V (min.). The ML63187/63189B is suitable for applications such as games,
toys, watches, etc. which are provided with an LCD display.
The ML63187/63189B is an M6318x series mask ROM-version product of OLMS-63K family,
which employs Oki's original CPU core nX-4/250.
FEATURES
• Rich instruction set
408 instructions
Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations,
mask operations, bit operations, ROM table reference, stack operations, flag operations,
branch, conditional branch, call/return, control.
• Rich selection of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank
register, HL register and XY register.
Data memory bank internal direct addressing mode.
• Processing speed
Two clocks per machine cycle, with most instructions executed in one machine cycle.
Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock)
1 ms (@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock
High-speed clock
: Crystal oscillation or RC oscillation selected with
mask option (30 to 80 kHz)
: Ceramic oscillation or RC oscillation selected with
software (2 MHz max.)
• Program memory space
• ML63187 : 16K words
• ML63189B : 32K words
Basic instruction length is 16 bits/1 word
• Data memory space
• ML63187 : 1024 nibbles
• ML63189B : 1536 nibbles
1/35
¡ Semiconductor
ML63187/63189B
• Stack level
Call stack level
Register stack level
: 16 levels
: 16 levels
• I/O ports
Input ports: Selectable as input with pull-up resistor/input with pull-down resistor/highimpedance input
Input-output ports: Selectable as input with pull-up resistor/input with pull-down resistor/
high-impedance input
Selectable as P-channel open drain output/N-channel open drain
output/CMOS output/high-impedance output
Can be interfaced with external peripherals that use a different power supply than this device
uses.
Number of ports:
ML63187
Input-output port
: 2 ports ¥ 4 bits
ML63189B
Input port
: 1 port ¥ 4 bits
Input-output port
: 4 ports ¥ 4 bits
• Melody output
Melody frequency
Tone length
Tempo
Melody data
Buzzer driver signal output
:
:
:
:
:
529 to 2979 Hz
63 types
15 types
Resides in the program memory
4 kHz
• LCD driver
Number of segments
: 1024 Max. (64 SEG ¥ 16 COM)
1/1 to 1/16 duty
1/4 or 1/5 bias (regulator built-in)
Selectable as all-ON mode/all-OFF mode/power down mode/normal display mode
Adjustable contrast
• Reset function
Reset through RESET pin
Power-on reset
Reset by low-speed oscillation halt
• Battery check
Low-voltage supply check
The value of the judgment voltage is selected by the software by setting the LD1 and LD0 bits
of BLDCON.
LD1
LD0
Judgment Voltage (V)
Remarks
0
0
1.05 ±0.10
Ta = 25°C
0
1
1.20 ±0.10
Ta = 25°C
1
0
1.80 ±0.10
Ta = 25°C
1
1
2.40 ±0.10
Ta = 25°C
2/35
¡ Semiconductor
ML63187/63189B
• Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
• Timers and counter
8-bit timer ¥ 4
Selectable as auto-reload mode/capture mode/clock frequency measurement mode
Watchdog timer ¥ 1
100 Hz timer ¥ 1
Measurable in steps of 1/100 sec.
15-bit time base counter ¥ 1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
• Shift register
Shift clock
Data length
• Interrupt sources
ML63187
External interrupt
Internal interrupt
ML63189B
External interrupt
Internal interrupt
: 1 ¥ or 1/2 ¥ system clock, timer 1 overflow,
external clock
: 8 bits
: 2
: 12 (watchdog timer interrupt is a nonmaskable interrupt)
: 3
: 12 (watchdog timer interrupt is a nonmaskable interrupt)
• Operating temperature
–20 to +70°C
• Operating voltage
When backup used
When backup not used
: 0.9 to 2.7 V
(Operating frequency: 30 to 80 kHz)
1.2 to 2.7 V
(Operating frequency: 300 to 500 kHz)
1.5 to 2.7 V
(Operating frequency: 200 kHz to 1 MHz)
: 1.8 to 5.5 V
(Operating frequency: 200 kHz to 2 MHz)
• Package:
128-pin plastic QFP (QFP128-P-1420-0.50-K) : (Product name: ML63187-xxxGA,
ML63189B-xxxGA)
Chip
: ML63187-xxx, ML63189B-xxx
xxx indicates a code number.
3/35
¡ Semiconductor
ML63187/63189B
BLOCK DIAGRAM (ML63187)
An asterisk (*) indicates the port secondary function.
indicates that the power is supplied
to the circuits corresponding to the signal names inside
from VDDI (power supply for
interface).
nX-4/250
TIMING
CONTROL
SP
CBR
H
L
RA
EBR
X
Y
A
C
ALU
RSP
G
MIE
STACK
INSTRUCTION
CAL : 16-level
DECODER
PC
Z
ROM
16KW
BUS
CONTROL
IR
REG : 16-level
INT
4
TIMER
8bit ¥ 4
RAM
1024N
RESET
RST
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
INT187
INT
1
INT
TST1
TST2
4
TST
TBC
SCLK*
SFT
SIN*
BLD
XT0
XT1
INT
OSC
1
OSC0
100HzTC
DATA BUS
SOUT*
INT
1
MELODY
OSC1
MD
MDB
INT
1
WDT
VDDH
VDD
CB1
BACK
UP
INT
2
I/O
PORT
PB.0-PB.3
PE.0-PE.3
CB2
VDD1
VDD2
VDD3
VDD4
VDD5
BIAS
LCD
&
DSPR
COM1-16
SEG0-63
C1
C2
VDDI
VSS
VDDL
4/35
¡ Semiconductor
ML63187/63189B
BLOCK DIAGRAM (ML63189B)
An asterisk (*) indicates the port secondary function.
indicates that the power is supplied
to the circuits corresponding to the signal names inside
from VDDI (power supply for
interface).
nX-4/250
TIMING
CONTROL
SP
CBR
H
L
RA
EBR
X
Y
A
C
ALU
RSP
G
MIE
STACK
INSTRUCTION
CAL : 16-level
DECODER
PC
Z
ROM
32KW
BUS
CONTROL
IR
REG : 16-level
INT
4
TIMER
8bit ¥ 4
RAM
1536N
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
INT
RESET
1
INT189
RST
INT
TST
SOUT*
BLD
XT0
INT
XT1
OSC
1
OSC0
OSC1
100HzTC
INT
1
MELODY
INPUT
PORT
CB1
P0.0-P0.3
WDT
VDDH
VDD
MD
MDB
INT
1
INT
1
SIN*
TBC
DATA BUS
4
TST1
TST2
SCLK*
SFT
P9.0-P9.3
BACK
UP
I/O
PORT
CB2
PB.0-PB.3
INT
VDD1
PA.0-PA.3
2
PE.0-PE.3
VDD2
VDD3
VDD4
VDD5
C1
C2
VDDL
BIAS
LCD
&
DSPR
COM1-16
SEG0-63
VDDI
VSS
5/35
¡ Semiconductor
ML63187/63189B
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
PIN CONFIGURATION (TOP VIEW) (ML63187)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
(NC)
(NC)
(NC)
(NC)
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
PB.3
PB.2
PB.1
PB.0
PE.3
PE.2
PE.1
PE.0
VDDI
(NC)
(NC)
(NC)
(NC)
(NC)
COM13
COM14
COM15
COM16
VSS
VDD1
VDD2
VDD3
VDD4
VDD5
C1
C2
VDDH
CB1
CB2
VDD
VDDL
OSC1
OSC0
RESET
XT1
XT0
TST1
TST2
MD
MDB
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
(NC)
(NC)
(NC)
(NC)
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
COM9
COM10
COM11
COM12
(NC)
(NC)
(NC)
(NC)
128-Pin Plastic QFP
Note: Pins marked as (NC) are no-connection pins which are left open.
6/35
¡ Semiconductor
ML63187/63189B
PAD CONFIGURATION (ML63187)
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
MDB
MD
TST2
TST1
XT0
XT1
RESET
OSC0
OSC1
VDDL
VDD
CB2
CB1
VDDH
C2
C1
VDD5
VDD4
VDD3
VDD2
VDD1
VSS
COM16
COM15
COM14
COM13
Pad Layout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
ML63187
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
COM12
COM11
COM10
COM9
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
Y
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
VDDI
PE.0
PE.1
PE.2
PE.3
PB.0
PB.1
PB.2
PB.3
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
Chip size
Chip thickness
Coordinate origin
Pad hole size
Pad size
Minimum pad pitch
:
:
:
:
:
:
X
4.238 mm ¥ 4.914 mm
350 mm (280 mm: available as required)
center of chip
100 mm ¥ 100 mm
110 mm ¥ 110 mm
140 mm
Note: The chip substrate voltage is VSS.
7/35
¡ Semiconductor
ML63187/63189B
Pad Coordinates (ML63187)
Pad
Pad
Pad
Pad No. Name X (µm) Y (µm) Pad No. Name X (µm) Y (µm) Pad No. Name X (µm) Y (µm)
1
SEG12
–1755
–2311
42
SEG53
1969
70
83
VDDI
–1969
1895
2
SEG13
–1615
–2311
43
SEG54
1969
211
84
PE.0
–1969
1755
3
SEG14
–1474
–2311
44
SEG55
1969
351
85
PE.1
–1969
1615
4
SEG15
–1334
–2311
45
SEG56
1969
491
86
PE.2
–1969
1474
5
SEG16
–1193
–2311
46
SEG57
1969
632
87
PE.3
–1969
1334
6
SEG17
–1053
–2311
47
SEG58
1969
772
88
PB.0
–1969
1193
7
SEG18
–913
–2311
48
SEG59
1969
913
89
PB.1
–1969
1053
8
SEG19
–772
–2311
49
SEG60
1969
1053
90
PB.2
–1969
913
9
SEG20
–632
–2311
50
SEG61
1969
1193
91
PB.3
–1969
772
10
SEG21
–491
–2311
51
SEG62
1969
1334
92
COM1
–1969
632
11
SEG22
–351
–2311
52
SEG63
1969
1474
93
COM2
–1969
491
12
SEG23
–211
–2311
53
COM9
1969
1615
94
COM3
–1969
351
13
SEG24
–70
–2311
54
COM10
1969
1755
95
COM4
–1969
211
14
SEG25
70
–2311
55
COM11
1969
1895
96
COM5
–1969
70
15
SEG26
211
–2311
56
COM12
1969
2036
97
COM6
–1969
–70
16
SEG27
351
–2311
57
COM13
1755
2311
98
COM7
–1969
–211
17
SEG28
491
–2311
58
COM14
1615
2311
99
COM8
–1969
–351
18
SEG29
632
–2311
59
COM15
1474
2311
100
SEG0
–1969
–491
19
SEG30
772
–2311
60
COM16
1334
2311
101
SEG1
–1969
–632
20
SEG31
913
–2311
61
VSS
1193
2311
102
SEG2
–1969
–772
21
SEG32
1053
–2311
62
VDD1
1053
2311
103
SEG3
–1969
–913
22
SEG33
1193
–2311
63
VDD2
913
2311
104
SEG4
–1969
–1053
23
SEG34
1334
–2311
64
VDD3
772
2311
105
SEG5
–1969
–1193
24
SEG35
1474
–2311
65
VDD4
632
2311
106
SEG6
–1969
–1334
25
SEG36
1615
–2311
66
VDD5
491
2311
107
SEG7
–1969
–1474
26
SEG37
1755
–2311
67
C1
351
2311
108
SEG8
–1969
–1615
27
SEG38
1969
–2036
68
C2
211
2311
109
SEG9
–1969
–1755
28
SEG39
1969
–1895
69
VDDH
70
2311
110
SEG10
–1969
–1895
29
SEG40
1969
–1755
70
CB1
–70
2311
111
SEG11
–1969
–2036
30
SEG41
1969
–1615
71
CB2
–211
2311
31
SEG42
1969
–1474
72
VDD
–351
2311
32
SEG43
1969
–1334
73
VDDL
–491
2311
33
SEG44
1969
–1193
74
OSC1
–632
2311
34
SEG45
1969
–1053
75
OSC0
–772
2311
35
SEG46
1969
–913
76
RESET
–913
2311
36
SEG47
1969
–772
77
XT1
–1053
2311
37
SEG48
1969
–632
78
XT0
–1193
2311
38
SEG49
1969
–491
79
TST1
–1334
2311
39
SEG50
1969
–351
80
TST2
–1474
2311
40
SEG51
1969
–211
81
MD
–1615
2311
41
SEG52
1969
–70
82
MDB
–1755
2311
8/35
¡ Semiconductor
ML63187/63189B
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
PIN CONFIGURATION (TOP VIEW) (ML63189B)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
(NC)
SEG3
SEG2
SEG1
SEG0
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
P0.3
P0.2
P0.1
P0.0
P9.3
P9.2
P9.1
P9.0
PA.3
PA.2
PA.1
PA.0
PB.3
PB.2
PB.1
PB.0
PE.3
PE.2
PE.1
PE.0
VDDI
(NC)
MDB
MD
(NC)
COM11
COM12
COM13
COM14
COM15
COM16
VSS
VDD1
VDD2
VDD3
VDD4
VDD5
C1
C2
VDDH
CB1
CB2
VDD
VDDL
OSC1
OSC0
RESET
XT1
XT0
TST1
TST2
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
(NC)
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
COM9
COM10
(NC)
128-Pin Plastic QFP
Note: Pins marked as (NC) are no-connection pins which are left open.
9/35
¡ Semiconductor
ML63187/63189B
PAD CONFIGURATION (ML63189B)
COM9
63
30
SEG31
ML63189B
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
PE.0
PE.1
PE.2
PE.3
PB.0
PB.1
PB.2
PB.3
PA.0
PA.1
PA.2
PA.3
P9.0
P9.1
P9.2
P9.3
P0.0
P0.1
P0.2
P0.3
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
SEG0
SEG1
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1
93
SEG2
VDDI
91 MD
90 TST2
89 TST1
88 XT0
87 XT1
86 RESET
85 OSC0
84 OSC1
83 VDDL
82 VDD
81 CB2
80 CB1
79 VDDH
78 C2
77 C1
76 VDD5
75 VDD4
74 VDD3
73 VDD2
72 VDD1
71 VSS
70 COM16
69 COM15
68 COM14
67 COM13
66 COM12
65 COM11
64 COM10
92
MDB
Pad Layout
Chip size
Chip thickness
Coordinate origin
Pad hole size
Pad size
Minimum pad pitch
:
:
:
:
:
:
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
Y
X
4.81 mm ¥ 5.20 mm
350 mm (280 mm: available as required)
center of chip
100 mm ¥ 100 mm
110 mm ¥ 110 mm
140 mm
Note: The chip substrate voltage is VSS.
10/35
¡ Semiconductor
ML63187/63189B
Pad Coordinates (ML63189B)
Pad
Pad
Pad
Pad No. Name X (µm) Y (µm) Pad No. Name X (µm) Y (µm) Pad No. Name X (µm) Y (µm)
1
SEG2
–2259
–2438
42
SEG43
2259
–632
83
VDDL
–772
2438
2
SEG3
–1895
–2438
43
SEG44
2259
–491
84
OSC1
–913
2438
3
SEG4
–1755
–2438
44
SEG45
2259
–351
85
OSC0
–1053
2438
4
SEG5
–1615
–2438
45
SEG46
2259
–211
86
RESET
–1193
2438
5
SEG6
–1474
–2438
46
SEG47
2259
–70
87
XT1
–1334
2438
6
SEG7
–1334
–2438
47
SEG48
2259
70
88
XT0
–1474
2438
7
SEG8
–1193
–2438
48
SEG49
2259
211
89
TST1
–1615
2438
8
SEG9
–1053
–2438
49
SEG50
2259
351
90
TST2
–1775
2438
9
SEG10
–913
–2438
50
SEG51
2259
491
91
MD
–1895
2438
10
SEG11
–772
–2438
51
SEG52
2259
632
92
MDB
–2259
2438
11
SEG12
–632
–2438
52
SEG53
2259
772
93
VDDI
–2259
2132
12
SEG13
–491
–2438
53
SEG54
2259
913
94
PE.0
–2259
1895
13
SEG14
–351
–2438
54
SEG55
2259
1053
95
PE.1
–2259
1755
14
SEG15
–211
–2438
55
SEG56
2259
1193
96
PE.2
–2259
1615
15
SEG16
–70
–2438
56
SEG57
2259
1334
97
PE.3
–2259
1474
16
SEG17
70
–2438
57
SEG58
2259
1474
98
PB.0
–2259
1334
17
SEG18
211
–2438
58
SEG59
2259
1615
99
PB.1
–2259
1193
18
SEG19
351
–2438
59
SEG60
2259
1755
100
PB.2
–2259
1053
19
SEG20
491
–2438
60
SEG61
2259
1895
101
PB.3
–2259
913
20
SEG21
632
–2438
61
SEG62
2259
2036
102
PA.0
–2259
772
21
SEG22
772
–2438
62
SEG63
2259
2176
103
PA.1
–2259
632
22
SEG23
913
–2438
63
COM9
2259
2438
104
PA.2
–2259
491
23
SEG24
1053
–2438
64
COM10
1895
2438
105
PA.3
–2259
351
24
SEG25
1193
–2438
65
COM11
1755
2438
106
P9.0
–2259
211
25
SEG26
1334
–2438
66
COM12
1615
2438
107
P9.1
–2259
70
26
SEG27
1474
–2438
67
COM13
1474
2438
108
P9.2
–2259
–70
27
SEG28
1615
–2438
68
COM14
1334
2438
109
P9.3
–2259
–211
28
SEG29
1755
–2438
69
COM15
1193
2438
110
P0.0
–2259
–351
29
SEG30
1895
–2438
70
COM16
1053
2438
111
P0.1
–2259
–491
30
SEG31
2259
–2438
71
VSS
913
2438
112
P0.2
–2259
–632
31
SEG32
2259
–2176
72
VDD1
772
2438
113
P0.3
–2259
–772
32
SEG33
2259
–2036
73
VDD2
632
2438
114
COM1
–2259
–913
33
SEG34
2259
–1895
74
VDD3
491
2438
115
COM2
–2259
–1053
34
SEG35
2259
–1755
75
VDD4
351
2438
116
COM3
–2259
–1193
35
SEG36
2259
–1615
76
VDD5
211
2438
117
COM4
–2259
–1334
36
SEG37
2259
–1474
77
C1
70
2438
118
COM5
–2259
–1474
37
SEG38
2259
–1334
78
C2
–70
2438
119
COM6
–2259
–1615
38
SEG39
2259
–1193
79
VDDH
–211
2438
120
COM7
–2259
–1755
39
SEG40
2259
–1053
80
CB1
–351
2438
121
COM8
–2259
–1895
40
SEG41
2259
–913
81
CB2
–491
2438
122
SEG0
–2259
–2036
41
SEG42
2259
–772
82
VDD
–632
2438
123
SEG1
–2259
–2176
11/35
¡ Semiconductor
ML63187/63189B
PIN DESCRIPTIONS
The basic functions of each pin of the ML63187/ML63189B are described in Table 1.
A symbol with a slash (/) denotes a pin that has a secondary function.
Refer to Table 2 for secondary functions.
For type, "—" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an inputoutput pin.
Table 1 Pin Descriptions (Basic Functions)
Function Symbol
Power
Pin No.
Pad No.
ML63187 ML63189B ML63187 ML63189B
Type
Description
VDD
54
56
72
82
— Positive power supply
— Negative power supply
VSS
43
45
61
71
VDD1
44
46
62
72
VDD2
45
47
63
73
VDD3
46
48
64
74
VDD4
47
49
65
75
VDD5
48
50
66
76
C1
49
51
67
77
— Capacitor connection pins for LCD bias generation.
C2
50
52
68
78
— A capacitor (0.1 mF) should be connected between C1 and C2.
VDDI
70
69
83
93
—
Power supply pins for LCD bias (internally generated).
Capacitors (0.1 mF) should be connected between these
— pins and VSS.
Supply
Positive power supply pin for external interface
(power supply for input, and input-output ports)
Positive power supply pin for internal logic (internally
VDDL
55
57
73
83
—
generated).
A capacitor (0.1 mF) should be connected between this
pin and VSS.
Voltage multiplier pin for power supply backup
VDDH
51
53
69
79
—
(internally generated).
A capacitor (1.0 mF) should be connected between this
pin and VSS.
CB1
52
54
70
80
— Pins to connect a capacitor for voltage multiplier.
CB2
53
55
71
81
—
XT0
60
62
78
88
I
XT1
59
61
77
87
O
OSC0
57
59
75
85
I
OSC1
56
58
74
84
O
Oscillation
A capacitor (1.0 mF) should be connected between CB1
and CB2.
Low-speed clock oscillation pins.
An option for using crystal oscillation or RC oscillation
is chosen by the mask option.
If the crystal oscillation is chosen, a crystal should be
connected between XT0 and XT1, and capacitor (CG)
should be connected between XT0 and VSS.
If the RC oscillation is chosen, external oscillation
resistor (ROSL) should be connected between XT0 and
XT1.
High-speed clock oscillation pins.
A ceramic resonator and capacitors (CL0, CL1) or external
oscillation resistor (ROSH) should be connected to these pins.
12/35
¡ Semiconductor
ML63187/63189B
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
TST1
Pin No.
Pad No.
ML63187 ML63189B ML63187 ML63189B
61
63
79
89
Type
I
Description
Input pins for testing.
A pull-down resistor is internally connected to these pins.
Test
TST2
62
64
80
90
I
The user cannot use these pins.
Reset input pin.
Setting this pin to "H" level puts this device into a
Reset
RESET
58
60
76
86
I
reset state.
Then, setting this pin to "L" level starts executing an
instruction from address 0000H.
A pull-down resistor is internally connected to this pin.
Melody
MD
63
66
81
91
O
Melody output pin (non-inverted output)
MDB
64
67
82
92
O
Melody output pin (inverted output)
P0.0/INT5
86
110
P0.1/INT5
87
111
P0.2/INT5
88
—
112
I
Pull-up resistor input, pull-down resistor input, or
high-impedance input is selectable for each bit.
P0.3/INT5
89
113
Applied to the ML63189B only.
P9.0
82
106
4-bit input-output ports.
P9.1
83
107
P9.2
—
84
—
108
I/O
In input mode, pull-up resistor input, pull-down
resistor input, or high-impedance input is selectable
P9.3
85
109
for each bit.
PA.0
78
102
In output mode, P-channel open drain output,
PA.1
79
103
PA.2
Port
—
4-bit input ports.
—
80
—
81
PA.3
104
I/O
high-impedance output is selectable for each bit.
P9.0 to P9.3 and PA.0 to PA.3 are applied to the
105
ML63189B only.
PB.0/INT0/
TM0CAP/
N-channel open drain output, CMOS output, or
75
74
88
98
76
75
89
99
PB.2/INT0/T02CK
77
76
90
100
PB.3/INT0/T13CK
78
77
91
101
PE.0/SIN
71
70
84
94
PE.1/SOUT
72
71
85
95
PE.2/SCLK
73
72
86
96
PE.3/INT2
74
73
87
97
TM0OVF
PB.1/INT0/
TM1CAP/
I/O
TM1OVF
I/O
13/35
¡ Semiconductor
ML63187/63189B
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
LCD
Symbol
Pin No.
Pad No.
ML63187 ML63189B ML63187 ML63189B
COM1
79
90
92
114
COM2
80
91
93
115
COM3
81
92
94
116
COM4
82
93
95
117
COM5
83
94
96
118
COM6
84
95
97
119
COM7
85
96
98
120
COM8
86
97
99
121
COM9
31
36
53
63
COM10
32
37
54
64
COM11
33
39
55
65
COM12
34
40
56
66
COM13
39
41
57
67
COM14
40
42
58
68
COM15
41
43
59
69
COM16
42
44
60
70
SEG0
87
98
100
122
SEG1
88
99
101
123
SEG2
89
100
102
1
SEG3
90
101
103
2
SEG4
91
103
104
3
SEG5
92
104
105
4
SEG6
93
105
106
5
SEG7
94
106
107
6
SEG8
95
107
108
7
SEG9
96
108
109
8
SEG10
97
109
110
9
SEG11
98
110
111
10
SEG12
103
111
1
11
SEG13
104
112
2
12
SEG14
105
113
3
13
SEG15
106
114
4
14
SEG16
107
115
5
15
SEG17
108
116
6
16
SEG18
109
117
7
17
SEG19
110
118
8
18
SEG20
111
119
9
19
20
SEG21
112
120
10
SEG22
113
121
11
21
SEG23
114
122
12
22
SEG24
115
123
13
23
Type
Description
LCD common signal output pins
O
LCD segment signal output pins
O
14/35
¡ Semiconductor
ML63187/63189B
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
LCD
Symbol
Pin No.
Pad No.
ML63187 ML63189B ML63187 ML63189B
SEG25
116
124
14
24
SEG26
117
125
15
25
SEG27
118
126
16
26
SEG28
119
127
17
27
SEG29
120
128
18
28
SEG30
121
2
19
29
SEG31
122
3
20
30
SEG32
123
4
21
31
SEG33
124
5
22
32
SEG34
125
6
23
33
SEG35
126
7
24
34
SEG36
127
8
25
35
SEG37
128
9
26
36
SEG38
5
10
27
37
SEG39
6
11
28
38
SEG40
7
12
29
39
SEG41
8
13
30
40
SEG42
9
14
31
41
SEG43
10
15
32
42
SEG44
11
16
33
43
SEG45
12
17
34
44
SEG46
13
18
35
45
SEG47
14
19
36
46
SEG48
15
20
37
47
SEG49
16
21
38
48
SEG50
17
22
39
49
SEG51
18
23
40
50
SEG52
19
24
41
51
SEG53
20
25
42
52
SEG54
21
26
43
53
SEG55
22
27
44
54
SEG56
23
28
45
55
SEG57
24
29
46
56
SEG58
25
30
47
57
SEG59
26
31
48
58
SEG60
27
32
49
59
SEG61
28
33
50
60
SEG62
29
34
51
61
SEG63
30
35
52
62
Type
Description
LCD segment signal output pins
O
15/35
¡ Semiconductor
ML63187/63189B
Table 2 shows the secondary functions of each pin of the ML63187/ML63189B.
Table 2 Pin Descriptions (Secondary Functions)
Function Symbol
External
Interrupt
Pin No.
Pad No.
ML63187 ML63189B ML63187 ML63189B
PB.0/INT0
75
74
88
98
PB.1/INT0
76
75
89
99
PB.2/INT0
77
76
90
100
PB.3/INT0
78
77
91
101
PE.3/INT2
74
73
87
97
Type
I
I
Description
External 0 interrupt input pins.
The change of input signal level causes an interrupt to
occur.
The Port B Interrupt Enable register (PBIE) enables or
disables an interrupt for each bit.
External 2 interrupt input pin.
The change of input signal level causes an interrupt to
occur.
P0.0/INT5
86
110
P0.1/INT5
87
111
P0.2/INT5
P0.3/INT5
—
88
89
—
112
113
I
External 5 interrupt input pins.
The change of input signal level causes an interrupt to
occur.
The Port 0 Interrupt Enable register (P0IE) enable or
disable an interrupt for each bit.
Applied to the ML63189B only.
16/35
¡ Semiconductor
ML63187/63189B
Table 2 Pin Descriptions (Secondary Functions) (continued)
Function Symbol
Capture
Timer
Pin No.
Pad No.
ML63187 ML63189B ML63187 ML63189B
PB.0/TM0CAP
75
74
88
98
PB.1/TM1CAP
76
75
89
PB.0/TM0OVF
75
74
88
PB.1/TM1OVF
76
75
PB.2/T02CK
77
76
PB.3/T13CK
78
PE.0/SIN
71
PE.1/SOUT
72
Description
I
Timer 0 capture input pin.
99
I
Timer 1 capture input pin.
98
O
Timer 0 overflow flag output pin.
89
99
O
Timer 1 overflow flag output pin.
90
100
I
External clock input pin for timer 0 and timer 2.
77
91
101
I
External clock input pin for timer 1 and timer 3.
70
84
94
I
Shift register receive data input pin.
71
85
95
O
Shift register transmit data output pin.
Shift register clock input-output pin.
Shift
Register
Type
Clock output when this device is used as a master
PE.2/SCLK
73
72
86
96
I/O processor.
Clock input when this device is used as a slave
processor.
17/35
¡ Semiconductor
ML63187/63189B
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V)
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage 1
VDD1
Ta = 25°C
–0.3 to +1.6
V
Power Supply Voltage 2
VDD2
Ta = 25°C
–0.3 to +2.9
V
Power Supply Voltage 3
VDD3
Ta = 25°C
–0.3 to +4.2
V
Power Supply Voltage 4
VDD4
Ta = 25°C
–0.3 to +5.5
V
Power Supply Voltage 5
VDD5
Ta = 25°C
–0.3 to +6.8
V
Power Supply Voltage 6
VDD
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 7
VDDI
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 8
VDDH
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 9
VDDL
Ta = 25°C
–0.3 to +6.0
V
Input Voltage 1
VIN1
VDD Input, Ta = 25°C
–0.3 to VDD + 0.3
V
Input Voltage 2
VIN2
VDDI Input, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 1
VOUT1
VDD1 Output, Ta = 25°C
–0.3 to VDD1 + 0.3
V
Output Voltage 2
VOUT2
VDD2 Output, Ta = 25°C
–0.3 to VDD2 + 0.3
V
Output Voltage 3
VOUT3
VDD3 Output, Ta = 25°C
–0.3 to VDD3 + 0.3
V
Output Voltage 4
VOUT4
VDD4 Output, Ta = 25°C
–0.3 to VDD4 + 0.3
V
Output Voltage 5
VOUT5
VDD5 Output, Ta = 25°C
–0.3 to VDD5 + 0.3
V
Output Voltage 6
VOUT6
VDD Output, Ta = 25°C
–0.3 to VDD + 0.3
V
Output Voltage 7
VOUT7
VDDI Output, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 8
VOUT8
VDDH Output, Ta = 25°C
–0.3 to VDDH + 0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
18/35
¡ Semiconductor
ML63187/63189B
RECOMMENDED OPERATING CONDITIONS
• When backup is used
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Crystal Oscillation Frequency
Low-speed RC Oscillation
Frequency
Ceramic Oscillation Frequency
Symbol
Condition
Range
Unit
Top
—
–20 to +70
°C
VDD
—
0.9 to 2.7
V
VDDI
—
0.9 to 5.5
V
fXT
CG = 5 to 25 pF
32.768 to 76.8
kHz
fROSL
fCM
ROSL = 1.5 MW
32 ±30%
ROSL = 700 kW
60 ±30%
ROSL = 500 kW
80 ±30%
VDD = 0.9 to 1.2 V
Not applied
VDD = 1.2 to 2.7 V
300k to 500k
VDD = 1.5 to 2.7 V
200k to 1M
VDD = 0.9 to 1.2 V
High-speed RC Oscillation
Frequency
fROSH
VDD = 1.2 to 2.7 V
kHz
Hz
Not applied
ROSH = 400 kW
200k ±30%
ROSH = 100 kW
700k ±30%
ROSH = 75 kW
1M ±30%
Hz
• When backup is not used
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Crystal Oscillation Frequency
Low-speed RC Oscillation
Frequency
Ceramic Oscillation Frequency
High-speed RC Oscillation
Frequency
Symbol
Condition
Range
Unit
Top
—
–20 to +70
°C
VDD
—
1.8 to 5.5
V
VDDI
—
1.8 to 5.5
V
fXT
CG = 5 to 25 pF
32.768 to 76.8
kHz
ROSL = 1.5 MW
32 ±30%
fROSL
ROSL = 700 kW
60 ±30%
ROSL = 500 kW
80 ±30%
fCM
VDD = 1.8 to 5.5 V
200k to 2M
fROSH
VDD = 1.8 to 5.5 V
ROSH = 100 kW
700k ±30%
ROSH = 75 kW
1M ±30%
ROSH = 51 kW
1.35M ±30%
VDD = 1.8 to 3.5 V, ROSH = 30 kW
kHz
Hz
Hz
2M ±30%
19/35
¡ Semiconductor
ML63187/63189B
• Typical characteristics of low-speed RC oscillation
When backup is used/backup is not used (VDD = VDDI = 1.5 V/VDD = VDDI = 3.0 V)
fROSL [kHz]
1000
100
10
100
1000
10000
ROSL [kW]
• Typical characteristics of high-speed RC oscillation
When backup is used (VDD = VDDI = 1.5 V)
fROSH [kHz]
10000
1000
100
10
100
1000
ROSH [kW]
20/35
¡ Semiconductor
ML63187/63189B
• Typical characteristics of high-speed RC oscillation
When backup is not used (VDD = VDDI = 3.0 V)
fROSH [kHz]
10000
1000
100
10
100
1000
ROSH [kW]
21/35
¡ Semiconductor
ML63187/63189B
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
VDD2 Voltage
(VDD = VDDI = 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
MeaSymbol
Condition
Min.
Typ.
Max. Unit suring
Circuit
1/5 bias, 1/4 bias
VDD2
1.7
1.8
1.9
V
(Ta = 25°C)
DVDD2
—
VDD1 Voltage
VDD1
1/5 bias, 1/4 bias
Typ.– 0.1 1/2 ¥ VDD2 Typ.+ 0.1
1/5 bias
Typ.– 0.3 3/2 ¥ VDD2 Typ.+ 0.3
VDD3 Voltage
VDD3
1/4 bias (connect
VDD2 Voltage Temperature Deviation
VDD3 and VDD2)
VDD4 Voltage
VDD4
VDD5 Voltage
VDD5
VDDH Voltage
(Backup used)
VDDL Voltage
VDDH
VDDL
Crystal Oscillation Start Voltage
VSTA
Crystal Oscillation Hold Voltage
VHOLD
Crystal Oscillation Stop Detect Time
—
Typ.– 0.2
–4
VDD2
—
Typ.+ 0.2
1/5 bias
Typ.– 0.4 2 ¥ VDD2 Typ.+ 0.4
1/4 bias
Typ.– 0.3 3/2 ¥ VDD2 Typ.+ 0.3
1/5 bias
Typ.– 0.5 5/2 ¥ VDD2 Typ.+ 0.5
1/4 bias
Typ.– 0.4 2 ¥ VDD2 Typ.+ 0.4
High-speed clock oscillation
stopped
VDD = 1.5 V
High-speed clock oscillation
(Ceramic oscillation, 1 MHz)
VDD = 1.5 V
High-speed clock
oscillation stopped
mV/°C
V
V
V
V
2.8
—
3.0
V
2.0
—
2.7
V
1
1.0
1.5
2.0
V
High-speed clock oscillation
(VDD = 1.2 to 5.5 V)
1.2
—
5.5
V
Oscillation start time:
within 5 seconds
1.2
—
—
V
Backup
0.9
—
—
V
Backup not used
1.7
—
—
V
TSTOP
—
0.1
—
5.0
ms
External Crystal Oscillator Capacitance
CG
—
5
—
25
pF
Internal Crystal Oscillator Capacitance
CD
—
20
25
30
pF
—
30
—
pF
External Ceramic Oscillator
Capacitance
Internal RC Oscillator Capacitance
POR Voltage
Non-POR Voltage
BLD Judgment Voltage
BLD Judgment Voltage
Temperature Deviation
CL0, 1
COS
VPOR1
VPOR2
VBLDC
DVBLDC
CSA2.00MG (Murata
MFG.-make) used
VDD = 3.0 V
—
8
12
16
pF
VDD = 1.5 V
0.0
—
0.4
V
VDD = 3.0 V
0.0
—
0.7
V
VDD = 1.5 V
1.2
—
1.5
V
VDD = 3.0 V
2.0
—
3.0
V
LD1 = 1, LD0 = 1, Ta = 25°C
2.30
2.40
2.50
LD1 = 1, LD0 = 0, Ta = 25°C
1.70
1.80
1.90
LD1 = 0, LD0 = 1, Ta = 25°C
1.10
1.20
1.30
LD1 = 0, LD0 = 0, Ta = 25°C
0.95
1.05
1.15
VBLDC = 2.40 V (LD1 = 1, LD0 = 1)
—
–3.5
—
VBLDC = 1.80 V (LD1 = 1, LD0 = 0)
—
–2.3
—
VBLDC = 1.20 V (LD1 = 0, LD0 = 1)
—
–1.6
—
VBLDC = 1.05 V (LD1 = 0, LD0 = 0)
—
–1.2
—
V
—
mV/°C
22/35
¡ Semiconductor
ML63187/63189B
Notes: 1. "TSTOP" indicates that if the crystal oscillator stops over the value of TSTOP, the system
reset occurs.
2. "POR" denotes Power On Reset.
3. "VPOR1" indicates that POR occurs when VDD falls from VDD to VPOR1 and again rises
up to VDD.
4. "VPOR2" indicates that POR does not occur when VDD falls from VDD to VPOR2 and
again rises up to VDD.
23/35
¡ Semiconductor
ML63187/63189B
DC Characteristics (continued)
• When backup is used
(VDD = VDDI = 1.5 V, VSS = 0 V, 1/5 bias, Ta = –20 to +70°C unless otherwise specified)
MeaParameter Symbol
Condition
Min. Typ. Max. Unit suring
Circuit
CPU is in HALT state.
5
6.5
Ta = –20 to +50°C —
mA
Supply Current 1 IDD1 (High-speed clock oscillation
Ta = –20 to +70°C —
5
10
stopped)
Supply Current 2
Supply Current 3
IDD2
IDD3
CPU is in HALT state.
Ta = –20 to +50°C
LCD is in Power Down mode.
(High-speed clock oscillation
Ta = –20 to +70°C
stopped)
—
4
5
—
4
8
CPU is in operation at
Ta = –20 to +50°C
low-speed oscillation.
(High-speed clock oscillation
Ta = –20 to +70°C
stopped)
—
16
18
mA
—
16
20
mA
mA
Supply Current 4
IDD4
CPU is in operation at high-speed oscillation
(RC oscillation, ROSH = 100 kW)
—
800
1000
mA
Supply Current 5
IDD5
CPU is in operation at high-speed oscillation
(Ceramic oscillation, 1 MHz)
—
700
850
mA
1
• When backup is not used
(VDD = VDDI = 3.0 V, VSS = 0 V, 1/5 bias, Ta = –20 to +70°C unless otherwise specified)
MeaParameter Symbol
Condition
Min. Typ. Max. Unit suring
Circuit
CPU is in HALT state.
2.2
3
Ta = –20 to +50°C —
mA
Supply Current 1 IDD1 (High-speed clock oscillation
Ta = –20 to +70°C —
2.2
5
stopped)
CPU is in HALT state.
Ta = –20 to +50°C
LCD is in Power Down mode.
(High-speed clock oscillation
Ta = –20 to +70°C
stopped)
—
1.8
2.5
—
1.8
4
—
7.5
9
IDD3
CPU is in operation at
Ta = –20 to +50°C
low-speed oscillation.
(High-speed clock oscillation
Ta = –20 to +70°C
stopped)
Supply Current 4
IDD4
Supply Current 5
IDD5
Supply Current 2
Supply Current 3
IDD2
mA
1
mA
—
7.5
12
CPU is in operation at high-speed oscillation
(RC oscillation, ROSH = 100 kW)
—
550
700
mA
CPU is in operation at high-speed oscillation
(Ceramic oscillation, 2 MHz)
—
850
1000
mA
24/35
¡ Semiconductor
ML63187/63189B
DC Characteristics (continued)
Parameter
Output Current 1
(P9.0 to P9.3)*
(PA.0 to PA.3)*
(PB.0 to PB.3)
(PE.0 to PE.3)
(VDD = VDDI = VDDH = 3.0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V, VDD4 = 4.4 V,
VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
MeaSymbol
Condition
Min. Typ. Max. Unit suring
Circuit
IOH1
IOL1
VDDI = 1.5 V
–2.5
–1.4
–0.4
mA
VOH1 = VDDI – 0.5 V VDDI = 3.0 V
–6.0
–3.5
–1.0
mA
VDDI = 5.0 V
–8.5
–5.0
–1.5
mA
VDDI = 1.5 V
0.4
1.4
2.5
mA
VDDI = 3.0 V
1.0
3.0
6.0
mA
VOL1 = 0.5 V
Output Current 2
(MD, MDB)
IOH2
IOL2
Output Current 3
(SEG0 to SEG63)
(COM1 to COM16)
(OSC1)
3.7
8.5
mA
–2.0
–0.5
mA
VDD = 3.0 V
–11.0
–6.0
–2.0
mA
VDD = VDDH = 5.0 V
–14.0
–9.0
–4.0
mA
VDD = 1.5 V
0.5
2.0
4.0
mA
VDD = 3.0 V
2.0
5.5
11.0
mA
VDD = VDDH = 5.0 V
4.0
7.0
14.0
mA
VOH3 = VDD5 – 0.2 V (VDD5 level)
—
—
–4
mA
VOHM3 = VDD4 + 0.2 V (VDD4 level)
4
—
—
mA
IOHM3S
VOHM3S = VDD4 – 0.2 V (VDD4 level)
—
—
–4
mA
IOMH3
VOMH3 = VDD3 + 0.2 V (VDD3 level)
4
—
—
mA
IOMH3S
VOMH3S = VDD3 – 0.2 V (VDD3 level)
—
—
–4
mA
IOML3
VOML3 = VDD2 + 0.2 V (VDD2 level)
4
—
—
mA
IOML3S
VOML3S = VDD2 – 0.2 V (VDD2 level)
—
—
–4
mA
IOLM3
VOLM3 = VDD1 + 0.2 V (VDD1 level)
4
—
—
mA
IOLM3S
VOLM3S = VDD1 – 0.2 V (VDD1 level)
—
—
–4
mA
IOH3
IOH4R
IOL4R
IOH4C
IOL4C
Output Leakage Current
(P9.0 to P9.3)*
(PA.0 to PA.3)*
(PB.0 to PB.3)
(PE.0 to PE.3)
VOL2 = 0.7 V
1.5
–4.0
IOHM3
IOL3
Output Current 4
VOH2 = VDD – 0.7 V
VDDI = 5.0 V
VDD = 1.5 V
VOL3 = VSS + 0.2 V (VSS level)
VOH4R = VDDH – 0.5 V VDD = VDDH = 3.0 V
4
—
—
mA
–2.5
–1.3
–0.25
mA
(RC oscillation)
VDD = VDDH = 5.0 V
–3.5
–1.7
–0.5
mA
VOL4R = 0.5 V
VDD = VDDH = 3.0 V
0.25
1.5
2.5
mA
(RC oscillation)
VDD = VDDH = 5.0 V
0.5
1.8
3.5
mA
VOH4C = VDDH – 0.5 V VDD = VDDH = 3.0 V
–500
–250
–100
mA
(ceramic oscillation)
VDD = VDDH = 5.0 V
–800
–350
–200
mA
VOL4C = 0.5 V
VDD = VDDH = 3.0 V
200
500
800
mA
(ceramic oscillation)
VDD = VDDH = 5.0 V
400
700
1000
mA
IOOH
VOH = VDDI
—
—
0.3
mA
IOOL
VOL = VSS
–0.3
—
—
mA
2
*: Applied to the ML63189B only.
25/35
¡ Semiconductor
ML63187/63189B
DC Characteristics (continued)
Parameter
Input Current 1
(P0.0 to P0.3)*
(P9.0 to P9.3)*
(PA.0 to PA.3)*
(PB.0 to PB.3)
(PE.0 to PE.3)
Input Current 2
(OSC0)
(VDD = VDDI = VDDH = 3.0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V, VDD4 = 4.4 V,
VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
MeaSymbol
Condition
Min. Typ. Max. Unit suring
Circuit
IIH1
IIL1
VIH1 = VDDI
(when pulled down)
VIL1 = VSS
(when pulled up)
2
20
45
mA
VDDI = 3.0 V
30
120
260
mA
VDDI = 5.0 V
70
350
650
mA
VDDI = 1.5 V
–45
–20
–2
mA
VDDI = 3.0 V
–260
–120
–30
mA
VDDI = 5.0 V
–650
–350
–70
mA
0.0
—
1.0
mA
IIH1Z
VIH1 = VDDI (in a high impedance state)
IIL1Z
VIL1 = VSS (in a high impedance state)
IIL2
–1.0
—
0.0
mA
VIL2 = VSS
VDD = VDDH = 3.0 V
–350
–170
–30
mA
(when pulled up)
VDD = VDDH = 5.0 V
–750
–450
–200
mA
IIH2R
VIH2R = VDDH (RC oscillation)
0.0
—
1.0
mA
IIL2R
VIL2R = VSS (RC oscillation)
–1.0
—
0.0
mA
0.5
1.8
4.0
mA
3
6
10
mA
VDD = VDDH = 3.0 V
–4.0
–1.8
–0.5
mA
(ceramic oscillation) VDD = VDDH = 5.0 V
–10
–6
–3
mA
IIH2C
IIL2C
VIH2C = VDDH
VDD = VDDH = 3.0 V
(ceramic oscillation) VDD = VDDH = 5.0 V
VIL2C = VSS
Input Current 3
(RESET)
VDDI = 1.5 V
IIH3
VIH3 = VDD
IIL3
VIL3 = VSS
VDD = 1.5 V
10
180
350
mA
VDD = 3.0 V
150
1100
2400
mA
VDD = VDDH = 5.0 V
Input Current 4
(TST1, TST2)
IIH4
IIL4
VIH4 = VDD
VIL4 = VSS
0.5
2.7
5.0
mA
–1.0
—
0.0
mA
VDD = 1.5 V
50
750
1500
mA
VDD = 3.0 V
0.5
3.0
5.5
mA
VDD = VDDH = 5.0 V
2.0
6.5
11.0
mA
–1.0
—
0.0
mA
3
*: Applied to the ML63189B only.
26/35
¡ Semiconductor
ML63187/63189B
DC Characteristics (continued)
Parameter
Input Voltage 1
(P0.0 to P0.3)*
(P9.0 to P9.3)*
(PA.0 to PA.3)*
(PB.0 to PB.3)
(PE.0 to PE.3)
Input Voltage 2
(OSC0)
(VDD = VDDI = VDDH = 3.0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V, VDD4 = 4.4 V,
VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
MeaSymbol
Condition
Min. Typ. Max. Unit suring
Circuit
VIH1
VIL1
VIH2
VIL2
Input Voltage 3
(RESET, TST1, TST2)
VIH3
VIL3
Hysteresis Width 1
(P0.0 to P0.3)*
(P9.0 to P9.3)*
(PA.0 to PA.3)*
(PB.0 to PB.3)
(PE.0 to PE.3)
DVT1
Hysteresis Width 2
(RESET, TST1, TST2)
Input Pin Capacitance
(P0.0 to P0.3)*
(P9.0 to P9.3)*
(PA.0 to PA.3)*
(PB.0 to PB.3)
(PE.0 to PE.3)
DVT2
CIN
VDDI = 1.5 V
1.2
—
1.5
V
VDDI = 3.0 V
2.4
—
3.0
V
VDDI = 5.0 V
4.0
—
5.0
V
VDDI = 1.5 V
0.0
—
0.3
V
VDDI = 3.0 V
0.0
—
0.6
V
VDDI = 5.0 V
0.0
—
1.0
V
VDD = VDDH = 3.0 V
2.4
—
3.0
V
VDD = VDDH = 5.0 V
4.0
—
5.0
V
VDD = VDDH = 3.0 V
0.0
—
0.6
V
VDD = VDDH = 5.0 V
0.0
—
1.0
V
VDD = 1.5 V
1.35
—
1.5
V
VDD = 3.0 V
2.4
—
3.0
V
VDD = 5.0 V
4.0
—
5.0
V
VDD = 1.5 V
0.0
—
0.15
V
VDD = 3.0 V
0.0
—
0.6
V
VDD = 5.0 V
0.0
—
1.0
V
VDDI = 1.5 V
0.05
0.1
0.3
V
VDDI = 3.0 V
0.2
0.5
1.0
V
VDDI = 5.0 V
0.25
1.0
1.5
V
VDD = 1.5 V
0.05
0.1
0.3
V
VDD = 3.0 V
0.2
0.5
1.0
V
VDD = 5.0 V
0.25
1.0
1.5
V
—
—
—
5
pF
4
1
*: Applied to the ML63189B only.
27/35
¡ Semiconductor
ML63187/63189B
Measuring circuit 1
CB1
CG
Cb12
XT0
CB2
C1
32.768 kHz
Crystal
XT1
C12
C2
q
*1
w
OSC0
OSC1
VSS VDD VDDI VDD1
A
Ca
V
Ca, Cb, Cc, Cd, Ce, Cl, C12
Cb12, Ch
CG
CL0
CL1
Ceramic Resonator
VDD2
VDD3
VDD4
VDD5
VDDH VDDL
Cb
Cc
Cd
Ce
Ch
V
: 0.1 mF
: 1 mF
: 15 pF
: 30 pF
: 30 pF
: CSA2.00MG (2 MHz)
CSB1000J (1 MHz)
(Murata MFG.-make)
V
V
V
Cl
V
V
*1 RC Oscillator
q
ROSH
w
Ceramic Oscillator
q
CL0
Ceramic Resonator
w
CL1
Measuring circuit 2
*3
VIH
A
*2
INPUT
VIL
VSS
OUTPUT
VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
*2 Input logic circuit to determine the specified measuring conditions.
*3 Measured at the specified output pins.
28/35
¡ Semiconductor
ML63187/63189B
Measuring circuit 3
*4
A
INPUT
OUTPUT
VSS VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
Measuring circuit 4
VIH
Waveform
Monitoring
*4
INPUT
VIL
VSS
OUTPUT
VDD
VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
*4 Measured at the specified input pins.
29/35
¡ Semiconductor
ML63187/63189B
AC Characteristics (Serial Interface, Shift Register)
(VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless otherwise
specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
SCLK Input Fall Time
tf
—
—
—
1.0
ms
SCLK Input Rise Time
tr
—
—
—
1.0
ms
SCLK Input "L" Level
Pulse Width
tCWL
—
0.8
—
—
ms
SCLK Input "H" Level
Pulse Width
tCWH
—
0.8
—
—
ms
tCYC
VDDI = 5 V to VDD
1.8
—
—
ms
—
30.5
—
ms
—
0.5
—
ms
Parameter
SCLK Input Cycle Time
tCYC1(O) CPU in operation state at 32.768 kHz
SCLK Output Cycle Time
CPU in operation at 2 MHz
tCYC2(O)
VDD = VDDH = 1.8 V to 3.5 V
SOUT Output Delay Time
tDDR
Cl = 10 pF
—
—
0.4
ms
SIN Input Setup Time
tDS
—
0.5
—
—
ms
SIN Input Hold Time
tDH
—
0.8
—
—
ms
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
tCYC
SCLK (PE.2)
5 V (VDDI)
tr
0 V (VSS)
tf
tCWH
tCWL
tDDR
tDDR
5 V (VDDI)
SOUT (PE.1)
0 V (VSS)
tDS
SIN (PE.0)
tDH
tDS
5 V (VDDI)
0 V (VSS)
30/35
¡ Semiconductor
ML63187/63189B
APPLICATION CIRCUITS (ML63187)
•Crystal oscillation is selected as low-speed
oscillation.
•RC oscillation is selected as high-speed
oscillation.
•Ports are powered from external memory
power source.
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cl, Cb12, C12,
Ch, and CG, are for reference only.
LCD
Crystal
32.768 kHz
CG
COM1-16
SEG0-63
XT0
OSC0
ROSH
5 to
25 pF
Ch
1.0 mF
1.5 V
XT1
VDDH
OSC1
PE.3
PE.2
PE.1
PE.0
VDD
Cv 0.1 mF
Cb12
1.0 mF
Cl
0.1 mF
Ce
0.1 mF
Cd
0.1 mF
Cc
0.1 mF
Cb
0.1 mF
Ca
0.1 mF
C12
PB.3
PB.2
PB.1
PB.0
CB2
VDDL
VDD5
VDD4
VDD3
ML63187
VDD2
VDD1
C1
0.1 mF
Push SW
Buzzer
CB1
C2
RESET
TST1
TST2
MD
VDDI
VDD
MDB
VSS
Note: VDDI is the power supply pin for the input-output ports.
Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this
device or to the positive power supply pin of the external memory.
Application Circuit Example with Power Supply Backup
31/35
¡ Semiconductor
ML63187/63189B
APPLICATION CIRCUITS (ML63187)
•Crystal oscillation is selected as low-speed
oscillation.
•Ceramic oscillation is selected as high-speed
oscillation.
•Ports, external memory, and IC share their
power supply.
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cl, C12, CG,
CL0, and CL1 are for reference only.
LCD
Crystal
32.768 kHz
CG
5 to 25 pF
VDD
COM1-16
OSC0
XT1
VDDH
OSC1
PE.3
PE.2
PE.1
PE.0
5.0 V
VDD
Cv 0.1 mF Open
Cl
0.1 mF
Ce
0.1 mF
Cd
0.1 mF
Cc
0.1 mF
Cb
0.1 mF
Ca
0.1 mF
CL0 30 pF
SEG0-63
XT0
CB1
CB2
VDDL
Ceramic
Resonator
(Example: 1 MHz)
CL1
30 pF
PB.3
PB.2
PB.1
PB.0
VDD5
VDD4
VDD3
VDD2
ML63187
VDD1
C1
C12
0.1 mF
Push SW
Buzzer
C2
RESET
TST1
TST2
MD
VDDI
VDD
MDB
VSS
Note: VDDI is the power supply pin for the input-output ports.
Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this
device or to the positive power supply pin of the external memory.
Application Circuit Example with No Power Supply Backup
32/35
¡ Semiconductor
ML63187/63189B
APPLICATION CIRCUITS (ML63189B)
•Crystal oscillation is selected as low-speed
oscillation.
•RC oscillation is selected as high-speed
oscillation.
•Ports are powered from external memory
power source.
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cl, Cb12, C12,
Ch, and CG, are for reference only.
LCD
Crystal
32.768 kHz
CG
COM1-16
SEG0-63
XT0
OSC0
ROSH
5 to
25 pF
Ch
1.0 mF
1.5 V
XT1
VDDH
OSC1
PE.3
PE.2
PE.1
PE.0
VDD
Cv 0.1 mF
Cb12
1.0 mF
Cl
0.1 mF
Ce
0.1 mF
Cd
0.1 mF
Cc
0.1 mF
Cb
0.1 mF
Ca
0.1 mF
C12
PB.3
PB.2
PB.1
PB.0
CB2
VDDL
VDD5
VDD4
VDD3
VDD2
VDD1
C1
0.1 mF
Push SW
Buzzer
CB1
C2
RESET
TST1
TST2
MD
ML63189B
PA.3
PA.2
PA.1
PA.0
P9.3
P9.2
P9.1
P9.0
P0.3
P0.2
P0.1
P0.0
VDDI
VDD
MDB
VSS
Note: VDDI is the power supply pin for the input and input-output ports.
Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this
device or to the positive power supply pin of the external memory.
Application Circuit Example with Power Supply Backup
33/35
¡ Semiconductor
ML63187/63189B
APPLICATION CIRCUITS (ML63189B)
•Crystal oscillation is selected as low-speed
oscillation.
•Ceramic oscillation is selected as high-speed
oscillation.
•Ports, external memory, and IC share their
power supply.
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cl, C12, CG,
CL0, and CL1 are for reference only.
LCD
Crystal
32.768 kHz
CG
5 to 25 pF
VDD
COM1-16
XT0
OSC0
XT1
VDDH
OSC1
PE.3
PE.2
PE.1
PE.0
5.0 V
VDD
Cv 0.1 mF Open
Cl
0.1 mF
Ce
0.1 mF
Cd
0.1 mF
Cc
0.1 mF
Cb
0.1 mF
Ca
0.1 mF
CB1
CB2
VDDL
VDD4
VDD3
VDD2
VDD1
0.1 mF
Push SW
Buzzer
C2
RESET
TST1
TST2
MD
Ceramic
Resonator
(Example: 1 MHz)
CL1
30 pF
PB.3
PB.2
PB.1
PB.0
VDD5
C1
C12
CL0 30 pF
SEG0-63
ML63189B
PA.3
PA.2
PA.1
PA.0
P9.3
P9.2
P9.1
P9.0
P0.3
P0.2
P0.1
P0.0
VDDI
VDD
MDB
VSS
Note: VDDI is the power supply pin for the input and input-output ports.
Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this
device or to the positive power supply pin of the external memory.
Application Circuit Example with No Power Supply Backup
34/35
¡ Semiconductor
ML63187/63189B
PACKAGE DIMENSIONS
(Unit : mm)
QFP128-P-1420-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.19 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
35/35
E2Y0002-29-62
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan