NXP N74F269D 8-bit bidirectional binary counter Datasheet

74F269
8-bit bidirectional binary counter
Rev. 05 — 25 March 2010
Product data sheet
1. General description
The 74F269 is a fully synchronous 8-stage up/down counter featuring a preset capability
for programmable operation, carry look-ahead for easy cascading and a U/D input to
control the direction of counting. All state changes, whether in counting or parallel loading,
are initiated by the rising edge of the clock.
2. Features and benefits
„
„
„
„
Synchronous counting and loading
Built-in look-ahead carry capability
Count frequency 115 MHz (typical)
Supply current 95 mA (typical)
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
N74F269D
0 °C to 70 °C
SO24
plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
N74F269DB
0 °C to 70 °C
SSOP24
plastic shrink small outline package; 24 leads;
body width 5.3 mm
SOT340-1
74F269
NXP Semiconductors
8-bit bidirectional binary counter
4. Functional diagram
24
CTR DIV256
M1 [LOAD]
M2 [COUNT]
1
23
D0
24
D1
21
D2
20
D3
18
D4
17
D5
16
D6
M4 [DOWN]
15
12
13
D7
11
PE
1
U/D
11
CP
12
CEP
13
22
M3 [UP]
G5
3, 5, 6 CT = 256
G6
4, 5, 8 CT = 0
2, 3, 5, 6+/C7
2, 3, 5, 6−
TC
14
23
1,7D
22
CET
21
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
20
2
14
3
4
5
6
8
9
10
18
001aai979
17
16
15
[1]
[2]
[4]
[8]
[16]
[32]
[64]
[128]
2
3
4
5
6
8
9
10
001aai980
Fig 1.
Logic symbol
74F269_5
Product data sheet
Fig 2.
IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
2 of 19
74F269
NXP Semiconductors
8-bit bidirectional binary counter
2
D0
23
DETAIL
A
22
DETAIL
A
21
DETAIL
A
20
DETAIL
A
18
DETAIL
A
17
DETAIL
A
16
DETAIL
A
15
DETAIL
A
3
D1
4
D2
5
D3
6
D4
8
D5
9
D6
10
D7
PE
CP
U/D
CEP
CET
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
24
11
1
12
13
14
TOGGLE
TC
DETAIL
A
Dn
D
Q
CP Q
PE
Fig 3.
CP
001aal296
Logic diagram
74F269_5
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
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NXP Semiconductors
74F269_5
Product data sheet
Rev. 05 — 25 March 2010
All information provided in this document is subject to legal disclaimers.
CP
U/D
PE
D0 D1 D2 D3 D4 D5 D6 D7
TC
CP
D0 D1 D2 D3 D4 D5 D6 D7
PE
U/D
U/D
CP
D0 D1 D2 D3 D4 D5 D6 D7
PE
PE
U/D
TC
CP
D0 D1 D2 D3 D4 D5 D6 D7
PE
U/D
TC
CP
TC
CEP
CEP
CEP
CEP
CET
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
CET
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
CET
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
CET
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
least significant 8-bit counter
most significant 8-bit counter
001aal295
74F269
Synchronous multistage counting scheme
8-bit bidirectional binary counter
4 of 19
© NXP B.V. 2010. All rights reserved.
Fig 4.
74F269
NXP Semiconductors
8-bit bidirectional binary counter
5. Pinning information
5.1 Pinning
74F269
U/D
1
24 PE
Q0
2
23 D0
Q1
3
22 D1
Q2
4
21 D2
Q3
5
20 D3
Q4
6
19 VCC
GND
7
18 D4
Q5
8
17 D5
Q6
9
16 D6
Q7 10
15 D7
CP 11
14 TC
13 CET
CEP 12
001aai981
Fig 5.
Pin configuration SO24 and SSOP24 package
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
Unit load
HIGH/LOW
Load value[1]
HIGH/LOW
U/D
1
up or down count control input
1.0/1.0
20 μA/0.6 mA
Q0 to Q7 2, 3, 4, 5, 6, 8, 9, 10
data output
50/33
1.0 mA/20 mA
GND
7
ground (0 V)
-
-
CP
11
clock input
1.0/1.0
20 μA/0.6 mA
CEP
12
count enable parallel input (active LOW)
1.0/1.0
20 μA/0.6 mA
CET
13
count enable trickle input (active LOW)
1.0/1.0
20 μA/0.6 mA
TC
14
terminal count output (active LOW)
50/33
1.0 mA/20 mA
D0 to D7
23, 22, 21, 20, 18, 17, 16, 15
data input
1.0/1.0
20 μA/0.6 mA
VCC
19
supply voltage
-
-
PE
24
parallel enable input (active LOW)
1.0/1.0
20 μA/0.6 mA
[1]
One FAST Unit Load (UL) is defined as 20 μA in HIGH state, 0.6 μA in LOW state.
74F269_5
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
5 of 19
74F269
NXP Semiconductors
8-bit bidirectional binary counter
6. Functional description
6.1 Function table
Table 3.
Function table[1]
Operating modes
Input
Output
CP
U/D
CEP
CET
PE
↑
X
X
X
I
I
L
*
↑
X
X
X
l
h
H
*
Count up (increment)
↑
h
I
I
h
X
count up
*
Count down (decrement)
↑
I
I
I
h
X
count down
*
Hold (do nothing)
↑
X
h
I
h
X
qn
*
↑
X
X
h
h
X
qn
H
Parallel load (Dn to Qn)
[1]
Dn
Qn
TC
H = HIGH voltage level steady state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level steady state
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
qn = Lower case letters indicate state of referenced output prior to the LOW-to-HIGH clock transition
X = don’t care
↑ = LOW-to-HIGH clock transition
* = The TC is LOW when CET is LOW and the counter is at terminal count
Terminal count up is with all Qn outputs HIGH and terminal count down is with all Qn outputs LOW.
74F269_5
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
6 of 19
74F269
NXP Semiconductors
8-bit bidirectional binary counter
PE
D0
D1
D2
D3
D4
D5
D6
D7
CP
U/D
CEP and CET
Q0
Q1
Q2
Q3
Q4
Q5
Q7
Q7
TC
SEQUENCE
253
LOAD
Fig 6.
254
255
0
COUNT UP
1
2
2
1
INHIBIT
0
255
254
COUNT DOWN
253
001aal297
Typical timing sequence
74F269_5
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
7 of 19
74F269
NXP Semiconductors
8-bit bidirectional binary counter
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC
supply voltage
Conditions
VI
input voltage
VO
output voltage
output in HIGH-state
IIK
input clamping current
VI < 0 V
IO
output current
output in LOW-state
Tamb
ambient temperature
Tstg
storage temperature
Max
Unit
−0.5
+7.0
V
[1]
−0.5
+7.0
V
[1]
−0.5
+5.5
V
−30
+5
mA
-
40
mA
[2]
in free air
Min
0
70
°C
−65
+150
°C
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VCC
Min
Typ
Max
Unit
supply voltage
4.5
5.0
5.5
V
VIH
HIGH-level input voltage
2.0
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
IIK
input clamping current
-
-
−18
mA
IOH
HIGH-level output current
−1
-
-
mA
IOL
LOW-level output current
-
-
20
mA
74F269_5
Product data sheet
Conditions
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Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
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74F269
NXP Semiconductors
8-bit bidirectional binary counter
9. Static characteristics
Table 6.
Static characteristics
Symbol Parameter
25 °C
Conditions
Min
Max
Min
Max
−1.2
−0.73
-
−1.2
-
V
VCC = ±10 %; IOH = −1 mA
-
-
-
2.5
-
V
VCC = ±5 %; IOH = −1 mA
-
3.4
-
2.7
-
V
VCC = ±10 %
-
0.30
-
-
0.50
V
VCC = ±5 %
-
0.30
-
-
0.50
V
100
μA
VIK
input clamping voltage
VCC = 4.5 V; IIK = −18 mA
VOH
HIGH-level output
voltage
VCC = 4.5 V; VI = VIL or VIH
LOW-level output
voltage
VOL
−40 °C to +85 °C Unit
Typ[1]
VCC = 4.5 V; IOL = 20 mA;
VI = VIL or VIH
II
input leakage current
VCC = 5.5 V; VI = 7.0 V
-
-
-
-
IIH
HIGH-level input current VCC = 5.5 V; VI = 2.7 V
-
-
-
-
20
μA
IIL
LOW-level input current
-
-
-
-
−0.6
mA
-
-
-
−60
−150
mA
Dn: VI = 4.5 V
-
93
-
-
120
mA
Dn: VI = GND
-
98
-
-
125
mA
VCC = 5.5 V; VI = 0.5 V
[2]
IO
output current
VCC = 5.5 V
ICC
supply current
PE = CET = CEP = U/D = GND;
VCC = 5.5 V; CP = rising edge
[1]
All typical values are measured at VCC = 5 V.
[2]
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit, see Figure 13.
Symbol Parameter
25 °C; VCC = 5.0 V
Conditions
Min
tPLH
tPHL
Typ
Max
0 °C to 70 °C;
Unit
VCC = 5.0 V ± 0.5 V
Min
Max
LOW to HIGH
CP to Qn; load; PE = LOW; see Figure 7
propagation delay CP to Qn; count; PE = HIGH; see Figure 7
3.0
6.0
8.5
3.0
9.0
ns
3.0
6.0
9.0
3.0
10.0
ns
CP to TC; see Figure 7
4.5
6.5
9.5
4.0
10.5
ns
CET to TC; see Figure 8
3.5
6.0
9.0
3.0
10.0
ns
U/D to TC; see Figure 9
4.5
7.0
9.0
4.0
10.0
ns
HIGH to LOW
CP to Qn; load; PE = LOW; see Figure 7
propagation delay CP to Qn; count; PE = HIGH; see Figure 7
4.0
6.5
8.5
4.0
9.0
ns
4.5
7.0
10.0
4.0
10.5
ns
CP to TC; see Figure 7
5.0
6.5
9.5
5.0
10.0
ns
CET to TC; see Figure 8
3.0
6.5
9.0
3.0
10.0
ns
U/D to TC; see Figure 9
4.5
7.0
9.5
4.0
10.0
ns
74F269_5
Product data sheet
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Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
9 of 19
74F269
NXP Semiconductors
8-bit bidirectional binary counter
Table 7.
Dynamic characteristics …continued
GND = 0 V; for test circuit, see Figure 13.
Symbol Parameter
tsu(H)
tsu(L)
th(H)
th(L)
set-up time HIGH
set-up time LOW
hold time HIGH
hold time LOW
25 °C; VCC = 5.0 V
Conditions
0 °C to 70 °C;
Unit
VCC = 5.0 V ± 0.5 V
Min
Typ
Max
Min
Max
Dn to CP; see Figure 10
3.5
-
-
2.5
-
ns
PE to CP; see Figure 10
5.5
-
-
5.5
-
ns
CEP or CET to CP; see Figure 11
6.0
-
-
5.0
-
ns
U/D to CP; see Figure 12
8.0
-
-
6.5
-
ns
Dn to CP; see Figure 10
3.5
-
-
2.5
-
ns
PE to CP; see Figure 10
6.5
-
-
6.5
-
ns
CEP or CET to CP; see Figure 11
8.0
-
-
6.5
-
ns
U/D to CP; see Figure 12
6.5
-
-
6.5
-
ns
Dn to CP; see Figure 10
1.0
-
-
0
-
ns
PE to CP; see Figure 10
0
-
-
0
-
ns
CEP or CET to CP; see Figure 11
0
-
-
0
-
ns
U/D to CP; see Figure 12
0
-
-
0
-
ns
Dn to CP; see Figure 10
1.0
-
-
1.0
-
ns
PE to CP; see Figure 10
0
-
-
0
-
ns
CEP or CET to CP; see Figure 11
0
-
-
0
-
ns
U/D to CP; see Figure 12
0
-
-
0
-
ns
tWH
pulse width HIGH
CP; see Figure 7
4.0
-
-
4.0
-
ns
tWL
pulse width LOW
CP; see Figure 7
4.5
-
-
5.0
-
ns
fmax
maximum
frequency
see Figure 7
100
115
-
85
-
MHz
11. Waveforms
1/fmax
VI
CP input
VM
GND
tWH
tWL
tPHL
tPLH
VOH
VM
Qn, TC output
VOL
001aal292
Measurement points are given in Table 8.
VM = 1.5 V
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 7.
Clock (CP) to outputs (Qn, TC) propagation delay, the clock pulse width
74F269_5
Product data sheet
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Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
10 of 19
74F269
NXP Semiconductors
8-bit bidirectional binary counter
VI
VM
CET
GND
tPLH
tPHL
VOH
VI
VM
TC
VOL
001aaa652
Measurement points are given in Table 8.
VM = 1.5 V
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 8.
Input (CET) to output (TC) propagation delay
VI
VM
U/D
GND
tPLH
tPHL
VOH
VI
VM
TC
VOL
001aaa653
Measurement points are given in Table 8.
VM = 1.5 V
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 9.
The up/down control input (U/D) to output (TC) propagation delay
VI
VM
VM
Dn
GND
tsu
th
VI
VM
PE
VM
VM
GND
VM
tsu(H)
tsu(L)
th = 0 ns
th = 0 ns
VI
VM
CP
GND
VM
001aal301
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
VM = 1.5 V
Fig 10. Data input (Dn), parallel enable input (PE) and clock input (CP) set-up and hold times
74F269_5
Product data sheet
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Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
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74F269
NXP Semiconductors
8-bit bidirectional binary counter
VI
VM
CET, CEP
VM
VM
VM
GND
th(L)
th(H)
tsu(L)
tsu(H)
VI
VM
CP
VM
GND
VOH
Qn
COUNT
NO CHANGE
VOL
001aal302
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
VM = 1.5 V
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 11. Count enable inputs (CEP and CET) and clock input (CP) set-up and hold times
VI
VM
U/D
VM
VM
VM
GND
tsu(L)
th
tsu(H)
th
VI
VM
CP
VM
GND
VOH
Qn
COUNT DOWN
COUNT UP
VOL
001aal303
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
VM = 1.5 V
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 12. Up/down count control input (U/D) and clock input (CP) set-up and hold times
74F269_5
Product data sheet
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Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
12 of 19
74F269
NXP Semiconductors
8-bit bidirectional binary counter
VI
tW
90 %
90 %
negative
pulse
VM
0V
VCC
10 %
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VEXT
VM
10 %
VI
RL
VO
G
DUT
RT
90 %
CL
RL
VM
VM
10 %
10 %
mna616
tW
001aai298
a. Input pulse definition
b. Test circuit
Test data is given in Table 8.
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Test circuit for measuring switching times
Table 8.
Test data
Input
Load
VEXT
VI
fI
tW
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
3.0 V
1 MHz
500 ns
≤ 2.5 ns
50 pF
500 Ω
open
open
7.0 V
74F269_5
Product data sheet
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Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
13 of 19
74F269
NXP Semiconductors
8-bit bidirectional binary counter
12. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
HE
y
v M A
Z
24
13
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.61
0.60
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT137-1
075E05
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 14. Package outline SOT137-1 (SO24)
74F269_5
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
14 of 19
74F269
NXP Semiconductors
8-bit bidirectional binary counter
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
D
SOT340-1
E
A
X
c
HE
y
v M A
Z
24
13
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
0.8
0.4
8
o
0
o
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
SOT340-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
Fig 15. Package outline SOT340-1 (SSOP24)
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Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
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13. Abbreviations
Table 9.
Abbreviations
Acronym
Description
BiCMOS
Bipolar Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
14. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74F269_5
20100325
Product data sheet
-
74F269_4
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20100308
Product data sheet
-
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Modifications:
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Modifications:
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Product data sheet
•
Table 6 “Static characteristics”: Conditions typical values corrected.
20100126
Product data sheet
-
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•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
DIP 24 (SOT222-1) package removed from Section 3 “Ordering information” and
Section 12 “Package outline”
19960105
Product specification
-
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 25 March 2010
74F269_1
© NXP B.V. 2010. All rights reserved.
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
suitable for use in medical, military, aircraft, space or life support equipment,
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
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Product data sheet
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
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16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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All information provided in this document is subject to legal disclaimers.
Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
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17. Contents
1
2
3
4
5
5.1
5.2
6
6.1
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 8
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 March 2010
Document identifier: 74F269_5
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