SL74HC161 Presettable Counters High-Performance Silicon-Gate CMOS The SL74HC161 is identical in pinout to the LS/ALS161. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC161 is programmable 4-bit synchronous counter that feature parallel Load, asynchronous Reset, a Carry Output for cascading and count-enable controls. The SL74HC161 is binary counter with asynchronous Reset. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC161N Plastic SL74HC161D SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 16 =VCC PIN 8 = GND FUNCTION TABLE Inputs Outputs Reset Load Enable P Enable T Clock Q0 Q1 Q2 Q3 Function L X X X X L L L L Reset to “0” H L X X P0 P1 P2 P3 Preset Data H H X L No change No count H H L X No change No count H H H H Count up Count H X X X No change No count X=don’t care P0,P1,P2,P3 = logic level of Data inputs Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3 SLS System Logic Semiconductor SL74HC161 MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN IOUT Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HC161 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Guaranteed Limit Test Conditions V 25 °C to -55°C ≤85 °C ≤125 °C Unit Minimum High-Level Input Vo ltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 Symbol Parameter VIH VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA V IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 4.0 40 160 µA SLS System Logic Semiconductor SL74HC161 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol fmax Parameter Maximum Clock Frequency (Figures 1,6) tPLH Maximum Propagation Delay Clock to Q Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit 2.0 4.5 6.0 6 30 35 5 24 28 4 20 24 MHz 2.0 4.5 6.0 120 20 16 160 23 20 200 28 22 ns tPHL (Figures 1,6) 2.0 4.5 6.0 145 22 18 185 25 20 320 30 23 ns tPHL Maximum Propagation Delay Reset to Q (Figures 2 and 6) 2.0 4.5 6.0 145 20 17 185 22 19 220 25 21 ns 2.0 4.5 6.0 110 16 14 150 18 15 190 20 17 ns 2.0 4.5 6.0 135 18 15 175 20 16 210 22 20 ns 2.0 4.5 6.0 120 22 18 160 27 22 200 30 25 ns tPLH Maximum Propagation Delay Enable T to Ripple Carry Out tPHL (Figures 3,6) tPLH Maximum Propagation Delay Clock to Ripple tPHL Carry Out (Figures 1,6) 2.0 4.5 6.0 145 22 20 185 28 24 220 35 28 ns tPHL Maximum Propagation Delay Reset to Ripple Carry Out (Figures 2,6) 2.0 4.5 6.0 155 22 18 190 26 22 230 30 25 ns Maximum Output Transition Time, Any Output (Figures 1 and 6) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns - 10 10 10 pF tTLH, t THL CIN Maximum Input Capacitance Power Dissipation Capacitance (Per Gate) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Typical @25°C,VCC=5.0 V 30 pF SLS System Logic Semiconductor SL74HC161 TIMING REQUIREMENTS (CL=50pF,Input t r=t f=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit tSU Minimum Setup Time, Preset Data Inputs to Clock (Figure 4) 2.0 4.5 6.0 40 15 12 60 20 18 80 30 20 ns tSU Minimum Setup Time, Load to Clock (Figure 4) 2.0 4.5 6.0 60 15 12 75 20 18 90 30 20 ns tSU Minimum Setup Time, Enable T or Enable P to Clock (Figure 5) 2.0 4.5 6.0 80 20 17 95 25 23 110 35 25 ns th Minimum Hold Time, Clock to Load or Preset Data Inputs (Figure 4) 2.0 4.5 6.0 3 3 3 3 3 3 3 3 3 ns th Minimum Hold Time, Clock to Enable T or Enable P (Figure 5) 2.0 4.5 6.0 3 3 3 3 3 3 3 3 3 ns trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 4.5 6.0 80 15 12 95 20 17 110 26 23 ns trec Minimum Recovery Time, Load Inactive to Clock (Figure 4) 2.0 4.5 6.0 80 15 12 95 20 17 110 26 23 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns tr, tf SLS System Logic Semiconductor SL74HC161 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Test Circuit SLS System Logic Semiconductor SL74HC161 VCC=Pin 16 GND=Pin 8 The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle-Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flipflop low. Figure 7.Expanded logic diagram SLS System Logic Semiconductor SL74HC161 Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one, and two. 4. Inhibit. Figure 8. Timing Diagram SLS System Logic Semiconductor SL74HC161 TYPICAL APPLICATIONS CASCADING Note:When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and clock. Figure 9. N-Bit Synchronous Counters Figure 10. Nibble Ripple Counter SLS System Logic Semiconductor