Intersil ISL8200M Complete current share 10a dc/dc power module Datasheet

ISL8200M
Features
The ISL8200M is a simple and easy to use high power,
current-sharing DC\DC power module for
Datacom\Telecom\FPGA power hungry applications. All
that is needed is the ISL8200M, a few passive
components and one VOUT setting resistor to have a
complete 10A design ready for market.
• Complete Switch Mode Power Supply in One Package
The ease of use virtually eliminates the design and
manufacturing risks while dramatically improving time
to market.
Need more output current? Just simply parallel up to six
ISL8200M modules to scale up to a 60A solution (see
Page 7, Figure 6).
The simplicity of the ISL8200M is in its "Off The Shelf",
unassisted implementation. Patented current sharing
in multi-phase operation greatly reduces ripple
currents, BOM cost and complexity.
The ISL8200M’s thermally enhanced, compact QFN
package, operates at full load and over-temperature,
without requiring forced air cooling. It's so thin it can
even fit on the back side of the PCB. Easy access to all
pins with few external components, reduces the PCB
design to a component layer and a simple ground
layer.
Complete Functional Schematic
EN
• Programmable Phase Shift (1 to 6 phase)
• Extremely Low Profile (2.2mm height)
• Input Voltage Range +3.0 V to +20V at 10A, Current
Share up to 60A
• A Single Resistor Sets VOUT from +0.6V to +6V
• Output Overvoltage, Overcurrent and
Over-Temperature, Built-in Protection and
Undervoltage indication
Applications*(see page 21)
• Servers, Telecom and Datacom Applications
• Industrial and Medical Equipment
• Point of Load Regulation
Related Literature*(see page 21)
• AN1544 ISL8200MEVAL2PHZ Evaluation Board
User’s Guide
• iSim Model - (See Respective Device Information
Page at http//:www.intersil.com)
ISL8200M Package
VOUT Range
0.6V to 6.0V
330 F
ISL8200M
Power
Module VOUT_SET
RSET
2.2mm
VSEN_REMPGND1
15
m
m
1
10 F
m
ISet
ISHARE
5
m
FF
PGND
R2
VEN
VOUT
VIN
PVIN
PVcc
22 F
R1
VIN Range
3V to 20V
• Patented Current Share Architecture Reduces Layout
Sensitivity When Modules are Paralleled
5k
FIGURE 1. COMPLETE 10A DESIGN, JUST SELECT RSET
FOR THE DESIRED VOUT
February 26, 2010
FN6727.1
1
FIGURE 2. THE 2.2mm HEIGHT IS IDEAL FOR THE
BACKSIDE OF PCBS WHEN SPACE AND
HEIGHT IS A PREMIUM
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8200M
Complete Current Share 10A DC/DC Power Module
ISL8200M
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL8200MIRZ
TEMP.
RANGE (°C)
PART MARKING
ISL8200M
PACKAGE
(Pb-Free)
-40 to +85
23 Ld QFN
PKG. DWG. #
L23.15x15
NOTE:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8200M. For more information on MSL please
see techbrief TB363.
Pinout Internal Circuit
CF1
VCC
PVCC
PVIN
21
14
17
RCC
CF2
BOOT1
VIN
13
EN
12
UGATE1
CBOOT1
Q1
LOUT1
PHASE1
FF
11
19
VOUT
18
PGND
16
PHASE
20
OCSET
1
VOUT_SET
2
VSEN_REM-
VCC
RPG
PGOOD
LGATE1
Q2
22
VCC
RCLK
ISEN1A
CLKOUT
8
VCC
RPHC
PH_CNTRL
RSEN
CONTROLLER
9
ISEN1B
ISET
5
CF3
ISHARE
COMP
ZCOMP1
6
CF4
ISHARE_BUS
10
ISFETDRV
3
FSYNC_IN
7
FB1
VMON1
ZCOMP2
VSEN1+
CVSEN
RFS
2
VSEN1-
15
4
PGND1
PGND1
ROS1
RCSR
FN6727.1
February 26, 2010
ISL8200M
Pin Configuration
ISL8200M
(32 LD QFN)
TOP VIEW
Pin Descriptions
PIN
NUMBER
PIN NAME
1
VOUT_SET
2
PIN DESCRIPTION
Analog Voltage Input - Used with VOUT to program the regulator output voltage. The typical input
impedance of VSEN1+ with respect to VSEN1- is 500kΩ. Voltage input typ. 0.6V.
VSEN_REM- Analog Voltage Input - This pin is the negative input of standard unity gain operational amplifier for
differential remote sense for the regulator, and should connect to the negative rail of the
load/processor. This pin can be used for VOUT trimming by connecting a resistor from this pin to the
VOUT_SET pin.
3
ISFETDRV
Digital Output - This pin is used to drive an optional NFET, which will connect ISHARE with the system
ISHARE bus upon completing a pre-bias startup. Voltage Output Range: 0V to 5V.
4, 15
PGND1
Normal Ground - All voltage levels are referenced to this pad.This pad provides a return path for the
low side MOSFET drives and internal power circuitries as well as all analog signals. PGND and PGND1
should be connected together with a ground plane.
5
ISET
Analog Current Output - This pin sources a 15µA offset current plus Channel 1’s average current. The
voltage (VISET) set by an external resistor (RISET) represents the average current level of the local
active module. For full-scale current, RISET should be ~10kΩ. Output current range: 15µA to 108µA
typ.
3
FN6727.1
February 26, 2010
ISL8200M
Pin Descriptions (Continued)
PIN
NUMBER
PIN NAME
PIN DESCRIPTION
6
ISHARE
Analog Current Output - Cascaded system level over current shutdown pin. This pin is used where you
have multiple modules configured for current sharing and is used with a common current share bus.
The bus sums each of the modules' average current contribution to the load to protect for a over current
condition at the load. The pin sources 15µA plus average module's output current. The shared bus
voltage (VISHARE) is developed across an external resistor (RISHARE). VISHARE represents the
average current of all active channel(s) that connected together.
The ISHARE bus voltage is compared with each module's internal reference voltage set by each
module's RISET resistor. This will generate and individual current share error signal in each cascaded
controller. The share bus impedance RISHARE should be set as RISET/NCTRL, RISET divided by number
of active current sharing controllers. The output current from this pin generates a voltage across the
external resistor. This voltage, VISHARE, is compared to and internal 1.2V threshold for average
overcurrent protection. For full-scale current, RISHARE should be ~10kΩ . Typically 10kΩ is used for
RSHARE and RSET. Output Current Range: 15µA to 108µA typ.
7
FSYNC IN
Analog input Control Pin - An optional external resistor (RFS-ext) connected to this pin and ground will
increase the oscillator switching frequency. It has an internal 59kΩ resistor for a default frequency of
700kHz. The internal oscillator will lock to an external frequency source when connected to a square
wave form. The external source is typically the CLKOUT signal from another ISL8200M or an external
clock. The internal oscillator synchronizes with the leading positive edge of the input signal. Input
Voltage Range for external source: 0V to 5V Square Wave.
8
CLKOUT
Digital Voltage Output - This pin provides a clock signal to synchronize with other ISL8200M(s). When
there is more than one ISL8200M in the system, the two independent regulators can be programmed
via PH_CNTRL for different degrees of phase delay.
9
PH_CNTRL
Analog Input - The voltage level on this pin is used to program the phase shift of CLKOUT clock signal
to synchronize with other module(s).
10
ISHARE_BUS Open pin until first PWM pulse is generated. Then, via an internal FET, this pin connects the module’s
ISHARE to the system’s ISHARE bus after pre-bias is complete and soft-start is initiated.
11
FF
Analog Voltage Input - The voltages on this pin is fed into the controller, adjusting the sawtooth
amplitude to generate the feed-forward function. Voltage input 0.7 to VCC.
12
EN
This is a double function pin: Analog Input Voltage - The input voltage to this pin is compared with a
precision 0.8V reference and enables the digital soft-start. Input Voltage Range is 0V to VCC or VIN
through a pull up resistor maintaining a typical current of 5mA.
Analog Voltage Output - This pin can be used as a voltage monitor for input bus undervoltage lockout.
The hysteresis levels of the lockout can be programmed via this pin using a resistor divider network.
Furthermore, during fault conditions (such as overvoltage, overcurrent, and over-temperature), this
pin is used to communicate the information to other cascaded modules by pulling low the wired OR as
it is an Open Drain. Output Voltage Range is 0V to VCC.
13
VIN
Analog Voltage Input - This pin should be tied directly to the input rail when using the internal linear
regulator. It provides power to the internal linear drive circuitry. When used with an external 5V supply,
this pin should be tied directly to VCC. The internal linear device is protected against the reversed bias
generated by the remained charge of the decoupling capacitor at VCC when losing the input rail. Input
Voltage Range 0V to 20V.
14
PVCC
Analog Output - This pin is the output of the internal series linear regulator. It provides the bias for
both low-side and high-side drives. Its operational voltage range is 3V to 5.6V. The decoupling ceramic
capacitor in the PVCC pin is 10µF.
16
PHASE
17
PVIN
Analog Input - This input voltage is applied to the power FETS with the FET’s ground being the PGND
pin. It is recommended to place input decoupling capacitance, 22µF, directly between PVIN pin and
PGND pin as close as possible to the module. Input Voltage Range: 0V to 20V.
18
PGND
All voltage levels are referenced to this pad. This is the low side MOSFET ground. PGND and PGND1
should be connected together with a ground plane.
19
VOUT
Output voltage from the module. Output Voltage Range: 0.6V to 6V.
20
OCSET
Analog Output = This pin is the phase node of the regulator. Output Voltage Range 0V to 30V.
Analog Input - This pin is used with PHASE pin to set the current limit of the module. Input Voltage
Range 0V to 30V.
4
FN6727.1
February 26, 2010
ISL8200M
Pin Descriptions (Continued)
PIN
NUMBER
PIN NAME
PIN DESCRIPTION
21
VCC
Analog Input - This pin provides bias power for the analog circuitry. It’s operational range is 2.97V to
5.6V. In 3.3V applications, VCC, PVCC and VIN should be shorted to allow operation at the low end
input as it relates to the VCC falling threshold limit. This pin can be powered either by the internal linear
regulator or by an external voltage source.
22
PGOOD
Analog Output - Provides an open drain Power Good signal when the output is within 9% of nominal
output regulation point with 4% hysteresis (13%/9%), and soft-start is complete. PGOOD monitors the
outputs (VMON1) of the internal differential amplifiers. Output Voltage Range: 0V to VCC.
23
NC
Not internal connected
PD1
Phase
Used for both the PHASE pin (Pin # 16) and for heat removal connecting to heat dissipation layers using
Thermal Pad Vias. Potential should be floating and not electrically connected to anything except PHASE pin 16.
PD2
VIN Thermal Used for both the PVIN pin (Pin # 17) and for heat removal connecting to heat dissipation layers using
Pad
Vias. Potential should be floating and not electrically connected to anything except VPVIN pin 17.
PD3
PGND
Used for both the PGND pin (Pin # 18) and for heat removal connecting to heat dissipation layers using
Thermal Pad Vias. Potential should be floating and not electrically connected to anything except PGND pin 18.
PD4
VOUT
Used for both the VOUT pin (Pin # 19) and for heat removal connecting to heat dissipation layers using
Thermal Pad Vias. Potential should be floating and not electrically connected to anything except VOUT pin 19.
Typical Application Circuits
VOUT
U201
ISL8200M
GND
VIN
PVIN
R1
16.5k
CIN(CER)
R2
4.12k
CEN
1nF
VOUT
VIN
2.2k
RSET
COUT
FF
EN
VOUT_SET
* Select R1 & R2
such that
0.8V<VEN<5.0V
FSYNC_IN
(See Table 1,
VOUT - RSET on page 13)
VSEN_REM-
CLKOUT
ISHARE_BUS
PGOOD
PGOOD1
VCC
PVCC
PGND
PHASE
PH_CNTRL
OCSET
ISET
ISFETDRV
ISHARE
ISF ETDRV1
PGND1
GND
CPVCC
10uF
RISHARE
5k
FIGURE 3. SINGLE PHASE 10A 1.2V OUTPUT CIRCUIT
5
FN6727.1
February 26, 2010
ISL8200M
Typical Application Circuits (Continued)
J3
VOUT1
J4
GND
U201
ISL8200M
J1
PVIN
VIN1
C3
270uF
R1
8.25k
C203
22uF
R2
2.05k
C211
1nF
VOUT
VOUT
VIN
C9
330uF
2.2k
R221
FF
EN
VOUT_SET
J2
FSYNC_IN
GND
VSEN_REM-
ISFETDRV2
CLKOUT
ISHARE_BUS
PGOOD
PGOOD
R234
10k
3
2
1
VOUT
VCC
PVCC
60k
R233
4
C209
10uF
5
Q203
2N7002DW
6
PGND1
PGND
ISET
PHASE
PH_CNTRL
OCSET
ISFETDRV
ISHARE
ISFETDRV2
C208
0.1uF
PGOOD
RISHARE2
5k
RISET2
10k
U301
ISL8200M
PVIN
C303
22uF
VOUT
VIN
2.2k
R321
FF
C311
1nF
EN
VOUT_SET
FSYNC_IN
VSEN_REMISFETDRV3
CLKOUT
PGOOD
R334
10k
2
VOUT
1
VCC
PVCC
PGND1
PGND
PHASE
PH_CNTRL
OCSET
ISET
ISHARE
ISFETDRV
3
ISHARE_BUS
ISFETDRV3
PGOOD
60k
R333
PGOOD
4
5
6
C309
10uF
RISET3
10k
Q303
2N7002DW
C308
0.1uF
FIGURE 4. TWO PHASE 20A 1.2V OUTPUT CIRCUIT
6
FN6727.1
February 26, 2010
ISL8200M
Absolute Maximum Ratings
Thermal Information
Input Voltage, PVIN, VIN . . . . . . . . . . . . . . . . -0.3V to +27V
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . -0.3V to +6.5V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . -0.3V to +6.5V
BOOT/UGATE Voltage, VBOOT . . . . . . . . . . . . . -0.3V to +36V
Phase Voltage, VPHASE . . . . . . . VBOOT - 7V to VBOOT + 0.3V
BOOT to PHASE Voltage,
VBOOT - VPHASE . . . . . . . . . . . . . . . .-0.3V to VCC + 0.3V
Input, Output or I/O Voltage . . . . . . . . .-0.3V to VCC + 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . 200V
Charge Device Model (Tested per JESD22-C101C) . . . . 1kV
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
QFN Package (Notes 4, 5) . . . . . . .
13
2.0
Maximum Storage Temperature Range . . . -40°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Input Voltage, PVIN, VIN . . . . . . . . . . . .
Driver Bias Voltage, PVCC . . . . . . . . . . .
Signal Bias Voltage, VCC . . . . . . . . . . . .
Boot to Phase Voltage (Overcharged),
VBOOT - VPHASE . . . . . . . . . . . . . . . . .
Commercial Ambient Temperature Range.
Industrial Ambient Temperature Range . .
Junction Temperature Range . . . . . . . . .
. . . . . . .3V to 20V
. . . . . . 3V to 5.6V
. . . . . . 3V to 5.6V
.
.
.
.
. . . . . . . . . .<6V
. . . 0°C to +70°C
. -40°C to +85°C
-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. Parameters with TYP limits are not production tested, unless otherwise specified.
7. Parameters are 100% tested for internal IC prior to module assembly.
Electrical Specifications
PARAMETER
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested. Boldface
limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
TEST CONDITIONS
MIN
TYP
(Note 6)
MAX
UNITS
VCC SUPPLY CURRENT
Nominal Supply VIN Current
IQ_VIN
PVIN = VIN = 20V; No Load;
FSW = 700kHz
36
mA
Nominal Supply VIN Current
IQ_VIN
PVIN = VIN = 4.5V; No Load;
FSW = 700kHz
27
mA
9
mA
Shutdown Supply VCC Current
IVCC
EN = 0V, VCC = 2.97V
Maximum Current
IPVCC
PVCC = 4V TO 5.6V
250
mA
PVCC = 3V TO 4V
150
mA
Saturated Equivalent
Impedance
RLDO
P-Channel MOSFET (VIN = 5V)
1
Ω
PVCC Voltage Level (Note 7)
PVCC
IPVCC = 0mA to 250mA
INTERNAL LINEAR REGULATOR
5.1
5.4
5.6
V
2.85
2.97
V
2.65
2.75
V
2.85
2.97
V
2.85
3.05
2.65
2.75
POWER-ON RESET (Note 7)
Rising VCC Threshold
Falling VCC Threshold
Rising PVCC Threshold
0°C to +70°C
-40°C to +85°C
Falling PVCC Threshold
System Soft-start Delay
tSS_DLY
After PLL, VCC, and PVCC PORs, and EN
above their thresholds
384
V
Cycles
ENABLE (Note 7)
Maximum Input Voltage
VEN
Turn-On Threshold Voltage
Hysteresis Sink Current
IEN_HYS
7
VCC
V
0.75
0.8
0.86
V
25
30
35
µA
FN6727.1
February 26, 2010
ISL8200M
Electrical Specifications
PARAMETER
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
Undervoltage Lockout
Hysteresis
VEN_HYS
Sink Current
IEN_SINK
Sink Impedance
REN_SINK
TEST CONDITIONS
MIN
VEN_RTH = 10.6V; VEN_FTH = 9V
TYP
(Note 6)
MAX
1.5
RUP = 53.6kΩ, RDOWN = 5.23kΩ
IEN_SINK = 5mA
UNITS
V
15
mA
65
Ω
OSCILLATOR
Oscillator Frequency
FOSC
RFS = 59kΩ; Figure 27
VCC = 5V; -40°C< TA <+85°C
Total Variation (Note 7)
700
kHz
-9
+9
%
FOSC
1500
kHz
FREQUENCY SYNCHRONIZATION AND PHASE LOCK LOOP (Note 7)
Synchronization Frequency
VCC = 5.4V (2.97V)
PLL Locking Time
VCC = 5.4V (2.97V); FSW = 700kHz
Maximum Input Signal Level
105
µs
V
VCC
Input Signal Duty Cycle Range
10
50
90
%
310
345
410
ns
PWM (Note 7)
Minimum PWM OFF Time
tMIN_OFF
Current Sampling Blanking
Time
175
tBLANKING
ns
OUTPUT CHARACTERISTICS
Output Continuous Current
Range
IOUT(DC)
Line Regulation Accuracy
ΔVOUT/ΔVIN
PVIN = VIN = 12V, VOUT = 1.2V
0
-
10
A
VOUT = 1.2V, IOUT = 0A,
PVIN = VIN = 3.5V to 20V
-
0.15
-
%
VOUT = 1.2V, IOUT = 10A,
PVIN = VIN = 5V to 20V
-
0.15
-
%
-
0.1
-
%
IOUT = 10A, VOUT = 1.2V,
PVIN = VIN = 12V
-
30
-
mVP-P
ΔVOUT/ΔIOUT IOUT = 0A to 10A, VOUT = 1.2V,
PVIN = VIN = 12V
Load Regulation Accuracy
Output Ripple Voltage
ΔVOUT
DYNAMIC CHARACTERISTICS
Voltage Change For Positive
Load Step
ΔVOUT-DP
IOUT = 0A to 5A. Current slew
rate = 2.5A/µs, PVIN = VIN = 12V,
VOUT = 1.2V
-
45
-
mVP-P
Voltage Change For Negative
Load Step
ΔVOUT-DN
IOUT = 5A to 0A. Current slew
rate = 2.5A/µs, PVIN = VIN = 12V,
VOUT = 1.2V
-
55
-
mVP-P
0.7
%
REFERENCE (Note 7)
VREF1
Reference Voltage (Include
Error and Differential
Amplifiers’ Offsets)
ISL8200MIRZ, TA = -40°C to +85°C
0.6
-0.7
V
DIFFERENTIAL AMPLIFIER (Note 7)
DC Gain
UG_DA
Unity Gain Bandwidth
Unity Gain Amplifier
UGBW_DA
Negative Input Source Current
IVSENIVSEN1-
Maximum Source Current for
Current Sharing
VSEN1- Source Current for Current
Sharing when parallel multiple modules
each of which has its own voltage loop
RVSEN+_to
_VSEN-
Input Impedance
Output Voltage Swing
0
8
0
dB
5
MHz
100
nA
350
µA
1
MΩ
VCC - 1.8
V
FN6727.1
February 26, 2010
ISL8200M
Electrical Specifications
PARAMETER
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
TEST CONDITIONS
Input Common Mode Range
MIN
TYP
(Note 6)
-0.2
Disable Threshold
VVSEN-
VMON1 = Tri-State
MAX
UNITS
VCC - 1.8
V
VCC - 0.4
V
108
µA
OVERCURRENT PROTECTION (Note 7)
ISOURCE
VCC = 2.97V to 5.6V
Channel Overcurrent Limit
ISOURCE
VCC = 5V;
Share Pin OC Threshold
VOC_SET
VCC = 2.97V to 5.6V
(comparator offset included)
Channel Overcurrent Limit
Share Pin OC Hysteresis
89
108
122
µA
1.16
1.20
1.22
V
VOC_SET_HYS VCC = 2.97V to 5.6V
(comparator offset included)
50
mV
±5
%
CURRENT SHARE
VCC = 2.97V and 5.6V, 1% Resistor
Sense, 10mV Signal
External Current Share
Accuracy
POWER GOOD MONITOR (Note 7)
Undervoltage Falling Trip Point
VUVF
Undervoltage Rising Hysteresis
VUVR_HYS
Overvoltage Rising Trip Point
VOVR
Overvoltage Falling Hysteresis
VOVF_HYS
Percentage Below Reference Point
-15
-13
11
13
Percentage Above UV Trip Point
Percentage Above Reference Point
Percentage below OV Trip Point
Sinking Impedance
IPGOOD = 2mA
Maximum Sinking Current
VPGOOD <0.8V
Maximum Open Drain Voltage
%
15
%
4
%
4
IPGOOD = 2mA
PGOOD Low Output Voltage
-11
%
0.35
70
10
V
Ω
mA
V
VCC
OVERVOLTAGE PROTECTION (Note 7)
OV Latching Up Trip Point
EN/FF= UGATE = LATCH Low,
LGATE = High
OV Non-Latching Up Trip Point
EN = Low, UGATE = Low, LGATE = High
LGATE Release Trip Point
EN = Low/HIGH, UGATE = Low,
LGATE = Low
118
120
122
%
113
%
87
%
Over-Temperature Trip
150
°C
Over-Temperature Release
Threshold
125
°C
OVER-TEMPERATURE PROTECTION
INTERNAL COMPONENT VALUES
Internal Resistor Between
PVCC and VCC pin
RCC
5
Ω
Internal Resistor Between
PHASE and OCSET Pins
RSEN1
2.2k
Ω
Internal Resistor Between
FSYNC_IN and SGND Pins
RFS
59k
Ω
Internal Resistor Between
PGOOD and VCC Pins
RPG
10k
Ω
Internal Resistor Between
CLKOUT and VCC Pins
RCLK
10k
Ω
Internal Resistor Between
PH_CNTRL and VCC Pins
RPHC
10k
Ω
Internal Resistor Between
VOUT_SET and VSEN_REM- pin
ROS1
2.2k
Ω
9
FN6727.1
February 26, 2010
ISL8200M
1.2V 10A
VOUT
VIN
PVIN
R1
16.5k
CIN(CER)
VOUT
ISL8200M
FF
CIN (BULK)
R2
4.12k
CEN
1nF
COUT
2.2k
RSET
VIN
10uF 25V
x 2
47uF 10V
x 8
EN
VOUT_SET
FSYNC_IN
VSEN_REM-
CLKOUT
ISHARE_BUS
PGOOD
ISFETDRV
PGOOD1
PH_CNTRL
PGND1
PGND
PHASE
OCSET
VCC
ISET
ISHARE
ISFETDRV1
PVCC
GND
CPVCC
10uF
RISHARE
5k
FIGURE 5. TEST CIRCUIT FOR ALL PERFORMANCE AND DERATING GRAPHS
Typical Performance Characteristics
Efficiency Performance
TA = +25°C, PVIN = VIN, CIN = 220µFx1, 10µF/Ceramic x 2, COUT = 47µF/Ceramic x 8.
The efficiency equation is:
100
100
95
95
EFFICIENCY (%)
EFFICIENCY (%)
( V OUT xI OUT )
P OUT
Output Power
- = ------------------------------------Efficiency = ----------------------------------------- = --------------P IN
( V IN xI IN )
Input Power
90
85
80
3.3V
75
2.5V
1.5V
70
1.2V
65
60
0
2
4
6
0.8V
8
90
85
80
75
70
3.3V
65
10
60
0
1.5V 1.2V
5.0V
2
LOAD CURRENT (A)
FIGURE 6. EFFICIENCY vs LOAD CURRENT (5VIN)
2.5V
0.8V
4
6
LOAD CURRENT (A)
8
10
FIGURE 7. EFFICIENCY vs LOAD CURRENT (12VIN)
VOUT
100
3.3V
EFFICIENCY (%)
95
2.5V
5.0V
90
IOUT
VIN = 12V
VOUT = 1.2V
IOUT = 0A to 5A
85
80
75
70
1.5V
65
60
0
2
4
6
1.2V
8
10
LOAD CURRENT (A)
FIGURE 8. EFFICIENCY vs LOAD CURRENT (20VIN)
10
FIGURE 9. 1.2V TRANSIENT RESPONSE
FN6727.1
February 26, 2010
ISL8200M
Typical Performance Characteristics
Transient Response Performance
(Continued)
TA = +25°C, PVIN = VIN = 12V, CIN = 220µFx1, 10µF/Ceramic x 2,
COUT = 47µF/Ceramic x 8 IOUT = 0A to 5A, Current slew rate = 2.5A/µs
VOUT
VOUT
IOUT
VIN = 12V
VOUT = 1.5V
IOUT = 0A to 5A
FIGURE 10. 1.5V TRANSIENT RESPONSE
IOUT
VIN = 12V
VOUT = 1.8V
IOUT = 0A to 5A
FIGURE 11. 1.8V TRANSIENT RESPONSE
VOUT
VOUT
IOUT
VIN = 12V
VOUT = 2.5V
IOUT = 0A to 5A
FIGURE 12. 2.5V TRANSIENT RESPONSE
11
IOUT
VIN = 12V
VOUT = 3.3V
IOUT = 0A to 5A
FIGURE 13. 3.3V TRANSIENT RESPONSE
FN6727.1
February 26, 2010
ISL8200M
Typical Performance Characteristics
Output Ripple Performance
(Continued)
TA = +25°C, PVIN = VIN = 12V, CIN = 220µFx1, 10µF/Ceramic x 2,
COUT = 47µF/Ceramic x 8 IOUT = 0, 5, 10A
VOUT 10A
VOUT 10A
VOUT 5A
VOUT 5A
VOUT 0A
VOUT 0A
FIGURE 14. 1.2V OUTPUT RIPPLE
FIGURE 15. 1.5V OUTPUT RIPPLE
VOUT 10A
VOUT 10A
VOUT 5A
VOUT 5A
VOUT 0A
VOUT 0A
FIGURE 16. 2.5V OUTPUT RIPPLE
12
FIGURE 17. 3.3V OUTPUT RIPPLE
FN6727.1
February 26, 2010
ISL8200M
Typical Performance Curves
FIGURE 18. 4-BOARD CLOCK SYNC (VIN = 12V)
FIGURE 19. OVER CURRENT PROTECTION
VIN = 0V to 18V
VOUT = 1.2V
IOUT = 0A
FIGURE 20. 50% PRE-BIAS START UP
Applications Information
Programming the Output Voltage (RSET)
The ISL8200M has an internal 0.6V ± 0.7% reference
voltage. Programming the output voltage requires a
dividing resistor (RSET) between VOUT_SET pin and
VOUT regulation point. The output voltage can be
calculated as shown in Equation 1:
R SET⎞
⎛
V OUT = 0.6 × ⎜ 1 + ---------------⎟
R OS ⎠
⎝
(EQ. 1)
13
Note: ISL8200M has integrated 2.2kΩ resistances into
the module dividing resistor for bottom side (ROS1). The
resistance for different output voltages are as follows:
TABLE 1. VOUT-RSET
VOUT
0.6V
0.8V
1.0V
1.2V
RSET
0Ω
732Ω
1.47kΩ
2.2kΩ
VOUT
1.5V
1.8V
2.0V
2.5
RSET
3.32kΩ
4.42kΩ
5.11kΩ
6.98kΩ
VOUT
3.3
5.0
6.0
RSET
10kΩ
16.2kΩ
20kΩ
FN6727.1
February 26, 2010
ISL8200M
The output voltage accuracy can be improved by
maintaining the impedance at VOUTSET (internal
VSEN1+) at or below 1kΩ effective impedance. Note: the
impedance between VSEN1+ and VSEN1- is about 500kΩ.
The module has minimum input voltage at a given output
voltage, which needs to be a minimum of 1.43 times
output voltage if operating at FSW = 700kHz switching
frequency. This is due to the Minimum PWM OFF Time
(tMIN-OFF).
The equation to determine the minimum VIN to support
the required VOUT is given by Equations 2 and 3:
V OUT × t SW
V IN_MIN = -----------------------------------------t SW – t MIN_OFF
(EQ. 2)
tSW = switching period = 1/FSW
for the 700kHz switching frequency = 1428ns
V IN_MIN = 1.43 × V OUT
(EQ. 3)
Selection of the Input Capacitor
The input filter capacitor should be based on how much
ripple the supply can tolerate on the DC input line. The
larger the capacitor, the less ripple expected, but
consideration should be taken for the higher surge
current during power-up. The ISL8200M provides the
soft-start function that controls and limits the current
surge. The value of the input capacitor can be calculated
by Equation 4:
I IN × Δt
C IN = ------------------ΔV
be needed if further reduction of output ripple or dynamic
transient spike is required.
Functional Description
Initialization
The ISL8200M requires VCC and PVCC to be biased by a
single supply. Power-On Reset (POR) circuits
continually monitor the bias voltages (PVCC and VCC)
and the voltage at EN pin. The POR function initiates
soft-start operation 384 clock cycles after the EN pin
voltage is pulled to be above 0.8V, all input supplies
exceed their POR thresholds and the PLL locking time
expires. The enable pin can be used as a voltage
monitor and to set desired hysteresis with an internal
30µA sinking current going through an external
resistor divider. The sinking current is disengaged after
the system is enabled. This feature is especially
designed for applications that require higher input rail
POR for better undervoltage protection. For example,
in 12V applications, RUP = 53.6k and RDOWN = 5.23k
will set the turn-on threshold (VEN_RTH) to 10.6V and
turn-off threshold (VEN_FTH) to 9V, with 1.6V
hysteresis (VEN_HYS).
During shutdown or fault conditions, the soft-start is
quickly reset while UGATE and LGATE immediately
change state (<100ns) upon the input dropping below
POR.
HIGH = ABOVE POR; LOW = BELOW POR
(EQ. 4)
VCC POR
Where:
PVCC POR
EN POR
AND
384
CYCLES
SOFT-START
OF MODULE
CIN is the input capacitance (µF)
PLL LOCKING
IIN is the input current (A)
FIGURE 21. SOFT-START INITIALIZATION LOGIC
Δt is the turn on time of the high-side switch (µs)
ΔV is the allowable peak-to-peak voltage (V)
In addition to the bulk capacitance, some low Equivalent
Series Inductance (ESL) ceramic capacitance is
recommended to decouple between the drain terminal of
the high side MOSFET and the source terminal of the low
side MOSFET. This is used to reduce the voltage ringing
created by the switching current across parasitic circuit
elements.
Output Capacitors
The ISL8200M is designed for low output voltage ripple.
The output voltage ripple and transient requirements can
be met with bulk output capacitors (COUT) with low
enough Equivalent Series Resistance (ESR). COUT can be
a low ESR tantalum capacitor, a low ESR polymer
capacitor or a ceramic capacitor. The typical capacitance
is 330µF and decoupled ceramic output capacitors are
used per phase. The internally optimized loop
compensation provides sufficient stability margins for all
ceramic capacitor applications with a recommended total
value of 300µF per phase. Additional output filtering may
14
Voltage Feedforward
The voltage applied to the FF pin is fed to adjust the
sawtooth amplitude of the channel. The amplitude the
sawtooth is set to 1.25 times the corresponding FF
voltage when the module is enabled. This configuration
helps to maintain a constant gain
( G M = V IN ⋅ D MAX ⁄ ΔV RAMP ) and input voltage to achieve
optimum loop response over a wide input voltage range.
The sawtooth ramp offset voltage is 1V (equal to
0.8V*1.25), and the peak of the sawtooth is limited to
VCC - 1.4V. With VCC = 5.4V, the ramp has a maximum
peak-to-peak amplitude of VCC - 2.4V (equal to 3V); so
the feed-forward voltage effective range is typically 3x as
the ramp amplitude ranges from 1V to 3V.
A 384 cycle delay is added after the system reaches its
rising POR and prior to the soft-start. The RC timing at
the FF pin should be sufficiently small to ensure that the
input bus reaches its static state and the internal ramp
circuitry stabilizes before soft-start. A large RC could
cause the internal ramp amplitude not to synchronize
with the input bus voltage during output start-up or
FN6727.1
February 26, 2010
ISL8200M
when recovering from faults. A 1nF capacitor is
recommended as a starting value for typical application.
The voltage on the FF pin needs to be above 0.7V prior to
soft-start and during PWM switching to ensure reliable
regulation. In a typical application, FF pin can be shorted
to EN pin.
allowable pre-charged level is 113%. If the pre-charged
level is above 113% but below 120%, the output will
hiccup between 113% (LGATE turns on) and 87%
(LGATE turns off) while EN is pulled low. If the precharged load voltage is above 120% of the targeted
output voltage, then the controller will be latched off and
not be able to power-up.
Fault Handshake
VOUT TARGET VOLTAGE
0.0V
384
t SS_DLY ≈ -----------F SW
FIGURE 22. SOFT-START WITH VOUT = 0V
Soft-Start
SS Settling at VREF + 100mV
FIRST PWM PULSE
The ISL8200M has an internal digital pre-charged
soft-start circuitry, which has a rise time inversely
proportional to the switching frequency and is
determined by an digital counter that increments with
every pulse of the phase clock. The full soft-start time
from 0V to 0.6V can be estimated by Equation 5.
VOUT TARGET VOLTAGE
INIT. VOUT
-100mV
FIGURE 23. SOFT-START WITH VOUT < TARGET
VOLTAGE
(EQ. 5)
OV = 113%
The ISL8200M has the ability to work under a precharged output. The PWM outputs will not feed to the
drivers until the first PWM pulse is seen. The low side
MOSFET is being held low for first clock cycle to provide
charge for the bootstrap capacitor. If the pre-charged
output voltage is greater than the final target level but
less than the 113% setpoint, switching will not start until
the output voltage is reduced to the target voltage and
the first PWM pulse is generated. The maximum
V EN_HYS
R UP = ----------------------------I EN_HYS
2560
t SS = ------------f SW
-100mV
Since the EN pins are pulled down under fault conditions,
the pull-up resistor (RUP) should be scaled to sink no
more than 5mA current from EN pin. Essentially, the EN
pins cannot be directly connected to VCC.
2560
t SS = ------------f SW
SS Settling at VREF + 100mV
FIRST PWM PULSE
In a multi-module system, with the EN pins wired OR’ed
together, all modules can immediately turn off, at one
time, when a fault condition occurs in one or more
modules. A fault would pull the EN pin low, disabling all
the modules and would not creating current bounce.
Thus, no single channel would be over stressed when a
fault occurs.
FIRST PWM PULSE
VOUT TARGET VOLTAGE
FIGURE 24. SOFT-START WITH VOUT BELOW OV BUT
ABOVE FINAL TARGET VOLTAGE
R
•V
UP
EN_REF
R DOWN = --------------------------------------------------------------V EN_FTH – V EN_REF
V EN_FTH = V EN_RTH – V EN_HYS
VCC_FF
GRAMP = 1.25
VCC - 1.4V
∑
ΔV
RAMP
= LIMIT(V
CC_FF
×G
RAMP
, VCC - 1.4V - V
RAMP_OFFSET
)
UPPER LIMIT
LIMITER
0.8V
SAWTOOTH
AMPLITUDE
(ΔVRAMP)
VIN
FF
VRAMP_OFFSET = 1.0V
LOWER LIMIT
(RAMP OFFSET)
0.8V
RUP
SYSTEM DELAY
RDOWN
EN
384 Clock
Cycles
SOFT-START
IEN_HYS = 30µA
OV, OT, OC, AND PLL LOCKING FAULTS
FIGURE 25. SIMPLIFIED ENABLE AND VOLTAGE FEEDFORWARD CIRCUIT
15
FN6727.1
February 26, 2010
ISL8200M
Overvoltage Protection (OVP)
Power Good
The Power-Good comparators monitor the voltage on the
internal VMON1 pin. The trip points are shown in
Figure 26. PGOOD will not be asserted until after the
completion of the soft-start cycle. The PGOOD pulls low
upon both EN’s disabling it or the internal VMON1 pin’ s
voltage is out of the threshold window. PGOOD will not
be asserted until after the completion of the soft-start
cycle. PGOOD will not pull low until the fault presents for
three consecutive clock cycles.
The UV indication is not enabled until the end of
soft-start. In a UV event, if the output drops below
-13% of the target level due to some reason (cases
when EN is not pulled low) other than OV, OC, OT, and
PLL faults, PGOOD will be pulled low.
CHANNEL 1 UV/OV
AND
PGOOD
END OF SS1
+20%
+13%
VMON1
+9%
There is another non-latch OV protection (113% of
target level). At the condition of EN low and the output
over 113% OV, the lower side MOSFET will turn on until
the output drops below 87%. This is to protect the
overall power trains in case of a single channel of a
multi-module system detecting OV. The low-side MOSFET
always turns on at the conditions of EN = LOW and the
output voltage above 113% (all EN pins are tied
together) and turns off after the output drops below
87%. Thus, in a high phase count application
(multi-module mode), all cascaded modules can latch off
simultaneously via the EN pins (EN pins are tied together
in multiphase mode), and each IC shares the same sink
current to reduce the stress and eliminate the bouncing
among phases.
Over-Temperature Protection (OTP)
-9%
When the junction temperature of the IC is greater than
+150°C (typically), EN pin will be pulled low to inform
other cascaded channels via their EN pins. All connected
ENs stay low and release after the IC’s junction
temperature drops below +125°C (typically), a +25°C
hysteresis (typically).
PGOOD latch off after 120% OV
FIGURE 26. POWER-GOOD THRESHOLD WINDOW
Current Share
The IAVG_CS is the current of the module. ISHARE and
ISET pins source a copy of IAVG_CS with 15µA offset,
i.e., the full scale will be 123µA.
The share bus voltage (VISHARE) set by an external
resistor (RISHARE = RISET/NCTRL) represents the
average current of all active modules. The voltage
(VISET) set by RISET represents the average current of
the corresponding module and is compared with the
share bus (VISHARE). The current share error signal
(ICSH_ER) is then fed into current correction block to
adjust each module’s PWM pulse accordingly. The current
share function provides at least 10% overall accuracy
between ICs, when using 1% resistor to sense 10mV
signal. The current share bus works for up to 6-phase.
When there is only one module in the system, the ISET
and ISHARE pins can be shorted together and
grounded via a single resistor to ensure zero share
error - a resistor value of 5k (paralleling 10k on ISET
and ISHARE) will allow operation up to the OCP level
16
OV protection is active from the beginning of
soft-start. An OV condition (>120%) would latch IC off
(the high-side MOSFET to latch off permanently; the
low-side MOSFET turns on immediately at the time of
OV trip and then turns off permanently after the output
voltage drops below 87%). The EN and PGOOD are
also latched low at OV event. The latch condition can
be reset only by recycling VCC.
VREF
-13%
PGOOD
The Overvoltage (OV) protection indication circuitry
monitor the voltage on the internal VMON1 pin.
Overcurrent Protection (OCP)
The OCP function is enabled at startup. The module’s
output current (ICS1) plus a fixed internal 15µA offset
forms a voltage (VISHARE) across the external resistor,
RISHARE. VISHARE is compared with a precision
internal 1.2V threshold. The Channel Overcurrent Limit
‘108µA OCP’ comparator, waits 7-cycles before
monitoring for an OCP condition.
In multi-module operation, by connecting modules’
ISHARE pin together, results in the VISHARE
representing the average current of all active channels.
The total system currents are compared with a
precision 1.2V threshold to determine the overcurrent
condition as well as each channel having additional
overcurrent trip point at 108µA with 7-cycle delay. This
scheme helps protect from damaging a module(s) in
multi-module mode by not having a single module
carrying more than 108µA. Note that it is not
necessary for the RISHARE to be scaled to trip at the
same level as the 108µA OCP comparator. Typically the
ISHARE pin average current protection level should be
higher than the phase current protection level. For
instance, when Channel 1 operates independently, the
FN6727.1
February 26, 2010
ISL8200M
OC trip set by 1.2V comparator can be lower than
108µA trip point as shown in Equation 6.
V OUT
⎛
⎞
1–D
⎜ I OC + ---------------- • ⎛⎝ ---------------- – T MIN_OFF⎞⎠ ⎟ • RDS
L
2F
⎝
⎠
SW
R ISEN1 = ----------------------------------------------------------------------------------------------------------------------I TRIP
1.2V
R ISHARE = --------------I TRIP
(EQ. 6)
When OCP is triggered, the controller pulls EN low
immediately to turn off UGATE and LGATE.
R ISET = R ISHARE ⋅ N CNTL
where NCNTL is the number of the ISL8200M modules
in parallel or multi-module operations; ITRIP = 108µA;
IOC is the load overcurrent trip point; TMIN_OFF is the
minimum UGATE turn off time that is 350ns; RISHARE
in Equation 7 represents the total equivalent resistance
in ISHARE pin bus of all ICs in multiphase or module
parallel operation.
ISL8200M has a low-side FET with typical rDS(ON) of
9mΩ (VGS = 10V, IDS = 30A).
Note: ISL8200M has integrated 2.2kΩ resistance
(RSEN-IN). Therefore, the equivalent resistance of RSEN
is:
R SEN-EX × R SEN-IN
R SEN = -------------------------------------------------------R SEN-EX + R SEN-IN
In a high input voltage, high output voltage
application, such as 20V input to 5V output, the
inductor ripple becomes excessive due to the fix
internal inductor value. In such application, the output
current will be limited from the rating to approximately
70% of the module’s rated current.
(EQ. 7)
For overload and hard short condition, the overcurrent
protection reduces the regulator RMS output current
much less than full load by putting the controller into
hiccup mode. A delay time, equal to 3 soft-start
intervals, is entered to allow the disturbance to be
cleared out. After the delay time, the controller then
initiates a soft-start interval. If the output voltage
comes up and returns to the regulation, PGOOD
transitions high. If the OC trip is exceeded during the
soft-start interval, the controller pulls EN low again.
The PGOOD signal will remain low and the soft-start
interval will be allowed to expire. Another soft-start
interval will be initiated after the delay interval. If an
overcurrent trip occurs again, this same cycle repeats
until the fault is removed.
Oscillator
The OC trip point varies in a system mainly due to the
MOSFET rDS(ON) variations (over process, current and
temperature). To avoid overcurrent tripping in the normal
operating load range, find the RSEN resistor from
Equation 8 of IPEAK with:
1. The maximum rDS(ON) at the highest junction
temperature
2. The minimum ISOURCE from the “Electrical
Specifications” table on page 9.
3. Determine IOC for:
( ΔI L )
I OC > I OUT ( MAX ) + ------------2
(EQ. 8)
where ΔIL is the output inductor ripple current.
The relationships between the external RSEN-EX values
and the typical output current IOUT(MAX) OCP levels for
ISL8200M are as follows:
TABLE 2.
RSEN-EX
(Ω)
OCP (A) @
VIN = 12V
OPEN
17
50kΩ
15.5
20kΩ
14.5
10kΩ
14
5kΩ
12.5
3kΩ
11
2kΩ
8
17
The Oscillator is a sawtooth waveform, providing for
leading edge modulation with 350ns minimum dead
time. The oscillator (Sawtooth) waveform has a DC
offset of 1.0V. Each channel’s peak-to-peak of the
ramp amplitude is set to proportional the voltage
applied to its corresponding FF pin.
Frequency Synchronization and Phase Lock
Loop
The FSYNC_IN pin has two primary capabilities: fixed
frequency operation and synchronized frequency
operation. By tying a resistor (RFS) to PGND1 from the
FSYNC_IN pin, the switching frequency can be set at
any frequency between 700kHz and 1.5MHz. ISL8200M
has integrated 59kΩ resistor between FSYNC_IN and
PGND1, which set the default frequency to 700kHz.
The frequency setting curve shown in Figure 27 is
provided to assist in selecting the an externally
connected resistor RFS-ext between FSYNC_IN and
PGND1 to increase the switching frequency.
FN6727.1
February 26, 2010
SWITCHING FREQUENCY (kHz)
ISL8200M
Layout Guide
1500
To achieve stable operation, low losses, and good
thermal performance some layout considerations are
necessary.
1400
1300
1200
• The ground connection between PGND1 (pin 15) and
PGND (pin 18) should be a solid ground plane under
the module.
1100
1000
900
800
700
0
100
200
300
400
RFS-ext (kΩ)
FIGURE 27. RFS-ext vs SWITCHING FREQUENCY
By connecting the FSYNC_IN pin to an external square
pulse waveform (such as the CLKOUT signal, typically
50% duty cycle from another ISL8200M), the
ISL8200M will synchronize its switching frequency to
the fundamental frequency of the input waveform. The
maximum voltage to the FSYNC_IN pin is VCC + 0.3V.
The Frequency Synchronization feature will
synchronize the leading edge of the CLKOUT signal
with the falling edge of Channel 1’s PWM clock signal.
CLKOUT is not available until the PLL locks.
The locking time is typically 130µs for FSW = 500kHz.
EN is not released for a soft-start cycle until FSYNC is
stabilized and the PLL is in locking. It is recommended
to connect all EN pins together in multiphase
configuration.
The loss of a synchronization signal for 13 clock cycles
causes the IC to be disabled until the PLL returns
locking, at which point a soft-start cycle is initiated and
normal operation resumes. Holding FSYNC_IN low will
disable the IC.
Setting Relative Phase-Shift on CLKOUT
Depending upon the voltage level at PH_CNTRL, set by
the VCC resistor divider output, the ISL8200M operates
with CLKOUT phase shifted, as shown in Table 3. The
phase shift is latched as VCC raises above POR so it
cannot be changed on the fly.
TABLE 3.
• Place a high frequency ceramic capacitor between
(1) PVIN and PGND (pin 18) and (2) a 10µF between
PVCC and PGND1 (pin 15) as close to the module as
possible to minimize high frequency noise. High
frequency ceramic capacitors close to the module
between VOUT and PGND will help to minimize noise
at the output ripple.
• Use large copper areas for power path (PVIN, PGND,
VOUT) to minimize conduction loss and thermal
stress. Also, use multiple vias to connect the power
planes in different layers.
• Keep the trace connection to the feedback resistor
short.
• Use remote sensed traces to the regulation point to
achieve a tight output voltage regulation, and keep
them in parallel. Route a trace from VSEN_REM- to a
location near the load ground, and a trace from
feedback resistor to the point-of-load where the tight
output voltage is desire.
• Avoid routing any sensitive signal traces, such as the
VOUT and VSENREM- sensing point near the PHASE
pin.
• FSYNC_IN is a sensitive pin. If it not use for
receiving external synchronization signal, then keep
the trace connecting to the pin short. A bypass
capacitor value 100pF connecting between
FSYNC_IN pin and GND1 can help to bypass the
noise sensitivity on the pin.
To
Load GND
To
VOUT
RFBT
CEN
DECODING
PH_CNTRL RANGE
PHASE for CLKOUT
WRT CHANNEL 1
REQUIRED
PH_CNTRL
<29% of VCC
-60°
15% VCC
29% to 45% of VCC
90°
37% VCC
45% to 62% of VCC
120°
53% VCC
62% to VCC
180°
VCC
CPVCC
PVIN
CIN
COUT
PGND
VOUT
FIGURE 28. RECOMMENDED LAYOUT
18
FN6727.1
February 26, 2010
ISL8200M
3.5
MAX LOAD CURRENT (A)
12
3.0
LOSS (W)
2.5
3.3V
2.0
1.5V
1.5
0.8V
1.0
0.5
0.0
0
2
6
4
8
10
10
8
3.3V
1.5V
6
0.8V
4
2
0
60
FIGURE 29. POWER LOSS vs LOAD CURRENT (5VIN)
90
100
110
12
MAX LOAD CURRENT (A)
4.5
5.0V
4.0
LOSS (W)
80
FIGURE 30. DERATING CURVE (5VIN)
5.0
3.5
3.3V
3.0
2.5
0.8V
2.0
1.5V
2.5V
1.5
1.0
0.5
0.0
70
AMBIENT TEMPERATURE (°C)
LOAD CURRENT (A)
0
2
4
6
8
10
LOAD CURRENT (A)
FIGURE 31. POWER LOSS vs LOAD CURRENT (12VIN)
Thermal Considerations
Experimental power loss curves along with θJA from
thermal modeling analysis can be used to evaluate the
thermal consideration for the module. The derating
curves are derived from the maximum power allowed
while maintaining the temperature below the maximum
junction temperature of +125°C. In actual application,
other heat sources and design margin should be
considered.
Package Description
The structure of ISL8200M belongs to the Quad Flatpack No-lead package (QFN). This kind of package has
advantages, such as good thermal and electrical
conductivity, low weight and small size. The QFN
package is applicable for surface mounting technology
and is being more readily used in the industry. The
ISL8200M contains several types of devices, including
resistors, capacitors, inductors and control ICs. The
ISL8200M is a copper lead-frame based package with
exposed copper thermal pads, which have good
electrical and thermal conductivity. The copper lead
frame and multi component assembly is overmolded
with polymer mold compound to protect these devices.
19
10
8
5.0V
3.3V
6
2.5V
1.5V
0.8V
4
2
0
60
70
80
90
100
110
AMBIENT TEMPERATURE (°C)
FIGURE 32. DERATING CURVE (12VIN)
The package outline and typical PCB layout pattern
design and typical stencil pattern design are shown in the
package outline drawing L23.15x15 on page 22. The
module has a small size of 15mm x 15mm x 2.2mm.
Figure 33 shows typical reflow profile parameters. These
guidelines are general design rules. Users could modify
parameters according to their application.
PCB Layout Pattern Design
The bottom of ISL8200M is a lead-frame footprint, which
is attached to the PCB by surface mounting process. The
PCB layout pattern is shown in the Package Outline
Drawing L23.15x15 on page 22. The PCB layout pattern
is essentially 1:1 with the QFN exposed pad and I/O
termination dimensions, except for the PCB lands being a
slightly extended distance of 0.2mm (0.4mm max)
longer than the QFN terminations, which allows for solder
filleting around the periphery of the package. This
ensures a more complete and inspectable solder joint.
The thermal lands on the PCB layout should match 1:1
with the package exposed die pads.
FN6727.1
February 26, 2010
ISL8200M
Thermal Vias
Reflow Parameters
A grid of 1.0mm to 1.2mm pitch thermal vias, which
drops down and connects to buried copper plane(s),
should be placed under the thermal land. The vias should
be about 0.3mm to 0.33mm in diameter with the barrel
plated to about 1.0 ounce copper. Although adding more
vias (by decreasing via pitch) will improve the thermal
performance, diminishing returns will be seen as more
and more vias are added. Simply use as many vias as
practical for the thermal land size and your board design
rules allow.
Due to the low mount height of the QFN, "No Clean" Type 3
solder paste per ANSI/J-STD-00 is recommended. Nitrogen
purge is also recommended during reflow. A system board
reflow profile depends on the thermal mass of the entire
populated board, so it is not practical to define a specific
soldering profile just for the QFN. The profile given in
Figure 33 is provided as a guideline, to be customized for
varying manufacturing practices and applications.
300
PEAK TEMPERATURE +230°C~+245°C;
KEEP ABOUT 30s ABOVE +220°C
Stencil Pattern Design
20
250
TEMPERATURE (°C)
Reflowed solder joints on the perimeter I/O lands should
have about a 50µm to 75µm (2mil to 3mil) standoff
height. The solder paste stencil design is the first step in
developing optimized, reliable solder joins. Stencil
aperture size to land size ratio should typically be 1:1. The
aperture width may be reduced slightly to help prevent
solder bridging between adjacent I/O lands. To reduce
solder paste volume on the larger thermal lands, it is
recommended that an array of smaller apertures be used
instead of one large aperture. It is recommended that the
stencil printing area cover 50% to 80% of the PCB layout
pattern. A typical solder stencil pattern is shown in the
Package Outline Drawing L23.15x15 on page 22. The gap
width between pad to pad is 0.6mm. The user should
consider the symmetry of the whole stencil pattern when
designing its pads. A laser cut, stainless steel stencil with
electropolished trapezoidal walls is recommended.
Electropolishing “smooths” the aperture walls resulting in
reduced surface friction and better paste release which
reduces voids. Using a trapezoidal section aperture (TSA)
also promotes paste release and forms a "brick like" paste
deposit that assists in firm component placement. A
0.1mm to 0.15mm stencil thickness is recommended for
this large pitch (1.3mm) QFN.
200
150
SLOW RAMP AND
SOAK FROM +100°C TO
+180°C FOR 90s~120s
100
RAMP RATE ≤1.5°C FROM +70°C TO +90°C
50
0
0
100
150
200
250
50
300
DURATION (s)
FIGURE 33. TYPICAL REFLOW PROFILE
FN6727.1
February 26, 2010
ISL8200M
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
2/26/10
FN6727.1
Updated page 1 title, description and features to better highlight the part’s ease-of-use. Added
Related Literature section. Replaced Figures 1, 3, 4, 5. Added Theta Jc and associated note.
Added 1st paragraph under Table 1. Changed instances of VMON to VMON1 throughout.
Removed VMON2 reference in test conditions for disable threshold. Changed ROS to ROS1 in
paragraph above Table 1 on page 13. Replaced last paragraph under “Programming the Output
Voltage (RSET)” on page 13. Added Equations 2 and 3 and related text.
12/22/09
FN6727.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL8200M
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
21
FN6727.1
February 26, 2010
Package Outline Drawing
L23.15x15
23 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN)
Rev 1, 12/09
A
3.22
18x 1.3 ±0.1
X4
3x 2.6
22
2.2
0.2 H AB
1.02
23 22 21 20
20 21 22
0.05 M H AB
1
2
3
4
5
3.4
9.9
18
15.0±0.2
13.8
4.7
4.26
2.36
1.34
18
0.8
2.28
3.4
4.38
X4
12 13 14 15
16
0.2 H AB
17
15.0±0.2
16
17
0.82
4.8
35x 0.40±0.2
15
11x 0.7
0.90
14 13 12
2.0
5.82
TOP VIEW
18x 0.75
3
4
B
5
6
7
8
10x 1.1 ±0.1
9
10
11
11x 1.85 ±0.05
7x 0.8
BOTTOM VIEW
8° ALL AROUND
2.2 ±0.2
NOTES:
S 0.2
0.25
S 0.05
S
FN6727.1
February 26, 2010
SIDE VIEW
1.
Dimensions are in millimeters.
2.
Unless otherwise specified, tolerance : Decimal ± 0.2;
Body Tolerance ±0.2mm
3.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
ISL8200M
6
7
8
9
10
11
1
2
4.7
19
35x 0.5
19
7x 1.9 ±0.05
23
5.18
4.73
4.68
4.03
4.08
3.63
8.15
3.58
2.93
6.88
2.98
5.58
2.48
22
1
0.00
0.00
3.02
4.13
2.13
2.83
3.43
0.83
1.53
1.07
0.00
1.77
2.37
3.07
1.47
3.52
1.92
4.64
6.11
5.67
4.97
4.37
3.67
3.07
2.37
1.77
1.07
0.60
6.48
6.88
8.14
5.53
5.03
2.08
1.58
0.78
0.18
1.82
0.65
0.00
2.32
3.12
3.62
4.88
5.68
4.12
4.72
5.22
5.82
6.07
0.00
4.07
4.77
5.17
5.87
6.02
STENCIL PATTERN WITH SQUARE PADS-1
TYPICAL RECOMMENDED LAND PATTERN
6.73
6.23
4.18
4.68
4.38
3.88
1.83
2.33
1.53
1.53
0.00
0.52
0.82
2.87
3.17
4.69
4.99
6.52
0.00
0.52
0.82
2.82
3.67
5.50
5.80
6.52
6.48
4.58
4.28
2.23
1.48
0.88
0.13
0.00
0.60
FN6727.1
February 26, 2010
STENCIL PATTERN WITH SQUARE PADS-2
ISL8200M
3.02
3.62
4.13
6.03
6.73
6.78
8.09
8.15
3.67
3.43
5.62
2.97
2.92
3.62
4.22
4.92
5.52
6.82
8.10
2.52
2.83
2.57
2.13
1.87
1.48
1.47
4.42
3.67
0.32
0.77
0.88
0.37
0.77
0.78
0.28
0.13
0.00
1.68
0.00
0.33
4.92
4.37
1.38
2.18
0.93
2.75
3.05
4.03
4.83
23
8.10
6.48
5.48
4.88
4.18
3.58
2.88
2.28
1.58
0.98
0.28
0.00
0.32
1.02
1.62
2.32
1.88
1.43
0.73
6.06
5.72
4.97
5.78
5.13
2.53
1.83
5.72
6.03
8.14
6.88
4.68
4.18
0.78
1.02
0.00
1.82
2.32
3.12
3.62
4.42
4.92
5.83
5.72
5.98