NB6N239S 3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider http://onsemi.com Description The NB6N239S is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16. Both divider circuits drive LVDS compatible outputs. (More device information on page 7). The NB6N239S is a member of the ECLinPS MAX™ family of high performance clock products. Features • • • • • • • • • • • • • • Maximum Clock Input Frequency, 3.0 GHz (1.5 GHz with B1) Input Compatibility with LVDS/LVPECL/CML/HSTL Rise/Fall Time 120 ps Typical < 5 ps Typical Within Device Output Skew Example; 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz Outputs Internal 50 W Termination Provided Random Clock Jitter < 2 ps RMS QA B1 Edge Aligned to QB Bn Edge Operating Range: VCC = 3.0 V to 3.465 V with GND = 0 V Master Reset for Synchronization of Multiple Chips VBBAC Reference Output Synchronous Output Enable/Disable TIA/EIA − 644 Compliant Pb−Free Packages are Available MARKING DIAGRAM* 16 1 1 Bottom View QFN−16 MN SUFFIX CASE 485G A L Y W G NB6N 239S ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. SELA0 SELA1 B1 B2 A B4 CLK VT CLK 50 W B8 50 W QA QA R VBBAC B2 B4 B B8 B16 EN QB QB SELB0 SELB1 + MR Figure 1. Simplified Logic Diagram © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 3 1 Publication Order Number: NB6N239S/D NB6N239S MR 16 SELA0 SELA1 VCC 15 14 13 12 QA 11 QA 3 10 QB 4 9 QB VT 1 CLK 2 CLK VBBAC NB6N239S 5 EN 6 7 8 SELB0 SELB1 GND Exposed Pad (EP) Figure 2. Pinout: QFN−16 (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 VT 2 CLK LVDS, LVPECL, CML, HSTL Input Noninverted Differential CLOCK Input. 3 CLK LVDS, LVPECL, CML, HSTL Input Inverted Differential CLOCK Input. 4 VBBAC 5 EN* LVCMOS/LVTTL Input Synchronous Output Enable 6 SELB0* LVCMOS/LVTTL Input Clock Divide Select Pin 7 SELB1* LVCMOS/LVTTL Input Clock Divide Select Pin 8 GND Power Supply Negative Supply Voltage 9 QB LVDS Output Inverted Differential Output. Typically terminated with 100 W across differential outputs. 10 QB LVDS Output Noninverted Differential Output. Typically terminated with 100 W across differential outputs. 11 QA LVDS Output Inverted Differential Output. Typically terminated with 100 W across differential outputs. 12 QA LVDS Output Noninverted Differential Output. Typically terminated with 100 W across differential outputs. 13 VCC Power Supply Positive Supply Voltage. 14 SELA1* LVCMOS/LVTTL Input Clock Divide Select Pin 15 SELA0* LVCMOS/LVTTL Input Clock Divide Select Pin 16 MR** LVCMOS/LVTTL Input Master Reset Asynchronous, Default Open High, Asserted LOW EP Power Supply (OPT) Internal 100 W Center−Tapped Termination Pin for CLK and CLK. Output Voltage Reference for Capacitor Coupled Inputs, only. The Exposed Pad on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GND on the PC board. *Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN. http://onsemi.com 2 NB6N239S + SELA0 VCC SELA1 A CLK VT CLK B1 B2 B4 50 W R B8 QA QA 50 W R B2 B EN B4 B8 QB QB B16 SELB0 SELB1 GND + MR VBBAC Figure 3. Logic Diagram Table 2. FUNCTION TABLE CLK EN* MR** X L H X H H L FUNCTION Divide Hold Q Reset Q Table 3. CLOCK DIVIDE SELECT, QA OUTPUTS SELA1* SELA0* L L H H L H L H QA Outputs Divide by 1 Divide by 2 Divide by 4 Divide by 8 Table 4. CLOCK DIVIDE SELECT, QB OUTPUTS SELB1* SELB0* L L H H L H L H QB Outputs Divide by 2 Divide by 4 Divide by 8 Divide by 16 = Low−to−High Transition = High−to−Low Transition X = Don’t Care *Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN. http://onsemi.com 3 NB6N239S Table 5. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection 75 kW 75 kW Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) QFN−16 Flammability Rating Oxygen Index: 28 to 34 > 1500 V > 100 V > 1000 V Pb Pkg Pb−Free Pkg Level 1 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 370 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Table 6. MAXIMUM RATINGS Symbol Parameter VCC Positive Mode Power Supply VI Input Voltage ISC Output Short Circuit Current TIA/EIA − 644 Compliant Condition 1 Condition 2 GND = 0 V GND = 0 V Line−to−Line Line−to−GND GND v VI v VCC Rating Unit 3.6 V 3.6 V 12 24 mA mA ± 0.5 mA −40 to +85 °C IBBAC VBBAC Sink/Source Current TA Operating Temperature Range Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 41.6 35.2 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 4.0 °C/W Tsol Wave Solder 265 265 °C Pb Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 4 NB6N239S Table 7. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS (VCC = 3.0 V to 3.465 V, GND = 0 V) −405C Symbol Characteristic Min Typ 255C Max 85°C Min Typ Max 35 45 55 Min Typ Max Unit ICC Power Supply Current (Inputs and Outputs OPEN) VOH Output HIGH Voltage (Notes 2) VOL Output LOW Voltage (Notes 2) 900 VOD Differential Output Voltage (Figure 21) 250 450 250 450 250 450 mV DVOD VOD Magnitude Change 0 50 0 50 0 50 mV VOS Offset Voltage (Figure 21) 1125 1375 1125 1375 1125 1375 mV DVOS VOS Magnitude Change 0 50 0 50 0 50 mV 1600 mA 1600 900 1600 900 mV mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 7, 10) Vth Input Threshold Reference Voltage (Note 3) 100 VCC − 100 100 VCC − 100 100 VCC − 100 mV VIH Single−ended Input HIGH Voltage Vth + 100 VCC Vth + 100 VCC Vth + 100 VCC mV VIL Single−ended Input LOW Voltage GND Vth − 100 GND Vth − 100 GND Vth − 100 mV VBBAC Output Voltage Reference @ 100 mA (Note 6) VCC = 3.3 V VCC−1460 VCC− 1330 VCC−1200 VCC−1460 VCC− 1340 VCC−1200 VCC−1460 VCC− 1350 VCC−1200 mV 1840 1970 2100 1840 1960 2100 1840 1950 2100 DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY (Figures 8, 9, 11) (Note 5) VIHD Differential Input HIGH Voltage 100 VCC 100 VCC 100 VCC mV VILD Differential Input LOW Voltage GND VCC – 100 GND VCC – 100 GND VCC – 100 mV VCMR Input Common Mode Range (Differential Cross−point Voltage) (Note 4) 50 VCC – 50 50 VCC – 50 50 VCC – 50 mV VID Differential Input Voltage (VIHD(CLK) − VILD(CLK)) and (VIHD(CLK) − VILD(CLK)) 100 VCC − GND 100 VCC − GND 100 VCC − GND mV RTIN Internal Input Termination Resistor 45 55 45 55 45 55 W 50 50 50 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Outputs loaded with 100 W across LVDS outputs. 3. Vth is applied to the complementary input when operating in single−ended mode. 4. VCMRMIN varies 1:1 with GND, VCMRMAX varies 1:1 with VCC. 5. Input and output voltage swing is a single−ended measurement operating in differential mode. 6. VBBAC used to rebias capacitor−coupled inputs only (see Figures 16 and 17). http://onsemi.com 5 NB6N239S Table 8. DC CHARACTERISTICS, LVTTL/LVCMOS INPUTS (VCC = 3.0 V to 3.465 V, GND = 0 V, TA = −40°C to +85°C) Symbol Max Unit VIH Input HIGH Voltage (LVCMOS/LVTTL) Characteristic Min 2.0 Typ VCC V VIL Input LOW Voltage (LVCMOS/LVTTL) GND 0.8 V IIH Input HIGH Current −150 150 mA IIL Input LOW Current −150 150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 9. AC CHARACTERISTICS VCC = 3.0 V to 3.465 V; GND = 0 V (Note 7) −40°C Min Characteristic Symbol finMAX Maximum Input CLOCK Frequency QA/QB = (B2, B4, B8, B16) QA = (B1) 3.0 1.5 VOUTPP Output Voltage Amplitude (Notes 9, 10) QA(B2, 4, 8), QB(Bn) fin v 3.0 GHz QA(B1), QB(Bn) fin v 1.5 GHz 200 200 tPLH, tPHL Propagation Delay to Output Differential @ 50 MHz 550 420 tRR Reset Recovery ts Setup Time @ 50 MHz th Hold Time @ 50 MHz tskew Within−Device Skew @ 50 MHz Device−to−Device Skew Duty Cycle Skew tPW Minimum Pulse Width tJITTER RMS Random Clock Jitter VINPP Input Voltage Swing (Differential Configuration) (Note 9) 100 tr tf Output Rise/Fall Times @ 50 MHz (20% − 80%) 70 CLK, Qn MR, Qn Typ 25°C Max Min Typ 85°C Max 3.0 1.5 350 350 450 450 200 200 780 660 550 420 Min Typ Max 3.0 1.5 350 350 450 450 200 200 780 660 550 420 Unit GHz 350 350 450 450 780 660 mV ps 0 −90 0 −90 0 −90 ps EN, CLK SELA/B, CLK 0 0 −60 −300 0 0 −60 −300 0 0 −60 −300 ps CLK, EN CLK, SELA/B 150 700 65 200 150 700 65 200 150 700 65 200 ps (Note 8) (Note 8) (Note 8) MR 5 25 25 30 80 40 550 5 30 30 550 120 6 30 30 100 190 70 120 VCC −GND 100 190 70 ps ps 2 VCC −GND 35 90 45 550 2 Qn, Qn 30 90 45 120 2 ps VCC −GND mV 190 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Measured using a 750 mV, 50% duty cycle clock source. All loading with 100 W across LVDS outputs. 8. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 9. Input and output voltage swing is a single−ended measurement operating in differential mode. 10. Output Voltage Amplitude (VOHCLK − VOLCLK) at input CLOCK frequency, fin. The output frequency, fout, is the input CLOCK frequency divided by n, fout = fin B n. Input CLOCK frequency is v3.0 GHz. http://onsemi.com 6 NB6N239S Application Information single−ended input capacitor−coupled CLOCK signals. For The NB6N239S is a high−speed, low skew clock divider the capacitor−coupled CLK and/or CLK inputs, VBBAC with two divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16. Both divider should be connected to the VT pin and bypassed to ground circuits drive differential LVDS compatible outputs. The with a 0.01 mF capacitor. Inputs CLK and CLK must be internal dividers are synchronous to each other. Therefore, signal driven or auto oscillation may result. the common output edges are precisely aligned. The common enable (EN) is synchronous so that the The NB6N239S clock inputs can be driven by a variety of internal divider flip−flops will only be enabled/disabled differential signal level technologies including LVDS, when the internal clock is in the LOW state. This avoids any LVPECL, HSTL, or CML. The differential clock input chance of generating a runt pulse on the internal clock when buffer employs a pair of internal 50 W termination resistors the device is enabled/disabled, as can happen with an asynchronous control. The internal enable flip−flop is in a 100 W center−tapped configuration and accessible via clocked on the falling edge of the input clock. Therefore, all the VT pin. This feature provides transmission line associated specification limits are referenced to the negative termination on−chip, at the receiver end, eliminating edge of the clock input. external components. The VBBAC reference output is recommended to be used to rebias differential or MR CLK Q (÷1) Q (÷2) Q (÷4) Q (÷8) Q (÷16) Figure 4. Timing Diagram CLK tRR tRR MR Q (÷n) NOTE: On the rising edge of MR, Q goes HIGH after the first rising edge of CLK. Figure 5. Master Reset Timing Diagram http://onsemi.com 7 NB6N239S Internal Clock Disabled Internal Clock Enabled CLK Q (÷n) EN Figure 6. Output Enable Timing Diagrams The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal divider flip−flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edge of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase relationships. CLK VIH CLK Vth VIL Vth CLK CLK Figure 8. Differential Inputs Driven Differentially Figure 7. Differential Input Driven Single−Ended CLK CLK VID = |VIHD(CLK) − VILD(CLK)| VIHD VILD Figure 9. Differential Inputs Driven Differentially VCC Vthmax VIHmax CLK VILmax GND VIHDmax VILDmax VCMR Vth Vthmin VCC VCMmax VIHmin CLK VCMmin VILmin GND Figure 10. Vth Diagram VIHDmin VILDmin Figure 11. VCMR Diagram http://onsemi.com 8 NB6N239S VCC = 3.3 V VCC = 3.3 V Zo = 50 W LVPECL Driver VT = VCC − 2.0 V VCC = 3.3 V NB6N239S CLK Zo = 50 W GND 50 W LVDS Driver 50 W Zo = 50 W GND Figure 13. LVDS Interface VCC = 3.3 V VCC = 3.3 V NB6N239S CLK VCC = 3.3 V Zo = 50 W 50 W CML Driver 50 W GND 50 W GND Figure 15. Standard 50 W Load HSTL Interface VCC = 3.3 V VCC = 3.3 V VCC = 3.3 V NB6N239S CLK Zo = 50 W 50 W Differential Driver VEE NB6N239S CLK 50 W Single−Ended Driver VT = VBBAC* 50 W Zo = 50 W CLK GND Figure 14. Standard 50 W Load CML Interface Zo = 50 W VT = GND Zo = 50 W CLK GND VCC = 3.3 V NB6N239S CLK 50 W HSTL Driver VT = VCC Zo = 50 W CLK GND Figure 12. LVPECL Interface Zo = 50 W VT = OPEN CLK GND VCC = 3.3 V NB6N239S CLK 50 W 50 W Zo = 50 W VCC = 3.3 V CLK VT = VBBAC* 50 W CLK VEE VEE Figure 16. Capacitor−Coupled Differential Interface (VT Connected to VBBAC) VEE Figure 17. Capacitor−Coupled Single−Ended Interface (VT Connected to VBBAC) *VBBAC bypassed to ground with a 0.01 mF capacitor. http://onsemi.com 9 VOUTPP, OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) NB6N239S 400 300 200 100 0 0 0.5 1.0 1.5 fout, CLOCK OUTPUT FREQUENCY (GHz) Figure 18. Output Voltage Amplitude (VOUTPP) versus Output Clock Frequency at 255C (Typical) fout (QA/QB) = fin B n; For n = 2, 4, 8, 16; fin v 3.0 GHz For n = 1; fin v 1.5 GHz CLK VINPP = VIH(CLK) − VIL(CLK) CLK Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 19. AC Reference Measurement NB6N239S LVDS Driver Device Q Zo = 50 W D 100 W Q Zo = 50 W LVDS Receiver Device D Figure 20. Typical LVDS Termination for Output Driver and Device Evaluation, If Receiver Has On−chip Termination, 100 W Resistor is Not Needed QN VOH VOS VOD VOL QN Figure 21. LVDS Output http://onsemi.com 10 NB6N239S ORDERING INFORMATION Package Shipping† NB6N239SMN QFN−16, 3 x 3 mm 123 Units / Rail NB6N239SMNG QFN−16, 3 x 3 mm (Pb−Free) 123 Units / Rail NB6N239SMNR2 QFN−16, 3 x 3 mm 3000 / Tape & Reel NB6N239SMNR2G QFN−16, 3 x 3 mm (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 11 NB6N239S PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE C D PIN 1 LOCATION ÇÇÇ ÇÇÇ 0.15 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG A B E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.15 C (A3) 0.10 C A 0.08 C 16 X SIDE VIEW SEATING PLANE A1 16X L 5 NOTE 5 0.575 0.022 e E2 12 1 16 1.50 0.059 3.25 0.128 e 13 b 0.10 C A B 0.05 C EXPOSED PAD 9 K 16X 3.25 0.128 0.30 0.012 EXPOSED PAD 8 4 16X SOLDERING FOOTPRINT* C D2 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.50 0.02 BOTTOM VIEW NOTE 3 0.30 0.012 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS and ECLinPS MAX are trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 12 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB6N239S/D