Revised January 1999 CD4016BC Quad Bilateral Switch General Description The CD4016BC is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with CD4066BC. Features ■ Extremely high control input impedance: 1012Ω (typ.) ■ Low crosstalk between switches: −50 dB (typ.) @ fIS = 0.9 MHz, RL = 1 kΩ ■ Frequency response, switch “ON”: 40 MHz (typ.) ■ Wide supply voltage range: 3V to 15V ■ Wide range of digital and analog switching: ±7.5 VPEAK Applications ■ “ON” resistance for 15V operation: 400Ω (typ.) • Analog signal switching/multiplexing ■ Matched “ON” resistance over 15V signal input: ∆RON = 10Ω (typ.) Signal gating ■ High degree of linearity: Chopper 0.4% distortion (typ.) Squelch control Modulator/Demodulator @ fIS = 1 kHz, VIS = 5 Vp-p, Commutating switch VDD−VSS = 10V, RL = 10 kΩ • Digital signal switching/multiplexing ■ Extremely low “OFF” switch leakage: • CMOS logic implementation 0.1 nA (typ.) • Analog-to-digital/digital-to-analog conversion @ VDD − VSS = 10V • Digital control of frequency, impedance, phase, and analog-signal gain TA = 25°C Ordering Code: Order Number Package Number Package Description CD4016BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4016BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code. Connection Diagram Schematic Diagram Pin Assignments for DIP and SOIC © 1999 Fairchild Semiconductor Corporation DS005661.prf www.fairchildsemi.com CD4016BC Quad Bilateral Switch November 1983 CD4016BC Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) (Note 2) −0.5V to +18V VDD Supply Voltage VIN Input Voltage TS Storage Temperature Range −0.5V to VDD + 0.5V −65°C to + 150°C VDD Supply Voltage 3V to 15V VIN Input Voltage 0V to VDD −40°C to +85°C TA Operating Temperature Range Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. Lead Temperature (Soldering, 10 seconds) 260°C Note 2: VSS = 0V unless otherwise specified. DC Electrical Characteristics (Note 2) Symbol IDD Parameter −40°C Conditions Min Max +85°C 25°C Min Typ Max Min Max Units Quiescent Device VDD = 5V, VIN = VDD or VSS 1.0 0.01 1.0 7.5 µA Current VDD = 10V, VIN = VDD or VSS 2.0 0.01 2.0 15 µA VDD = 15V, VIN = VDD or VSS 4.0 0.01 4.0 30 µA VDD = 10V 610 275 660 840 Ω VDD = 15V 370 200 400 520 Ω Signal Inputs and Outputs RON “ON” Resistance RL = 10kΩ to (VDD − V SS)/2 VC = VDD, VIS = VSS or VDD RL = 10kΩ to (VDD − V SS)/2 VC = VDD ∆RON IIS VDD = 10V, VIS = 4.75 to 5.25V 1900 850 2000 2380 Ω VDD = 15V, VIS = 7.25 to 7.75V 790 400 850 1080 Ω ∆“ON” Resistance RL = 10kΩ to (VDD − V SS)/2 Between any 2 of VC = VDD, VIS = VSS to VDD 4 Switches VDD = 10V 15 (In Same Package) VDD = 15V 10 Input or Output VC = 0, VDD = 15V Leakage VIS = 0V or 15V, Switch “OFF” VOS = 15V or 0V ±50 ±0.1 Ω Ω ±50 ±200 nA Control Inputs VILC LOW Level Input VIS = VSS and VDD Voltage VOS = VDD and VSS IIS = ±10 µA VIHC VDD = 5V 0.9 0.7 0.4 V VDD = 10V 0.9 0.7 0.4 V VDD = 15V 0.9 0.7 0.4 V HIGH Level Input VDD = 5V 3.5 3.5 3.5 V Voltage VDD = 10V 7.0 7.0 7.0 V VDD = 15V 11.0 11.0 11.0 V (Note 3) and Figure 8 IIN Input Current VCC − VSS = 15V ±0.3 ±10−5 ±0.3 ±1.0 µA VDD ≥ VIS ≥ VSS VDD ≥ VC ≥ VSS Note 3: If the switch input is held at VDD, VIHC is the control input level that will cause the switch output to meet the standard “B” series VOH and IOH output levels. If the analog switch input is connected to VSS, VIHC is the control input level — which allows the switch to sink standard “B” series |IOH|, high level current, and still maintain a VOL ≤ “B” series. These currents are shown in Figure 8. www.fairchildsemi.com 2 (Note 4) TA = 25°C, tr = tf = 20 ns and VSS = 0V unless otherwise specified Symbol tPHL, tPLH tPZH, tPZL tPHZ, tPLZ Parameter Conditions Typ Max VDD = 5V 58 100 ns VDD= 10V 27 50 ns VDD = 15V 20 40 ns Propagation Delay Time VC = VDD, CL = 50 pF, (Figure 1) Signal Input to Signal Output RL = 200k Min Units Propagation Delay Time RL = 1.0 kΩ, CL = 50 pF, (Figure 2, Figure 3) Control Input to Signal VDD = 5V 20 50 ns Output HIGH Impedance to VDD = 10V 18 40 ns Logical Level VDD = 15V 17 35 ns Propagation Delay Time RL = 1.0 kΩ, CL = 50 pF, (Figure 2, Figure 3) Control Input to Signal VDD = 5V 15 40 ns Output Logical Level to VDD = 10V 11 25 ns HIGH Impedance VDD = 15V 10 22 ns Sine Wave Distortion VC = VDD = 5V, VSS = −5 0.4 % 40 MHz 1.25 MHz 0.9 MHz 150 mVP-P VDD = 5V 6.5 MHz VDD = 10V 8.0 MHz VDD = 15V 9.0 MHz RL = 10 kΩ, VIS = 5 VP-P, f = 1 kHz, (Figure 4) Frequency Response — Switch VC = VDD = 5V, VSS = −5V, “ON” (Frequency at −3 dB) RL = 1 kΩ, VIS = 5 VP-P, 20 Log10 V OS/VOS (1 kHz) −dB, (Figure 4) Feedthrough — Switch “OFF” VDD = 5V, VC = VSS = −5V, (Frequency at −50 dB) RL = 1 kΩ, VIS = 5 VP-P, 20 Log10 (VOS/VIS) = −50 dB, (Figure 4) Crosstalk Between Any Two VDD = VC(A) = 5V; VSS = VC(B) = −5V, Switches (Frequency at −50 dB) RL = 1 kΩVIS(A) = 5 VP-P, 20 Log10 (VOS(B)/VOS(A) ) = −50 dB, (Figure 5) Crosstalk; Control Input to VDD = 10V, RL = 10 kΩ Signal Output RIN = 1 kΩ, VCC = 10V Square Wave, CL = 50 pF (Figure 6) Maximum Control Input RL = 1 kΩ, CL = 50 pF, (Figure 7) VOS(f) = ½ VOS(1 kHz) CIS Signal Input Capacitance COS Signal Output Capacitance VDD = 10V CIOS Feedthrough Capacitance VC = 0V CIN Control Input Capacitance 4 pF 4 pF 0.2 5 pF 7.5 pF Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: These devices should not be connected to circuits with the power “ON”. Note 6: In all cases, there is approximately 5 pF of probe and jig capacitance on the output; however, this capacitance is included in CL wherever it is specified. Note 7: VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. VC is the voltage at the control input. 3 www.fairchildsemi.com CD4016BC AC Electrical Characteristics CD4016BC AC Test Circuits and Switching Time Waveforms FIGURE 1. tPLH, tPLH Propagation Delay Time Control to Signal Output FIGURE 2. tPZH, tPHZ Propagation Delay Time Control to Signal Output FIGURE 3. tPZH, tPHZ Propagation Delay Time Control to Signal Output VC = VDD for distortion and frequency response tests VC = VSS for feedthrough test FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough www.fairchildsemi.com 4 CD4016BC AC Test Circuits and Switching Time Waveforms (Continued) FIGURE 5. Crosstalk Between Any Two Switches FIGURE 6. Crosstalk — Control to Input Signal Output FIGURE 7. Maximum Control Input Frequency 5 www.fairchildsemi.com CD4016BC AC Test Circuits and Switching Time Waveforms Temperature Range COMMERCIAL (Continued) Switch Input Switch Output VDD VIS −40°C 25°C +85°C 5 0 0.2 0.16 0.12 5 5 −0.2 −0.16 −0.12 IIS (mA) VOS(V) 10 0 0.5 0.4 0.3 10 10 −0.5 −0.4 −0.3 15 0 1.4 1.2 1.0 15 15 −1.4 −1.2 −1.0 Min 0.4 4.6 0.5 9.5 1.5 13.5 FIGURE 8. CD4016B Switch Test Conditions for VIHC Typical Performance Characteristics ’ON’ Resistance Temperature Variation for VDD − VSS = 10V ’ON’ Resistance vs. Signal Voltage TA = 25°C ’ON’ Resistance Temperature Variation for VDD − VSS = 15V www.fairchildsemi.com 6 Max CD4016BC Typical Applications 4 Input Multiplexer Sample/Hold Amplifier Special Considerations non-linear. It is recommended that at 5V, voltages on the in/ out pins be maintained within about 1V of either VDD or VSS; and that at 3V the voltages on the in/out pins should be at VDD or VSS for reliable operation. The CD4016B is composed of 4, two-transistor analog switches. These switches do not have any linearization or compensation circuitry for “R ON” as do the CD4066B's. Because of this, the special operating considerations for the CD4066B do not apply to the CD4016B, but at low supply voltages, ≤5V, the CD4016B's on resistance becomes 7 www.fairchildsemi.com CD4016BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A www.fairchildsemi.com 8 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. CD4016BC Quad Bilateral Switch Physical Dimensions inches (millimeters) unless otherwise noted (Continued)