LINER LTC1417C Low power 14-bit, 400ksps sampling adc converter with serial i/o Datasheet

LTC1417
Low Power 14-Bit, 400ksps
Sampling ADC Converter
with Serial I/O
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FEATURES
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DESCRIPTIO
The LTC ®1417 is a low power, 400ksps, 14-bit A/D converter. This versatile device can operate from a single 5V or
±5V supplies. An onboard high performance sample-andhold, a precision reference and internal trimming minimize
external circuitry requirements. The low 20mW power
dissipation is made even more attractive with two userselectable power shutdown modes.
16-Pin Narrow SSOP Package (SO-8 Footprint)
Sample Rate: 400ksps
±1.25LSB INL and ±1LSB DNL Max
Power Dissipation: 20mW (Typ)
Single Supply 5V or ±5V Operation
Serial Data Output
No Missing Codes Over Temperature
Power Shutdown: Nap and Sleep
External or Internal Reference
Differential High Impedance Analog Input
Input Range: 0V to 4.096V or ±2.048V
81dB S/(N + D) and – 95dB THD at Nyquist
The LTC1417 converts 0V to 4.096V unipolar inputs when
using a 5V supply and ±2.048V bipolar inputs when using
±5V supplies. DC specs include ±1.25LSB INL, ±1LSB
DNL and no missing codes over temperature. Outstanding
AC performance includes 81dB S/(N + D) and 95dB THD
at a Nyquist input frequency of 200kHz.
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APPLICATIO S
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High Speed Data Acquisition
Digital Signal Processing
Isolated Data Acquisition Systems
Audio and Telecom Processing
Spectrum Instrumentation
, LTC and LT are registered trademarks of Linear Technology Corporation.
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The internal clock is trimmed for 2µs maximum conversion time. A separate convert start input and a data ready
signal (BUSY) ease connections to FIFOs, DSPs and
microprocessors.
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EQUIVALE T BLOCK DIAGRA
A 400kHz, 14-Bit Sampling A/D Converter in a Narrow 16-Lead SSOP Package
5V
Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
10µF
16
VDD
14
LTC1417
REFCOMP
2
4
14-BIT ADC
6
14
SERIAL
PORT
4.096V
7
8
9
EXTCLKIN
SCLK
CLKOUT
DOUT
BUFFER
10µF
VREF
12
S/H
3
8k
2.5V
REFERENCE
TIMING AND
LOGIC
1µF
14
BUSY
12
RD
13
CONVST
11
SHDN
1417 TA01
5
AGND
15
VSS
10
(0V OR – 5V)
DGND
74
68
10
62
8
6
S/(N + D) (dB)
AIN–
1
EFFECTIVE BITS
AIN+
86
80
4
2
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
1417 TA02
1
LTC1417
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PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
Positive Supply Voltage (VDD) .................................. 6V
Negative Supply Voltage (VSS)
Bipolar Operation Only .......................... – 6V to GND
Total Supply Voltage (VDD to VSS)
Bipolar Operation Only ....................................... 12V
Analog Input Voltage (Note 3)
Unipolar Operation .................. – 0.3V to (VDD + 0.3V)
Bipolar Operation............ (VSS – 0.3) to (VDD + 0.3V)
Digital Input Voltage (Note 4)
Unipolar Operation ............................... – 0.3V to 10V
Bipolar Operation.........................(VSS – 0.3V) to 10V
Digital Output Voltage
Unipolar Operation ................... – 0.3 to (VDD + 0.3V)
Bipolar Operation........... (VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1417C .............................................. 0°C to 70°C
LTC1417I ............................................ – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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ABSOLUTE
ORDER
PART NUMBER
TOP VIEW
AIN+
1
16 VDD
AIN–
2
15 VSS
VREF
3
14 BUSY
REFCOMP
4
13 CONVST
AGND
5
12 RD
EXTCLKIN
6
11 SHDN
SCLK
7
10 DGND
CLKOUT
8
9
LTC1417ACGN
LTC1417CGN
LTC1417AIGN
LTC1417IGN
GN PART MARKING
DOUT
1417A
1417
1417AI
1417I
GN PACKAGE
16-LEAD (NARROW) PLASTIC SSOP
TJMAX = 110°C, θJA = 95°C/W
Consult factory for Military grade parts.
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CO VERTER CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Specifications are measured while using the internal reference unless
otherwise noted. (Notes 5, 6)
PARAMETER
CONDITIONS
MIN
LTC1417
TYP MAX
LTC1417A
MIN TYP MAX
UNITS
Resolution
●
14
14
Bits
No Missing Codes
●
13
14
Bits
Integral Linearity Error
(Note 7)
Differential Linearity Error
Transition Noise
●
±0.8
±0.5 ±1.25
LSB
●
±0.7 ±1.5
±0.35
LSB
0.33
0.33
(Note 12)
±2
±1
LSBRMS
Offset Error
External Reference (Note 8)
±5
±20
±2
±10
LSB
Full-Scale Error
Internal Reference
External Reference = 2.5V
±15
±5
±60
±30
±15
±5
±60
±15
LSB
LSB
Full-Scale Tempco
IOUT(REF) = 0, Internal Reference, 0°C ≤ TA ≤ 70°C
IOUT(REF) = 0, Internal Reference, – 40°C ≤ TA ≤ 85°C
IOUT(REF) = 0, External Reference
±15
●
±10
±20
±1
±5
ppm/°C
ppm/°C
ppm/°C
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A ALOG I PUT
The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 9)
4.75V ≤ VDD ≤ 5.25V (Unipolar)
4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 4.75V (Bipolar)
●
●
IIN
Analog Input Leakage Current
CONVST = High
●
2
MIN
TYP
MAX
0 to 4.096
±2.048
UNITS
V
V
±1
µA
LTC1417
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A ALOG I PUT
The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
CIN
Analog Input Capacitance
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
tACQ
Sample-and-Hold Acquisition Time
tAP
Sample-and-Hold Aperture Time
tjitter
Sample-and-Hold Aperture Time Jitter
CMRR
Analog Input Common Mode Rejection Ratio
MIN
TYP
MAX
UNITS
14
3
150
●
pF
pF
500
ns
–1.5
0V < (AIN+ = AIN–) < 4.096V (Unipolar)
– 2.048V < (AIN+ = AIN–) < 2.048V (Bipolar)
ns
5
psRMS
65
65
dB
dB
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DY A IC ACCURACY The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
S/(N + D)
Signal-to-(Noise + Distortion) Ratio
100kHz Input Signal
●
79
81
dB
THD
Total Harmonic Distortion
100kHz Input Signal, First Five Harmonics
●
– 85
– 95
dB
SFDR
Spurious Free Dynamic Range
200kHz Input Signal
– 98
dB
IMD
Intermodulation Distortion
fIN1 = 97.3kHz, fIN2 = 104.6kHz
– 97
Full Power Bandwidth
S/(N + D) ≥ 77dB
Full Linear Bandwidth
TYP
MAX
UNITS
dB
10
MHz
0.8
MHz
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I TER AL REFERE CE CHARACTERISTICS
The ● indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
VREF Output Tempco
IOUT = 0, 0°C ≤ TA ≤ 70°C
IOUT = 0, – 40°C ≤ TA ≤ 85°C
±10
±20
ppm/°C
ppm/°C
VREF Line Regulation
4.75V ≤ VDD ≤ 5.25V
– 5.25V ≤ VSS ≤ – 4.75V
0.05
0.05
LSB/V
LSB/V
VREF Output Resistance
0.1mA ≤ |IOUT| ≤ 0.1mA
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MIN
TYP
MAX
UNITS
2.480
2.500
2.520
V
kΩ
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.75V
●
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
●
±10
µA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VDD = 4.75V, IO = – 10µA
VDD = 4.75V, IO = – 200µA
●
VDD = 4.75V, IO = 160µA
VDD = 4.75V, IO = – 1.6mA
●
2.4
V
1.4
pF
4.74
V
V
4.0
0.05
0.10
0.4
V
V
IOZ
High-Z Output Leakage DOUT, CLKOUT
VOUT = 0V to VDD, RD High
●
±10
µA
COZ
High-Z Output Capacitance DOUT, CLKOUT
RD High (Note 9)
●
15
pF
ISOURCE
Output Source Current
VOUT = 0V
– 10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
3
LTC1417
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POWER REQUIRE E TS
The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
UNITS
5.25
V
VDD
Positive Supply Voltage (Notes 10, 11)
VSS
Negative Supply Voltage (Note 10)
Bipolar Only (VSS = 0V for Unipolar)
IDD
Positive Supply Current
Unipolar, RD High (Note 5)
Bipolar, RD High (Note 5)
SHDN = 0V, RD = 0V
SHDN = 0V, RD = 5V
●
●
4.0
4.3
750
0.1
5.5
6.0
mA
mA
µA
µA
Nap Mode
Sleep Mode
4.75
MAX
– 4.75
– 5.25
V
ISS
Negative Supply Current
Nap Mode
Sleep Mode
Bipolar, RD High (Note 5)
SHDN = 0V, RD = 0V
SHDN = 0V, RD = 5V
●
2.0
0.7
1.5
2.8
mA
µA
nA
PDIS
Power Dissipation
Unipolar
Bipolar
●
●
20.0
31.5
27.5
44
mW
mW
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TI I G CHARACTERISTICS
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
fSAMPLE(MAX)
Maximum Sampling Frequency
CONDITIONS
●
MIN
TYP
MAX
tCONV
Conversion Time
●
1.8
2.25
µs
tACQ
Acquisition Time
●
150
500
ns
tACQ + tCONV
Acquisition Plus Conversion Time
●
2.1
2.5
µs
t1
SHDN↑ to CONVST↓ Wake-Up Time from Nap Mode
(Note 10)
t2
CONVST Low Time
(Notes 10, 11)
●
t3
CONVST to BUSY Delay
CL = 25pF
●
t4
Data Ready Before BUSY↑
CL = 25pF
●
7
t5
Delay Between Conversions
(Note 10)
●
250
ns
t6
Wait Time RD↓ After BUSY↑
●
–5
ns
t7
Data Access Time After RD↓
400
kHz
500
ns
40
ns
35
CL = 25pF
UNITS
70
12
ns
ns
15
30
40
ns
ns
20
●
40
55
ns
ns
35
ns
●
CL = 100pF
t8
Bus Relinquish Time
●
t9
RD Low Time
●
t7
ns
t10
CONVST High Time
●
40
ns
t11
Delay Time, SCLK↓ to DOUT Valid
CL = 25pF
●
t12
Time from Previous Data Remain Valid After SCLK↓
CL = 25pF
●
5
fSCLK
Shift Clock Frequency
(Note 13)
●
0
fEXTCLKIN
External Conversion Clock Frequency
●
0.05
tdEXTCLKIN
Delay Time, CONVST↓ to External Conversion Clock Input (Note 9)
●
4
15
40
10
ns
ns
20
MHz
9
MHz
20
µs
LTC1417
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TI I G CHARACTERISTICS
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
tH SCLK
SCLK High Time
(Note 9)
●
10
ns
tL SCLK
SCLK Low Time
(Note 9)
●
10
ns
tH EXTCLKIN
EXTCLKIN High Time
●
0.04
20
µs
tL EXTCLKIN
EXTCLKIN Low Time
●
0.04
20
µs
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA without latchup if the pin is driven below VSS (ground
for unipolar mode) or above VDD.
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN– grounded.
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SIGNAL/(NOISE + DISTORTION) (dB)
0.5
DNL ERROR (LSBs)
0.5
0
0
– 0.5
–0.5
0
4096
8192
12288
16384
OUTPUT CODE
1417 G01
80
VIN = 0dB
70
60
VIN = –20dB
50
40
30
VIN = –60dB
20
10
0
–1.0
–1.0
UNITS
S/(N + D) vs Input Frequency
and Amplitude
1.0
1.0
MAX
(TA = 25°C)
Differential Nonlinearity
vs Output Code
Typical INL Curve
TYP
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 625ns after
conversion start or after BUSY rises.
Note 12: Typical RMS noise at the code transitions. See Figure 2 for
histogram.
Note 13: t11 of 40ns maximum allows fSCLK up to 10MHz for rising
capture with 50% duty cycle. fSCLK up to 20MHz for falling capture with
5ns setup time.
TYPICAL PERFOR A CE CHARACTERISTICS
INL (LSBs)
MIN
0
4096
12288
8192
OUTPUT CODE
16384
1417 G02
1k
100k
10k
INPUT FREQUENCY (Hz)
1M
1417 G03
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LTC1417
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TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C)
Signal-to-Noise Ratio
vs Input Frequency
70
60
50
40
30
20
10
0
10k
100k
INPUT FREQUENCY (Hz)
– 20
– 40
– 60
– 80
THD
–100
3RD
–120
1M
2ND
1
–80
–100
200
Intermodulation Distortion Plot
0
–40
– 40
–60
–80
–120
–120
0
50
80
VDD
DGND
120
10k
100k
1M
RIPPLE FREQUENCY (Hz)
10M
1417 G10
20 40 60 80 100 120 140 160 180 200
FREQUENCY (kHz)
1417 G09
Input Offset Voltage Shift
vs Source Resistance
10
60
50
40
30
20
10
9
8
7
6
5
4
3
2
1
0
0
1k
0
200
100
150
FREQUENCY (kHz)
CHANGE IN OFFSET VOTLAGE (LSB)
COMMON MODE REJECTION (dB)
60
100
– 80
–100
70
VSS
– 60
1417 G08
0
40
1M
1417 G06
Input Common Mode Rejection
vs Input Frequency
VRIPPLE = 60mV
fSAMPLE = 400kHz
20 fIN = 200kHz
10k
100k
INPUT FREQUENCY (Hz)
fSAMPLE = 400kHz
fIN1 = 97.303466kHz
– 20 fIN2 = 104.632568kHz
VIN = 4.096VP-P
Power Supply Feedthrough
vs Ripple Frequency
FEEDTHROUGH (dB)
1k
fSAMPLE = 400kHz
fIN = 197.949188kHz
–20 SFDR = –98dB
SINAD = 81.1dB
1417 G07
6
–120
–100
100
150
FREQUENCY (kHz)
–100
AMPLITUDE (dB)
AMPLITUDE (dB)
AMPLITUDE (dB)
–60
50
–80
0
fSAMPLE = 400kHz
fIN = 10.05859375kHz
SFDR = –97.44dB
SINAD = 81.71dB
0
–60
Nonaveraged, 4096 Point FFT,
Input Frequency = 200kHz
–40
–120
–40
1417 G05
Nonaveraged, 4096 Point FFT,
Input Frequency = 10kHz
–20
–20
1000
10
100
INPUT FREQUENCY (kHz)
1417 G04
0
SPURIOUS FREE DYNAMIC RANGE (dB)
SIGNAL-TO-NOISE RATIO (dB)
80
0
0
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
90
1k
Spurious-Free Dynamic Range
vs Input Frequency
Distortion vs Input Frequency
1
100
10
INPUT FREQUENCY (kHz)
1000
1417 G11
1
100
1k
10k 100k
10
INPUT SOURCE RESISTANCE (Ω)
1M
1417 G12
LTC1417
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TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C)
VDD Supply Current vs
Temperature (Bipolar Mode)
3.0
5
5
2.5
4
3
2
1
VSS SUPPLY CURRENT (mA)
6
0
–75 –50 –25
4
3
2
1
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
4.0
4.0
2.0
1.5
1.0
0 25 50 75 100 125 150
TEMPERATURE (°C)
VSS Supply Current vs Sampling
Frequency (Bipolar Mode)
2.5
3.5
3.0
2.5
2.0
1.5
1.0
2.0
1.5
1.0
0.5
0.5
0.5
0
0.5
1417 G15
VSS SUPPLY CURRENT (mA)
4.5
VDD SUPPLY CURRENT (mA)
5.0
4.5
2.5
1.0
VDD Supply Current vs Sampling
Frequency (Bipolar Mode)
5.0
3.0
1.5
1417 G14
VDD Supply Current vs Sampling
Frequency (Unipolar Mode)
3.5
2.0
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
1417 G13
VDD SUPPLY CURRENT (mA)
VSS Supply Current vs
Temperature (Bipolar Mode)
6
VDD SUPPLY CURRENT (mA)
VDD SUPPLY CURRENT (mA)
VDD Supply Current vs
Temperature (Unipolar Mode)
0
0
50 100 150 200 250 300 350 400 450 500
SAMPLING FREQUENCY (kHz)
0
50 100 150 200 250 300 350 400 450 500
SAMPLING FREQUENCY (kHz)
1417 G16
1417 G17
0
0
50 100 150 200 250 300 350 400 450 500
SAMPLING FREQUENCY (kHz)
1417 G18
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PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input.
AIN– (Pin 2): Negative Analog Input.
VREF (Pin 3): 2.50V Reference Output. Bypass to AGND
with 1µF.
REFCOMP (Pin 4): 4.096V Reference Output. Bypass to
AGND using 10µF tantalum in parallel with 0.1µF ceramic.
AGND (Pin 5): Analog Ground.
EXTCLKIN (Pin 6): External Conversion Clock Input. A 5V
input will enable the internal conversion clock.
SCLK (Pin 7): Data Clock Input.
CLKOUT (Pin 8): Conversion Clock Output.
DOUT (Pin 9): Serial Data Output.
DGND (Pin 10): Digital Ground.
SHDN (Pin 11): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by RD. RD = 0V for
Nap mode and RD = 5V for Sleep mode.
RD (Pin 12): Read Input. This enables the output drivers.
RD also sets the shutdown mode when SHDN goes low.
RD and SHDN low selects the quick wake-up Nap mode,
RD high and SHDN low selects Sleep mode.
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LTC1417
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PIN FUNCTIONS
CONVST (Pin 13): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
BUSY (Pin 14): The BUSY output shows the converter
status. It is low when a conversion is in progress.
VSS (Pin 15): Negative Supply, –5V for Bipolar Operation.
Bypass to AGND using 10µF tantalum in parallel with
0.1µF ceramic. Analog ground for unipolar operation.
VDD (Pin 16): 5V Positive Supply. Bypass to AGND with
10µF tantalum in parallel with 0.1µF ceramic.
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
1k
1k
DOUT
DOUT
DOUT
1k
CL
DOUT
DGND
30pF
1k
CL
30pF
DGND
A) HI-Z TO VOH AND VOL TO VOH
A) VOH TO HI-Z
B) HI-Z TO VOL AND VOH TO VOL
B) VOL TO HI-Z
1417 TC02
1417 TC01
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FUNCTIONAL BLOCK DIAGRA
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CSAMPLE
AIN+
1
16
CSAMPLE
AIN–
VREF
15
2
3
8k
ZEROING SWITCHES
2.5V REF
VDD
VSS
(0V FOR UNIPOLAR MODE
–5V FOR BIPOLAR MODE)
+
REF AMP
COMP
14-BIT CAPACITIVE DAC
–
REFCOMP
(4.096V)
AGND
DGND
4
5
10
9
SHIFT REGISTER
7
INTERNAL
CLOCK
MUX
6
EXTCLKIN
8
14
SUCCESSIVE APPROXIMATION
REGISTER
CONTROL LOGIC
11
SHDN
13
CONVST
12
RD
8
14
CLKOUT BUSY
1417 BD
DOUT
SCLK
LTC1417
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APPLICATIONS INFORMATION
The LTC1417 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit serial output. The ADC is complete with a precision reference and an internal clock. The
control logic provides easy interface to microprocessors
and DSPs (please refer to Digital Interface section for the
data format).
Conversion start is controlled by the CONVST input. At the
start of the conversion, the successive approximation
register (SAR) is reset. Once a conversion cycle has
begun, it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
Referring to Figure 1, the AIN+ and AIN– inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by
the zeroing switches. In this acquire phase, a minimum
delay of 500ns will provide enough time for the sampleand-hold capacitors to acquire the analog signal. During
the convert phase, the comparator zeroing switches open,
placing the comparator in compare mode. The input
switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively
compared with the binary weighted charges supplied by
the differential capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion, the
differential DAC output balances the AIN+ and AIN– input
charges. The SAR contents (a 14-bit data word) that
represent the difference of AIN+ and AIN– are output
through the serial pin DOUT.
DC Performance
One way of measuring the transition noise associated with
a high resolution ADC is to use a technique where a DC
signal is applied to the input of the ADC and the resulting
output codes are collected over a large number of conversions. For example in Figure 2, the distribution of output
code is shown for a DC input that has been digitized 4096
times. The distribution is Gaussian and the RMS code
transition is about 0.33LSB.
4000
3500
3000
2500
COUNTS
CONVERSION DETAILS
2000
1500
1000
500
AIN+
AIN–
CSAMPLE
SAMPLE
+
0
–1
0
1
2
1417 F02
CSAMPLE–
SAMPLE
–2
CODE
ZEROING SWITCHES
HOLD
HOLD
Figure 2. Histogram for 4096 Conversions
HOLD
HOLD
DYNAMIC PERFORMANCE
CDAC+
+
CDAC–
VDAC+
COMP
–
VDAC–
14
SAR
SHIFT
REGISTER
DOUT
1417 F01
Figure 1. Simplified Block Diagram
The LTC1417 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and
noise performance at the rated throughput. By applying
a low distortion sine wave and analyzing the digital output
using an FFT algorithm, the ADC’s spectral content can be
examined for frequencies beyond the fundamental.
Figure 3 shows a typical LTC1417 FFT plot.
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0
fSAMPLE = 400kHz
fIN = 10.05859375kHz
SFDR = –97.44dB
SINAD = 81.71dB
AMPLITUDE (dB)
–20
–40
–60
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
ENOB (N) = [S/(N + D) – 1.76]/6.02
–80
–100
–120
Effective Number of Bits
0
50
100
150
FREQUENCY (kHz)
200
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 400kHz, the LTC1417 maintains near ideal ENOBs
up to the Nyquist input frequency of 200kHz (refer to
Figure 4).
1417 G07
14
Figure 3a. LTC1417 Nonaveraged, 4096 Point FFT,
Input Frequency = 10kHz
86
80
12
74
68
EFFECTIVE BITS
AMPLITUDE (dB)
fSAMPLE = 400kHz
fIN = 197.949188kHz
–20 SFDR = –98dB
SINAD = 81.1dB
–40
10
62
8
6
–60
4
–80
2
1k
–100
–120
10k
100k
INPUT FREQUENCY (Hz)
S/(N + D) (dB)
0
1M
1417 TA02
0
50
100
150
FREQUENCY (kHz)
200
Figure 4. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
1417 G08
Figure 3b. LTC1417 Nonaveraged, 4096 Point FFT,
Input Frequency = 200kHz
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 3b shows a typical spectral content with
a 400kHz sampling rate and a 200kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 200kHz.
10
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
V22 + V32 + V42 + ...Vn2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs Input Frequency is
shown in Figure 5. The LTC1417 has good distortion
performance up to the Nyquist frequency and beyond.
THD = 20Log
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APPLICATIONS INFORMATION
(
0
– 20
– 40
)
Amplitude at fa
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
– 80
THD
–100
3RD
2ND
1
10
100
INPUT FREQUENCY (kHz)
1000
1417 G05
Figure 5. Distortion vs Input Frequency
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
etc. For example, 2nd order IMD terms include (fa ± fb). If
the two input sine waves are equal in magnitude, the value
(in decibels) of the 2nd-order IMD products can be
expressed by the following formula:
0
fSAMPLE = 400kHz
fIN1 = 97.303466kHz
– 20 fIN2 = 104.632568kHz
VIN = 4.096VP-P
AMPLITUDE (dB)
(
Amplitude at fa ± fb
Peak Harmonic or Spurious Noise
– 60
–120
)
IMD fa + fb = 20Log
– 40
– 60
– 80
–100
–120
0
20 40 60 80 100 120 140 160 180 200
FREQUENCY (kHz)
1417 G09
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is the input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB from a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 77dB (12.5 effective bits).
The LTC1417 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with
frequencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1417 are easy to
drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN– input is grounded). The AIN+ and
AIN– inputs are sampled at the same instant. Any
unwanted signal that is common to both inputs will be
reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1417
inputs can be driven directly. As source impedance
increases, so will acquisition time (see Figure 7). For
minimum acquisition time, with high source impedance, a
buffer amplifier must be used. The only requirement is that
the amplifier driving the analog input(s) must settle after
the small current spike before the next conversion starts —
500ns for full throughput rate.
Figure 6. Intermodulation Distortion Plot
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LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA supply current, ±2.5V to ±15V supplies. High AVOL, 1mV
offset and 80ns settling to 1mV (4V step, inverting and
noninverting configurations) make it suitable for fast DC
applications. Excellent AC specifications. Dual and quad
versions are available as LT1361 and LT1362.
ACQUISITION TIME (µs)
100
10
1
LT1468: 90MHz Voltage Feedback Amplifier. ±5V to ±15V
supplies. Lower distortion and noise. Settles to 0.01% in
770ns. Distortion is –115dB to 20kHz.
0.1
0.01
1
10
100
1k
10k
SOURCE RESISTANCE (Ω)
100k
1417 F07
Figure 7. tACQ vs Source Resistance
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, choose an amplifier that
has a low output impedance (<100Ω) at the closed-loop
bandwidth frequency. For example, if an amplifier is used
in a gain of 1 and has a closed-loop bandwidth of 10MHz,
then the output impedance at 10MHz must be less than
100Ω. The second requirement is that the closed-loop
bandwidth must be greater than 10MHz to ensure adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.
The best choice for an op amp to drive the LTC1417 will
depend on the application. Generally, applications fall into
two categories: AC applications where dynamic specifications are most critical and time domain applications where
DC accuracy and settling time are most critical. The
following list is a summary of the op amps that are suitable
for driving the LTC1417. More detailed information is
available in the Linear Technology Databooks and on the
LinearViewTM CD-ROM.
®
LT 1354: 12MHz, 400V/µs Op Amp. 1.25mA maximum
supply current. Good AC and DC specifications. Suitable
for dual supply application.
LT1498/LT1499: 10MHz, 6V/µs, Dual/Quad Rail-to-Rail
Input and Output Op Amps. 1.7mA supply current per
amplifier. 2.2V to ± 15V supplies. Good AC performance,
input noise voltage = 12nV/√Hz (typ).
LT1630/LT1631: 30MHz, 10V/µs, Dual/Quad Rail-to-Rail
Input and Output Precision Op Amps. 3.5mA supply
current per amplifier. 2.7V to ±15V supplies. Best AC
performance, input noise voltage = 6nV/√Hz (typ),
THD = – 86dB at 100kHz.
LT1813: Dual 100MHz 750V/µs 3mA VFA. 5V to ±5V
supplies. Distortion is – 86dB to 100kHz and – 77dB to
1MHz with ±5V supplies (2VP-P into 500Ω). Great part for
fast AC applications with ±5V supplies.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1417 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 10MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 8 shows a 1000pF
100Ω
ANALOG INPUT
1000pF
1
AIN+
2
AIN–
3
4
LT1357: 25MHz, 600V/µs Op Amp. 2.5mA maximum
supply current. Good AC and DC specifications. Suitable
for dual supply application.
LinearView is a trademark of Linear Technology Corporation.
12
10µF
5
VREF
LTC1417
REFCOMP
AGND
1417 F08
Figure 8. RC Input Filter
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capacitor from + AIN to ground and a 100Ω source resistor
to limit the input bandwidth to 1.6MHz. The 1000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors can
also generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
Input Range
The ±2.048V and 0V to 4.096V input ranges of the
LTC1417 are optimized for low noise and low distortion.
Most op amps also perform well over these ranges,
allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry.
reference amplifier compensation pin (REFCOMP, Pin 4)
and ground. The reference is stable with capacitors of 1µF
or greater. For the best noise performance, a 10µF in
parallel with a 0.1µF ceramic is recommended.
The VREF pin can be driven with a DAC or other means
to provide input span adjustment. The reference should
be kept in the range of 2.25V to 2.75V for specified linearity.
UNIPOLAR / BIPOLAR OPERATION AND ADJUSTMENT
Figure 10a shows the input/output characteristics for the
LTC1417. The code transitions occur midway between
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB, … FS – 1.5LSB). The output code is natural binary
with 1LSB = FS/16384 = 4.096V/16384 = 250µV. Figure
10b shows the input/output transfer characteristics for the
bipolar mode in two’s complement format.
1LSB =
111...111
111...101
000...001
ANALOG
INPUT
2.5V
1
AIN+
2
AIN–
3
LT1460-2.5
4
10µF
0.1µF
5
000...000
0V
VDD
1
LSB
FS – 1LSB
INPUT VOLTAGE (V)
1417 F10a
Figure 10a. LTC1417 Unipolar Transfer Characteristics
011...111
BIPOLAR
ZERO
011...110
OUTPUT CODE
5V
VOUT
UNIPOLAR
ZERO
000...010
The LTC1417 has an on-chip, temperature compensated,
curvature corrected, bandgap reference which is factory
trimmed to 2.500V. It is internally connected to a reference
amplifier and is available at Pin 3. An 8k resistor is in series
with the output so that it can be easily overdriven in
applications where an external reference is required, see
Figure 9. A capacitor must be connected between the
VIN
111...100
000...011
INTERNAL REFERENCE
5V
FS = 4.096V
16384 16384
111...110
OUTPUT CODE
Some applications may require other input ranges. The
LTC1417 differential inputs and reference circuitry can
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
000...001
000...000
111...111
111...110
LTC1417
VREF
100...001
REFCOMP
100...000
AGND
FS = 4.096V
1LSB = FS/16384
–FS/2
1417 F09
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 – 1LSB
1417 F10b
Figure 9. Using the LT1460 as an External Reference
Figure 10b. LTC1417 Bipolar Transfer Characteristics
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Unipolar Offset and Full-Scale Error Adjustment
Bipolar Offset and Full-Scale Error Adjustment
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figures
11a and 11b show the extra components required for fullscale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN– input. For zero offset
error, apply 125µV (i.e., 0.5LSB) at the input and adjust
the offset at the AIN– input until the output code flickers
between 0000 0000 0000 00 and 0000 0000 0000 01. For
full-scale adjustment, an input voltage of 4.095625V
(FS – 1.5LSBs) is applied to AIN+ and R2 is adjusted until
the output code flickers between 1111 1111 1111 10 and
1111 1111 1111 11.
Bipolar offset and full-scale errors are adjusted in a
similar fashion to the unipolar case using the circuit in
Figure 11b. Again, bipolar offset error must be adjusted
before full-scale error. Bipolar offset error adjustment is
achieved by adjusting the offset applied to the AIN– input.
For zero offset error, apply – 125µV (i.e., – 0.5LSB) at AIN+
and adjust the offset at the AIN– input until the output code
flickers between 0000 0000 0000 00 and 1111 1111 1111
11. For full-scale adjustment, an input voltage of 2.047625V
(FS – 1.5LSBs) is applied to AIN+ and R2 is adjusted until
the output code flickers between 0111 1111 1111 10 and
0111 1111 1111 11.
R8
100Ω
R7
48k
5V
ANALOG INPUT
OFFSET R1
ADJ 50k
R3
24k
R4
100Ω
1
AIN+
2
AIN–
3
R5
FS R2
47k ADJ 50k
R6
24k
VREF
4
LTC1417
REFCOMP
5
AGND V
SS
0.1µF
10µF
VDD
1417 F11a
Figure 11a. Offset and Full-Scale Adjust Circuit
If – 5V Is Not Available
5V
–5V
ANALOG INPUT
OFFSET R1
ADJ 50k
R3
24k
R4
100Ω
1
AIN+
2
AIN–
3
FS R2
R5
47k ADJ 50k
R6
24k
4
5
10µF
0.1µF
VREF
VDD
LTC1417
REFCOMP
AGND V
SS
1417 F11b
–5V
Figure 11b. Offset and Full-Scale Adjust Circuit
If – 5V Is Available
14
BOARD LAYOUT AND GROUNDING
To obtain the best performance from the LTC1417, a
printed circuit board with ground plane is required. The
ground plane under the ADC area should be as free of
breaks and holes as possible, such that a low impedance
path between all ADC grounds and all ADC decoupling
capacitors is provided. It is critical to prevent digital noise
from being coupled to the analog input, reference or
analog power supply lines. Layout should ensure that
digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital track alongside an analog signal track.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND) and Pin 10 (DGND) and all other analog
grounds should be connected to this single analog ground
plane. The REFCOMP bypass capacitor and the VDD bypass capacitor should also be connected to this analog
ground plane. No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential
to low noise operation of the ADC and the foil width for
these tracks should be as wide as possible. In applications
where the ADC data outputs and control signals are
connected to a continuously active microprocessor bus, it
is possible to get errors in the conversion results. These
errors are due to feedthrough from the microprocessor to
the successive approximation comparator. The problem
can be eliminated by forcing the microprocessor into a
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1
AIN+
AIN–
ANALOG
INPUT
CIRCUITRY
+
–
2
DIGITAL
SYSTEM
LTC1417
VREF
REFCOMP
3
4
1µF
AGND
VDD
VSS
5
15
10µF
DGND
16
10
10µF
10µF
ANALOG GROUND PLANE
1417 F12
Figure 12. Power Supply Grounding Practice
wait state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the
pins and bypass capacitors must be kept short and should
be made as wide as possible.
The LTC1417 has differential inputs to minimize noise
coupling. Common mode noise on the AIN+ and AIN– leads
will be rejected by the input CMRR. The AIN– input can be
used as a ground sense for the AIN+ input; the LTC1417 will
hold and convert the difference voltage between AIN+ and
AIN–. The leads to AIN+ (Pin 1) and AIN– (Pin 2) should be
kept as short as possible. In applications where this is not
possible, the AIN+ and AIN– traces should be run side by
side to equalize coupling.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the VDD and REFCOMP pins.
Surface mount ceramic capacitors such as Taiyo Yuden
LMK325BJ106MN provide excellent bypassing in a small
board space. Alternatively 10µF tantalum capacitors in
parallel with 0.1µF ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
Example Layout
Figures 13a, 13b, 13c and 13d show the schematic and
layout of a suggested evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground
plane with a 2-layer printed circuit board.
POWER SHUTDOWN
The LTC1417 provides two power shutdown modes, Nap
and Sleep, to save power during inactive periods. The
Nap mode reduces ADC power dissipation by 80% and
leaves only the digital logic and reference powered up.
The wake-up time from Nap to active is 500ns (see Figure
14). In Sleep mode, all bias currents are shut down and
only leakage current remains— about 2µA. Wake-up
time from Sleep mode is much slower since the reference
circuit must power up and settle to 0.005% for full 14-bit
accuracy. Sleep mode wake-up time is dependent on the
value of the capacitor connected to the REFCOMP (Pin 4).
The wake-up time is 30ms with the recommended 10µF
capacitor. Shutdown is controlled by Pin 11 (SHDN); the
ADC is in shutdown when it is low. The shutdown mode
is selected with Pin␣ 12 (RD); low selects Nap mode, high
selects Sleep mode.
SHDN
t1
CONVST
1417 F14
Figure 14. SHDN to CONVST Wake-Up Timing
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C1
0.1µF
C2
0.1µF
5A
U3
LT1363CN8
R1
10k
C3
1000pF
50V
R4
75Ω
J2
BNC
R2
10k
2
3
JP3
C6
1µF
4
C7
10µF
16V
+
5
6
7
8
–AIN
VSS
VREF
BUSY
AGND
EXTCLKIN
SCK
CLKOUT
C8
5A 10µF
16V
C9
10µF
16V
AGND DGND
–5A
JP7
U2A
TC74HCT244AF
1
2
18
19
VDD
CONVST
RD
SHDN
DGND
DOUT
E3
–5V
+
16
15
12
9
1
3
13
10
–5A
C11
10µF
16V
U2B
14
11
5A
C10
10µF
16V
E2
GND
–5A
+AIN
REFCOMP
8
C5
0.1µF
U1
LTC1417CGN
1
6
4
OPTIONAL
+
1
–
C4
0.1µF
R3
75Ω
JP2
8
4
+
U4
LT1363CS8
+
J1
BNC
2
1
–
JP1
6
5
+
2
3
5
+
E1
5V
7
7
3
4
5A
U2C
1
16
19
JP4
R5
100k
JP6
R6
100k
1
7
JP5B
JP5C
8
R8
100k
U2F
BUSY
13
RD
DOUT
19
U2G
1
12
SCLK
19
1
9
C12
0.1µF
5A
15
19
U2E
1
14
19
JP5A
J3
BNC
U2D
1
5
6
17
19
19
U2H
CLKOUT
11
EXTCLKIN
R7
100k
J8
CON7
1
2
3
4
5
6
7
1417 F13a
5A
BYPASS CAPACITOR FOR U2
Figure 13a. Suggested Evaluation Circuit Schematic
Figure 13b. Suggested Evaluation
Circuit Board—Component Side Silkscreen
16
Figure 13c. Suggested Evaluation
Circuit Board—Component Side
Figure 13d. Suggested Evaluation
Circuit Board—Solder Side
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DIGITAL INTERFACE
status is indicated by the BUSY output. BUSY is low during
a conversion.
The LTC1417 operates in serial mode. The RD control input
is common to all peripheral memory interfacing. Only four
digital interface lines are required, SCLK, CONVST,
EXTCLKIN and DOUT. SCLK, the serial data shift clock can
be an external input or supplied by the LTC1417’s internal
clock.
Data Output
Output will be active when RD is low. A high RD will threestate the ouput. In unipolar mode (VSS = 0V), the data will
be in straight binary format (corresponding to the unipolar
input range). In bipolar mode (VSS = – 5V), the data will be
in two’s complement format (corresponding to the bipolar
input range).
Internal Clock
The ADC has an internal clock. Either the internal clock or
an external clock may be used as the conversion clock (see
Figure 15). The internal clock is factory trimmed to achieve
a typical conversion time of 1.8µs, and a maximum conversion time over the full operating temperature range of
2.5µs. No external adjustments are required, and with the
guaranteed maximum acquisition time of 0.5µs, throughput performance of 400ksps is assured.
Serial Output Mode
Conversion Control
Conversions are started by a falling CONVST edge. After a
conversion is completed and the output shift register has
been updated, BUSY will go high and valid data will be
available on DOUT (Pin 9). This data can be clocked out
either before the next conversion starts or it can be clocked
out during the next conversion. To enable the serial data
output buffer and shift clock, RD must be low.
Conversion start is controlled by the signal applied to the
CONVST input. A falling edge on the signal applied to the
CONVST pin starts a conversion. Once initiated, it cannot
be restarted until the conversion is complete. Converter
Figure 15 shows a function block diagram of the LTC1417.
There are two pieces to this circuitry: the conversion clock
selection circuit (EXTCLKIN and CLKOUT) and the serial
port (SCLK, DOUT and RD).
•••
DATA
IN
14
CLOCK
INPUT
SHIFT
REGISTER
7
12
DATA
OUT
THREE
STATE
BUFFER
9
SCLK
RD
DOUT
16 CONVERSION CLOCK CYCLES
SAR
THREE
STATE
BUFFER
8
•••
EOC
6
CLKOUT
EXTCLKIN
CLOCK
DETECTOR
INTERNAL
CLOCK
14
BUSY
1417 F15
Figure 15. Functional Block Diagram
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Conversion Clock Selection
In Figure 15, the conversion clock controls the internal
ADC operation. The conversion clock can be either internal or external. By connecting EXTCLKIN high, the internal clock is selected. This clock generates 16 clock cycles
which feed into the SAR for each conversion.
To select an external conversion clock, apply an external
conversion clock to EXTCLKIN (Pin 6). (When an external
shift clock (SCLK) is used during a conversion, the SCLK
should be used as the external conversion clock to avoid
the noise generated by the asynchronous clocks. To
maintain accuracy, the external conversion clock frequency must be between 50kHz and 9MHz.) The SAR
sends an end of conversion signal, EOC, that gates the
external conversion clock so that only 16 clock cycles can
go into the SAR, even if the external clock, EXTCLKIN,
contains more than 16 cycles.
When RD is low, these 16 cycles of conversion clock
(whether internally or externally generated) will appear
on CLKOUT during each conversion and then CLKOUT
will remain low until the next conversion. If desired,
CLKOUT can be used as a master clock to drive the serial
port. Because CLKOUT is running during the conversion,
it is important to avoid excessive loading that can cause
large supply transients and create noise. For the best
performance, limit CLKOUT loading to 20pF.
Serial Port
The serial port in Figure 15 is made up of a 16-bit shift
register and a three-state output buffer that are controlled by two inputs: SCLK and RD. The serial port has
one output, DOUT, that provides the serial output data.
SCLK
The SCLK is used to clock the shift register. Data may be
clocked out with the internal conversion clock operating
as a master by connecting CLKOUT (Pin 8) to SCLK
(Pin␣ 7) or with an external data clock applied to SCLK.
The minimum number of SCLK cycles required to transfer a data word is 14. Normally, SCLK contains 16 clock
cycles for a word length of 16 bits; 14 bits with MSB first,
followed by two trailing zeros.
A logic high on RD disables SCLK and three-states DOUT.
In case of using a continuous SCLK, RD can be controlled
to limit the number of shift clocks to the desired number
(i.e., 16 cycles) and to three-state DOUT after the data
transfer.
In power shutdown mode (SHDN = low), a high RD
selects Sleep mode while a low RD selects Nap mode.
DOUT outputs the serial data; 14 bits, MSB first, on the
falling edge of each SCLK (see Figures 16 and 17). If 16
SCLKs are provided, the 14 data bits will be followed by
two zeros. The MSB (D13) will be valid on the first rising
and the first falling edge of the SCLK. D12 will be valid on
the second rising and the second falling edge as will all
the remaining bits. The data may be captured using either
edge. The largest hold time margin is achieved if data is
captured on the rising edge of SCLK.
BUSY gives the end-of-conversion indication. When the
LTC1417 is configured as a serial bus master, BUSY can
be used as a framing pulse. To three-state the serial port
after transferring the serial output data, BUSY and RD
should be connected together at the ADC (see Figure 17).
Figures 17 to 20 show several serial modes of operation,
demonstrating the flexibility of the LTC1417 serial interface.
VIL
t11
t12
VOH
DOUT
VOL
1417 F16
Figure 16. SCLK to DOUT Delay
18
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APPLICATIONS INFORMATION
Serial Data Output During a Conversion
conversion time; consequently, this mode can provide the
best overall speed performance. To select the internal
conversion clock, tie EXTCLKIN (Pin 6) high. The internal
clock appears on CLKOUT (Pin 8) which can be tied to
SCLK (Pin 7) to supply the SCLK.
Using Internal Clock for Conversion and Data Transfer.
Figure 17 shows data from the previous conversion being
clocked out during the conversion with the LTC1417
internal clock providing both the conversion clock and the
SCLK. The internal clock has been optimized for the fastest
CONVST
13
CONVST
BUSY
12
RD
LTC1417
DOUT
µP OR DSP
(CONFIGURED
AS SLAVE)
OR
SHIFT
REGISTER
7
SCLK
CLKOUT
BUSY (= RD)
14
8
CLKOUT ( = SCLK)
9
DOUT
(SAMPLE N)
t2
EXTCLKIN = 5
(SAMPLE N + 1)
CONVST
t10
t3
t5
HOLD
BUSY (= RD)
SAMPLE
HOLD
t7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
D13
D12
D11
CLKOUT (= SCLK)
t4
DOUT
Hi-Z
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FILL
ZEROS
D13
Hi-Z
DATA (N – 1)
tCONV
DATA N
t8
CLKOUT
(= SCLK)
1417 F17
VIL
t11
t12
DOUT
D13
D12
CAPTURE ON
RISING CLOCK
D11
VOH
VOL
CAPTURE ON
FALLING CLOCK
Figure 17. Internal Conversion Clock Selected. Data Transferred During Conversion Using
the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)
19
LTC1417
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APPLICATIONS INFORMATION
Using External Clock for Conversion and Data Transfer.
In Figure 18, data from the previous conversion is output
during the conversion with an external clock providing
both the conversion clock and the shift clock. To select an
external conversion clock, apply the clock to EXTCLKIN.
The same clock is also applied to SCLK to provide a data
CONVST
13
CONVST
BUSY
shift clock. To maintain conversion accuracy, the external
clock frequency must be between 50kHz and 9MHz.
Using an external clock to transfer data while an internal
clock controls the conversion process is not recommended. As both signals are asynchronous, clock noise
can corrupt the conversion result.
BUSY (= RD)
14
12
RD
LTC1417
7
SCLK
DOUT
µP OR DSP
EXTCLKIN ( = SCLK)
6
EXTCLKIN
DOUT
9
(SAMPLE N)
t2
(SAMPLE N + 1)
CONVST
t10
t3
t5
HOLD
BUSY (= RD)
SAMPLE
HOLD
tdEXTCLKIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
D13
D12
D11
EXTCLKIN (= SCLK)
t7
DOUT
Hi-Z
t4
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FILL
ZEROS
D13
Hi-Z
DATA (N – 1)
tCONV
DATA N
t8
EXTCLKIN
(= SCLK)
tLEXTCLKIN
VIL
tHEXTCLKIN
t11
t12
DOUT
D13
D12
CAPTURE ON
RISING CLOCK
D11
VOH
VOL
CAPTURE ON
FALLING CLOCK
Figure 18. External Conversion Clock Selected. Data Transferred During Conversion Using
the External Clock (External Clock Drives Both EXTCLKIN and SCLK)
20
1417 F18
LTC1417
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APPLICATIONS INFORMATION
Serial Data Output After a Conversion
Using an Internal Conversion Clock and an External Data
Clock. In this mode, data is output after the end of each
conversion and before the next conversion is started
(Figure 19). The internal clock is used as the conversion
clock and an external clock is used for the SCLK. This
mode is useful in applications where the processor acts as
a serial bus master device. This mode is SPI and
CONVST
13
CONVST
BUSY
MICROWIRETM compatible. It also allows operation when
the SCLK frequency is very low (less than 30kHz). To
select the internal conversion clock, tie EXTCLKIN high.
The external SCLK is applied to SCLK. RD can be used to
gate the external SCLK, such that data will clock only after
RD goes low and to three-state DOUT after data transfer. If
more than 16 SCLKs are provided, more zeros will be filled
in after the data word indefinitely.
MICROWIRE is a trademark of National Semiconductor Corporation.
14
INT
12
RD
C0
µP OR DSP
LTC1417
7
SCLK
DOUT
SCK
9
MISO
t2
EXTCLKIN = 5
CONVST
t10
t3
t5
SAMPLE
HOLD
BUSY
t6
t9
RD
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
SCLK
t7
Hi-Z
DOUT
t8
D13 12 11 10 9
8
7
6
5
4
3
2
1
FILL
ZEROS
0
Hi-Z
(SAMPLE N)
tCONV
DATA N
1417 F19
t LSCLK
SCLK
VIL
t HSCLK
t11
t12
DOUT
D12
D13
CAPTURE ON
RISING CLOCK
D11
VOH
VOL
CAPTURE ON
FALLING CLOCK
Figure 19. Internal Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY↑ Indicates End of Conversion
21
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APPLICATIONS INFORMATION
Using an External Conversion Clock and an External
Data Clock. In Figure 20, data is also output after each
conversion is completed and before the next conversion is
started. An external clock is used for the conversion clock
and either another or the same external clock is used for
the SCLK. This mode is identical to Figure 19 except that
an external clock is used for the conversion. This mode
allows the user to synchronize the A/D conversion to an
external clock either to have precise control of the internal
bit test timing or to provide a precise conversion time. As in
CONVST
13
Figure 19, this mode works when the SCLK frequency is
very low (less than 30kHz). However, the external conversion clock must be between 30kHz and 9MHz to maintain
accuracy. If more than 16 SCLKs are provided, more zeros
will be filled in after the data word indefinitely. To select the
external conversion clock, apply an external conversion
clock to EXTCLKIN. The external SCLK is applied to SCLK.
RD can be used to gate the external SCLK such that data will
be clocked out only after RD goes low.
6
CONVST EXTCLKIN
BUSY
CLKOUT
14
INT
µP OR DSP
LTC1417
12
RD
7
SCLK
DOUT
tdEXTCLKIN 1
2
3
4
5
6
7
8
C0
SCK
9
MISO
9 10 11 12 13 14 15 16
1
2
3
EXTCLKIN
t2
t4
CONVST
t10
t3
t5
SAMPLE
HOLD
BUSY
t6
t9
RD
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
SCLK
t7
Hi-Z
DOUT
t8
D13 12 11 10 9
8
7
6
5
4
3
2
1
FILL
ZEROS
0
Hi-Z
(SAMPLE N)
tCONV
DATA N
t LSCLK
SCLK
VIL
t HSCLK
t11
t12
DOUT
D12
D13
D11
VOH
VOL
1417 F20
CAPTURE ON
RISING CLOCK
Figure 20. External Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY↑ Indicates End of Conversion
22
CAPTURE ON
FALLING CLOCK
4
LTC1417
U
TYPICAL APPLICATIONS
Figure 21 shows the connections necessary for interfacing
the LTC1417 and LTC1391 8-channel signal acquisition
system to an SPI port. With the sample software routine
shown in Listing A, the SPI uses MOSI to send serial data
to the LTC1391 8-channel multiplexer, selecting one of
eight MUX channels.
While data is sent to the LTC1391, SPI uses MISO to
retrieve conversion data from the LTC1417. After the data
transfer is complete, the conversion start signal is sent to
the LTC1417. The end of conversion is signaled by a logic
high on the BUSY output. When this occurs, data is
exchanged between the LTC1417/LTC1391 and the
controller.
The timing diagram in Figure 22 shows the relation between MUX channel selection data and the conversion
data that are simultaneously exchanged. There is a two
conversion delay between the MUX data selects a given
channel and when that channel’s data is retrieved.
5V
5V
0.1µF
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
1
2
3
4
5
6
7
8
V+
S0
S1
D
LTC1391
S2
S3
S4
S5
V–
DOUT
DIN
CS
S6
CLK
S7
DGND
10µF
16
15
1
AIN+
2
AIN–
1µF
14
3
10µF
13
4
NC
12
5
11
6
5V
10
9
7
NC
8
VDD
LTC1417
VREF
REFCOMP
AGND
VSS
BUSY
CONVST
RD
EXTCLKIN
SHDN
SCLK
DGND
CLKOUT
DOUT
16
15
14
PORT C, BIT 7
13
12
PORT C, BIT 0
SS
11
10
MC68HC11
9
MISO
CLK
MOSI
1417 F21
Figure 21. 0V to 4.096V, 8-Channel Data Acquisition System Configured
for Control and Data Retrieval by a 68HC11 µC. Code is Shown in Listing A
23
LTC1417
U
TYPICAL APPLICATIONS
Listing A
***********************************************************************
*
*
* This example program retrieves data from a previous LTC1417
*
* conversion and loads the next LTC1391 MUX channel. It stores the
*
* 14-bit, right justified data in two consecutive memory locations.
*
* It finishes by initiating the next conversion.
*
*
*
***********************************************************************
*
************************************
* 68HC11 register definitions
*
************************************
*
PIOC
EQU
$1002 Parallel I/O control register
*
“STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB”
PORTC EQU
$1003 Port C data register
*
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
DDRC
EQU
$1007 Port D data direction register
*
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
*
1 = output, 0 = input
PORTD EQU
$1008 Port D data register
*
“ - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD “
DDRD
EQU
$1009 Port D data direction register
SPCR
EQU
$1028 SPI control register
*
“SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”
SPSR
EQU
$1029 SPI status register
*
“SPIF,WCOL, - ,MODF; - , - , - , - “
SPDR
EQU
$102A SPI data register; Read-Buffer; Write-Shifter
*
* RAM variables to hold the LTC1417’s 14 conversion result
*
DIN1
EQU
$00
This memory location holds the LTC1417’s bits 13 - 08
DIN2
EQU
$01
This memory location holds the LTC1417’s bits 07 - 00
MUX
EQU
$02
This memory location holds the MUX address data
*
*******************************************
* Start GETDATA Routine
*
*******************************************
*
ORG
$C000 Program start location
INIT1 LDAA
#$03
0,0,0,0,0,0,1,1
*
“STAF=0,STAI=0,CWOM=0,HNDS=0, OIN=0, PLS=0, EGA=1,INVB=1”
STAA
PIOC
Ensures that the PIOC register’s status is the same
*
as after a reset, necessary of simple Port D manipulation
LDAA
#$01
0,0,0,0,0,0,0,1
*
“Bit7=input,- ,- ,- ,- ,- ,- ,Bit0=output”
*
Bit7 used for BUSY signal input, Bit0 used for CONVST
*
signal output
STAA
DDRC
The direction of PortD’s bits are now set
LDAA
PORTC Get contents of Port C
ORAA
#%00000001
Set Bit0 high
STAA
PORTC Initialize CONVST to a logic high
LDAA
#$2F
-,-,1,0;1,1,1,1
*
-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
STAA
PORTD Keeps SS* a logic high when DDRD, bit 5 is set
LDAA
#$38
-,-,1,1;1,0,0,0
STAA
DDRD
SS* , SCK, MOSI are configured as Outputs
*
MISO, TxD, RxD are configured as Inputs
* DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output
LDAA
#$50
STAA
SPCR
The SPI is configured as Master, CPHA = 0, CPOL = 0
*
and the clock rate is E/2
24
LTC1417
U
TYPICAL APPLICATIONS
*
(This assumes an E-Clock frequency of 4MHz. For higher
*
E-Clock frequencies, change the above value of $50 to a
*
value that ensures the SCK frequency is 2MHz or less.)
GETDATAPSHX
PSHY
PSHA
*
*****************************************
* Setup indecies
*
*****************************************
*
LDX
#$0
The X register is used as a pointer to the memory
*
locations that hold the conversion data
LDY
#$1000
*
*****************************************
* The next short loop ensures that the *
* LTC1417’s conversion is finished
*
* before starting the SPI data transfer *
*****************************************
*
CONVENDLDAA
PORTC
Retrieve the contents of port D
ANDA
#%10000000
Look at Bit7
*
Bit7 = Hi; the LTC1417’s conversion is complete
*
Bit7 = Lo; the LTC1417’s conversion is not
*
complete
BPL
CONVEND
Branch to the loop’s beginning while Bit7 remains
*
low
*
*************************************************************************
* This routine sends data to the LTC1417 and sets its MUX channel. The *
* very first time this routine is entered produces invalid data. Each
*
* time thereafter, the data will correspond to the previous active
*
* CONVST signal sent to the LTC1417.
*
*************************************************************************
*
LDAA
#$00
Dummy value for upper byte of 16-bit SPI transfer
BCLR
PORTD,Y %00100000
This sets the SS* output bit to a logic
*
low, selecting the LTC1417
STAA
SPDR
Transfer Accum. A contents to SPI register to initiate
*
serial transfer
WAITMX1 LDAA SPSR
Get SPI transfer status
BPL
WAITMX1If the transfer is not finished, read status
LDAA
SPDR
Load accumulator A with the current byte of LTC1417 data
*
that was just received
STAA
DIN1
Transfer the LTC1417’s high byte (Bit13 - Bit6) to memory
LDAA
MUX
Retrieve MUX address
ORAA
#$08
Set the MUX’s ENABLE bit
STAA
SPDR
Transfer Accum. A contents to SPI register to initiate
*
serial transfer
WAITMX2 LDAA SPSR
Get SPI transfer status
BPL
WAITMX2If the transfer is not finished, read status
BSET
PORTD,Y %00100000
This sets the SS* output bit to a logic
*
high, de-selecting the LTC1417
LDAA
SPDR
Load accumulator A with the current byte of LTC1417 data
*
that was just received
STAA
DIN2
Transfer the LTC1417’s low byte (Bit5 - Bit0) to memory
LDD
DIN1
Load the contents of DIN1 and DIN2 into the double
*
accumulator D
LSRD
LSRD
Two logical shifts to the right to right justify the
*
14-bit conversion results
STD
DIN1
Place right justified result back in memory
25
LTC1417
U
TYPICAL APPLICATIONS
*
*****************************************
* Initiate a LTC1417 conversion
*
*****************************************
*
BCLR
PORTC,Y %00000001
This sets PORTC, Bit0 output to a logic
*
low, initiating a conversion
BSET
PORTC,Y %00000001
This resets PORTC, Bit0 output to a logic
*
high, returning CONVST to a logic high
*
PULA
Restore the A register
PULY
Restore the Y register
PULX
Restore the X register
RTS
CONVST
BUSY
RD
MUX
DATA
CH1
CH2
CH3
CH4
CH5
ADC
DATA
CH7
CH0
CH1
CH2
CH3
MUX
OUT
1417 F22
CH0
CH1
CH2
CH3
CH4
Figure 22. This Diagram Shows the Relationship Between the Selected LTC1391 MUX Channel and the Conversion Data Retrieved
from the LTC1417 When Using the Sample Program in Listing A. At Any Point in Time, a Two Conversion Delay Exists Between the
Selected MUX Channel and When Its Data Is Retrieved
26
LTC1417
U
TYPICAL APPLICATIONS
Figure 23 uses the DG408 to select one of eight ±2.048V
bipolar signals and apply it to the LTC1417’s analog input.
The circuit is designed to connect to a 68HC11 µC. The
MUX’s parallel input is connected to the controller’s port
C and the LTC1417’s serial interface is accessed through
the controller’s SPI interface.
5V
The sequence to generate a conversion is shown in sample
program Listing B. The first step selects a MUX channel.
This is followed by initiating a conversion and waiting for
BUSY to go high, signifying end of conversion. Once BUSY
goes low, the SPI is used to retrieve the 14-bit conversion
data. The timing relationships between the various control
signals and data transmission are shown in Figure 24.
– 5V
5V
– 5V
0.1µF
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
1
2
3
4
5
6
7
8
S1
V+
13
S2
V–
3
DG408
S3
S4
GND
EN
S5
A2
S6
A1
S7
A0
S8
D
14
1
AIN+
2
AIN–
1µF
0.1µF
3
10µF
2
4
5
5V
6
7
NC
8
VDD
LTC1417
VREF
REFCOMP
AGND
VSS
BUSY
CONVST
RD
EXTCLKIN
SHDN
SCLK
DGND
CLKOUT
DOUT
16
15
14
13
PORT C, BIT 7
PORT C, BIT 6
12
11
10
9
SS
MISO
MC68HC11
CLK
PORT C, BIT 2
PORT C, BIT 1
PORT C, BIT 0
1417 F23
Figure 23. With an Input Range of ±2.048V for Each of Eight Inputs,
This Data Acquisition System is Configured for Communication with the 68HC11 µC
27
LTC1417
U
TYPICAL APPLICATIONS
Listing B
*************************************************************************
*
*
* This example program selects a DG408 MUX channel using parallel
*
* port C, initiates a conversion, and retrieves data from the LTC1417. *
* It stores the 14-bit, right justified data in two consecutive memory *
* locations.
*
*
*
*************************************************************************
*
*****************************************
* 68HC11 register definitions
*
*****************************************
*
PIOC
EQU
$1002 Parallel I/O control register
*
“STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB”
PORTC EQU
$1003 Port C data register
*
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
DDRC
EQU
$1007 Port D data direction register
*
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
*
1 = output, 0 = input
PORTD EQU
$1008 Port D data register
*
“ - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD “
DDRD
EQU
$1009 Port D data direction register
SPCR
EQU
$1028 SPI control register
*
“SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”
SPSR
EQU
$1029 SPI status register
*
“SPIF,WCOL, - ,MODF; - , - , - , - “
SPDR
EQU
$102A SPI data register; Read-Buffer; Write-Shifter
*
* RAM variables to hold the LTC1417’s 14 conversion result
*
DIN1
EQU
$00
This memory location holds the LTC1417’s bits 13 - 08
DIN2
EQU
$01
This memory location holds the LTC1417’s bits 07 - 00
MUX
EQU
$02
This memory location holds the MUX address data
*
*****************************************
* Start GETDATA Routine
*
*****************************************
*
ORG
$C000 Program start location
INIT1 LDAA
#$03
0,0,0,0,0,0,1,1
*
“STAF=0,STAI=0,CWOM=0,HNDS=0, OIN=0, PLS=0, EGA=1,INVB=1”
STAA
PIOC
Ensures that the PIOC register’s status is the same
*
as after a reset, necessary of simple Port D manipulation
LDAA
#$47
0,1,0,0,0,1,1,1
*
“Bit7=input,Bit6=output,- ,- ,- ,Bit2=output,Bit1=output,
*
Bit0=output”
*
Bit7 used for BUSY input
*
Bit6 used for CONVST signal output
*
Bits 2 - 0 are used for the MUX address
STAA
DDRC
Direction of PortD’s bit are now set
LDAA
#$2F
-,-,1,0;1,1,1,1
*
-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
STAA
PORTD Keeps SS* a logic high when DDRD, Bit5 is set
LDAA
#$38
-,-,1,1;1,0,0,0
STAA
DDRD
SS* , SCK, MOSI are configured as Outputs
*
MISO, TxD, RxD are configured as Inputs
* DDRD’s Bit5 is a 1 so that port D’s SS* pin is a general output
LDAA
#$50
STAA
SPCR
The SPI is configured as Master, CPHA = 0, CPOL = 0
*
and the clock rate is E/2
*
(This assumes an E-Clock frequency of 4MHz. For higher
28
LTC1417
U
TYPICAL APPLICATIONS
*
E-Clock frequencies, change the above value of $50 to a
*
value that ensures the SCK frequency is 2MHz or less.)
GETDATAPSHX
PSHY
PSHA
*
*****************************************
* Setup indecies
*
*****************************************
*
LDX
#$0
The X register is used as a pointer to the memory
*
locations that hold the conversion data
LDY
#$1000
*
*****************************************
* Initialize the LTC1417’s CONVST input *
* to a logic high before a conversion
*
* start
*
*****************************************
*
BSET
PORTC,Y %01000000
This sets PORTC, Bit6 output to a logic
*
high, forcing CONVST to a logic high
*
*****************************************
* Retrieve the MUX address from memory *
* and send it to the DG408
*
*****************************************
*
LDAA
PORTC Capture the contents of PortC
ORAA
MUX
“Add” the MUX address
STAA
PORTC Select the MUX channel
*
*****************************************
* Initiate a LTC1417 conversion
*
*****************************************
*
BCLR
PORTC,Y %01000000
This sets PORTC, Bit6 output to a logic
*
low, initiating a conversion
BSET
PORTC,Y %01000000
This resets PORTC, Bit6 output to a logic
*
high, returning CONVST to a logic high
*
*****************************************
* The next short loop ensures that the *
* LTC1417’s conversion is finished
*
* before starting the SPI data transfer *
*****************************************
*
CONVENDLDAA
PORTC
Retrieve the contents of port D
ANDA
#%10000000
Look at Bit7
*
Bit7 = Hi; the LTC1417’s conversion is complete
*
Bit7 = Lo; the LTC1417’s conversion is not
*
complete
BPL
CONVEND
Branch to the loop’s beginning while Bit7
*
remains high
*
*************************************************************************
* This routine sends data to the LTC1417 and sets its MUX channel. The *
* very first time this routine is entered produces invalid data. Each
*
* time thereafter, the data will correspond to the previous active
*
* CONVST signal sent to the LTC1417.
*
*************************************************************************
*
29
LTC1417
U
TYPICAL APPLICATIONS
BCLR
*
TRFLP1 LDAA
STAA
*
WAIT1 LDAA
*
BPL
*
*
LDAA
*
STAA
INX
CPX
BNE
*
BSET
*
LDD
*
LSRD
LSRD
*
STD
PULA
PULY
PULX
RTS
PORTD,Y %00100000
This sets the SS* output bit to a logic
low, selecting the LTC1417
#$0
Load accumulator A with a null byte for SPI transfer
SPDR
This writes the byte into the SPI data register and
starts the transfer
SPSR
This loop waits for the SPI to complete a serial
transfer/exchange by reading the SPI Status Register
WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR’s
MSB and is set to one at the end of an SPI transfer. The
branch will occur while SPIF is a zero.
SPDR
Load accumulator A with the current byte of LTC1417 data
that was just received
0,X
Transfer the LTC1417’s data to memory
Increment the pointer
#DIN2+1Has the last byte been transferred/exchanged?
TRFLP1 If the last byte has not been reached, then proceed to
the next byte for transfer/exchage
PORTD,Y %00100000
This sets the SS* output bit to a logic
high, de-selecting the LTC1417
DIN1
Load the contents of DIN1 and DIN2 into the double
accumulator D
Two logical shifts to right justify the 14-bit
conversion results
Return right justified data to memory
Restore the A register
Restore the Y register
Restore the X register
DIN1
CONVST
BUSY
RD
CH5
SCLK
CH0 DATA
DOUT
MUX
DATA
CH0
CH1 DATA
CH1
CH2 DATA
CH2
CH3 DATA
CH3
1417 F24
Figure 24. Using the Sample Program In Listing 2, the LTC1417, Combined with the DG408 8-Channel MUX,
Has No Latency Between the Selected Input Voltage and Its Conversion Data as Shown In the Timing Relationship Above
30
LTC1417
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
0.009
(0.229)
REF
2 3
4
5 6
0.053 – 0.068
(1.351 – 1.727)
7
8
0.004 – 0.0098
(0.102 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.025
(0.635)
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
GN16 (SSOP) 0398
31
LTC1417
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
ADCs
LTC1274/LTC1277
Low Power, 12-Bit, 100ksps ADCs with Parallel Output
10mW Power Dissipation, Parallel/Byte Interface
LTC1401
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LTC1404
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LTC1412
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Best Dynamic Performance, SINAD = 72dB at Nyquist
LTC1415
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LTC1416
Low Power, 14-Bit, 400ksps ADC with Parallel Output
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LTC1418
Low Power, 14-Bit, 200ksps ADC with Parallel and Serial I/O
True 14-Bit Linearity, 81.5dB, SINAD, 15mW Dissipation
LTC1419
Low Power, 14-Bit, 800ksps ADC with Parallel Output
True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipaton
LTC1604
16-Bit, 333ksps Sampling ADC with Parallel Output
±2.5V Input, 90dB SINAD, 100dB THD
LTC1605
Single 5V, 16-Bit, 100ksps ADC with Parallel Output
Low Power, ±10V Inputs, Parallel/Byte Interface
LTC1595
Serial 16-Bit CMOS Mulitplying DAC in SO-8
±1LSB Max INL/DNL, 1nV • sec Glitch, DAC8043 Upgrade
LTC1596
Serial 16-Bit CMOS Mulitplying DAC
±1LSB Max INL/DNL, DAC8143/AD7543 Upgrade
LTC1650
Serial 16-Bit ±5V Voltage Output DAC
Low Noise and Low Glitch Rail-to-Rail VOUT
LTC1655
Serial 16-Bit Voltage Output DAC
Low Power, SO-8 with Internal Reference
LTC1658
Serial 14-Bit Voltage Output DAC
Low Power, 8-Lead MSOP Rail-to-Rail VOUT
LT1019-2.5
Precision Bandgap Reference
0.05% Max, 5ppm/°C Max
LT1460-2.5
Micropower 3-Termainal Bandgap Reference
0.075% Max, 10ppm/°C Max
LT1461-2.5
Ultraprecise Micropower Low Dropout Reference
0.04%, 3ppm/°C
DACs
Reference
32
Linear Technology Corporation
1417fs sn1417 LT/TP 0100 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1999