M48Z08 M48Z18 5V, 64 Kbit (8Kb x 8) ZEROPOWER® SRAM FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ ■ INTEGRATED, ULTRA LOW POWER SRAM AND POWER-FAIL CONTROL CIRCUIT UNLIMITED WRITE CYCLES READ CYCLE TIME EQUALS WRITE CYCLE TIME AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): – M48Z08: VCC = 4.75 to 5.5V 4.5V ≤ VPFD ≤ 4.75V – M48Z18: VCC = 4.5 to 5.5V 4.2V ≤ VPFD ≤ 4.5V SELF-CONTAINED BATTERY IN THE CAPHAT™ DIP PACKAGE PIN AND FUNCTION COMPATIBLE WITH JEDEC STANDARD 8K x 8 SRAMs RoHS COMPLIANCE Lead-free components are compliant with the RoHS Directive. Figure 1. 28-pin CAPHAT, DIP Package 28 1 PCDIP28 (PC) Battery CAPHAT™ Rev 5.0 December 2005 1/16 M48Z08, M48Z18 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. 28-pin CAPHAT, DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Table 1. Figure 3. Figure 4. Logic Diagram . . Signal Names . . DIP Connections Block Diagram . . ................... ................... ................... ................... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....3 .....3 .....3 .....4 OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. WRITE Enable Controlled, WRITE Mode AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 7. Chip Enable Controlled, WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. AC Testing Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline . . . . . . . . . . . . . . . . 13 Table 11. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data. . . . . . . . . 13 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 M48Z08, M48Z18 SUMMARY DESCRIPTION The M48Z08/18 ZEROPOWER® RAM is a 8K x 8 non-volatile static RAM which is pin and functional compatible with the DS1225. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution. The M48Z08/18 is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 28-pin, 600mil DIP CAPHAT™ houses the M48Z08/18 silicon with a long life lithium button cell in a single package. Figure 2. Logic Diagram Table 1. Signal Names VCC A0-A12 Address Inputs DQ0-DQ7 Data Inputs / Outputs E Chip Enable G Output Enable W WRITE Enable E VCC Supply Voltage G VSS Ground NC Not Connected Internally 13 8 A0-A12 W DQ0-DQ7 M48Z08 M48Z18 VSS AI01022 Figure 3. DIP Connections NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 M48Z08 22 M48Z18 21 8 9 20 10 19 11 18 12 17 13 16 14 15 VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 AI01183 3/16 M48Z08, M48Z18 Figure 4. Block Diagram A0-A12 LITHIUM CELL POWER VOLTAGE SENSE AND SWITCHING CIRCUITRY 8K x 8 SRAM ARRAY DQ0-DQ7 E VPFD W G VSS VCC AI01394 OPERATION MODES The M48Z08/18 also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data until valid power returns. Table 2. Operating Modes Mode VCC Deselect WRITE READ 4.75 to 5.5V or 4.5 to 5.5V READ E G W DQ0-DQ7 Power VIH X X High Z Standby VIL X VIL DIN Active VIL VIL VIH DOUT Active VIL VIH VIH High Z Active Deselect VSO to VPFD(min)(1) X X X High Z CMOS Standby Deselect ≤ VSO(1) X X X High Z Battery Back-up Mode Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10., page 12 for details. 4/16 M48Z08, M48Z18 READ Mode The M48Z08/18 is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 65,536 locations in the static storage array. Thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next address access. Figure 5. READ Mode AC Waveforms tAVAV A0-A12 VALID tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI01385 Note: WRITE Enable (W) = High. Table 3. READ Mode AC Characteristics Symbol Parameter(1) M48Z08/M48Z18 Unit Min Max tAVAV READ Cycle Time tAVQV Address Valid to Output Valid 100 ns tELQV Chip Enable Low to Output Valid 100 ns tGLQV Output Enable Low to Output Valid 50 ns 100 ns tELQX(2) Chip Enable Low to Output Transition 10 ns tGLQX(2) Output Enable Low to Output Transition 5 ns tEHQZ(2) Chip Enable High to Output Hi-Z 50 ns tGHQZ(2) Output Enable High to Output Hi-Z 40 ns tAXQX Address Transition to Output Transition 5 ns Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 30pF. 5/16 M48Z08, M48Z18 WRITE Mode WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. The M48Z08/18 is in the WRITE Mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Figure 6. WRITE Enable Controlled, WRITE Mode AC Waveform tAVAV VALID A0-A12 tAVWH tWHAX tAVEL E tWLWH tAVWL W tWLQZ tWHQX tWHDX DQ0-DQ7 DATA INPUT tDVWH AI01386 Figure 7. Chip Enable Controlled, WRITE Mode AC Waveforms tAVAV VALID A0-A12 tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI01387B 6/16 M48Z08, M48Z18 Table 4. WRITE Mode AC Characteristics Symbol Parameter(1) tAVAV WRITE Cycle Time tAVWL M48Z08/M48Z18 Unit Min Max 100 ns Address Valid to WRITE Enable Low 0 ns tAVEL Address Valid to Chip Enable 1 Low 0 ns tWLWH WRITE Enable Pulse Width 80 ns tELEH Chip Enable Low to Chip Enable 1 High 80 ns tWHAX WRITE Enable High to Address Transition 10 ns tEHAX Chip Enable High to Address Transition 10 ns tDVWH Input Valid to WRITE Enable High 50 ns tDVEH Input Valid to Chip Enable 1 High 30 ns tWHDX WRITE Enable High to Input Transition 5 ns tEHDX Chip Enable High to Input Transition 5 ns tWLQZ(2,3) WRITE Enable Low to Output Hi-Z 50 ns tAVWH Address Valid to WRITE Enable High 80 ns tAVEH Address Valid to Chip Enable High 80 ns WRITE Enable High to Output Transition 10 ns tWHQX(2,3) Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 30pF. 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. 7/16 M48Z08, M48Z18 Data Retention Mode VCC Noise And Negative Going Transients With valid VCC applied, the M48Z08/18 operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as “Don't care.” Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z08/18 may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data. The internal button cell will maintain data in the M48Z08/18 for an accumulated period of at least 11 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). E should be kept high as VCC rises past VPFD (min) to prevent inadvertent write cycles prior to system stabilization. Normal RAM operation can resume trec after VCC exceeds VPFD (max). For more information on Battery Storage Life refer to the Application Note AN1012. ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure 8.) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 8. Supply Voltage Protection VCC VCC 0.1µF DEVICE VSS AI02169 8/16 M48Z08, M48Z18 MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 5. Absolute Maximum Ratings Symbol TA TSTG TSLD(1) Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Value Unit 0 to 70 °C –40 to 85 °C 260 °C VIO Input or Output Voltages –0.3 to 7 V VCC Supply Voltage –0.3 to 7 V IO Output Current 20 mA PD Power Dissipation 1 W Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. 9/16 M48Z08, M48Z18 DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. Operating and AC Measurement Conditions Parameter M48Z08 M48Z18 Unit 4.75 to 5.5 4.5 to 5.5 V 0 to 70 0 to 70 °C Load Capacitance (CL) 100 100 pF Input Rise and Fall Times ≤5 ≤5 ns 0 to 3 0 to 3 V 1.5 1.5 V Supply Voltage (VCC) Ambient Operating Temperature (TA) Input Pulse Voltages Input and Output Timing Ref. Voltages Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 9. AC Testing Load Circuit 5V 1.8kΩ DEVICE UNDER TEST OUT 1kΩ CL = 100pF or 30pF CL includes JIG capacitance AI01398 Table 7. Capacitance Parameter(1,2) Symbol CIN CIO(3) Min Max Unit Input Capacitance 10 pF Input / Output Capacitance 10 pF Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25°C, f = 1MHz. 3. Outputs deselected. 10/16 M48Z08, M48Z18 Table 8. DC Characteristics Symbol ILI ILO(2) Parameter Input Leakage Current Output Leakage Current Test Condition(1) Min Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±1 µA Outputs open 80 mA E = VIH 3 mA E = VCC – 0.2V 3 mA ICC Supply Current ICC1 Supply Current (Standby) TTL ICC2 Supply Current (Standby) CMOS VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2.2 VCC + 0.3 V VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage IOH = –1mA 2.4 V Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. Outputs deselected. 11/16 M48Z08, M48Z18 Figure 10. Power Down/Up Mode AC Waveforms VCC VPFD (max) VPFD (min) VSO tF tDR tPD INPUTS tR tFB tRB tREC DON'T CARE RECOGNIZED NOTE RECOGNIZED HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) AI00606 Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD (min). Some systems may perform inadvertent WRITE cycles after VCC rises above VPFD (min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system is running. Table 9. Power Down/Up AC Characteristics Symbol Parameter(1) tPD E or W at VIH before Power Down tF(2) tFB(3) Min Max Unit 0 µs VPFD (max) to VPFD (min) VCC Fall Time 300 µs VPFD (min) to VSS VCC Fall Time 10 µs tR VPFD (min) to VPFD (max) VCC Rise Time 0 µs tRB VSS to VPFD (min) VCC Rise Time 1 µs trec E or W at VIH before Power Up 2 ms Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. Table 10. Power Down/Up Trip Points DC Characteristics Symbol Parameter(1,2) VPFD Power-fail Deselect Voltage VSO Battery Back-up Switchover Voltage tDR(3) Expected Data Retention Time Min Typ Max Unit M48Z08 4.5 4.6 4.75 V M48Z18 4.2 4.3 4.5 V 3.0 11 Note: 1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 3. At 25°C, VCC = 0V. 12/16 V YEARS M48Z08, M48Z18 PACKAGE MECHANICAL INFORMATION Figure 11. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline A2 A1 B1 B A L C e1 eA e3 D N E 1 PCDIP Note: Drawing is not to scale. Table 11. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data mm inches Symb Typ Min Max A 8.89 A1 Typ Min Max 9.65 0.350 0.380 0.38 0.76 0.015 0.030 A2 8.38 8.89 0.330 0.350 B 0.38 0.53 0.015 0.021 B1 1.14 1.78 0.045 0.070 C 0.20 0.31 0.008 0.012 D 39.37 39.88 1.550 1.570 E 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 eA 15.24 16.00 0.600 0.630 L 3.05 3.81 0.120 0.150 N 28 28 13/16 M48Z08, M48Z18 PART NUMBERING Table 12. Ordering Information Scheme Example: M48Z 08 –100 PC 1 TR Device Type M48Z Supply Voltage and Write Protect Voltage 08(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 18 = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V Speed –100 = 100ns Package PC = PCDIP28 Temperature Range 1 = 0 to 70°C Shipping Method blank = ECOPACK Package, Tubes TR = ECOPACK Package, Tape & Reel Note: 1. The M48Z08/18 part is offered with the PCDIP28 (e.g., CAPHAT™) package only. For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you. 14/16 M48Z08, M48Z18 REVISION HISTORY Table 13. Document Revision History Date Version Revision Details March 1999 1.0 First issue 19-Jul-01 2.0 2-socket SOH and 2-pin SH packages removed; reformatted; temperature information added to tables (Table 7, 8, 3, 4, 9, 10) 19-Dec-01 2.1 Remove all references to “clock” 21-Dec-01 2.2 Changes to text to reflect addition of M48Z08Y option 20-May-02 2.3 Modify reflow time and temperature footnotes (Table 5) 10-Sep-02 2.4 Remove all references to “SNAPHAT” and M48Z08Y part (Figure 2; Table 5, 6, 3, 4, 10, 12) 01-Apr-03 3.0 v2.2 template applied; updated test condition (Table 10) 28-Aug-04 4.0 Reformatted; removed references to ‘crystal’ (Figure 1) 14-Dec-05 5.0 Updated template, Lead-free text, removed footnote (Table 8, 12) 15/16 M48Z08, M48Z18 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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