LINER LTC5800WR 2.4 ghz 802.15.4 eternatm embedded network manager-on-chip Datasheet

Advanced Information
S m a r t M e s h® I P
LTC5800-IPR
2.4 GHz 802.15.4 Eterna
TM
Embedded Network Manager-on-Chip
About SmartMesh IP
Dust Networks’ new standards-based SmartMesh® IP product line achieves unsurpassed levels of networking resilience and reliability, with
advanced network management and comprehensive security. Based on Dust’s breakthrough Eterna™ SoC technology, SmartMesh IP
enables up to 8 times lower power consumption than competing solutions even in harsh, dynamically changing RF environments. Cost
effective, IP (Internet Protocol) compatible, and widely applicable, SmartMesh IP serves an extensive range of applications, such as energy
management, building automation, renewable energy, and other implementations in smart infrastructure that call for ultra low power..
Product Descriptions – LTC5800-IPR
Based on the ITEF 6LoWPAN and IEEE 802.15.4e Standards, the LTC5800-IPR SmartMesh IP embedded network manager-on-chip
anchors the SmartMesh IP product line. It serves not only as a wireless-to-wired access point, but more importantly provides the core
networking functionality, enabling the network to achieve unsurpassed levels of resiliency, reliability, and scalability. The LTC5800-IPR
continuously optimizes the network and provides robustness in the face of constantly changing RF environments. Furthermore, the network
manager’s load balancing algorithms add more bandwidth for the busiest motes while maintaining traffic flow for the rest of the network.
The LTC5800-IPR combines Dust Networks’ robust sensor networking solution with Dust’s breakthrough EternaTM SoC Technology in an
easy-to-integrate 72-pin 10 mm x 10 mm QFN package. As part of the SmartMesh IP system, the LTC5800-IPR enables customers to
integrate a standards-based wireless network into sensors and actuators to provide scalable bidirectional communications.
The manager offers a comprehensive application programming interface (API) via a UART interface, providing full visibility and control
over network configuration, security administration, network status, and performance statistics. The LTC5800-IPR integrates all radio
circuitry components and requires only an AC coupling capacitor and an antenna for robust wireless connectivity. With its combination of
low power, compact easy-to-integrate form factor, and sophisticated network management, the LTC5800-IPR embedded network manager
is ideally suited for deploying resilient, reliable mesh networks in a wide variety of environments and applications.
Key Product Features
SmartMesh IP Mesh Networking Performance
•
•
•
•
•
•
Advanced network management—dynamically optimizes
mesh connectivity based on the changing RF environment
Load balancing & optimization—adds bandwidth for the
busiest motes while maintaining normal traffic flow for the
rest of network
Intelligent power management—balances traffic so that
power consumption is also balanced within the network
Battery powered routers
Auto-forming, self-healing, self-sustaining—automatically
configures and maintains the network without requiring onsite wireless expertise.
Compact manager design manages networks up to 32 motes
Time Synchronized Mesh Networking
•
•
•
Zero collision packet exchange—for scalability and
efficiency
Time-synchronized channel hopping seamlessly
compensates for in band blocking and multipath fading in
dynamic RF environments
Highly Accurate Time Stamping
Full Application Flexibility
•
•
Dynamic bandwidth—creates temporary high bandwidth
“pipes”
Low latency mode—mode for fastest packet transfer Industryleading radio technology capable of line-powered, batterypowered, or energy-scavenging operation
Ultra-low Power Operation
•
Industry-leading radio technology capable of line-powered,
battery-powered, or energy-scavenging operation
IP Standards Compliance
•
Compliant to IETF 6LoWPAN and IEEE 802.15.4e standards
Easy to Integrate and Deploy
•
•
Fully engineered RF transceiver, with power amplifier (PA),
integrated balun, and antenna matching circuitry
Comprehensive APIs provide a rich and flexible functionality
to ease software development and device integration
Secure Global Market Solution
•
•
Operates on 2.4 GHz global license-free band, providing
customers with a single product for world-wide use
AES-128 bit encryption
Linear Technology / Dust Networks
Advanced Information
Table of Contents
General ..............................................................................................................4
1.0
1.1
Related Documentation ..................................................................................... 4
1.2
Conventions..................................................................................................... 4
1.2.1 Signal Naming .............................................................................................. 4
1.2.2 Number Format ............................................................................................ 4
2.0
Introduction .......................................................................................................5
2.1
Power Supply ................................................................................................... 5
2.1.1 Supply Monitoring and Reset .......................................................................... 6
2.2
Precision Timing ............................................................................................... 6
2.2.1 Time Synchronization .................................................................................... 6
2.3
Time References............................................................................................... 6
2.3.1 Relaxation Oscillator...................................................................................... 6
2.3.2 32.768 kHz Crystal ....................................................................................... 6
2.3.3 20 MHz Crystal ............................................................................................. 6
2.4
Radio .............................................................................................................. 6
2.5
UARTs............................................................................................................. 7
2.5.2 API UART Protocol......................................................................................... 7
2.5.3 CLI UART..................................................................................................... 8
2.6
Autonomous MAC ............................................................................................. 8
2.7
Security .......................................................................................................... 8
2.8
Temperature Sensor ......................................................................................... 8
2.8.1 Radio Inhibit ................................................................................................ 8
2.8.2 Sleep .......................................................................................................... 9
2.10 Flash Programming ........................................................................................... 9
3.0
SmartMesh Intelligent Networking Platform ......................................................9
3.1
Dynamic Network Optimization ........................................................................... 9
3.2
Deterministic Power Management ....................................................................... 9
3.3
Intelligent Routing ............................................................................................ 9
3.4
Bandwidth Flexibility ......................................................................................... 9
4.0
Operation .........................................................................................................10
4.1
Start Up .........................................................................................................10
4.1.1 Fuse Table ..................................................................................................10
4.2
Serial Flash Emulation ......................................................................................11
4.3
Operation .......................................................................................................11
4.3.1 Active State ................................................................................................11
4.3.2 Doze State..................................................................................................11
4.4
5.0
2
Duty Cycling and Autonomous Peripherals...........................................................11
Pinout ..............................................................................................................12
5.1
Eterna Mote-on-Chip ........................................................................................12
5.3
Power Supply ..................................................................................................14
Linear Technology / Dust Networks
Eterna Datasheet
Advanced Information
5.3.1 Antenna .....................................................................................................14
5.5
JTAG..............................................................................................................14
6.0
Absolute Maximum Ratings ..............................................................................15
7.0
Recommended Operating Conditions................................................................16
8.0
Electrical Characteristics ..................................................................................16
8.1
Radio Specifications .........................................................................................16
8.2
DC Characteristics ...........................................................................................16
8.3
Radio Receive Characteristics ............................................................................17
8.4
Radio Transmitter Characteristics.......................................................................18
8.5
Digital I/O Characteristics .................................................................................18
8.6
Temperature Sensor Characteristics ...................................................................19
8.8
System Characteristics .....................................................................................19
8.9
UART AC Characteristics ...................................................................................19
8.10 TIMEn AC Characteristics ..................................................................................20
8.11 SLEEPn AC Characteristics ................................................................................21
8.12 RADIO_INHIBIT AC Characteristics.....................................................................21
8.13 FLASH AC Characteristics..................................................................................22
8.14 Flash Programming AC Characteristics ................................................................22
9.0
Typical Performance Characteristics ................................................................23
10.0
Mechanical Details ...........................................................................................25
10.1 Mote-on-Chip ..................................................................................................25
10.3 Soldering Information ......................................................................................25
11.0
Regulatory and Standards Compliance .............................................................25
11.1 Compliance to Restriction of Hazardous Substances (RoHS) ...................................25
12.0
References .......................................................................................................26
13.0
Order Information............................................................................................26
Eterna Datasheet
Linear Technology / Dust Networks
3
Advanced Information
1.0
1.1
General
Related Documentation
• 040-0102 Eterna Integration Guide
• 040-0109 Design Specific Configuration Guide
• 040-0110 Eterna Serial Programmer Guide
1.2
Conventions
1.2.1
Signal Naming
The naming convention for Eterna signals is UPPER_CASE_SEPARATED_BY_UNDERSCORE. Active-low signals, such
as RESETn, add a trailing lower case n. An exception to the naming convention is UART transmit and receive signals which
are named consistent with industry practice as RX and TX, omitting the lower case n, despite being active low signals. The
terms assertion and active refers to a signal in a logically true state: logic ‘1’ for active high signals and logic ‘0’ for active
low signals. The terms negated and inactive refer to a signal being in its logically false state: logic ‘0’ for active high signals
and logic ‘1’ for active low signals.
1.2.2
Number Format
The 0x prefix indicates a hexadecimal number follows.
The 0b prefix indicates a binary number follows.
The lack of a prefix indicates a decimal number follows.
4
Linear Technology / Dust Networks
Eterna Datasheet
Advanced Information
Introduction
2.0
Eterna is the world’s most energy-efficient IEEE 802.15.4 compliant platform enabling battery and energy harvested
endpoint, routing and network management solutions. With a powerful 32-bit ARM® Cortex™-M3, best in class radio, flash,
RAM and purpose-built peripherals, Eterna provides a flexible, scalable and robust networking solution for applications
demanding both minimal energy consumption and data reliability in even the most challenging RF environments.
Shown in Figure 1, Eterna integrates purpose-built peripherals that excel in both low operating-energy consumption and the
ability to rapidly and precisely cycle between operating and low-power states. Items in the shaded region correspond to the
analog/RF components.
32 kHz
32 kHz, 20 MHz
Timers
Sched.
Voltage Reference
Primary
DC/DC
Converter
SRAM
72 KB
Core Regulator
Clock Regulator
Flash
512 KB
Relaxation
Oscillator
Flash
Controller
Analog Regulator
PA
DC/DC
Converter
PoR
AES
802.15.4
Mod
DAC
20 MHz
PMU /
Clock
Control
LPF
PA
Code
Auto
MAC
Cortex-M3
802.15.4
Framing
DMA
PLL
System
802.15.4
Demod
ADC
Limiter
BPF
AGC
IPCS
SPI
Slave
CLI
UART
(2 pin)
API
UART
(6-pin)
ADC
Ctrl.
10-bit
ADC
VGA
PPF
LNA
RSSI
S
PTAT
Bat.
Load
4-bit
DAC
Figure 1
Eterna Block Diagram
2.1
Power Supply
Eterna is powered from a single pin, VSUPPLY, which powers the I/O cells and is also used to generate internal supplies.
Eterna’s two on-chip DC/DC converters minimize Eterna’s energy consumption while the device is awake. To prevent power
from being wasted the DC/DC converter is disabled when the device is in low-power state. Eterna’s rejection of supply noise
is substantial owing to the two integrated DC/DC converters and three integrated low-dropout regulators. Eterna’s operating
supply range is high enough to support direct connection to Li-SClO2 sources and wide enough to support battery operation
over a broad temperature range.
Eterna Datasheet
Linear Technology / Dust Networks
5
Advanced Information
2.1.1
Supply Monitoring and Reset
Eterna integrates an Power on Reset (PoR) circuit and as the RESETn input pin is nominally configured with an internal pullup resistor, thus no connection is required. For a graceful shutdown, the software and networking layers be cleanly halted
prior to assertion of the RESETn pin. Eterna includes a soft brown-out monitor that fully protects the Flash from corruption
in the event that power is removed while writing to flash. Integrated flash supervisory functionality in conjunction with ***
(do we do a JFS?) yields a robust non-volatile file system.
2.2
Precision Timing
Eterna, differs from competing 802.15.4 product offerings by providing low-power dedicated timing hardware and timing
algorithms that provide timing precision two to three orders of magnitude better than any other available low-power solution.
Improved timing accuracy allows motes to minimize the amount of radio listening time required to ensure packet reception
thereby lowering even further the power consumed by an Eterna network. Eterna’s patented timing hardware and timing
algorithms provide superior performance over rapid temperature changes, further differentiating Eterna’s reliability when
compared with other wireless products. In addition, precise timing enables networks to reduce spectral dead time, increasing
total network throughput.
2.2.1
Time Synchronization
In addition to coordinating timeslots across the network, which is transparent to the user, Eterna’s unparalleled timing
management is used to support two mechanisms to share network time. Having an accurate, shared, network-wide time base
enables events to be accurately time stamped or tasks to be performed in a synchronized fashion across a network. Eterna
will send a time packet through its serial interface when one of the following occurs:
•
Eterna receives an HDLC request to read time
•
The TIMEn signal is asserted
The use of TIMEn has the advantage of being more accurate. The value of the timestamp is captured in hardware relative to
the rising edge of TIMEn. If the HDLC request is used, due to packet processing the value of the timestamp may be captured
several milliseconds after receipt of the packet. See Section 8.10 for the time functions definition and specifications.
2.3
Time References
Eterna includes three clock sources: a low power oscillator designed for a 32.768 kHz crystal, the radio reference oscillator
designed for a 20 MHz crystal, and an internal relaxation oscillator.
2.3.1
Relaxation Oscillator
The relaxation oscillator is the primary clock source for Eterna, providing the clock for the CPU, memory subsystems, and all
peripherals. The internal relaxation oscillator typically starts up in a few μs, providing an expedient, low-energy method for
duty cycling between active and low power states. Quick start-up from the doze state, defined in section 4.0, allows Eterna to
wake up and receive data over the UART and SPI interfaces by simply by detecting activity the appropriate signals.
2.3.2
32.768 kHz Crystal
Once Eterna is powered up and the 32.768 kHz crystal source has begun oscillating, the 32.768 kHz crystal remains
operational while in the Active state, and is used as the timing basis when in Doze state. See Section 4.0 for a description of
Eterna’s operational states.
2.3.3
20 MHz Crystal
The 20 MHz crystal source provides a frequency reference for the radio, and is automatically enabled and disabled by Eterna
as needed.
2.4
Radio
Eterna is the lowest-power commercially available 2.4 GHz IEEE 802.15.4e radio by a substantial margin. (Please refer to
section 8.2 for power consumption numbers.). Eterna’s integrated power amplifier is calibrated and temperature-compensated
to consistently provide power at a limit suitable for worldwide radio certifications. Additionally, Eterna uniquely includes a
6
Linear Technology / Dust Networks
Eterna Datasheet
Advanced Information
hardware-based autonomous MAC that handles precise sequencing of peripherals, including the transmitter, the receiver, and
AES peripherals. The hardware-based autonomous MAC minimizes CPU activity, thereby further decreasing power
consumption.
2.5
UARTs
The principal network interface is through the application programming interface (API) UART. A command-line interface
(CLI) is also provided for support of test and debug functions. Both UARTs sense activity continuously, consuming virtually
no power until data is transferred over the port and then automatically returning to their lowest power state after the
conclusion of a transfer.
2.5.2
API UART Protocol
Eterna’s API UART operates in Mode 4, incorporating optional flow control, at 115200 baud. Packets are HDLC encoded
with one stop bit and no parity bits. The flow control signals for Eterna’s API receive path are shown in Figure 5. If the flow
control signals are used (recommended) transfers are initiated from a companion processor by asserting UART_RX_RTSn.
Eterna responds by asserting UART_RX_CTSn. If flow control is used, after detecting the assertion of UART_RX_CTSn the
companion processor may send the entire packet. Following the transmission of the final byte in the packet the companion
processor negates UART_RX_RTSn and waits until the negation of UART_RX_CTSn before asserting UART_RX_RTSn
again. Flow control automatically ensures compliance with inter-packet delay requirements, so explicit delay-checking is not
required.
If flow control is not desired or needed it may be disabled by tying UART_RX_RTSn high. When flow control is not used
the companion processor may send the entire packet; in this case the companion processor must comply with the minimum
inter-packet delay as defined in section 8.9.
Figure 5
UART Mode 4 Receive Flow Control
UART Mode 4 also incorporates level-sensitive flow control for Eterna UART transmissions on the UART TX pin. Packets
are HDLC encoded with one stop bit and no parity bits. The flow control signals for TX are shown in Figure 6. A transfer
request is signaled by Eterna device asserting UART_TX_RTSn. The UART_TX_CTSn signal may be actively driven by the
companion processor when it is ready to receive a packet or it may be tied low if the companion processor will always be
ready to receive a packet. After detecting a logic ‘0’ on UART_TX_CTSn Eterna sends the entire packet. Following the
transmission of the final byte in the packet Eterna negates UART_TX_RTSn and waits for a minimum period (what is the
period called?) defined in section 8.9 before asserting UART_TX_RTSn again (if a packet needs to be transmitted)
Eterna Datasheet
Linear Technology / Dust Networks
7
Advanced Information
Figure 6
UART Mode 4 Transmit Flow Control
For details on the timing of the UART protocol, see section 8.9 (UART AC Characteristics).
2.5.3
CLI UART
The Command Line Interface (CLI) UART port is a two wire protocol (TX and RX) that operates at a fixed 9600 baud rate
with one-stop bit and no parity. The CLI UART interface is intended to support command-line instructions and response
activity.
2.6
Autonomous MAC
Eterna was designed as a system solution with the objective of providing a reliable, ultra-low power, and secure network. A
reliable network capable of dynamically optimizing operation over changing environments requires solutions that are far too
complex to completely support through hardware acceleration alone. As described in Section 2.2, proper time management is
essential for optimizing a solution that is both low power and reliable. To address this solution Eterna includes the
Autonomous MAC, which includes hardware support for controlling all of the time-critical radio operations. The
Autonomous MAC provides two benefits: first, preventing variable software latency from affecting network timing and
second, greatly reducing system power consumption by allowing the CPU to remain inactive during the majority of the radio
activity. The Autonomous MAC, unique to Eterna, provides software-independent timing control of the radio and radiorelated functions, resulting in superior reliability and exceptionally low power.
2.7
Security
Network security is an often overlooked component of a complete network solution. Proper implementation of security
protocols is significant in terms of both engineering effort and market value in an OEM product. Eterna system solutions
provide a FIPS-197 validated encryption scheme, and goes further, providing a complete set of mechanisms to protect
network security. Eterna includes hardware support for electronically locking devices, thereby preventing access to Eterna’s
flash and RAM memory. This lock-out feature provides a means to securely unlock a device should support of a product
require access. For details see 040-0109 Design Specific Configuration Guide.
2.8
Temperature Sensor
Eterna includes a calibrated temperature sensor on chip. The temperature readings are available locally through Eterna’s
serial API, in addition to being available via the network manager. The performance characteristics of the temperature sensor
can be found in Section 8.6.
2.8.1
Radio Inhibit
The RADIO_INHIBIT digital interrupt enables an external controller to temporarily disable the radio software drivers (for
example, to take a sensor reading that is susceptible to radio interference). When RADIO_INHIBIT is asserted the software
radio drivers will disallow radio operations including clear channel assessment, packet transmits, or packet receipts. If a radio
event is in progress radio inhibit will take effect after the present operation completes. For details on the timing associated
with RADIO_INHIBIT, see Section 8.12.
8
Linear Technology / Dust Networks
Eterna Datasheet
Advanced Information
2.8.2
Sleep
The SLEEPn digital interrupt enables an external controller to temporarily disable Eterna’s duty cycling between active and
Doze states (see Section 4.0 for state definitions). Forcing Eterna to the Doze state should only be done when absolutely
necessary, such as when taking a very sensitive sensor reading, as forcing a device into a Doze state will on the average
increase the energy consumption of other devices in the network. When SLEEPn is asserted the software will go into a Doze
state until the SLEEPn signal is negated. For details on the timing associated with SLEEPn, see Section 8.11.
2.10
Flash Programming
Eterna’s software images are loaded via the IPCS, in-circuit programming control system, SPI interface. Sequencing of
RESETn and FLASH_P_ENn, as described in Section 4.0, places Eterna in a state emulating a serial flash to support incircuit programming. Hardware and software for supporting development and production programming of devices is
described in 040-0110 Eterna Serial Programmer Guide. The serial protocol, SPI, and timing parameters are described in
Section 8.13.
3.0
SmartMesh Intelligent Networking Platform
The SmartMesh Eterna network manager is built upon Dust Networks’ Intelligent Networking Platform, which provides
dynamic network optimization, deterministic power management, intelligent routing, and bandwidth flexibility to achieve the
carrier class data reliability, and ultra-low power and ease of use required for industrial automation applications.
3.1
Dynamic Network Optimization
Dynamic network optimization allows Eterna to address the changing RF requirements in harsh industrial environments
resulting in a network that is continuously self-monitoring and self-adjusting. The manager performs dynamic network
optimization based upon periodic reports on network health and link quality that it receives from the network motes. The
manager uses this information to provide performance statistics to the application layer and proactively solve problems in the
network. Dynamic network optimization not only maintains network health, but also allows Eterna to deliver deterministic
power management.
3.2
Deterministic Power Management
Deterministic power management balances traffic in the network by diverting traffic around heavily loaded motes (for
example, motes with high reporting rates). In doing so, it reduces power consumption for these motes and balances power
consumption across the network. Deterministic power management provides predictable maintenance schedules to prevent
down time and lower the cost of network ownership. When combined with field devices using Eterna’s industry-leading low
power radio technology, deterministic power management enables over a decade of battery life for network motes.
3.3
Intelligent Routing
Intelligent routing provides each packet with an optimal path through the network. The shortest distance between two points
is a straight line, but in RF the quickest path is not always the one with the fewest hops. Intelligent routing finds optimal
paths by considering the link quality (one path may lose more packets than another) and the retry schedule, in addition to the
number of hops. The result is reduced network power consumption, elimination of in-network collisions, and unmatched
network scalability and reliability.
3.4
Bandwidth Flexibility
Efficient use of network resources enables Dust Networks to deliver bandwidth flexibility—the ability to assign different
levels of bandwidth to satisfy unique throughput and latency requirements. Bandwidth flexibly addresses the range of latency
and throughput needs of industrial automation applications such as request/response, fast file transfer, and alerting.
Eterna Datasheet
Linear Technology / Dust Networks
9
Advanced Information
4.0
Operation
In order to provide capabilities and flexibility in addition to ultra low power, Eterna operates in various states, as shown in
Figure 8 and described in this section.
Power-On
Reset
VSUPPLY > PoR
RESETn low and
FLASH_P_ENn low
Load Fuse
Settings
RESETn low and
FLASH_P_ENn high
Serial Flash
Emulation
Set RESETn high and
FLASH_P_EN high
for 125 µs, then
set RESETn low
Reset
De-assert RESETn
Boot
Start Up
Assert RESETn
Assert RESETn
Assert RESETn
CPU and peripherals
inactive
Doze
Deep Sleep
Active
HW or PMU Event
lowPowerSleep
Command
Operation
Figure 8
4.1
Inactive
State Diagram – Operating Modes
Start Up
Start Up occurs as a result of either tripping of the power-on-reset circuit or the assertion of RESETn. After the completion
of power-on-reset (see Section 2.1.1) or the falling edge of an internally synchronized RESETn, Eterna loads its Fuse Table
(see section 4.1.1), including setting I/O direction. In this state, Eterna checks the state of the FLASH_P_ENn and RESETn
and enters the serial flash emulation mode, if both signals are asserted. If the FLASH_P_ENn pin is not asserted but RESETn
is not asserted, Eterna automatically reduces its energy consumption to a minimum until RESETn is released. Once RESETn is deasserted, Eterna goes through a boot sequence, and then enters the Active state.
4.1.1
Fuse Table
Eterna’s Fuse Table is a 2 KB page in flash that contains two data structures, one for hardware configuration immediately
following Power on Reset or the assertion of RESETn and one for configuration of design specific parameters. Hardware
support for configuration includes configuration of I/O, preventing I/O leakage from negatively affecting current
consumption during power on, which can be a significant issue for current limited supplies. Examples of design-specific
parameters include setting of UART modes, clock sources and trim values. Fuse Tables are created via the Fuse Table
application software described in 040-0109 Design Specific Configuration Guide. Fuse Tables are loaded into flash using the
same software and in-circuit programmer used to load Eterna’s networking software image – see the 040-0110 Eterna Serial
Programmer Guide for details.
10
Linear Technology / Dust Networks
Eterna Datasheet
Advanced Information
4.2
Serial Flash Emulation
When both RESETn and FLASH_P_ENn are asserted, Eterna disables normal operation and enters a mode to emulate the
operation of a serial flash. In this mode, its flash can be programmed with software updates. For details, see Section 2.10.
4.3
Operation
Once Eterna has completed startup, Eterna transitions to the Operational group of states (active / CPU active, active / CPU
inactive, and Doze). There, Eterna cycles between the various states, automatically selecting the lowest power state possible
while fulfilling the demands of network operation.
4.3.1
Active State
In Active state, the Eterna’s relaxation oscillator is running and peripherals are enabled as needed. The ARM Cortex-M3
cycles as needed between CPU-active and CPU-inactive (referred to in the ARM Cortex-M3 literature as “Sleep Now” or
“Sleep on Exit” modes). Eterna’s extensive use of DMA and intelligent peripherals that can independently move Eterna
between the Active and Doze states minimizes the time the CPU is active, significantly reducing Eterna’s energy
consumption.
4.3.2
Doze State
The Doze state consumes orders of magnitude less current than the Active state (see Table 6) and is entered when all of the
peripherals, save the low power portion of the timer module, and the CPU are inactive. In the Doze state Eterna’s full state is
retained and Eterna is configured to detect, wake, and rapidly respond to activity on I/Os (such as UART signals and the
TIMEn pin). The Doze state also uses the 32.768-kHz oscillator and 32 kHz based timers are active.
4.4
Duty Cycling and Autonomous Peripherals
Eterna’s ability to quickly and efficiently transition between Doze and Active states, in conjunction with the ability of
peripherals to operate autonomously for most operations (shown in Figure 9), enables the system solution to significantly
reduce power consumption. For example the system can automatically go from Doze to Active and determine if RF energy is
present. The CPU is then only woken if a packet is detected, otherwise Eterna returns to Doze mode.
Figure 9
Low Energy Duty Cycling
Eterna Datasheet
Linear Technology / Dust Networks
11
Advanced Information
5.0
5.1
Pinout
Eterna Mote-on-Chip
Figure 10 and Table 1 show the default pinout and pin-assignment for Eterna. For clarity the pins are grouped by function in
the pin-assignment table. In some cases, a pin may have multiple possible functions; the behavior is determined by the
software application layer.
Note: All unused input pins not configured with a pull resistor (see Pull column in pinout table) must be driven to their
inactive state or be configured by the Fuse Table to pull to an inactive state to avoid excess leakage and undesired operation.
Leakage due to floating inputs can be substantially greater than Eterna’s average power consumption. Pin functions shown in
gray are not currently supported via software.
RADIO_INHIBIT / GPIO15
CAP_PA_1P
CAP_PA_1M
CAP_PA_2M
CAP_PA_2P
CAP_PA_3P
CAP_PA_3M
CAP_PA_4M
CAP_PA_4P
VDDPA
LNA_EN / GPIO17
RADIO_TX / GPIO18
RADIO_TXn / GPIO19
ANTENNA
AI_0
AI_1
AI_3
AI_2
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1
54
2
53
3
52
4
51
5
50
6
49
7
48
8
47
Paddle
9
46
(GND)
10
45
11
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VPP
SPIS_SSn / SDA
SPIS_SCK / SCL
GPIO26 / SPIS_MOSI / UARTC1_RX
SPIS_MISO / 1-Wire / UARTC1_TX
PWM0 / GPIO16
GPIO20
SPIM_SS_0n / GPIO12
SPIM_SS_1n / GPIO13
IPCS_SSn / GPIO3
IPCS_SCK / GPIO4
SPIM_SCK / GPIO9
IPCS_MOSI / GPIO5
SPIM_MOSI / GPIO10
IPCS_MISO / GPIO6
SPIM_MISO / GPIO11
UARTC0_RX
UARTC0_TX
Figure 10 Eterna Mote-on-Chip Pinout – Top View
12
Linear Technology / Dust Networks
Eterna Datasheet
Advanced Information
Table 1
No
Eterna Mote-on-Chip Pinout Assignments
Type
I/O
Pull
P
GND
Power Supply
Power
-
-
Ground connection P = QFN Paddle
Description
2
CAP_PA_1P
Power
-
-
PA DC/DC converter capacitor 1 plus terminal
3
CAP_PA_1M
Power
-
-
PA DC/DC converter capacitor 1 minus terminal
4
CAP_PA_2M
Power
-
-
PA DC/DC converter capacitor 2 minus terminal
5
CAP_PA_2P
Power
-
-
PA DC/DC converter capacitor 2 plus terminal
6
CAP_PA_3P
Power
-
-
PA DC/DC converter capacitor 3 plus terminal
7
CAP_PA_3M
Power
-
-
PA DC/DC converter capacitor 3 minus terminal
8
CAP_PA_4M
Power
-
-
PA DC/DC converter capacitor 4 minus terminal
9
CAP_PA_4P
Power
-
-
PA DC/DC converter capacitor 4 plus terminal
10
VDDPA
Power
-
-
Internal power amplifier power supply
30
VDDA
Power
-
-
Regulated analog supply
31
VCORE
Power
-
-
Regulated core supply
32
VOSC
Power
-
-
Regulated oscillator supply
54
VPP
-
-
Test – do not connect
56
VPRIME
Power
-
-
Internal primary core power supply
57
CAP_PRIME_4P
Power
-
-
Primary DC/DC converter capacitor 4 plus terminal
58
CAP_PRIME_4M
Power
-
-
Primary DC/DC converter capacitor 4 minus terminal
59
CAP_PRIME_3M
Power
-
-
Primary DC/DC converter capacitor 3 minus terminal
60
CAP_PRIME_3P
Power
-
-
Primary DC/DC converter capacitor 3 plus terminal
61
CAP_PRIME_2P
Power
-
-
Primary DC/DC converter capacitor 2 plus terminal
62
CAP_PRIME_2M
Power
-
-
Primary DC/DC converter capacitor 2 minus terminal
63
CAP_PRIME_1M
Power
-
-
Primary DC/DC converter capacitor 1 minus terminal
64
CAP_PRIME_1P
Power
-
-
Primary DC/DC converter capacitor 1 plus terminal
65
VSUPPLY
Power
-
-
Power supply input to Eterna
Type
I/O
Pull
1*
I
-
Radio Inhibit
-
-
-
Single-ended antenna port
Crystals
Type
I/O
Pull
19
OSC_32K_XOUT
Crystal
I
-
32 kHz crystal xout
20
OSC_32K_XIN
Crystal
I
-
32 kHz crystal xin
28
OSC_20M_XIN
Crystal
I
-
20 MHz crystal xin
29
OSC_20M_XOU
T
Crystal
I
-
20 MHz crystal xout
Type
I/O
Pull
1
I
UP
Type
I/O
Pull
No
-
Radio
1
RADIO_INHIBIT
14
ANTENNA
No
No
22
Reset
RESETn
No
JTAG
23
TDI
1
I
UP
24
TDO
1
O
-
25
TMS
1
I
UP
26
TCK
1
I
DOWN
Type
I/O
Pull
No
Special
Purpose Digital
Description
Description
Description
Reset, Input, active low
Description
JTAG test data in
JTAG test data out
JTAG test mode select
JTAG test clock
Description
35
SLEEPn
1*
I
-
Deep Sleep, active low
72
TIMEn
1*
I
-
Time capture request, active low
Eterna Datasheet
Linear Technology / Dust Networks
13
Advanced Information
Type
I/O
Pull
37
No
UARTC0_TX
2
O
-
CLI UART 0 transmit
38
UARTC0_RX
1
I
UP
CLI UART 0 receive
Type
I/O
Pull
No
CLI
IPCS SPI
/FLASH
Programming
Description
Description
40
IPCS_MISO
2
O
-
SPI flash emulation (MISO) master in slave out port
42
IPCS_MOSI
1
I
-
SPI flash emulation (MOSI) master out slave in port
44
IPCS_SCK
1
I
-
SPI flash emulation (SCK) serial clock port
45
IPCS_SSn
1
I
-
55
FLASH_P_ENn
1
I
UP
UART
Type
I/O
Pull
UART_RX_RTSn
1*
I
-
No
66
SPI flash emulation slave select, active low
Flash program enable, active low
Note that this functionality is available only when
RESETn is asserted
Description
UART receive (RTS) request to send, active low
67
UART_RX_CTSn
1
O
-
UART receive (CTS) clear to send, active low
68
UART_RX
1*
I
-
UART receive
69
UART_TX_RTSn
1
O
-
UART transmit (RTS) request to send, active low
70
UART_TX_CTSn
1*
I
-
UART transmit (CTS) clear to send, active low
71
UART_TX
2
O
-
UART transmit
* Input signals that must be driven or pulled to a valid state to avoid leakage.
5.3
Power Supply
Eterna is powered from a single pin, VSUPPLY, and generates all required supplies internally. With two integrated DC/DC
converters and four voltage regulators, the sensitivity to noise on VSUPPLY is minimal. However, during typical operation
Eterna will vary its load on the power supply from the μA range to 10’s of mA over a few μs. During such transients, the
power supply must meet the specifications for supply noise tolerance. Eterna is designed to operate with specific decoupling
capacitance on VCORE, VDDA, VOSC, VDDPA, and VPRIME, as well as the internal converter capacitors C1 through C4.
Failure to use correctly sized ceramic capacitors can result in supply instability and performance degradation.
5.3.1
Antenna
Eterna allows direct connection to a single-ended 50-Ohm antenna; an internal TX/RX switch simplifies external circuitry
requirements. Because both the transmit and the receive paths are single-ended, a balun (with its associated cost and
efficiency loss) are not required. Eterna provides options to set typical output power to 0 dBm or to +8 dBm using the on-chip
PA. For further details on radio transmit and receive, see section 2.4.
5.5
JTAG
Eterna includes an IEEE 1149.1-compliant JTAG port for boundary scan.
14
Linear Technology / Dust Networks
Eterna Datasheet
Advanced Information
6.0
Absolute Maximum Ratings
The absolute maximum ratings shown in Table 3 should not be violated under any circumstances. Permanent damage to the
device may be caused by exceeding one or more of these parameters. Unless otherwise noted, all voltages in Table 3 are
relative to GND.
Table 3
Absolute Maximum Ratings
Parameter
Min
Typ
Max
Units
Comments
Supply voltage (VSUPPLY to GND)
–0.3
3.76
V
Voltage on any digital I/O pin
–0.3
VSUPPLY
+ 0.3
up to 3.76
V
+10
dBm
+105
°C
Extended storage at high
temperature is discouraged, as this
negatively affects the data
retention of Eterna’s calibration
data.
Lead temperature
+245
°C
For 10 seconds
VSWR of antenna
3:1
Input RF level
Storage temperature range
–55
Input power at antenna connector
ESD protection
Antenna pad
±1000
V
HBM
All other pads
±1000
V
HBM
±100
V
CDM
Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent
permanent damage.
Eterna Datasheet
Linear Technology / Dust Networks
15
Advanced Information
Recommended Operating Conditions
7.0
Table 4
Recommended Operation Conditions
Parameter
Conditions
Min
Typ
Max
VSUPPLY range
Including noise and load regulation
2.1
3.6
3.76
V
Voltage supply noise
Requires recommended RLC filter,
50 Hz to 2 MHz
250
mVp-p
+85
°C
90
% RH
Operating temperature range
Operating relative humidity
–40
Non-condensing
10
Power on Reset threshold
1.5
Temperature ramp
V
-8
8.0
Electrical Characteristics
8.1
Radio Specifications
Units
+8
°C/min
Max
Units
2.4835
GHz
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 5
Detailed Radio Specifications
Parameter
Frequency Band
Conditions
As specified by [ 1 ]
Min
Typ
2.4000
Number of channels
15
Channel separation
As specified by [ 1 ]
Occupied channel bandwidth
At –20 dBc
Channel Center Frequency
Where k = 11 to 25.‡
Modulation
IEEE 802.15.4 DSSS
Raw data rate
As specified by [ 1 ]
Range*
†
Indoor
Outdoor†
Free space
25 °C, 50% RH, +2 dBi
omni-directional antenna
5
MHz
2.7
MHz
2405 +
5 * (k-11)
MHz
250
kbps
100
300
1200
m
m
m
* Actual RF range performance is subject to a number of installation-specific variables including, but not restricted to
ambient temperature, relative humidity, presence of active interference sources, line-of-sight obstacles, and nearpresence of objects (for example, trees, walls, signage, and so on) that may induce multipath fading. As a result, actual
performance varies.
†
1 meter above ground.
‡ Channel 26 as specified by [ 1 ] is not used..
8.2
DC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 6
DC Specifications
Parameter
Reset
Conditions
After power-on reset
Deep Sleep
Doze
RAM on; ARM Cortex-M3, flash, radio,
and peripherals off, all data and state
retained, 32.768 kHz reference active
Serial Flash Emulation
Peak Operating current
16
Min
Typ
Max
Units
1.2
µA
0.8
µA
1.2
µA
20
mA
System operating at 14.7 MHz
Radio Tx
Flash Write
Linear Technology / Dust Networks
Eterna Datasheet
Advanced Information
Max
Units
at +8 dBm output power
Parameter
Conditions
Min
Typ
30
mA
at 0 dBm output power
26
mA
ARM Cortex-M3, RAM, and flash on;
radio and peripherals off
Active*
CLK = 7.37 MHz, Vcore = 1.8 V
Flash write
Single bank write
Flash erase
Single bank page or mass erase
†
2.4
mA
3
mA
2.5
mA
0 dBm output power
+8 dBm output power
5.4
9.7
mA
mA
Mesh Network - CLK = 7.3728 MHz,
AES active
4.5
mA
Mesh Network - CLK = 7.3728 MHz,
AES active
Radio Tx
Radio Rx†
Note: See section 3.0 for detailed operational definitions of states.
* CLK = Clock frequency of CPU and peripherals.
†
Current with autonomous MAC handling packet transmission and reception; CPU idle.
8.3
Radio Receive Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 7
Radio Receive Characteristics
Parameter
Conditions
Min
Typ
Max
Units
Receiver sensitivity
PER = 1%, as specified by [ 1 ]
–93
dBm
Receiver sensitivity
PER = 50%
–95
dBm
0
dBm
Adjacent channel rejection (high
side)
Desired signal at -82 dBm, adjacent
modulated channel at 5 MHz, PER =
1%, as specified by [ 1 ]
22
dBc
Adjacent channel rejection (low
side)
Desired signal at -82 dBm, adjacent
modulated channel at -5 MHz, PER
= 1%, as specified by [ 1 ]
19
dBc
Alternate channel rejection (high
side)
Desired signal at -82 dBm, adjacent
modulated channel at 10 MHz, PER
= 1%, as specified by [ 1 ]
40
dBc
Alternate channel rejection (low
side)
Desired signal at -82 dBm, adjacent
modulated channel at -10 MHz, PER
= 1%, as specified by [ 1 ]
36
dBc
Second alternate channel
rejection
Desired signal at -82 dBm, adjacent
modulated channel at +/-10 MHz,
PER = 1%, as specified by [ 1 ]
42
dBc
Co-channel rejection
Desired signal at -82 dBm.
Undesired signal is 802.15.4
modulated at same frequency. PER
= 1%, as specified by [ 1 ]
–6
dBc
<–55
dBm
±50
ppm
Saturation (maximum input level)
LO feed through
Frequency error tolerance
[ 1 ] requires ±40
Symbol rate error tolerance
±50
ppm
–10 to –90
dBm
RSSI accuracy
±6
dB
RSSI resolution
1
dB
RSSI input range
Eterna Datasheet
Linear Technology / Dust Networks
17
Advanced Information
8.4
Radio Transmitter Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 8
Radio Transmitter Characteristics
Parameter
Conditions
Output power
Calibrated settings
Delivered to a 50 Ω load,
over temperature and voltage
ranges
Spurious emissions
Conducted measurement with a
50 Ω single-ended load, +8 dBm
output power. All measurements
made with Max Hold. RF
implementation per Eterna reference
design.
30 MHz to 1000 MHz
1 GHz to 12.75 GHz
Upper Band Edge (Peak)
Upper Band Edge (Average)
Lower Band Edge
Harmonic emissions
2nd Harmonic
Min
RBW = 120 kHz, VBW = 100 Hz
RBW = 1 MHz, VBW = 3 MHz
RBW = 1 MHz, VBW = 3 MHz
RBW = 1 MHz, VBW = 10 Hz
RBW = 100 kHz, VBW = 100 kHz
Conducted measurement delivered
to a 50 Ω load, Resolution
Bandwidth = 1 MHz, Video
Bandwidth = 1 MHz, RF
implementation per Eterna reference
design
Max
Units
0
+8
dBm
dBm
<–70
–45
-37
-49
-45
dBm
dBm
dBm
dBm
dBc
dBm
–50
rd
–45
3 Harmonic
8.5
Typ
Digital I/O Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 9
Digital I/O Type 1
Parameter
Conditions
Min
Typ
Max
Units
VIL (low-level input voltage)
–0.3
0.6
V
VIH (high-level input voltage)
VSUPPLY
- 0.3†
VSUPPLY
+ 0.3†
V
0.4
V
VSUPPLY
+ 0.3†
V
VOL (low-level output voltage)
IOL(max) = 1.2 mA
VOH (high-level output voltage)
IOH(max) = −1.8 mA
Input leakage current
pull-up / pull-down pins disabled.
†
VSUPPLY
- 0.3†
50
nA
Min and Min and Max IO input levels must respect the Minimum and Maximum voltages for VSUPPLY.
Table 10 Digital I/O Type 2
Parameter
Conditions
Min
Typ
Max
Units
VIL (low-level input voltage)
–0.3
0.6
V
VIH (high-level input voltage)
VSUPPLY
- 0.3†
VSUPPLY
+ 0.3†
V
0.4
V
VSUPPLY
+ 0.3†
V
0.4
V
VOL (low-level output voltage)
Low Drive
IOL(max) = 2.2 mA
VOH (high-level output voltage)
Low Drive
IOH(max) = −3.2 mA
VOL (low-level output voltage)
High Drive
IO(max) = 4.5 mA
18
VSUPPLY
- 0.3†
Linear Technology / Dust Networks
Eterna Datasheet
Advanced Information
VOH (high-level output voltage)
High Drive
IOH(max) = −6.3 mA
Input leakage current
†
VSUPPLY
+ 0.3†
VSUPPLY
- 0.3†
50
V
nA
Min and Min and Max IO input levels must respect the Minimum and Maximum voltages for VSUPPLY.
8.6
Temperature Sensor Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 11 Temperature Sensor Characteristics
Parameter
Conditions
Min
Typ
Max
Units
Offset
Temperature offset error at 25 ºC
±0.25
°C
Slope error
Slope error from -40 to +85 ºC
±0.033
°C/°C
8.8
System Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 13 System Characteristics
Parameter
Conditions
Min
Doze to Active state delay
Doze to Radio TX or RX
QCCA charge to sample RF channel
Start from Doze state
Radio baud rate
RESETn pulse width
8.9
Typ
Max
Units
5
µs
1.2
ms
4
µC
250
kbps
125
µs
UART AC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 14 UART Timing Values
Parameter
Conditions
Min
Typ
Max
Unit
tRX_BAUD
Deviation from baud rate
–2
+2
%
tTX_BAUD
Deviation from baud rate
–1
+1
%
tRX_RTS_R to RX_CTS
Assertion of UART_RX_RTSn to
assertion of UART_RX_CTSn, or
negation of UART_RX_RTSn to
negation of UART_RX_CTSn
0
22
ms
tCTS_R to RX
Assertion of UART_RX_CTSn to start
of byte
0
20
ms
tEOP to RX_RTS
End of packet (end of the last stop bit)
to negation of UART_RX_RTSn
0
22
ms
tTX_RTS_T to TX_CTS
Assertion of UART_TX_RTSn to
assertion of UART_TX_CTSn, or
negation of UART_TX_RTSn to
negation of UART_TX_CTSn
0
22
ms
tTX_CTS_T to TX
Assertion of UART_TX_CTSn to start
of byte
0
2
bit
period
tEOP to TX_RTS
End of packet (end of the last stop bit)
to negation of UART_TX_RTSn
0
1
bit
period
tRX_INTERBYTE
Receive Inter-byte delay
100
ms
tTX to TX_CTS
Start of byte to negation of
UART_TX_CTSn
tINTERPACKET
Transmit and Receive Inter-packet
delay (Mode 4 only)
Eterna Datasheet
Linear Technology / Dust Networks
0
ms
100
ms
19
Advanced Information
Figure 16 UART Timing
8.10
TIMEn AC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified. Note that the time
pin must remain negated until the time packet has been received.
Table 15 Timestamp Characteristics
Parameter
Conditions
tstrobe
Min
Typ
Max
125
Unit
µs
tresponse
From rising edge of TIMEn
100
ms
Resolution
See the serial API definition for
getParameter<time>
+/- 1
µs
Network-wide time accuracy
Stable temperature environment
+/- 5
µs
Figure 17 Timestamp Timing Diagram
20
Linear Technology / Dust Networks
Eterna Datasheet
Advanced Information
8.11
SLEEPn AC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified. Note that the time
pin must remain negated until the time packet has been received.
Table 16 SLEEPn Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
tdoze
From falling edge of SLEEPn
20
ms
Tsleep_strobe
Maximum strobe width
2
s
Figure 18 SLEEPn Timing Diagram
8.12
RADIO_INHIBIT AC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified. Note that the time
pin must remain negated until the time packet has been received.
Table 17 RADIO_INHIBIT Characteristics
Max
Unit
tradio_off
Parameter
Conditions
From rising edge of RADIO_INHIBIT
Min
Typ
20
ms
Tradio_inhibit_strobe
Maximum strobe width
2
s
Figure 19 RADIO_INHIBIT Timing Diagram
Eterna Datasheet
Linear Technology / Dust Networks
21
Advanced Information
8.13
FLASH AC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 18 FLASH AC Timing Values
Parameter
Conditions
Min
Typ
Max
Unit
t32-BIT_WORD
Writing a 32-bit word
21
µs
tPAGE_ERASE
Page Erase
21
ms
tMASS_ERASE
Bank Erase
21
ms
8.14
Flash Programming AC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C with 10 pF load capacitance, unless otherwise
specified.
Table 19 SPI Slave AC Timing Values
Parameter
Conditions
Min
Typ
Max
Unit
tSSS
IPCS_SSn setup to leading edge of
IPCS_SCK
15
ns
tSSH
IPCS_SSn hold from trailing edge of
IPCS_SCK
15
ns
tCK
IPCS_SCK period
50
ns
tDIS
IPCS_MOSI data setup
15
ns
tDIH
IPCS_MOSI data hold
5
ns
tDOV
IPCS_MISO data valid
3
15
ns
tOFF
IPCS_MISO data tri-state
0
15
ns
Figure 20 Flash Programming Slave Timing
22
Linear Technology / Dust Networks
Eterna Datasheet
Advanced Information
9.0
Typical Performance Characteristics
All TIMEn synchronization error testing was performed with the hop-1 mote inside a temperature chamber. Timing errors
due to temperature changes and temperature differences both between the AP and this mote and between this mote and its
descendents therefore propagated down through the network. The synchronization of the hop-3 and hop-5 motes to the AP
was then affected by the temperature ramps even though they were at room temperature. For 2°C/min. testing the temperature
chamber was cycled between -40°C and 85°C at this rate for 24 hours. For 8°C/min. testing, the temperature chamber was
rapidly cycled between 85°C and about 45°C for 8 hours, followed by rapid cycling between -5°C and about 45°C for 8
hours, and lastly, rapid cycling between -40°C and about 15°C for 8 hours..
Eterna Datasheet
Linear Technology / Dust Networks
23
Advanced Information
Network motes typically route through at least two parents traffic destined for the manager. The bandwidth and keep-alive
overhead required to support network motes will be shared across all of the mote's parents. The supply current plots include a
parameter called traffic-weighted descendants. In these graphs the term traffic-weighted descendants refers to an amount of
activity equivalent to the number of descendants were all of the network traffic and keep-alives directed to the mote in
question. Generally the number of descendants of a parent is more (typically 2x or more) than the number of traffic-weighted
descendants. For example, with reference to Figure 25 mote P1 has 0.75 traffic-weighted descendants. To obtain this value
notice that mote D1 routes half its packets through mote P1 adding 0.5 to the traffic-weighted descendant value; the other
half of D1's traffic is routed through its other parent, P2. Mote D2 routes half its packets through mote D1 (the other half
going through parent P3), which we know routes half its packets to mote P1, adding another 0.25 to the traffic-weighted
descendant value for a total traffic-weighted descendant value of 0.75.
Figure 25 Network Graph Depicting Traffic Weighted Descendant Value Calculation
The following plots correspond to networks with 1024 slots/frame, an assumed path stability of 80%, an 80 byte packet and
unless otherwise specified operation at 25 degrees C.
24
Linear Technology / Dust Networks
Eterna Datasheet
Advanced Information
10.0
Mechanical Details
10.1
Mote-on-Chip
Eterna comes in 72-lead 10 x 10 mm, 0.5 mm lead pitch QFN, as illustrated in Figure 26.
Figure 26 Mechanical Drawing – Eterna QFN Package Outline Drawing
10.3
Soldering Information
Eterna is suitable for both eutectic PbSn and RoHS-6 reflow. The maximum reflow soldering temperature is 260 ºC.
11.0
Regulatory and Standards Compliance
Eterna is suitable for systems targeting compliance with worldwide radio frequency regulations: ETSI EN 300 328 and
EN300 440 class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
11.1
Compliance to Restriction of Hazardous Substances (RoHS)
Restriction of Hazardous Substances (RoHS) is a directive that places maximum concentration limits on the use of cadmium
(Cd), lead (Pb), hexavalent chromium (Cr+6), mercury (Hg), Polybrominated Biphenyl (PBB), and Polybrominated Diphenyl
Ethers (PBDE). Dust Networks is committed to meeting the requirements of the European Community directive 2002/95/EC.
This product has been specifically designed to utilize RoHS-compliant materials and to eliminate or reduce the use of
restricted materials to comply with 2002/95/EC.
The RoHS-compliant design features include:
•
•
RoHS-compliant solder for solder joints
RoHS-compliant base metal alloys
Eterna Datasheet
Linear Technology / Dust Networks
25
Advanced Information
• RoHS-compliant precious metal plating
• RoHS-compliant cable assemblies and connector choices
• Lead-free QFN package
• Halogen-free mold compound
• RoHS-compliant and 245 °C re-flow compatible
Note: Customers may elect to use certain types of lead-free solder alloys in accordance with the European Community
directive 2002/95/EC. Depending on the type of solder paste chosen, a corresponding process change to optimize reflow
temperatures may be required.
12.0
[1]
References
IEEE Std. 802.15.4-2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications
for Low-Rate Wireless Personal Area Networks (LR-WPANs)
http://standards.ieee.org/getieee802/download/802.15.4-2006.pdf
13.0 Order Information
LEAD FREE FINISH
TRAY
PART
MARKING*
PACKAGE
DESCRIPTION
TEMPERATURE
RANGE
LTC5800IWR-IPRA#PBF
LTC5800IWR-IPRA#PBF
LTC5800WR
72-Lead (10mm x 10mm
x 0.85 mm) QFN
-40 °C to 85 °C
LTC5800HWR-IPRA#PBF
LTC5800HWR-IPRA#PBF
LTC5800WR
72-Lead (10mm x 10mm
x 0.85 mm) QFN
-55 °C to 105 °C
*The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
26
Linear Technology / Dust Networks
Eterna Datasheet
Advanced Information
Trademarks
SmartMesh Industrial and Eterna are trademarks of Dust Networks, Inc. The Dust Networks logo, Dust, Dust Networks, and SmartMesh are registered
trademarks of Dust Networks, Inc. The Linear logo is a registered trademark of Linear Technology Corporation. All third-party brand and product names
are the trademarks of their respective owners and are used solely for informational purposes.
ARM and Cortex are trademarks or registered trademarks of ARM Limited in the EU and other countries.
Copyright
This documentation is protected by United States and international copyright and other intellectual and industrial property laws. It is solely owned by
Dust Networks, Inc. and its licensors and is distributed under a restrictive license. This product, or any portion thereof, may not be used, copied, modified,
reverse assembled, reverse compiled, reverse engineered, distributed, or redistributed in any form by any means without the prior written authorization of
Dust Networks, Inc.
RESTRICTED RIGHTS: Use, duplication, or disclosure by the U.S. Government is subject to restrictions of FAR 52.227-14(g) (2)(6/87) and FAR
52.227-19(6/87), or DFAR 252.227-7015 (b)(6/95) and DFAR 227.7202-3(a), and any and all similar and successor legislation and regulation.
Disclaimer
This documentation is provided “as is” without warranty of any kind, either expressed or implied, including but not limited to, the implied warranties of
merchantability or fitness for a particular purpose.
This documentation might include technical inaccuracies or other errors. Corrections and improvements might be incorporated in new versions of the
documentation.
Dust Networks does not assume any liability arising out of the application or use of any products or services and specifically disclaims any and all
liability, including without limitation consequential or incidental damages.
Dust Networks products are not designed for use in life support appliances, devices, or other systems where malfunction can reasonably be expected to
result in significant personal injury to the user, or as a critical component in any life support device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Dust Networks customers using or selling these
products for use in such applications do so at their own risk and agree to fully indemnify and hold Dust Networks and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Dust Networks was
negligent regarding the design or manufacture of its products.
Dust Networks reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products or services at any
time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should
verify that such information is current and complete. All products are sold subject to Dust Network's terms and conditions of sale supplied at the time of
order acknowledgment or sale.
Dust Networks does not warrant or represent that any license, either express or implied, is granted under any Dust Networks patent right, copyright, mask
work right, or other Dust Networks intellectual property right relating to any combination, machine, or process in which Dust Networks products or
services are used. Information published by Dust Networks regarding third-party products or services does not constitute a license from Dust Networks to
use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or
other intellectual property of the third party, or a license from Dust Networks under the patents or other intellectual property of Dust Networks.
Dust Networks, Inc is a wholly owned subsidiary of Linear Technology Corporation.
© Dust Networks, Inc. 2012. All Rights Reserved.
Eterna Datasheet
Linear Technology / Dust Networks
27
Advanced Information
Last Revised:
Document Status
July 26, 2012
Product Status
Definition
Advanced Information
Planned or under development
This datasheet contains the design specifications for product
development. Dust Networks reserves the right to change
specifications in any manner without notice.
Preliminary
Engineering samples and
pre-production prototypes
This datasheet contains preliminary data; supplementary data will
be published at a later time. Dust Networks reserves the right to
make changes at any time without notice in order to improve
design and supply the best possible product. The product is not
fully qualified at this point.
No Identification Noted
Full production
This datasheet contains the final specifications. Dust Networks
reserves the right to make changes at any time without notice in
order to improve design and supply the best possible product.
Obsolete
Not in production
This datasheet contains specifications for a product that has been
discontinued by Dust Networks. The datasheet is printed for
reference information only.
28
Linear Technology / Dust Networks
Eterna Datasheet