High Definition Audio SoundMAX Codec AD1882A FEATURES Six 192 kHz, 95 dB DACs All independent sample rates, 8 kHz through 192 kHz 16-, 20-, and 24-bit PCM resolution Selectable stereo mixer on outputs Four 192 kHz, 90 dB ADCs Simultaneous record of up to 2 stereo channels All independent sample rates, 8 kHz through 192 kHz 16-, 20-, and 24-bit resolution S/PDIF output Supports all sample rates 44.1 kHz through 192 kHz 16-, 20-, and 24-bit data widths; PCM and AC3 formats Digital PCM gain control Dedicated auxiliary pins Stereo CD input w/GND sense Mono out pin for internal speaker with EAPD support Analog PCBeep input pin S/PDIF Tx Stereo digital microphone Two 192 kHz digital microphone channels Supports 1 or 2 microphones on 1 pin Selectable bit clock rates of 1.5 MHz, 2.0 MHz, and 3.0 MHz All sample rates, 8 kHz through 192 kHz 16-, 20-, and 24-bit resolution Microsoft Vista Premium® logo for notebook and desktop Impedance and presence detection on all jack pins 2 general-purpose digital I/O (GPIO) pins Advanced power management modes EAPD control for internal speakers 3.3 V analog and digital supply voltage 1.5 V and 3.3 V HD Audio link signaling Very low power consumption in D3 state AD1882A S/PDIF OUT DIGITAL BEEP H D A U D I O I N T E R F A C E DAC0 ⌺ DAC1 ⌺ DAC2 ⌺ PORT G ⌺ MONO OUT DIGITAL MICROPHONE ⌺ DM_CLK DM_DATA ADC0 ⌺ PORT F HP HP PORT D PORT A ⌺ PORT C ⌺ PORT E PCBEEP PORT B CD IN ADC1 Figure 1. AD1882A Block Diagram Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. AD1882A CONTENTS Features ................................................................. 1 Contents ................................................................ 2 Revision History ...................................................... 2 General Description ................................................. 3 Special Software Features ........................................ 3 Additional Information .......................................... 3 Jack Configuration ................................................ 3 Specifications .......................................................... 4 Test Conditions .................................................... 4 Performance ........................................................ 4 General Specifications ............................................ 4 HD Audio Link Specifications .................................. 6 Power-Down States ............................................... 6 Absolute Maximum Ratings .................................... 7 ESD Caution ........................................................ 7 Environmental Conditions ...................................... 7 Pin Configuration and Function Descriptions ................. 8 Digital Microphone Interface Timing Specifications ....... 11 HD Audio Parameters ............................................. 12 Widget Parameters ................................................. 13 HD Audio Widgets ................................................ 14 Connection List ..................................................... 15 Default Configuration Bytes ..................................... 16 Outline Dimensions ............................................... 17 Ordering Guide ..................................................... 17 REVISION HISTORY 8/08—Revision 0: Initial Version Rev. 0 | Page 2 of 20 | August 2008 AD1882A GENERAL DESCRIPTION The AD1882A audio codec and SoundMAX® software provides superior HD audio quality that exceeds Vista Premium performance. The AD1882A has six DACs and four ADCs, two stereo headphone ports, C/LFE swapping, digital and analog PCBeep, and S/PDIF output, making the AD1882A the right choice for desktop and notebook PCs where performance is the primary consideration. JACK CONFIGURATION The guidelines shown in Table 1 through Table 4 should be used when selecting ports for particular functions. Table 1. Typical Desktop Configuration with Discrete Jacks Port Port A Port B Port C Port D Port E Port F Port G The jack retasking feature on this product supports various configurations including platforms for 5.1 on 5 or 3 jacks, and front panel jack retasking. The AD1882A is available in a 48-lead Pb-free lead frame chip scale package in both reels and trays. See Ordering Guide on Page 17. SPECIAL SOFTWARE FEATURES Table 2. Typical Desktop Configuration with 5.1 on 3 Jacks The AD1882A audio codec also supports the following additional software features: Port Port A Port B Port C Port D Port E • BlackHawk® and SoundMAX GUI contain all user audio controls • Voice input enhancements: Andrea Electronics best-inclass noise reduction, beam forming, and echo cancellation • Output enhancements: Sensaura/Sonic Focus, spreading/downmixing, MP3 refinement, adaptive dynamics, compressor/limiter, speaker/graphic EQ, Voice Clarity/ X-MatrixTM, AGC, UI tuning tools Function Front Panel Headphone Front Panel Microphone Rear Panel Line-In/Surround Rear Panel Line-Out/Headphone Rear Panel Microphone/C/LFE Table 3. Typical Notebook Configuration Port Port A Port B Port C Port D Port E • DTS®, SRS®, EAX for gaming ADDITIONAL INFORMATION This data sheet provides a general overview of the AD1882A SoundMAX codec’s architecture and functionality. Additional information on the AD1882A is available in the AD1882A Programmers Reference Manual. Please contact your local Analog Devices, Inc., sales representative for more information. For information on SoundMAX codecs and software, see Analog Devices website at http://www.analog.com/soundMAX. Rev. 0 | Function Front Panel Headphone Front Panel Microphone Rear Panel Line-In Rear Panel Line-Out/Headphone Rear Panel Microphone Rear Panel Surround Rear Panel C/LFE Function Headphone Microphone Internal Microphone Internal Stereo Speakers Docking Station Line/Microphone In Table 4. Typical Notebook Configuration with Digital Microphone Page 3 of 20 | Port Port A Port B Digital Microphone Port D Port E August 2008 Function Headphone Microphone Internal Microphone Internal Stereo Speakers Docking Station Line/Microphone In AD1882A SPECIFICATIONS TEST CONDITIONS Parameter Temperature Digital Supply Analog Supply MIC_BIAS_IN (via Low-Pass Filter) Sample Rate fS Input Signal (Frequency Sine Wave) Amplitude for THD + N Analog Output Pass Band DAC ADC Test Condition 25°C 3.3 V 3.3 V 5.0 V 48 kHz 1008 Hz –3.0 dB Full Scale 20 Hz to 20 kHz 10 kΩ Output Load: Line-Out Tests 32 Ω Output Load: Headphone Tests 0 dB Gain PERFORMANCE Parameter Line-Out Drive (10 kΩ Loads—DAC to Pin) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in Ref to fS A-Weighted) Signal-to-Noise Ratio Headphone Drive (32 Ω Loads—DAC to Pin) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in Ref to fS A-Weighted) Signal-to-Noise Ratio Input Ports (Pin to ADC, Mic Boost = 0 dB) Total Harmonic Distortion (THD + N) Dynamic Range (–60 dB in Ref to fS A-Weighted) Signal-to-Noise Ratio Min Typ Max Unit –85 95 95 dB dB dB –83 95 95 dB dB dB –81 90 90 dB dB dB GENERAL SPECIFICATIONS Parameter DIGITAL DECIMATION AND INTERPOLATION FILTERS—fS = 8 kHz to 96 kHz1 Pass Band Pass-Band Ripple Stop Band Stop-Band Rejection Group Delay Group Delay Variation Over Pass Band ANALOG-TO-DIGITAL CONVERTERS Resolution Gain Error (Full-Scale Span Relative to Nominal Input Voltage)2 Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error1 ADC Crosstalk1 Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) Line Inputs to Other Rev. 0 | Page 4 of 20 | Min Typ 0 Max Unit 0.4 fS ±0.005 Hz dB Hz dB 1/fS μs 0.6 fS +20 0 –100 24 –85 –100 August 2008 ±10 ±0.5 ±5 Bits % dB mV –80 dB dB AD1882A Parameter DIGITAL-TO-ANALOG CONVERTERS Resolution Gain Error (Full-Scale Span Relative to Nominal Input Voltage)1 Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk (Input L, Zero R, Read R_OUT; Input R, Zero L, Read L_OUT)1 DAC VOLUMES Step Size (DAC0, DAC1, DAC2) Output Gain/Attenuation Range Mute Attenuation of 0 dB Fundamental1 ADC VOLUMES Step Size (ADCSEL-0, ADCSEL-1) PGA Gain/Attenuation Range Mute Attenuation of 0 dB Fundamental1 ANALOG MIXER Signal-to-Noise Ratio (SNR) Input to Output Step Size: All Mixer Inputs Input Gain/Attenuation Range: All Mixer Inputs ANALOG LINE LEVEL OUTPUTS Full-Scale Output Voltage Ports C, E, F, and G Mono Out Output Impedance1 External Load Impedance1 Output Capacitance1 External Load Capacitance1 ANALOG HP DRIVE OUTPUTS Full-Scale Output Voltage Ports A and D Output Impedance1 External Load Impedance1 Output Capacitance1 External Load Capacitance1 ANALOG INPUTS CD, Port D (When Used as Input) Microphone Boost Amplifier, Ports B, C, or E (When Used as Inputs) Min Max 24 ±10 ±0.5 –95 1.5 –58.5 +22.5 dB dB dB –80 95 1.5 –34.5 +12.0 1.0 2.83 300 10 15 1000 7.5 V rms3 V p-p V rms3 V p-p V rms3 V p-p V rms3 V p-p V rms3 V p-p kΩ pF 15 Boost = 20 dB Boost = 30 dB DVGPIO × 0.60 0 V rms3 V p-p Ω kΩ pF pF 1000 0.5 32 Boost = 0 dB dB dB dB V rms3 V p-p Ω Ω pF pF 1.0 2.83 1 2.83 1 2.83 0.316 0.894 0.1 0.283 0.032 0.089 20 5 Bits % dB dB dB dB dB dB 1.5 –58.5 Unit 0 –80 Boost = 10 dB Input Impedance1 Input Capacitance1 DIGITAL GPIO PINS: GPIO_0, GPIO_1/EAPD Input Signal High (VIH) Input Signal Low (VIL) Input Leakage Current (Signal High), (IIH) Input Leakage Current (Signal Low), (IIL) Output Signal High (VOH) Output Signal Low (VOL) DM_CLK Output Signal High (VOH) Output Signal Low (VOL) Typ DVGPIO DVGPIO × 0.24 IOUT = –500 μA IOUT = +1500 μA DVGPIO × 0.72 0 DVGPIO DVGPIO × 0.10 V V nA μA V V IOUT = –500 μA IOUT = +1500 μA DVGPIO × 0.72 0 DVGPIO DVGPIO × 0.10 V V 150 50 Rev. 0 | Page 5 of 20 | August 2008 AD1882A Parameter DM_DATA Input Signal High (VIH) Input Signal Low (VIL) Input Leakage Current (Signal High) (IIH) Input Leakage Current (Signal Low) (IIL) S/PDIF_OUT Output Signal High (VOH) IOUT = –500 μA IOUT = +1500 μA Output Signal Low (VOL) POWER SUPPLY Analog (AVDD) 3.3 V ± 5% Power Supply Range Power Dissipation Supply Current Digital (DVDD) 3.3 V ± 10% Power Supply Range Power Dissipation Supply Current Digital I/O (DVIO) 3.3 V ± 10% Power Supply Range Power Dissipation Supply Current Digital I/O (DVIO) 1.5 V ± 5.5% Power Supply Range Power Dissipation Supply Current Digital GPIO (DVGPIO) 3.3 V ± 10% Power Supply Range Power Dissipation Supply Current Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1 Min Typ DVGPIO × 0.60 0 Max Unit DVGPIO DVGPIO × 0.24 V V nA nA DVGPIO DVGPIO × 0.10 V V –150 –50 DVGPIO × 0.72 0 3.13 3.30 116 35 3.46 V mW mA 2.97 3.30 162 49 3.63 V mW mA 2.97 3.30 3.96 1.20 3.63 V mW mA 2.97 3.30 3.96 1.20 3.63 V mW mA 2.97 3.30 3.63 1.10 80 3.63 V mW mA dB 1 Guaranteed but not tested. Measurements reflect main ADC. 3 RMS values assume sine wave input. 2 HD AUDIO LINK SPECIFICATIONS HD Audio signals comply with the High Definition Audio specifications. Please refer to these specifications at: http://www.intel.com/standards/hdaudio/ POWER-DOWN STATES Table 5. Power-Down States Parameter Function Node In D0, All Nodes Active Function Node in D3 Codec in RESET Individual Block Power Savings DAC Pair Powered Down Saves (Each) ADC Pair Powered Down Saves (Each) Mixer Power Control (and Associated Amps) Saves MIC_BIAS Powered Down Saves1 1 IDVDD Typ 49 16 3 IAVDD Typ 35 0.7 3 Unit mA mA mA 6 5 0 0 6 4.4 3 1.0 mA mA mA mA Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits, setting them to the high-Z state. Rev. 0 | Page 6 of 20 | August 2008 AD1882A ABSOLUTE MAXIMUM RATINGS ENVIRONMENTAL CONDITIONS Stresses greater than those listed below may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient Temperature Rating: Parameter Digital (DVDD) Digital I/O (DVIO) Digital GPIO (DVGPIO) Analog (AVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature Rating –0.30 V to +3.65 V –0.30 V to +3.65 V –0.30 V to +3.65 V –0.30 V to +3.65 V ±10.0 mA –0.30 V to AVDD + 0.3 V –0.30 V to DVIO + 0.3 V 0°C to +70°C –65°C to +150°C TAMB = TCASE – (PD × θCA) TCASE = case temperature in °C PD = power dissipation in W θCA = thermal resistance (case-to-ambient) θJA = thermal resistance (junction-to-ambient) θJC = thermal resistance (junction-to-case) All measurements per EIA-JESD51 with 2S2P test board per EIA-JESD51-7. Package LFCSP_VQ ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 20 | August 2008 θJA 47 θJC 15 θCA 32 Unit °C/W AD1882A S/PDIF_OUT GPIO_1/EAPD DM_CLK DM_DATA PORT-G_R PORT-G_L AVSS PORT-A_R MONO_OUT PORT-A_L AVDD RESERVED (NC) PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 DVCORE 1 36 PORT-D_R GPIO_0 2 35 PORT-D_L DVGPIO 3 34 SENSE_B/SRC_A DVIO 4 33 MIC_BIAS_IN SDATA_OUT 5 BIT_CLK AD1882AJCPZ 6 TOP VIEW DVSS 7 (Not To Scale) 32 RESERVED (NC) 31 MIC_BIAS-E 30 RESERVED (NC) 29 MIC_BIAS-C 28 MIC_BIAS-B 27 VREF_FLT PCBEEP 12 25 AVDD 15 16 17 18 19 20 21 22 23 Figure 2. AD1882A 48-Lead Package and Pinout Rev. 0 | Page 8 of 20 | August 2008 24 PORT-C_R 14 PORT-E_R 13 PORT-C_L AVSS PORT-B_R 26 PORT-B_L 11 CD_R RESET CD_GND 10 CD_L SYNC PORT-F_R 9 PORT-F_L DVDD PORT-E_L 8 SENSE_A/SRC_B SDATA_IN AD1882A Table 6. AD1882A Pin Descriptions Mnemonic DIGITAL INTERFACE SDATA_OUT Pin No. Function Description 5 I BIT_CLK SDATA_IN SYNC RESET DIGITAL I/O GPIO_0 GPIO_1/EAPD 6 8 10 11 I I/O I I Link Serial Data Output. AD1882A input stream. Clocked on both edges of the BIT_CLK. Link Bit Clock. 24.000 MHz serial data clock. Link Serial Data Input. AD1882A output stream clocked only on one edge of BIT_CLK. Link Frame Sync. Link Reset. AD1882A master hardware reset 2 47 I/O I/O S/PDIF_OUT DM_DATA DM_CLK JACK SENSE AND EAPD SENSE_A/SRC_B SENSE_B/SRC_A ANALOG I/O PCBEEP PORT-E_L PORT-E_R PORT-F_L PORT-F_R CD_L CD_GND 48 45 46 O I O General-Purpose Input/Output. Supports S/PDIF output as primary function. General-Purpose Input/Output Pin/EAPD Pin. Digital signal used to control external circuitry. By default pin is in a high-Z state. When used as EAPD: high-Z = amp-on, DVSS = amp off. S/PDIF output. Digital Microphone Data Input. Support for 2 digital microphones Digital Microphone Clock Output. 13 34 I/O I/O JACK SENSE A-D Input/Sense B Drive. JACK SENSE E-H Input/Sense A Drive. 12 14 15 16 17 18 19 LI LI, MIC, LO, SWAP LI, MIC, LO, SWAP I/O I/O LI LI CD_R PORT-B_L PORT-B_R PORT-C_L PORT-C_R PORT-D_L PORT-D_R PORT-A_L MONO_OUT PORT-A_R PORT-G_L PORT-G_R FILTER/REFERENCE MIC_BIAS-B MIC_BIAS-C MIC_BIAS-E DVCORE 20 21 22 23 24 35 36 39 40 41 43 44 LI LI, MIC, HP, LO LI, MIC, HP, LO LI, MIC, LO LI, MIC, LO LI, HP, LO LI, HP, LO LI, MIC, HP, LO LO LI, MIC, HP, LO LO, SWAP LO, SWAP Monaural Input from System for Analog PCBeep. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. CD Audio Left Channel. CD Audio Analog Ground Reference (for Differential CD Input). Must be connected to AGND via 0.1 μF capacitor if not in use as CD_GND. CD Audio Right Channel. Front Panel Stereo MIC/Line-In. Front Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Rear Panel Headphone/Line-Out. Rear Panel Headphone/Line-Out. Front Panel Headphone/Line-Out. Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone. Front Panel Headphone/Line-Out. Rear Panel C/LFE Output. Rear Panel C/LFE Output. Switchable Microphone Bias. For use with Port B (Pins 21, 22). Switchable Microphone Bias. For use with Port C (Pins 23, 24). Switchable Microphone Bias. For use with Port E (Pins 14, 15). CAUTION: DO NOT APPLY 3.3 V TO THIS PIN! Filter connection for internal core voltage regulator. This pin must be connected to filter caps: 10 μF, 1.0 μF, and 0.1 μF connected in parallel between Pin 1 and DVSS (Pin 4). VREF_FLT 27 O Voltage Reference Filter. This pin must be connected to filter caps: 1.0 μF and 0.1μF connected in parallel between Pin 27 and AVSS (Pins 26, 42). The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving headphone load, MIC = input supports microphones with MIC bias and boost amplifier, SWAP = outputs can swap L/R channels (typically used to support C/LFE or shared C/LFE function). 28 29 31 1 O O O O Rev. 0 | Page 9 of 20 | August 2008 AD1882A Table 6. AD1882A Pin Descriptions (Continued) Mnemonic POWER AND GROUND DVIO 3.3 V ± 10% or DVIO 1.5 V ± 5.5% DVGPIO DVSS DVDD (3.3 V) Pin No. Function Description 4 I Connect to the I/O Voltage Used for the HD Audio Controller Signals. 3 7 9 I I I Connect to 3.3 V digital supply to power the GPIO and S/PDIF pins. Digital Supply Return (Ground). Digital Supply Voltage 3.3 V. This is regulated down to DVCORE on Pin 1 to supply the internal digital core internal to the AD1882A. 25, 38 I CAUTION: DO NOT APPLY 5.0 V TO THESE PINS! AVDD (3.3 V) Analog Supply Voltage 3.3 V ONLY. Note: AVDD supplies should be well regulated and filtered as supply noise degrades audio performance. MIC_BIAS_IN 33 I Source Power for Microphone Bias Circuitry. Connect this pin to 5.0 V via a low-pass filter. When connected this way, the AD1882A is capable of providing 3.9 V as a mic bias to all of the MIC_BIAS pins. If 5 V is not available, connect this pin to 3.3 V (AVDD) via a low-pass filter. 26, 42 I Analog Supply Return (Ground). AVSS should be connected to DVSS using a AVSS conductive trace under, or close to, the AD1882A. The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving headphone load, MIC = input supports microphones with MIC bias and boost amplifier, SWAP = outputs can swap L/R channels (typically used to support C/LFE or shared C/LFE function). Rev. 0 | Page 10 of 20 | August 2008 AD1882A DIGITAL MICROPHONE INTERFACE TIMING SPECIFICATIONS The digital microphone interface can support one or two digital microphones using two or three codec pins. Both uniplex (one microphone per data pin) and multiplex (two microphones sharing the same data pin) are supported. The timing for these configurations are shown in Figure 3 and Figure 4. The interface can generate a microphone clock at 1.5 MHz, 2.0 MHz, or 3.0 MHz to suit quality and power requirements. Table 7. Microphone Timing Parameters Parameter Timing Requirements t0 DM_CLK (1.5 MHz) Period Duty Cycle t0 DM_CLK (2.0 MHz) Period Duty Cycle DM_CLK (3.0 MHz) Period t0 Duty Cycle DM_CLK Rise Time t1 t2 DM_CLK Fall Time Data Setup to DM_CLK Edge t3 t4 Data Hold from DM_CLK Edge Min Typ Max 667 50/50 500 50/50 333 50/50 ns % ns % ns % ns ns ns ns 5 5 100 5 t0 t2 t1 t3 t4 DM_CLK DM_DATA Figure 3. Uniplex Microphone Timing t0 t1 t2 DM_CLK t3 t4 DM_DATA LEFT DATA VALID t3 t4 RIGHT DATA VALID Figure 4. Multiplex Microphone Timing Rev. 0 | Page 11 of 20 | August 2008 Unit LEFT DATA VALID AD1882A HD AUDIO PARAMETERS The SSID value is set on codec power-up only. SSID is not reset by link or soft reset in order to preserve modifications by BIOS control. Table 8. Root and Function Node Parameters Node ID 00 01 1 Name ROOT FUNCTION Vendor ID 00 11D4882A 01 Revision ID 021 03 00100100 Sub Node Count 04 00010001 0002003B Func. Group Audio F.G. Type Caps 05 08 GPIO Caps 11 00000001 40000002 00010C0C Subject to change with silicon stepping. Table 9. SubSystem ID 1 Node ID 01 1 Name FUNCTION Value BFD20000 31:16 SSID BFD2 15:8 SKU 00 The default SSID is overwritten by platform BIOS after power on. It is preserved across HD Audio link reset and verb reset. Rev. 0 | Page 12 of 20 | August 2008 7:0 Asm ID 00 AD1882A WIDGET PARAMETERS Table 10. Widget Parameters Node ID 01 02 03 04 05 08 09 0C 0D 10 11 12 13 14 15 16 17 18 19 1A 1B 1E 1F 20 21 22 23 24 26 27 29 2A 2C 2D 2F 37 39 3A 3C Widget Capabilities 09 0x0000 0480 0x0003 031D 0x0000 0405 0x0000 0405 0x0000 0405 0x0010 0501 0x0010 0501 0x0030 010D 0x0030 010D 0x0070 000C 0x0040 058D 0x0040 058D 0x0040 050C 0x0040 0081 0x0040 018D 0x0040 058D 0x0040 098D 0x0040 0081 0x0050 0500 0x0040 0000 0x0040 0301 0x0020 0103 0x0040 000B 0x0020 010B 0x0030 010D 0x0020 0103 0x00F0 0100 0x0040 098D 0x0020 0103 0x0020 0103 0x0020 0103 0x0020 0103 0x0020 0103 0x0020 0100 0x00F0 0100 0x0030 0101 0x0030 010D 0x0030 010D 0x0030 010D PCM Size, Rate 0A 0x000E 07FF 0x000E 07E0 0x000E 07FF 0x000E 07FF 0x000E 07FF 0x000E 07FF 0x000E 07FF Stream Formats 0B 0x0000 0001 0x0000 0005 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 Pin Capabilities 0C Input Amp Capabilities 0D 0x80000000 0x0000 373F 0x0001 003F 0x0001 0010 0x0000 3727 0x0000 3737 0x0001 0017 0x0000 3737 0x0000 0024 0x0000 0020 0x0000 0010 0x0000 0020 0x8000 0000 0x0017 0300 0x8005 1F17 0x8000 0000 0x0000 0017 0x8000 0000 0x8000 0000 0x8000 0000 0x8000 0000 0x8000 0000 Rev. 0 | Page 13 of 20 | August 2008 ConnList Length 0E 0x0000 0001 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0001 0x0000 0001 0x0000 0008 0x0000 0008 0x0000 0000 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0000 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0000 0x0000 0002 0x0000 0000 0x0000 0001 0x0000 0002 0x0000 0000 0x0000 0008 0x0000 0001 0x0000 0002 0x0000 0008 0x0000 0001 0x0000 0002 0x0000 0002 0x0000 0002 0x0000 0002 0x0000 0002 0x0000 0001 0x0000 0003 0x0000 0002 0x0000 0001 0x0000 0001 0x0000 0001 Output Amp Power States Capabilities 0F 12 0x0000 0009 0x0005 2727 0x8005 2727 0x0000 0009 0x0005 2727 0x0000 0009 0x0005 2727 0x0000 0009 0x0005 2727 0x0000 0009 0x0000 0009 0x8005 3627 0x8005 3627 0x800B 0F0F 0x8000 0000 0x0000 0009 0x8000 0000 0x0000 0009 0x8005 1F1F 0x0000 0009 0x8000 0000 0x8000 0000 0x8000 0000 0x0000 0009 0x8005 1F1F 0x8000 0000 0x0027 0300 0x0027 0300 0x0027 0300 AD1882A HD AUDIO WIDGETS In the following table, node IDs that are not shown are reserved for future use. Table 11. HD Audio Widgets Node ID 00 01 02 03 04 05 08 09 0C 0D 10 11 12 13 14 15 16 17 18 19 1A 1B 1E 1F 20 21 22 23 24 26 27 29 2A 2C 2D 2F 37 39 3A 3C Name ROOT FUNCTION S/PDIF DAC DAC_0 DAC_1 DAC_2 ADC_0 ADC_1 ADC Selector 0 ADC Selector 1 Digital Beep Port A (Headphone) Port D (Front L/R) Mono Out Port B (Front Mic) Port C (Line In) Port F (Surr Back) Port E (Rear Mic) CD In Mixer Power Down Analog PCBeep S/PDIF Out Mono Out Mixer Digital Microphone Analog Mixer Mixer Output Atten Port A Mixer VREF Power Down Port G (C/LFE) Port E Mixer Port G Mixer Port D Mixer Port F Mixer Port C Mixer Stereo Mix Down BIAS Power Down Port A Out Selector Port B Boost Port C Boost Port E Boost Type ID x x 0 0 0 0 1 1 3 3 7 4 4 4 4 4 4 4 4 5 4 4 2 4 2 3 2 F 4 2 2 2 2 2 2 F 3 3 3 3 Type Root Function Audio Output Audio Output Audio Output Audio Output Audio Input Audio Input Audio Selector Audio Selector Beep Generator Pin Complex Pin Complex Pin Complex Pin Complex Pin Complex Pin Complex Pin Complex Pin Complex Power Widget Pin Complex Pin Complex Audio Mixer Pin Complex Audio Mixer Audio Selector Audio Mixer Vendor Defined Pin Complex Audio Mixer Audio Mixer Audio Mixer Audio Mixer Audio Mixer Audio Mixer Vendor Defined Audio Selector Audio Selector Audio Selector Audio Selector Description Device Identification Designates this Device as an Audio Codec S/PDIF Digital Stream Output Interface Headphone/Surround Side (7.1) Channel Digital/Audio Converters Stereo Front Channel Digital/Audio Converters Stereo C/LFE Channel Digital/Audio Converters Stereo Record Channel 1 Audio/Digital Converters Stereo Record Channel 2 Audio/Digital Converters Selects and Amplifies/Attenuates the Input to ADC0 Selects and Amplifies/Attenuates the Input to ADC1 Internal Digital PCBeep Signal Front Panel Headphone/Microphone Jack Rear Panel Front/Headphone Jack Monorail Output Pin (Internal Speakers or Telephony System) Front Panel Microphone/Headphone Jack Rear Panel Line-In Jack Rear Panel Surround-Rear (5.1) Jack Rear Panel Mic Jack Analog CD Input Powers Down the Analog Mixer and Associated Amps External Analog PCBeep Signal Input S/PDIF Output Pin Selects Which Source Drives the Mono Out Signal Digital Microphone Interface Mixes Individually Gainable Analog Inputs Attenuates the Mixer Output to Drive the Port Mixers Mixes the Port A Selected DAC and Mixer Output Amps to Drive Port A Powers Down the Internal and External VREF Circuitry Rear Panel C/LFE Jack Mixes DAC1 and Mixer Output Amps to Drive Port E Mixes DAC1 and Mixer Output Amps to Drive Port G Mixes DAC0 and Mixer Output Amps to Drive Port D Mixes DAC2 and Mixer Output Amps to Drive Port F Mixes the Port C Selected DAC and Mixer Output Amps to Drive Port C Mixes the Stereo L/R Channels to Drive Mono Output Powers Down the Internal MIC_BIAS_IN and all MIC_BIAS Pins Selects the Port A DAC (0, 1) Microphone Boost Amp for Port B Microphone Boost Amp for Port C Microphone Boost Amp for Port E Rev. 0 | Page 14 of 20 | August 2008 AD1882A CONNECTION LIST Table 12. Connection List Connections Node ID 02 03 04 05 08 09 0C 0D 10 11 12 13 14 15 16 17 18 19 1A 1B 1E 1F 20 21 22 23 24 26 27 29 2A 2C 2D 2F 37 39 3A 3C [0–3] 0x0000 001D 0x0000 000C 0x0000 000D 0x18BC 3911 0x18BC 3911 [4–7] 0x2012 3B1F 0x2012 3B1F 0 NID 1D 1 I 0x0C 0x0D 0x11 0x11 0x18 0x18 0x1F 0x1F 0x3B 0x3B 0x12 10x2 0x20 0x20 0x3A 0x11 0x12 0x3C 0x3B 0x18 0x1A 0x21 0x18 0x20 0x22 0x24 0x2E 0x30 0x20 0x21 0x0000 0002 0x0000 2104 0x02 0x04 0x21 0xBC30 AE24 0x39 0x20 0x37 0x11 1 0x27 0x05 0x05 0x04 0x03 0x03 0x1E 0x14 0x03 0x14 0x15 0x17 1 0x21 0x21 0x21 0x21 0x21 0x15 0x04 Rev. 0 | 0x17 Page 15 of 20 | August 2008 NID I 1 NID I NID 7 0x3C 0x3C 0x0000 2120 I 6 1 1 0x2C 0x2A 0x26 NID 5 0x39 0x39 0x0000 002C 0x0000 002A 0x0000 0026 I 4 NID 0x22 0x29 0x2D 0x1A18 3B3C 3 I 0x0000 0022 0x0000 0029 0x0000 002D 0x1211 3A39 0x0000 0020 0x0000 2137 0xA220 9811 0x0000 0027 0x0000 2105 0x0000 2105 0x0000 2104 0x0000 2103 0x0000 2103 0x0000 001E 0x0017 1514 0x0000 0403 0x0000 0014 0x0000 0015 0x0000 0017 2 NID I 1 NID 0x3C AD1882A DEFAULT CONFIGURATION BYTES In Table 13, default configuration values are set on codec power-up only. Default configuration values are not reset by link or soft reset to preserve modifications by BIOS control. Table 13. Default Configuration Bytes 31:30 29:28 27:24 23:20 19:16 15:12 Location Name Port A (Headphone) Port D (Front L/R) Mono Out Port B (Front Mic) Port C (Line In) Port F (Surr Back) Port E (Rear Mic) CD IN Analog PCBeep S/PDIF Out Digital Microphone Port G (C/LFE) Value Connectivity 0x0221 401F Jack 0x0101 4010 Jack 0x9017 01F0 Fixed 0x02A1 90F0 Jack 0x0181 3021 Jack 0x0101 1012 Jack 0x01A1 9020 Jack 0x9933 012E Fixed 0x90F7 01F0 Fixed 0x0145 11F0 Jack 0x97A6 09F0 Fixed 0x0101 6011 Jack Chassis External External Internal External External External External Internal Internal External Internal External Position Front Rear N/A Front Rear Rear Rear Special 3 N/A Rear Special 1 Rear 8 7:4 3:0 Def Assn 1 1 F F 2 1 2 2 F F F 1 Sequence F 0 0 0 1 2 0 E 0 0 0 1 Misc. Def. Device HP Out Line Out Speaker Mic In Line In Line Out Mic In CD Other SPDIF Out Mic In Line Out Rev. 0 | Page 16 of 20 | Conn Type Color 1/8” Jack Green 1/8” Jack Green Other Analog Unknown 1/8” Jack Pink 1/8” Jack Blue 1/8” Jack Black 1/8” Jack Pink ATAPI Unknown Other Analog Unknown Optical Black Other Digital Unknown 1/8” Jack Orange August 2008 JD 0 0 1 0 0 0 0 1 1 1 1 0 AD1882A OUTLINE DIMENSIONS Dimensions are shown in millimeters. 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 1 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 25 24 12 13 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 12° MAX PIN 1 INDICATOR 48 *EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 *NOTE: THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO VSS. THIS SHOULD BE IMPLEMENTED BY SOLDERING THE EXPOSED PAD TO A VSS PCB LAND THAT IS THE SAME SIZE AS THE EXPOSED PAD. THE VSS PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE VSS PLANE IN THE PCB WITH AN ARRAY OF THERMAL VIAS FOR BEST PERFORMANCE. Figure 5. 48-Lead, Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model AD1882AJCPZ1 AD1882AJCPZ-RL1 1 Temperature Range 0°C to 70°C 0°C to 70°C Package Description 48-Lead LFCSP_VQ 48-Lead LFCSP_VQ, 13” Tape and Reel Z = RoHS Compliant Part. Rev. 0 | Page 17 of 20 | August 2008 Package Option CP-48-1 CP-48-1 AD1882A Rev. 0 | Page 18 of 20 | August 2008 AD1882A Rev. 0 | Page 19 of 20 | August 2008 AD1882A ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07549-0-8/08(0) Rev. 0 | Page 20 of 20 | August 2008