HD74LV4040A 12-stage Binary Counter REJ03D0337–0200Z (Previous ADE-205-282 (Z)) Rev.2.00 Jul. 20, 2004 Description The HD74LV4040A is a 12 stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input. Low-voltage and highspeed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • • • • • • • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV4040AFPEL SOP–16 pin (JEITA) FP–16DAV FP EL (2,000 pcs/reel) HD74LV4040ARPEL HD74LV4040ATELL SOP–16 pin (JEDEC) TSSOP–16 pin FP–16DNV TTP–16DAV RP T EL (2,500 pcs/reel) ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs Output CLK CLR Qn ↑ ↓ X L L H Remains unchanged Changed All outputs low Note: H: L: X: ↑: ↓: High level Low level Immaterial Low to high transition High to low transition Rev.2.00 Jul. 20, 2004 page 1 of 10 HD74LV4040A Pin Arrangement Q12 1 16 VCC Q6 2 15 Q11 Q5 3 14 Q10 Q7 4 13 Q8 Q4 5 12 Q9 Q3 6 11 CLR Q2 7 10 9 Q1 GND 8 (Top view) Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range Input voltage range*1 Output voltage range*1, 2 VCC VI VO V V V Input clamp current Output clamp current Continuous output current IIK IOK IO Continuous current through VCC or GND ICC or IGND –0.5 to 7.0 –0.5 to 7.0 –0.5 to VCC + 0.5 –0.5 to 7.0 –20 ±50 ±25 ±50 Maximum power dissipation at 3 Ta = 25°C (in still air)* PT Storage temperature Tstg 785 500 –65 to 150 mA mA mA mA mW Conditions Output: H or L VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.2.00 Jul. 20, 2004 page 2 of 10 HD74LV4040A Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC Input voltage range Output voltage range Output current VI VO IOH 2.0 0 0 — — — — — — — — 0 0 0 5.5 5.5 VCC –50 –2 –6 –12 50 2 6 12 200 100 20 V V V µA mA –40 85 °C IOL Input transition rise or fall rate ∆t /∆v Operating free-air temperature Ta Note: Unused or floating inputs must be held high or low. Rev.2.00 Jul. 20, 2004 page 3 of 10 µA mA ns/V Conditions H or L VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V HD74LV4040A Logic Diagram CLR (11) (10) R (9) T R (7) T R (6) T R (5) T R (3) T R T Rev.2.00 Jul. 20, 2004 page 4 of 10 (2) R Q1 T R Q5 T R Q6 (12) T R Q4 (13) T R Q3 Q7 T R Q2 (4) T Q8 Q9 (14) Q 10 (15) Q 11 (1) Q 12 HD74LV4040A Timing Diagram 1 2 3 4 8 16 32 64 128 256 512 1024 2048 4096 CLR Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 COUNT CLEAR CLEAR DC Electrical Characteristics Ta = –40 to 85°C Item Symbol VCC (V)* Min Typ Max Unit Input voltage VIH 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 1.5 VCC×0.7 VCC×0.7 VCC×0.7 — — — — VCC–0.1 2.0 2.48 3.8 — — — — — — — — — — — — — — — — 0.5 VCC×0.3 VCC×0.3 VCC×0.3 — — — — V — — — — — — — — — — — — 0.1 0.4 0.44 0.55 ±1 20 µA µA IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VIN = 5.5 V or GND VIN = VCC or GND, IO = 0 — — — 3.7 5 — µA pF VI or VO = 0 to 5.5 V VI = VCC or GND VIL Output voltage VOH VOL Input current IIN Quiescent supply current Output leakage current Input capacitance ICC Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 IOFF CIN 0 3.3 V Test Conditions IOH = –50 µA IOH = –2 mA IOH = –6 mA IOH = –12 mA Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.2.00 Jul. 20, 2004 page 5 of 10 HD74LV4040A Switching Characteristics VCC = 2.5 ± 0.2 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax tPLH/tPHL — — 16.0 19.6 15.4 18.0 5.5 40 25 1.0 1.0 1.0 1.0 — — — 18.3 22.2 17.5 20.4 6.3 MHz Propagation delay time 90 60 10.0 12.7 9.9 11.8 3.0 Propagation delay time skew Setup time ∆tpd 50 30 — — — — — tSU 7.0 — — 7.0 — ns Pulse width tw 7.0 7.0 — — — — 7.0 7.0 — — ns tPHL ns ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF FROM (Input) TO (Output) CLK Q1 CLR Qn Qn+1 CLR inactive before CLK ↓ CLK high or low CLR high VCC = 3.3 ± 0.3 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax tPLH/tPHL — — 11.9 15.4 12.8 16.3 4.4 70 50 1.0 1.0 1.0 1.0 — — — 14.0 17.5 15.0 18.5 5.0 MHz Propagation delay time 140 80 7.5 10.0 8.3 10.8 2.4 Propagation delay time skew Setup time ∆tpd 75 55 — — — — — tSU 5.0 — — 5.0 — ns Pulse width tw 5.0 5.0 — — — — 5.0 5.0 — — ns tPHL Rev.2.00 Jul. 20, 2004 page 6 of 10 ns ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF FROM (Input) TO (Output) CLK Q1 CLR Qn Qn+1 CLR inactive before CLK ↓ CLK high or low CLR high HD74LV4040A Switching Characteristics (Cont.) VCC = 5.0 ± 0.5 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax tPLH/tPHL — — 7.3 9.3 8.6 10.6 3.1 125 80 1.0 1.0 1.0 1.0 — — — 8.5 10.5 10.0 12.0 3.5 MHz Propagation delay time 210 125 4.8 6.3 5.6 7.1 1.6 Propagation delay time skew Setup time ∆tpd 150 95 — — — — — tSU 5.0 — — 5.0 — ns Pulse width tw 5.0 5.0 — — — — 5.0 5.0 — — ns tPHL ns ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF FROM (Input) TO (Output) CLK Q1 CLR Qn Qn + 1 CLR inactive before CLK ↓ CLK high or low CLR high Operating Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC = (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 3.3 5.0 — — 17.3 19.0 — — pF f = 10 MHz Noise Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC = (V) Min Typ Max Unit Quiet output, maximum dynamic VOL VOL (P) 3.3 — 0.4 0.8 V Quiet output, minimum dynamic VOL VOL (V) 3.3 — –0.5 –0.8 V Quiet output, minimum dynamic VOH VOH (V) 3.3 — 3.0 — V High-level dynamic input voltage VIH (D) 3.3 2.31 — — V Low-level dynamic input voltage VIL (D) 3.3 — — 0.99 V Rev.2.00 Jul. 20, 2004 page 7 of 10 Test Conditions HD74LV4040A Test Circuit Measurement point CL * Note: C L includes the probe and jig capacitance. Waveform − 1 tf tr VCC 90% 50% VCC 10% GND tW tW 1/fmax tPLH Q1 tPHL 50% VCC Waveform − 2 VCC 50% VCC GND tsu tW CLR VCC 50% VCC GND tPHL Any Q Rev.2.00 Jul. 20, 2004 page 8 of 10 50% VCC HD74LV4040A Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0 ˚ – 8˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 16 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DAV — Conforms 0.24 g As of January, 2003 Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.40 ± 0.06 0.15 *0.20 ± 0.05 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0˚ – 8˚ 0.67 0.60 +– 0.20 0.25 M *Ni/Pd/Au plating Rev.2.00 Jul. 20, 2004 page 9 of 10 Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g HD74LV4040A As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 *0.20 ± 0.05 1.0 0.13 M Rev.2.00 Jul. 20, 2004 page 10 of 10 *0.15 ± 0.05 1.10 Max *Ni/Pd/Au plating 0.10 0.07 +0.03 –0.04 6.40 ± 0.20 0.65 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-16DAV — — 0.05 g Sales Strategic Planning Div. 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