ON NCV887701D1R2G Automotive grade start-stop non-synchronous boost controller Datasheet

NCV8877
Automotive Grade
Start-Stop Non-Synchronous
Boost Controller
The NCV8877 is a Non-Synchronous Boost controller designed to
supply a minimum output voltage during Start-Stop vehicle operation
battery voltage sags. The controller drives an external N-channel
MOSFET. The device uses peak current mode control with internal
slope compensation. The IC incorporates an internal regulator that
supplies charge to the gate driver.
Protection features include, cycle-by-cycle current limiting and
thermal shutdown.
Additional features include low quiescent current sleep mode
operation. The NCV8877 is enabled when the supply voltage drops
below the wake up threshold. Boost Operation is initiated when the
supply voltage drops below the regulation set point.
Features
• Automatic Enable Below Wake Up Threshold Voltage (Factory
•
•
•
•
•
•
•
•
•
•
•
Programmable)
Override Disable Function
Boost Mode Operation at Regulation Set Point
$2% Output Accuracy Over Temperature Range
Peak Current Mode Control with Internal Slope Compensation
Externally Adjustable Frequency Operation
Wide Input Voltage Range of 2 V to 40 V, 45 V Load Dump
Low Quiescent Current in Sleep Mode (<12 mA Typical)
Cycle−by−Cycle Current Limit Protection
Hiccup−Mode Overcurrent Protection (OCP)
Thermal Shutdown (TSD)
This is a Pb−Free Device
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MARKING
DIAGRAM
8
SOIC−8
D SUFFIX
CASE 751
8
1
8877xx
ALYW
G
1
8877xx = Specific Device Code
xx = 00, 01, 20, 40
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
DISB 1
8 ROSC
ISNS 2
7 VC
GND 3
6 VOUT
GDRV 4
5 VDRV
(Top View)
ORDERING INFORMATION
Typical Applications
• Applications Requiring Regulated Voltage through Cranking and
Start−Stop Operation
Device
Package
Shipping†
NCV887700D1R2G
NCV887701D1R2G
NCV887711D1R2G
SOIC−8
NCV887720D1R2G (Pb−Free)
2500 / Tape &
Reel
NCV887721D1R2G
NCV887740D1R2G
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
September, 2016 − Rev. 7
1
Publication Order Number:
NCV8877/D
NCV8877
BATTERY
IN
LP
VOUT
Cg
DB
Co
DISABLE
Q
DISB
VDRV
GDRV
CDRV
ISNS
ROSC
RSNS
ROSC
VOUT
VC
GND
RC
CC
Figure 1. Typical Application
Battery In
Sleep Threshold
Wake Up Threshold
Regulation
VOUT
(Internal signal)
DISB
Wakeup
Internal Clamp
Voltage
COMP
GDRV
Wake Up Delay
GDRV Switching Delay
Figure 2. Functional Waveforms
PACKAGE PIN DESCRIPTIONS
Pin No.
Pin
Symbol
1
DISB
Disable input. This part is disabled when this pin is brought low.
2
ISNS
Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense resistor to ground to sense the switching current for regulation and current limiting.
3
GND
Ground reference.
4
GDRV
Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from GDRV
to the gate to tailor EMC performance.
5
VDRV
Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VOUT. Bypass
with a 1.0 mF ceramic capacitor to ground.
6
VOUT
Monitors output voltage and provides IC input voltage.
7
VC
8
ROSC
Function
Output of the voltage error transconductance amplifier. An external compensator network from VC to GND is
used to stabilize the converter.
Use a resistor to ground to set the frequency.
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2
NCV8877
ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated)
Rating
Value
Unit
−0.3 to 40
V
Peak Transient Voltage (Load Dump on VOUT)
45
V
Dc Supply Voltage (VDRV, GDRV)
12
V
−0.3 to 3.6
V
−0.3 to 6
V
Dc Supply Voltage (VOUT)
Dc Voltage (VC, ISNS, ROSC)
Dc Voltage (DISB)
Dc Voltage Stress (VOUT − VDRV)
−0.7 to 40
V
Operating Junction Temperature
−40 to 150
°C
Storage Temperature Range
−65 to 150
°C
Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C
265 peak
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
PACKAGE CAPABILITIES
Characteristic
ESD Capability (All Pins)
Human Body Model
Machine Model
Moisture Sensitivity Level
1. 1
Unit
≥2.0
≥200
kV
V
1
Package Thermal Resistance
in2,
Value
°C/W
100
Junction−to−Ambient, RqJA (Note 1)
1 oz copper area used for heatsinking.
TYPICAL VALUES
Part No.
Dmax
fS
Sa
Vcl
Isrc
Isink
VOUT
SCE
NCV887700
83%
170 kHz
34 mV/ms
400 mV
800 mA
600 mA
6.8 V
N
NCV887701
83%
170 kHz
53 mV/ms
200 mV
800 mA
600 mA
6.8 V
N
NCV887711
83%
170 kHz
34 mV/ms
200 mV
800 mA
600 mA
8.55 V
N
NCV887720
83%
170 kHz
53 mV/ms
200 mV
800 mA
600 mA
10 V
N
NCV887721
83%
170 kHz
53 mV/ms
200 mV
800 mA
600 mA
10.28 V
N
NCV887740
83%
170 kHz
53 mV/ms
200 mV
800 mA
600 mA
12 V
N
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NCV8877
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.6 V < VOUT < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
VOUT = 13.2 V, TJ = 25°C, DISB = 0 V
−
12
14
mA
Into VOUT pin, VOUT,reg < VOUT <
VOUT,des, No switching
−
2.2
4.0
mA
153
−
501
kHz
GENERAL
Quiescent Current, Sleep Mode
Iq,sleep
Quiescent Current, No switching
Iq,off
OSCILLATOR
Switching Frequency
ROSC Voltage
FSW
−
1.0
−
V
Switching Frequency
VROSC
FSW
ROSC = Open
153
170
187
kHz
Default Switching
FSW
ROSC = Open
ROSC = 100 kW
ROSC = 20 kW
ROSC = 10 kW
153
180
283
409
170
200
315
455
187
220
347
501
kHz
90
115
145
ns
81
83
85
%
30
46
46
46
46
46
34
53
53
53
53
53
38
60
60
60
60
60
mV/ ms
−
0.6
1.0
mA
Minimum Pulse Width
ton,min
Maximum Duty Cycle
Dmax
Slope Compensating Ramp
(Note 2)
ROSC = OPEN
Sa
NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
DISABLE
DISB Pull−down Current (Note 2)
IDIS
DISB Input High Voltage
Vd,ih
2.0
−
5.0
V
Vd,hys
−
500
−
mV
Vd,il
0
−
800
mV
Input−to−output gain at dc, ISNS ≤ 1 V
0.9
1.0
1.1
V/V
2.5
−
−
MHz
−
30
50
mA
360
180
180
180
180
180
400
200
200
200
200
200
440
220
220
220
220
220
mV
−
80
125
ns
125
150
175
%
−
80
125
ns
0.8
1.2
1.63
mS
DISB Input High Voltage Hysteresis
DISB Input Low Voltage
VDIS = 5 V
CURRENT SENSE AMPLIFIER
Low−Frequency Gain
Acsa
Bandwidth
BWcsa
Gain of Acsa − 3 dB
ISNS Input Bias Current
Isns,bias
Out of ISNS pin
Current Limit Threshold Voltage
Vcl
Voltage on ISNS pin
Current Limit, Response Time (Note
2)
tcl
CL tripped until GDRV falling edge,
VISNS = Vcl(typ) + 60 mV
Overcurrent Protection,
Threshold Voltage
%Vocp
Overcurrent Protection,
Response Time (Note 2)
tocp
NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
Percent of Vcl
From overcurrent event, Until switching
stops, VISNS = VOCP + 40 mV
VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
VOUT = ±100 mV
Transconductance
gm,vea
VEA Output Resistance (Note 2)
Ro,vea
2.0
−
−
MΩ
VEA Maximum Output Voltage
Vc,max
2.5
−
−
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Not tested in production. Limits are guaranteed by design.
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NCV8877
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.6 V < VOUT < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
VEA Sourcing Current
Isrc,vea
VEA output current, Vc = 2.0 V
80
100
−
mA
VEA Sinking Current
Isnk,vea
VEA output current, Vc = 1.5 V
80
100
−
mA
VEA Clamp Voltage
Vc,clamp
VOUT < VOUT,des
−
1.1
−
V
VOUT < VOUT,des or when IC DISB goes
from low to high with Vc pin compensation
network disconnected
−
55
64
ms
GDRV Switching Delay
GATE DRIVER
Sourcing Current
Isrc
VDRV ≥ Typical Driving Voltage Specification, VDRV − VGDRV = 2 V
550
800
−
mA
Sinking Current
Isink
VGDRV ≥ 2 V
480
600
−
mA
VOUT − VDRV, IvDRV = 25 mA
−
0.3
0.6
V
VOUT − VDRV = 1 V
35
45
−
mA
−
−
0.7
V
5.8
5.8
5.7
5.8
5.92
5.8
6.0
6.0
5.9
6.0
6.12
6.0
6.2
6.2
6.1
6.2
6.32
6.2
V
−
21
−
kW
Driving Voltage Dropout (Note 2)
Vdrv,do
Driving Voltage Source Current
Idrv
Backdrive Diode Voltage Drop
Vd,bd
VDRV – VOUT, Id,bd = 5 mA
Driving Voltage
VDRV
IVDRV = 0.1 − 25 mA
NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
Pull−down Resistance
UVLO
Undervoltage Lock−out,
Threshold Voltage
Vuvlo
VOUT falling
NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
3.60
3.60
3.54
3.60
3.67
3.60
3.80
3.80
3.73
3.80
3.87
3.80
4.00
4.00
3.93
4.00
4.08
4.00
V
Undervoltage Lock−out,
Hysteresis
Vuvlo,hys
VOUT rising
NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
330
330
325
330
337
330
450
450
442
450
459
450
570
570
563
570
581
570
mV
THERMAL SHUTDOWN
Thermal Shutdown Threshold (Note
2)
Tsd
TJ rising
160
170
180
°C
Thermal Shutdown Hysteresis (Note
2)
Tsd,hys
TJ falling
10
15
20
°C
Thermal Shutdown Delay (Note 2)
tsd,dly
From TJ > Tsd to stop switching
−
−
100
ns
6.66
6.66
8.06
9.80
10.08
11.76
6.80
6.80
8.55
10.00
10.28
12.00
6.94
6.94
8.72
10.20
10.49
12.24
V
VOLTAGE REGULATION
Voltage Regulation
VOUT,reg
NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Not tested in production. Limits are guaranteed by design.
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NCV8877
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.6 V < VOUT < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
VOLTAGE REGULATION
Threshold IC Enable
VOUT descending
NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
7.10
7.10
8.86
10.36
10.65
12.64
7.30
7.30
9.11
10.65
10.95
13.00
7.50
7.50
9.35
10.94
11.29
13.36
V
Threshold IC Disable
VOUT ascending
NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
7.55
7.55
9.37
10.96
11.27
13.40
7.75
7.75
9.62
11.25
11.57
13.75
7.95
7.95
9.87
11.54
11.86
14.10
V
Threshold IC Enable – Voltage Regulation
NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
0.32
0.32
0.33
0.39
0.40
0.52
0.5
0.5
0.5
0.6
0.6
0.8
−
−
−
−
−
−
V
Threshold IC Disable – Threshold
IC Enable
NCV887700
NCV887701
NCV887711
NCV887720
NCV887721
NCV887740
−
−
−
−
−
−
0.4
0.4
0.4
0.5
0.5
0.7
−
−
−
−
−
−
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Not tested in production. Limits are guaranteed by design.
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NCV8877
TYPICAL CHARACTERISTICS
2.12
Iq,on, QUIESCENT CURRENT (mA)
Iq,sleep, SLEEP CURRENT (mA)
15
VOUT = 13.2 V
14
13
12
11
10
−50
0
50
100
2.10
2.08
2.06
2.04
2.02
2.00
−50
150
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Sleep Current vs. Temperature
Figure 4. Quiescent Current vs. Temperature
150
1.020
124
NORMALIZED CURRENT LIMIT
123
122
121
120
119
118
117
116
115
−50
0
50
100
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
−50
150
0
50
100
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Minimum On Time vs. Temperature
Figure 6. Normalized Current vs. Temperature
NORMALIZED VOUT REGULATION (V)
1.006
1.004
1.002
1.000
0.998
0.996
−50
0
50
100
150
TJ, JUNCTION TEMPERATURE (°C)
SWITCHING FREQUENCY (ROSC = Open) (kHz)
ton,min, MINIMUM ON TIME (ns)
VOUT = VOUT,reg < VOUT < VOUT descending
fs = 170 kHz
169.0
168.8
168.6
168.4
168.2
168.0
167.8
167.6
167.4
167.2
167.0
−50
ROSC = Open
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 8. Switching Frequency vs.
Temperature
Figure 7. VOUT Regulation vs. Temperature
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7
150
NCV8877
TYPICAL CHARACTERISTICS
7.9
VOUT Rising
THRESHOLD IC VOLTAGE (V)
UVLO THRESHOLD (V)
4.3
4.2
4.1
4.0
3.9
VOUT Falling
3.8
−50
0
50
100
DISABLE
7.7
7.6
7.5
7.4
ENABLE
7.3
−50
150
50
100
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. UVLO Threshold vs. Temperature
Figure 10. NCV887700/01 Threshold IC Voltage
vs. Temperature
11.3
THRESHOLD IC VOLTAGE (V)
DISABLE
11.0
10.9
10.8
10.7
10.6
ENABLE
10.5
10.4
−50
0
50
100
DISABLE
11.2
11.1
11.0
10.9
10.8
ENABLE
10.7
10.6
−50
150
TJ, JUNCTION TEMPERATURE (°C)
0
50
100
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. NCV887711 Threshold IC Voltage
vs. Temperature
Figure 12. NCV887720 Threshold IC Voltage
vs. Temperature
13.8
11.5
DISABLE
THRESHOLD IC VOLTAGE (V)
THRESHOLD IC VOLTAGE (V)
0
TJ, JUNCTION TEMPERATURE (°C)
11.1
THRESHOLD IC VOLTAGE (V)
7.8
11.4
11.3
11.2
11.1
11.0
ENABLE
10.9
10.8
−50
0
50
100
13.6
13.5
13.4
13.3
13.2
13.1
13.0
−50
150
DISABLE
13.7
TJ, JUNCTION TEMPERATURE (°C)
ENABLE
0
50
100
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. NCV887721 Threshold IC Voltage
vs. Temperature
Figure 14. NCV887740 Threshold IC Voltage
vs. Temperature
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NCV8877
TYPICAL CHARACTERISTICS
Idisb, PULLDOWN CURRENT (nA)
750
700
650
600
550
500
−50
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. DISB Pulldown Current vs.
Temperature
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150
NCV8877
THEORY OF OPERATION
VIN
ROSC
ROSC
Oscillator
PWM Comparator
L
GDRV
S Q
Gate
Drive
R
CO
RL
ISNS
+
VOUT
RSNS
CSA
Slope
Compensation
GND
Voltage
Error
WAKEUP
RDAMP
VOUT
CDECOUPLING
VEA
NCV8877
VC
DISB
DISABLE
Figure 16. Current Mode Control Schematic
DISB
Current Mode Control
The DISB pin provides an IC disable function. When a DC
logic-low voltage is applied to this pin, the NCV8877 enters
a low quiescent sleep mode, permitting an external signal to
either shutdown the IC or disable the wakeup function.
The NCV8877 incorporates a current mode control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the on−time of the
power switch. The oscillator is used as a fixed−frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and the error amplifier, which is commonly
found in voltage mode controllers. The second benefit
comes from inherent pulse−by−pulse current limiting by
merely clamping the peak switching current. Finally, since
current mode commands an output current rather than
voltage, the filter offers only a single pole to the feedback
loop. This allows for a simpler compensation.
The NCV8877 also includes a slope compensation
scheme in which a fixed ramp generated by the oscillator is
added to the current ramp. A proper slope rate is provided to
improve circuit stability without sacrificing the advantages
of current mode control.
Regulation
The NCV8877 is a non−synchronous boost controller
designed to supply a minimum output voltage during
Start−Stop vehicle operation battery voltage sags. The
NCV8877 is in low quiescent current sleep mode under
normal battery operation (12 V) and is enabled when the
supply voltage drops below the descending threshold (7.3 V
for the NCV887700). Boost operation is initiated when the
supply voltage is below the regulation set point (6.8 V for the
NCV887700). Once the supply voltage sag condition ends
and begins to increase, the NCV8877 boost operation will
cease when the supply voltage increases beyond the
regulation set point. The NCV8877 low quiescent current
sleep mode resumes once the supply voltage increases
beyond the ascending voltage threshold (7.6 V for the
NCV887700).
The NCV8877 VOUT pin serves the dual purpose: (1)
powering the NCV8877 and (2) providing the regulation
feedback signal. The feedback network is imbedded within
the IC to eliminate the constant current battery drain that would
exist with the use of external voltage feedback resistors.
There is no soft−start operating mode. The NCV8877 will
instantly respond to a voltage sag so as to maintain normal
operation of downstream loads. Once the NCV8877 is
enabled, the voltage error operational transconductance
amplifier supplies current to set VC to 1.1 V to minimize the
feedback loop response time when the battery voltage sag
goes below the regulation set point.
Current Limit
The NCV8877 features two current limit protections,
peak current mode and over current latch off. When the
current sense amplifier detects a voltage above the peak
current limit between ISNS and GND after the current limit
leading edge blanking time, the peak current limit causes the
power switch to turn off for the remainder of the cycle. Set
the current limit with a resistor from ISNS to GND, with R
= VCL / Ilimit.
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10
NCV8877
If the voltage across the current sense resistor exceeds the
over current threshold voltage the device enters over current
hiccup mode. The device will remain off for the hiccup time
and then go through the soft−start procedure.
D min + 1 *
D max + 1 *
UVLO
V IN(max)
V OUT
V IN(min)
V OUT
Both duty cycles will actually be higher due to power loss
in the conversion. The exact duty cycles will depend on
conduction and switching losses. If the maximum input
voltage is higher than the output voltage, the minimum duty
cycle will be negative. This is because a boost converter
cannot have an output lower than the input. In situations
where the input is higher than the output, the output will
follow the input, minus the diode drop of the output diode
and the converter will not attempt to switch.
If the calculated Dmax is higher the Dmax of the NCV8877,
the conversion will not be possible. It is important for a boost
converter to have a restricted Dmax, because while the ideal
conversion ration of a boost converter goes up to infinity as
D approaches 1, a real converter’s conversion ratio starts to
decrease as losses overtake the increased power transfer. If
the converter is in this range it will not be able to regulate
properly.
If the following equation is not satisfied, the device will
skip pulses at high VIN:
Input Undervoltage Lockout (UVLO) is provided to
ensure that unexpected behavior does not occur when VIN
is too low to support the internal rails and power the
controller. The IC will start up when enabled and VIN
surpasses the UVLO threshold plus the UVLO hysteresis
and will shut down when VIN drops below the UVLO
threshold or the part is disabled.
VDRV
An internal regulator provides the drive voltage for the
gate driver. Bypass with a ceramic capacitor to ground to
ensure fast turn on times. The capacitor should be between
0.1 mF and 1 mF, depending on switching speed and charge
requirements of the external MOSFET.
VDRV uses an internal linear regulator to charge the
VDRV bypass capacitor. VOUT must be decoupled at the IC
by a capacitor that is equal or larger in value than the VDRV
decoupling capacitor.
APPLICATION INFORMATION
Design Methodology
D min
w t on(min)
fs
This section details an overview of the component selection
process for the NCV8877 in continuous conduction mode
boost. It is intended to assist with the design process but does
not remove all engineering design work. Many of the
equations make heavy use of the small ripple approximation.
This process entails the following steps:
1. Define Operational Parameters
2. Select Operating Frequency
3. Select Current Sense Resistor
4. Select Output Inductor
5. Select Output Capacitors
6. Select Input Capacitors
7. Select Compensator Components
8. Select MOSFET(s)
9. Select Diode
10. Design Notes
11. Determine Feedback Loop Compensation Network
Where: fs: switching frequency [Hz]
ton(min): minimum on time [s]
2. Select Operating Frequency
The default setting is an open ROSC pin, allowing the
oscillator to operate at the default frequency Fs. Adding a
resistor to GND increases the switching frequency.
The graph in Figure 17, below, shows the required
resistance to program the frequency. From 200 kHz to
500 kHz, the following formula is accurate to within 3% of
the expected
100
90
80
ROSC (kW)
70
1. Define Operational Parameters
Before beginning the design, define the operating
parameters of the application. These include:
VIN(min): minimum input voltage [V]
VIN(max): maximum input voltage [V]
VOUT: output voltage [V]
IOUT(max): maximum output current [A]
ICL: desired typical cycle-by-cycle current limit [A]
60
50
40
30
20
10
0
150
From this the ideal minimum and maximum duty cycles
can be calculated as follows:
200
250
300
350 400
FSW (kHz)
450
Figure 17. ROSC vs. FSW
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11
500 550
NCV8877
R OSC +
V OUT(ripple) +
2859
(F sw * 170)
DI OUT(max)
fC OUT
Where: fsw: switching frequency [kHz]
ROSC: resistor from ROSC pin to GND [k]
Note: The ROSC resistor ground return to the NCV8877 pin
3 must be independent of power grounds.
I Cout(RMS) + I OUT
Current sensing for peak current mode control and current
limit relies on the MOSFET current signal, which is
measured with a ground referenced amplifier. The easiest
method of generating this signal is to use a current sense
resistor from the source of the MOSFET to device ground.
The sense resistor should be selected as follows:
I OUT(max)
1*D
)
V IN(min)D
2fL
Ǔ
R ESR
Ǹ
D WC
D
) WC
12
DȀ WC
ǒ
DȀ WC
L
R
OUT
T
SW
Ǔ
2
The use of parallel ceramic bypass capacitors is strongly
encouraged to help with the transient response.
6. Select Input Capacitors
The input capacitor reduces voltage ripple on the input to
the module associated with the ac component of the input
current.
V
R S + CL
I CL
Where: RS: sense resistor [W]
VCL: current limit threshold voltage [V]
ICL: desire current limit [A]
I Cin(RMS) +
V IN(WC) 2 D WC
Lf sV OUT2 Ǹ3
7. Select Compensator Components
4. Select Output Inductor
Current Mode control method employed by the NCV8877
allows the use of a simple, Type II compensation to optimize
the dynamic response according to system requirements.
The output inductor controls the current ripple that occurs
over a switching period. A high current ripple will result in
excessive power loss and ripple current requirements. A low
current ripple will result in a poor control signal and a slow
current slew rate in case of load steps. A good starting point
for peak to peak ripple is around 20−40% of the inductor
current at the maximum load at the worst case VIN, but
operation should be verified empirically. The worst case VIN
is half of VOUT, or whatever VIN is closest to half of VOUT.
After choosing a peak current ripple value, calculate the
inductor value as follows:
8. Select MOSFET(s)
In order to ensure the gate drive voltage does not drop out
the MOSFET(s) chosen must not violate the following
inequality:
Q g(total) v
DI L,max f s
Where: VIN(WC): VIN value as close as possible to
half of VOUT [V]
DWC: duty cycle at VIN(WC)
DIL,max: maximum peak to peak ripple [A]
The maximum average inductor current can be calculated
as follows:
I Q(max) + I out
ǸD
DȀ
The maximum voltage across the MOSFET will be the
maximum output voltage, which is the higher of the
maximum input voltage and the regulated output voltaged:
V Q(max) + V OUT(max)
V OUTI OUT(max)
9. Select Diode
V IN(min)h
The output diode rectifies the output current. The average
current through diode will be equal to the output current:
The Peak Inductor current can be calculated as follows:
I L,peak + I L,avg )
I drv
fs
Where: Qg(total): Total Gate Charge of MOSFET(s) [C]
Idrv: Drive voltage current [A]
fs: Switching Frequency [Hz]
The maximum RMS Current can be calculated as follows:
V IN(WC) D WC
I L,AVG +
ǒ
The capacitors need to survive an RMS ripple current as
follows:
3. Select Current Sense Resistor
L+
)
DI L,max
I D(avg) + I OUT(max)
2
Additionally, the diode must block voltage equal to the
higher of the output voltage and the maximum input voltage:
Where: IL,peak: Peak inductor current value [A]
V D(max) + V OUT(max)
5. Select Output Capacitors
The output capacitors smooth the output voltage and
reduce the overshoot and undershoot associated with line
transients. The steady state output ripple associated with the
output capacitors can be calculated as follows:
The maximum power dissipation in the diode can be
calculated as follows:
P D + V f (max) I OUT(max)
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12
NCV8877
Where: Pd: Power dissipation in the diode [W]
Vf(max): Maximum forward voltage of the diode [V]
♦
10. Design Notes
• VOUT serves a dual purpose (feedback and IC power).
•
•
•
•
•
•
•
The VDRV circuit has a current pulse power draw
resulting in current flow from the output sense location
to the IC. Trace ESL will cause voltage ripple to
develop at IC pin VOUT which could affect
performance.
♦ Use a 1 mF IC VOUT pin decoupling capacitor close
to IC in addition to the VDRV decoupling capacitor.
Classic feedback loop measurements are not possible
(VOUT pin serves a dual purpose as a feedback path
and IC power). Feedback loop computer modeling
recommended.
♦ A step load test for stability verification is
recommended.
Compensation ground must be dedicated and connected
directly to IC ground.
♦ Do not use vias. Use a dedicated ground trace.
ROSC programming resistor ground must be dedicated
and connected directly to IC ground
♦ Do not use vias. Use a dedicated ground trace.
IC ground & current sense resistor ground sense point
must be located on the same side of PCB.
♦ Vias introduce sufficient ESR/ESL voltage drop
which can degrade the accuracy of the current
feedback signal amplitude (signal bounce) and
should be avoided.
Star ground should be located at IC ground pad.
♦ This is the location for connecting the compensation
and current sense grounds.
The IC architecture has a leading edge ISNS blanking
circuit. In some instances, current pulse leading edge
current spike RC filter may be required.
♦ If required, 330 pF + 250 W are a recommended
evaluation starting point.
RDAMPING (optional)
♦ The IC-VOUT pin may be located a few cm from
the output voltage sensing point. Parasitic
inductance from the feedback trace (roughly
5 nH/cm) results in the requirement for a decoupling
capacitor (Cdecoupling = 1 mF recommended) next to
the IC-VOUT pin to support the VDRV charging
pulses. The IC-VDRV energy is replenished from
current pulses by an internal linear regulator whose
charging frequency corresponds to that of the IC
oscillator (phase lag may occur; some charging
pulses may occasionally be skipped depending on
the state of the VDRV voltage). The trace’s parasitic
inductance can introduce a low amplitude damped
voltage oscillation between the IC-VOUT and the
♦
output voltage sense location which may result in
minor frequency jitter.
If the measured frequency jitter is objectionable, it
may be attenuated by placing a series damping
resistor (Rdamp) in the feedback path between the
output voltage sense and IC-VOUT. The resulting
filter introduced by Rdamp introduces a high
frequency pole in the feedback loop path. The RC
filter 3 dB pole frequency must be chosen at a
minimum of 1 decade above the design’s feedback
loop cross-over frequency (at minimum power
supply input voltage where the worst case phase
margin will occur) to avoid deteriorating the
feedback loop cross-over frequency phase margin.
The average operating current demand from the IC
is dominated by the MOSFET gate drive power
energy consumption (IVDRV = Qg(tot)_6V x fosc).
The IVDRV x Rdamp voltage drop results in a
corresponding increase in power supply regulation
voltage. Rdamp is typically 0.68 W, so the resulting
increase in output voltage regulation will be minimal
(10-30 mV may be typical).
11. Determine Feedback Loop Compensation Network
The purpose of a compensation network is to stabilize the
dynamic response of the converter. By optimizing the
compensation network, stable regulation response is
achieved for input line and load transients.
Compensator design involves the placement of poles and
zeros in the closed loop transfer function. Losses from the
boost inductor, MOSFET, current sensing and boost diode
losses also influence the gain and compensation
expressions. The OTA has an ESD protection structure
(RESD ≈ 502 W, data not provided in the datasheet) located
on the die between the OTA output and the IC package
compensation pin (VC). The information from the OTA
PWM feedback control signal (VCTRL) may differ from the
IC−VC signal if R2 is of similar order of magnitude as RESD .
The compensation and gain expressions which follow take
influence from the OTA output impedance elements into
account.
Type−I compensation is not possible due to the presence
of RESD . The Figure 18 compensation network corresponds
to a Type−II network in series with RESD . The resulting
control−output transfer function is an accurate mathematical
model of the IC in a boost converter topology. The model
does have limitations and a more accurate SPICE model
should be considered for a more detailed analysis:
• The attenuating effect of large value ceramic capacitors
in parallel with output electrolytic capacitor ESR is not
considered in the equations.
• The efficiency term h should be a reasonable operating
condition estimate.
www.onsemi.com
13
NCV8877
L
rL
VIN
Vd
VOUT
rCf
R OUT
Rds(on)
VC
COUT
GDRV
R2
RESD
C2
C1
ISNS
R1
VCTRL
OTA
RLOW
Ri
R0
VREF
VOUT
GND
Figure 18. NCV8877 OTA and Compensation
A worksheet as well as a SPICE model which may be used
for selecting compensation components R2 , C1 , C2 is
available at the ON Semiconductor web site
(http://onsemi.com/PowerSolutions/product.do?id=NCV8
877). The following equations may be used to analyze the
Figure 10 boost converter. Required input design parameters
for analysis are:
Vd = Boost diode Vf (V)
VIN = Boost supply input voltage (V)
Ri = Current sense resistor (W)
RDS(on) = MOSFET RDS(on) (W)
COUT = Bulk output capacitor value (F)
Rsw_eq = RDS(on) + Ri, for the boost continuous
conduction mode (CCM) expressions
rCF = Bulk output capacitor ESR (W)
ROUT = Equivalent resistance of output load (W)
Pout = Output Power (W)
L = Boost inductor value (H)
rL = Boost inductor ESR (W)
Ts = 1/fs, where fs = clock frequency (Hz)
VOUT = Device specific output voltage (e.g. 6.8 V
for NCV887701) (V)
Vref = OTA internal voltage reference = 1.2 V
R0 = OTA output resistance = 3 MW
Sa = IC slope compensation (e.g. 53 mV/ms for
NCV887701)
gm = OTA transconductance = 1.2 mS
D = Controller duty ratio
D’ = 1 − D
www.onsemi.com
14
NCV8877
Necessary equations for describing the modulator gain (Vctrl−to−Vout gain) Hctrl_output(f) are described in Table 1.
Table 1. BOOST CCM TRANSFER FUNCTION EXPRESSIONS
Duty ratio (D)
ȡ
ȧ
ȧ
ȧ
ȧ
Ȣ
−V
2R
Ǹ ǒ
OUT
R
OUT
V V
ƪ
R
ǒ
V
IN
* R sw_eq)R
*2
OUT V
OUT d IN
OUT
V
OUT
Ǔ
2
ȣ
ȧ
ȧ
ȧ
ȧ
Ȥ
2)2R
V
sw_eqV INV OUT*4V dR sw_eqV IN
OUT IN
2
)R sw_eq 2V
2*4r V V *4r V
2
−4R sw_eqV
OUT
L d IN
L OUT
OUT
2R
ǒVOUT 2 ) VdVINǓ
OUT
1
1*D
Vout/Vin Power Supply DC Conversion Ratio (M)
P OUT
Average Inductor Current (Ilave)
V INh
V IN * I Laveǒr L ) R sw_eqǓ
Inductor On−slope (Sn)
L
1)
Compensation Ramp (mc)
Ri
Sa
Sn
1
r CFC OUT
Cout ESR Zero (wz1)
Right−half−plane Zero (wz2)
Ǔƫ
(1 * D )
L
2
ǒ
R OUT *
2
Low Frequency Modulator Pole
(wp1)
R
OUT
r CFR OUT
Ǔ
r CF ) R OUT
)
Ts
LM 3
*
rL
L
mc
C OUT
p
Ts
Sampling Double Pole (wn)
1
p(m c(1 * D) * 0.5)
Sampling Quality Coefficient (Qp)
1
Fm
2M )
R
Ǔ
hR OUT
Hd
Control−output Transfer Function
(Hctrl_output(f))
ǒ
T
S
OUT s 1
) a
2
Sn
LM 2
Ri
ǒ1 ) j z1Ǔ
2pf
w
F mH d
ǒ* j z2Ǔ
ǒ1 ) j Ǔ ǒ1 ) j
2pf
w
p1
2pf
w
2pf
w nQ p
Ǔ
) ǒj 2pf
wn
Ǔ
2
Once the desired cross−over frequency (fc) gain adjustment and necessary phase boost are determined from the Hctrl_output(f)
gain and phase plots, the Table 2 equations may be used. It should be noted that minor compensation component value
adjustments may become necessary when R2 ≤ ~10 · Resd as a result of approximations for determining components R2, C1,
C2.
www.onsemi.com
15
NCV8877
Table 2. OTA COMPENSATION TRANSFER FUNCTION AND COMPENSATION VALUES
Desired OTA Gain at Cross−over
Frequency fc (G)
10
ǒq
Desired Phase Boost at Cross−
over Frequency fc (boost)
desired_G fc_gain_db
20
ǒHctrl_output(fc)Ǔ 180°
* 90° Ǔ
p
margin * arg
p
180°
w p1e
Select OTA Compensation Zero to
Coincide with Modulator Pole at
fp1 (fz)
2p
f zf c ) f c 2 tan(boost)
Resulting OTA High Frequency
Pole Placement (fp)
f c * f z tan(boost)
Ǹ
Compensation Resistor (R2)
1)
V OUT
f pG
Ǹ
f p * f z 1.2 g m
1)
Compensation Capacitor (C1)
1
2pf 2R 2
Compensation Capacitor (C2)
1 1.2 g m
2pf p V OUT
OTA DC Gain (G0_OTA)
V ref
V OUT
Low Frequency Zero (wz1e)
High Frequency Zero (wz2e)
ǒR 2 ) R esdǓȱ
ȧ
Ȳ
ǒ
Ǔȱ
1 R )R
ȧ1 )
2 R R C
Ȳ
ǒR ) R ) R Ǔȱ
ȧ1 *
R ǒR ) R ǓC
Ȳ
ǒR ) R ) R Ǔȱ
ȧ1 )
R ǒR ) R ǓC
Ȳ
1
2
R 2R esdC 2
2
1*
esd
2 esd 2
Low Frequency Pole (wp1e)
1
2
High Frequency Pole (wp2e)
1
2
0
2
2
0
0
2
esd
esd
2
0
2
esd
esd
2
OTA Transfer Function (GOTA(f))
Ǹ
1*4
Ǹ
1*4
Ǹ
Ǹ
1*4
1*4
2pf
1)
2
fc
fp
ǒǓ
fz
fp
g mR 0
1 ) jw
−G 0_OTA
ǒǓ
z1e
j w2pf
p1e
R 2R esdC 2
ǒR 2 ) R esdǓ
2
C1
R 2R esdC 2
ǒR 2 ) R esdǓ
2
C1
ȳ
ȧ
ȴ
ȳ
ȧ
ȴ
R 2ǒR 0 ) R esdǓC 2
ǒR 0 ) R 2 ) R esdǓ
2
C1
R 2ǒR 0 ) R esdǓC 2
ǒR 0 ) R 2 ) R esdǓ
2
C1
ȳ
ȧ
ȴ
ȳ
ȧ
ȴ
2pf
1 ) jw
1)
z2e
j w2pf
p2e
The open−loop−response in closed−loop form to verify the gain/phase margins may be obtained from the following
expressions.
T(f) + G OTA(f)H ctrl_output(f)
www.onsemi.com
16
NCV8877
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
S
J
SOLDERING FOOTPRINT*
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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