TI BQ24123 Single-chip switchmode, li-ion and li-polymer charge-management ic with enhanced emi performance Datasheet

bq24120
bq24123
Actual Size
3,5 mm x 4,5 mm
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SLUS688 – MARCH 2006
SINGLE-CHIP SWITCHMODE, LI-ION AND LI-POLYMER CHARGE-MANAGEMENT
IC WITH ENHANCED EMI PERFORMANCE(bqSWITCHER™)
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APPLICATIONS
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Handheld Products
Portable Media Players
Industrial and Medical Equipment
Portable Equipment
Portable DVD Players
The bqSWITCHER charges the battery in three
phases: conditioning, constant current, and constant
voltage. Charge is terminated based on userselectable minimum current level. A programmable
charge timer provides a safety backup for charge
termination. The bqSWITCHER automatically restarts
the charge cycle if the battery voltage falls below an
internal threshold. The bqSWITCHER automatically
enters sleep mode when VCC supply is removed.
RHL PACKAGE
(TOP VIEW BQ24123)
STAT1
IN
IN
PG
VCC
TTC
ISET1
ISET2
2
1
OUT
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The bqSWITCHER™ series are highly integrated
Li-ion
and
Li-polymer
switch-mode
charge
management devices targeted at a wide range of
portable applications. The bqSWITCHER™ series
offers integrated synchronous PWM controller and
power FETs, high-accuracy current and voltage
regulation, charge preconditioning, charge status, and
charge termination, in a small, thermally enhanced
QFN package.
20 19
3
18
4
17
5
16
6
15
7
14
8
13
9 10
11 12
STAT2
PGND
PGND
CE
SNS
BAT
CELLS
TS
VTSB
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Enhanced EMI Performance
Integrated Power FETs For Up To 2-A Charge
Rate
Ideal For Highly Efficient Charger Designs For
Single-Cell or Two-Cell Li-Ion and Li-Polymer
Battery Packs
Synchronous Fixed-Frequency PWM
Controller Operating at 1.1 MHz With 0% to
100% Duty Cycle
High-Accuracy Voltage and Current
Regulation
Status Outputs For LED or Host Processor
Interface Indicates Charge-In-Progress,
Charge Completion, Fault, and AC-Adapter
Present Conditions
20-V Absolute Maximum Voltage Rating on IN
and OUT Pins
Accurate High-Side Battery Current Sensing
Battery Temperature Monitoring
Automatic Sleep Mode for Low Power
Consumption
Reverse Leakage Protection Prevents Battery
Drainage
Thermal Shutdown and Protection
Built-In Battery Detection
Available in 20 pin 3,5 mm x 4,5 mm QFN
Package
OUT
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DESCRIPTION
VSS
FEATURES
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
bqSWITCHER, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
bq24120
bq24123
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SLUS688 – MARCH 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
TJ
CHARGE REGULATION
VOLTAGE (V)
INTENDED
APPLICATION
4.2 V
–40°C to 125°C
Stand-alone
4.2 V/8.4 V
(1)
(2)
(3)
PART NUMBER (2) (3)
MARKINGS
BQ24120RHLR / BQ24120RHLT
BQU
BQ24123RHLR / BQ24123RHLT
BQV
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
The RHL package is available in the following options:
R - taped and reeled in quantities of 3,000 devices per reel
T - taped and reeled in quantities of 250 devices per reel
This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes.
PACKAGE DISSIPATION RATINGS
(1)
PACKAGE
ΘJA
ΘJC
TA < 40°C
POWER RATING
DERATING FACTOR
ABOVE TA = 40°C
RHL (1)
46.87°C/W
2.15°C/W
1.81 W
0.021 W/°C
This data is based on using the JEDEC High-K board, and the exposed die pad is connected to a copper pad on the board. This is
connected to the ground plane by a 2x3 via matrix.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT
Supply voltage range (with respect to VSS)
IN, VCC
Input voltage range (with respect to VSS and PGND)
20 V
STAT1, STAT2, PG, CE, CELLS, SNS, BAT
–0.3 V to 20 V
OUT
–0.7 V to 20 V
TS, TTC
7V
VTSB
3.6 V
ISET1, ISET2
3.3 V
±1 V
Voltage difference between SNS and BAT inputs (VSNS - VBAT)
Output sink
STAT1, STAT2, PG
Output current (average)
OUT
10 mA
2.2 A
TA
Operating free-air temperature range
–40°C to 85°C
TJ
Junction temperature range
–40°C to 125°C
Tstg
Storage temperature
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
300°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Supply voltage, VCC and IN (Tie together)
4.35 (1)
16.0 (2)
V
Operating junction temperature range, TJ
–40
125
°C
(1)
(2)
2
The IC continues to operate below Vmin, to 3.5 V, but the specifications are not tested and not guaranteed.
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the IN or OUT pins. A tight layout
minimizes switching noise.
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bq24120
bq24123
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SLUS688 – MARCH 2006
ELECTRICAL CHARACTERISTICS
TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VCC > VCC(min), PWM switching
IVCC(VCC)
VCC supply current
Battery discharge sleep current, (SNS,
BAT, OUT pins)
I(SLP)
10
VCC > VCC(min), PWM NOT switching
5
VCC > VCC(min), CE = HIGH
315
0°C ≤ TJ ≤ 65°C, VI(BAT) = 4.2 V,
VCC < V(SLP) or VCC > V(SLP) but not in charge
3.5
0°C ≤ TJ ≤ 65°C, VI(BAT) = 8.4 V,
VCC < V(SLP) or VCC > V(SLP) but not in charge
5.5
0°C ≤ TJ ≤ 65°C, VI(BAT) = 12.6 V,
VCC < V(SLP) or VCC > V(SLP) but not in charge
7.7
mA
µA
µA
VOLTAGE REGULATION
VOREG
Output voltage, bq24123
Output voltage, bq24120
Voltage regulation accuracy
CELLS = Low, in voltage regulation
4.2
CELLS = High, in voltage regulation
8.4
Operating in voltage regulation
4.2
TA = 25°C
V
–0.5%
0.5%
–1%
1%
150
2000
–10%
10%
CURRENT REGULATION - FAST CHARGE
IOCHARGE
Output current range of converter
VLOWV ≤ VI(BAT) < VOREG,
V(VCC) - VI(BAT) > V(DO-MAX)
100 mV ≤ VIREG≤ 200 mV,
V
IREG
mA
(1)
1V 1000,
RSET1
VIREG
Voltage regulated across R(SNS) Accuracy
V(ISET1)
Output current set voltage
V(LOWV) ≤ VI(BAT) ≤ VO(REG),
V(VCC) ≥ VI(BAT) + V (DO-MAX)
1
K(ISET1)
Output current set factor
VLOWV ≤ VI(BAT) < VO(REG) ,
V(VCC) ≥ VI(BAT) + V(DO-MAX)
1000
Programmed Where
5 kΩ ≤ RSET1 ≤ 10 kΩ, Select RSET1 to
program VIREG,
VIREG(measured) = IOCHARGE× RSNS
(–10% to 10% excludes errors due to RSET1
and R(SNS) tolerances)
V
V/A
PRECHARGE AND SHORT-CIRCUIT CURRENT REGULATION
VLOWV
Precharge to fast-charge transition voltage
threshold, BAT
t
Deglitch time for precharge to fast charge
transition
IOPRECHG
68
71.4
75
%VO(REG)
Rising voltage;
tRISE, tFALL = 100 ns, 2-mV overdrive
20
30
40
ms
Precharge range
VI(BAT) < VLOWV, t < tPRECHG
15
200
mA
V(ISET2)
Precharge set voltage, ISET2
VI(BAT) < VLOWV, t < tPRECHG
K(ISET2)
Precharge current set factor
10 mV ≤ VIREG-PRE ≤ 100 mV,
V
VIREG-PRE
Voltage regulated across RSNS-Accuracy
IREGPRE
100
mV
1000
V/A
(1)
0.1V 1000,
RSET2
Where
1.0 kΩ ≤ RSET2 ≤ 10 kΩ, Select RSET2
to program VIREG-PRE,
VIREG-PRE (Measured) = IOPRE-CHG × RSNS
(–20% to 20% excludes errors due to RSET2
and RSNS tolerances)
–20%
20%
15
200
CHARGE TERMINATION (CURRENT TAPER) DETECTION
ITERM
Charge current termination detection range
VI(BAT) > VOREG- VRCH
VTERM
Charge termination detection set voltage,
ISET2
VI(BAT) > VOREG- VRCH
(1)
100
mA
mV
Inductor peak current should be less than 2.6 A. Use equations 12, 13, 15, 18, and 19 to make sure the peak inductor current is less
than 2.6 A.
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bq24123
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ELECTRICAL CHARACTERISTICS (continued)
TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated)
PARAMETER
K(ISET2)
tdg-TERM
TEST CONDITIONS
MIN
Termination current set factor
TYP
MAX
1000
Charger termination accuracy
VI(BAT) > VOREG- VRCH
Deglitch time for charge termination
Both rising and falling,
2-mV overdrive tRISE, tFALL = 100 ns
–20%
UNIT
V/A
20%
20
30
40
72.8
73.5
74.2
ms
TEMPERATURE COMPARATOR AND VTSB BIAS REGULATOR
VLTF
Cold temperature threshold, TS
VHTF
Hot temperature threshold, TS
Initiate Charge
33.7
34.4
35.1
VTCO
Cutoff temperature threshold, TS
During Charge
28.7
29.3
29.9
0.5
1.0
1.5
20
30
40
LTF hysteresis
tdg-TS
Deglitch time for temperature fault, TS
Both rising and falling,
2-mV overdrive tRISE, tFALL = 100 ns
VO(VTSB)
TS bias output voltage
VCC > VIN(min),
I(VTSB) = 10 mA 0.1 µF ≤ CO(VTSB) ≤ 1 µF
VO(VTSB)
TS bias voltage regulation accuracy
VCC > IN(min),
I(VTSB) = 10 mA 0.1 µF ≤ CO(VTSB) ≤ 1 µF
3.15
–10%
%VO(VTSB)
ms
V
10%
BATTERY RECHARGE THRESHOLD
VRCH
tdg-RCH
Recharge threshold voltage
Below VOREG
75
100
125
mV/cell
Deglitch time
VI(BAT) < decreasing below threshold,
tFALL = 100 ns 10-mV overdrive
20
30
40
ms
STAT1, STAT2, AND PG OUTPUTS
VOL(STATx)
Low-level output saturation voltage, STATx
IO = 5 mA
0.5
VOL(PG)
Low-level output saturation voltage, PG
IO = 10 mA
0.1
V
CE , CELLS INPUTS
VIL
Low-level input voltage
IIL = 5 µA
VIH
High-level input voltage
IIH = 20 µA
0
0.4
1.3
VCC
V
TTC INPUT
tPRECHG
Precharge timer
tCHARGE
Programmable charge timer range
t(CHG) = C(TTC) × K(TTC)
Charge timer accuracy
0.01 µF ≤ C(TTC) ≤ 0.18 µF
KTTC
Timer multiplier
CTTC
Charge time capacitor range
VTTC_EN
TTC enable threshold voltage
1440
1800
25
-10%
2160
s
572
minutes
10%
2.6
0.01
V(TTC) rising
min/nF
0.22
200
µF
mV
SLEEP COMPARATOR
VSLP-ENT
Sleep-mode entry threshold
2.3 V ≤ VI(OUT) ≤ VOREG, for 1 or 2 cells
VSLP-EXIT
Sleep-mode exit hysteresis,
2.3 V ≤ VI(OUT)≤ VOREG
tdg-SLP
Deglitch time for sleep mode
VCC ≤ VIBAT
+5 mV
VCC ≤ VIBAT
+75 mV
40
160
VCC decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive,
PMOS turns off
VCC decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive,
STATx pins turn off
V
mV
µs
5
20
30
40
3.50
ms
UVLO
VUVLO-ON
IC active threshold voltage
VCC rising
3.15
3.30
IC active hysteresis
VCC falling
120
150
V
mV
PWM
Internal P-channel MOSFET on-resistance
Internal N-channel MOSFET on-resistance
fOSC
7 V ≤ VCC ≤ VCC(max)
400
4.5 V ≤ VCC ≤ 7 V
500
7 V ≤ VCC ≤ VCC(max)
130
4.5 V ≤ VCC ≤ 7 V
DMAX
4
150
Oscillator frequency
1.1
Frequency accuracy
–9%
Maximum duty cycle
MHz
9%
100%
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bq24123
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SLUS688 – MARCH 2006
ELECTRICAL CHARACTERISTICS (continued)
TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DMIN
Minimum duty cycle
0%
tTOD
Switching delay time (dead time)
20
ns
tsyncmin
Minimum synchronous FET on time
60
ns
Synchronous FET minimum current-off
threshold (2)
50
400
mA
BATTERY DETECTION
IDETECT
Battery detection current during time-out
fault
VI(BAT) < VOREG – VRCH
IDISCHRG1
Discharge current
tDISCHRG1
Discharge time
IWAKE
tWAKE
2
mA
VSHORT < VI(BAT) < VOREG – VRCH
400
µA
VSHORT < VI(BAT) < VOREG – VRCH
1
s
Wake current
VSHORT < VI(BAT) < VOREG – VRCH
2
mA
Wake time
VSHORT < VI(BAT) < VOREG – VRCH
0.5
s
IDISCHRG2
Termination discharge current
Begins after termination detected,
VI(BAT) ≤ VOREG
400
µA
tDISCHRG2
Termination time
262
ms
OUTPUT CAPACITOR
COUT
Required output ceramic capacitor range
from SNS to PGND, between inductor and
RSNS
CSNS
Required SNS capacitor (ceramic) at SNS
pin
4.7
10
47
µF
µF
0.1
PROTECTION
Threshold over VOREG to turn off P-channel
MOSFET, STAT1, and STAT2 during charge
or termination states
110
117
2.6
3.6
4.5
A
Short-circuit voltage threshold, BAT
VI(BAT) falling
1.95
2
2.05
V/cell
ISHORT
Short-circuit current
VI(BAT) ≤ VSHORT
TSHTDWN
Thermal trip
VOVP
OVP threshold voltage
ILIMIT
Cycle-by-cycle current limit
VSHORT
65
165
Thermal hysteresis
(2)
35
121
10
%VO(REG)
mA
°C
N-channel always turns on for ~60 ns and then turns off if current is too low.
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TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
bq24120
bq24123
BAT
14
14
I
Battery voltage sense input. Bypass it with a capacitor to VSS if there are long inductive leads to
battery.
CE
16
16
I
Charger enable input. This active low input, if set high, suspends charge and places the device in the
low-power sleep mode. Do not pull up this input to VTSB.
13
I
Available on parts with selectable output voltage. Ground or float for single-cell operation (4.2 V). For
two-cell operation (8.4 V) pull up this pin with a resistor to VIN.
Charger input voltage. Bypass it with a 10µF capacitor from IN to PGND.
CELLS
IN
3, 4
3, 4
I
ISET1
8
8
I/O
Charger current set point 1 (fast charge). Use a resistor to ground to set this value.
ISET2
9
9
I/O
Charge current set point 2 (precharge and termination), set by a resistor connected to ground.
N/C
13
–
No connection. This pin must be left floating in the application.
1
1
O
20
20
O
5
5
O
17,18
17,18
SNS
15
15
I
Charge current-sense input. Battery current is sensed via the voltage drop developed on this pin by
an external sense resistor in series with the battery pack. A 0.1µF capacitor to VSS is required.
STAT1
2
2
O
Charge status 1 (open-drain output). When the transistor turns on indicates charge in process. When
it is off and with the condition of STAT2 indicates various charger conditions (See Table 1)
STAT2
19
19
O
Charge status 2 (open-drain output). When the transistor turns on indicates charge is done. When it
is off and with the condition of STAT1 indicates various charger conditions (See Table 1)
TS
12
12
I
Temperature sense input. This input monitors its voltage against an internal threshold to determine if
charging is allowed. Use an NTC thermistor and a voltage divider powered from VTSB to develop this
voltage. (See Figure 12)
TTC
7
7
I
Timer and termination control. Connect a capacitor from this node to VSS to set the bqSWITCHER
timer. When this input is low, the timer and termination detection are disabled.
I
Analog device input. A 0.1µF capacitor to VSS is required.
OUT
PG
PGND
VCC
6
6
VSS
10
10
VTSB
11
11
Pad
Pad
Exposed
Thermal
Pad
6
Charge current output inductor connection.
Power-good status output (open drain). The transistor turns on when a valid VCC is detected. It is
turned off in the sleep mode. PG can be used to drive a LED or communicate with a host processor.
Power ground input
Analog ground input
O
TS internal bias regulator voltage. Connect capacitor (with a value between a 0.1µF and 1µF)
between this output and VSS.
There is an internal electrical connection between the exposed thermal pad and VSS. The exposed
thermal pad must be connected to the same potential as the VSS pin on the printed circuit board.
The power pad can be used as a star ground connection between VSS and PGND. A common ground
plane may be used. VSS pin must be connected to ground at all times.
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bq24123
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TYPICAL APPLICATION CIRCUITS
ICHARGE = 1.3A, IPRECHARGE = 133mA, Charge Safety Timer = 5.0 hours, Battery Charging Qualification Temperature Range =
0°C to 45°C
LO
BQ24120
VIN
CIN
1.5 KW
10 mF
1.5 KW
Adapter
Present
1.5 KW
Done
Charge
3
IN
OUT 1
4
IN
OUT 20
6
VCC
RSNS
10mH
COUT
10mF
Battery
Pack
Pack+
0.1W
Pack-
PGND 17
103AT
2
STAT1 PGND 18
19 STAT2
CTTC
5
PG
7
TTC
16 CE
0.1 mF
SNS 15
BAT 14
ISET1 8
ISET2 9
13 NC
7.5 KW
R ISET2
VTSB
9.31 KW
R T1
442 KW
RT2
TS 12
10 VSS
0.1 mF
7.5 KW R
ISET1
VTSB 11
0.1 mF
0.1 mF
Figure 1. Stand-Alone 1-Cell Application
LO
BQ24123
VIN
1.5 KW
CIN
10 mF
1.5 KW
Adapter
Present
1.5 KW
Done
3
IN
OUT 1
4
IN
OUT 20
6
VCC
2
STAT1 PGND 18
10 mH
Charge
RSNS
COUT
10mF
0.1W
Battery
Pack
Pack+
Pack-
PGND 17
103AT
19 STAT2
C TTC
5
PG
7
TTC
BAT 14
ISET2 9
10 VSS
0.1 mF
ISET1 8
7.5 KW R
ISET1
7.5 KW
16 CE
0.1 mF
SNS 15
TS 12
RT1
9.31 KW
RISET2
13 CELLS VTSB 11
VIN
VTSB
442 KW
RT2
0.1 mF
0.1 mF
10 KW
Figure 2. Stand-Alone 2-Cells Application
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TYPICAL OPERATING PERFORMANCE
See Figure 1 for a 1-cell application test circuit schematic and Figure 2 for the stand-alone cells application test
circuits schematic.
Level [dBµV]
BQ2412X Typical Radiated EMI Performance on EVM
60
VIN = 16 V
50
ICHARGE = 1 A
40
30
20
10
0
-10
30M
50M
70M
100M
Frequency [Hz]
200M
300M
500M
700M
1G
MES bq2412x_16v_1.0A
Figure 3. Typical Radiated EMI Performance Measured on EVM
100
VIN = 9 V
90
90
80
80
70
70
VIN = 16 V
60
50
40
30
60
50
40
30
20
20
VBAT = 4.2 V
10
VBAT = 8.4 V
10
0
0
8
VIN = 12 V
VIN = 16 V
Efficiency - %
Efficiency - %
100
500
1000
1500
2000
2500
0
0
500
1000
1500
2000
Iload - mA
Iload - mA
Figure 4. Efficiency 1-Cell
Figure 5. Efficiency 2-Cells
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2500
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SLUS688 – MARCH 2006
CH3
1.38 A
CH3
200 mA/div
CH3 = Inductor Current
CH1 = BAT
CH1
2 V/div
CH1
3.8 V
CH2 = OUT
CH2
5 V/div
CH2
9V
t = Time = 400 ns/div
Figure 6. Switching Waveforms in Fast Charge Mode
CH3 = Inductor Current
CH3
500 mA/div
CH3
500 mA
CH1 = BAT
CH1
8.4 V
CH1
5 V/div
CH2 = OUT
CH2
16 V
CH2
10 V/div
t - Time = 400 ns/div
Figure 7. Switching Waveforms in Voltage Regulation Mode
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CH1 = BAT
CH1
2 V/div
CH1
4.2 V
CH3 = Inductor Current
CH3
200 mA/div
CH3
480 mA
CH2 = OUT
CH2
5V
CH2
2 V/div
20 ns
35 ns
t = Time = 50 ns/div
Figure 8. Dead Time
CH1 = BAT
CH1
2 V/div
CH1
3.8 V
CH3 = Inductor Current
CH3
1.3 A
CH2 = OUT
CH2
5V
CH3
500 mA/div
CH2
5 V/div
t = Time = 1 ms/div
Figure 9. Soft Start Waveforms
10
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FUNCTIONAL BLOCK DIAGRAM
Protection PMOS FET is OFF when not charging
or in SLEEP to prevent discharge of battery
when IN < BAT
1
IN 3
Sense FET
IN 4
Poff VCC PG
CHARGE
SLEEP
Isynch
BG
TG
OUT
20 OUT
Synch
V(150 mA)
VCC−6V
18 PGND
VCC 6
Sense FET
Vuvlo UVLO/POR
POR
VCC
Icntrl
VCC−6V
PkILim
Voltage
Reference
V(3.6A)
2.1V
6V
VTSB 11
VTSB
17 PGND
VCC
TG
I
VCC/10
RAMP
(Vpp=VCC/10)
Gate
Drive
BG
SYNCH
VCC−6V
MOD
OSC
Q S
MOD
RAMP
Q R
OVP
PkILim or OVP
TIMEOUT FAULT
SUSPEND
TERM
UVLO/POR
15 SNS
VCC
PG 5
SUSPEND
SLEEP
+
−
VCC
−
+
CLAMP
VCC
VCC
UVLO/
POR
BAT
1V
50 mV
CE
CE 16
+
−
Ibat Reg
+
−
*
COMPENSATION
TIMEOUT
Vbat Reg
+
−
1k
14 BAT
BAT
2.1V
Vrch
CONTROL
LOGIC
(STATE
MACHINE)
SNS+
VCC
LowV
TERM
SLEEP
SUSPEND
13 CELLS
2C
BAT
BAT_PRS_
disch
CHARGE
20uA
20uA
Term_Det
1C
Vreg
1V
DISCHARGE
VSHORT
Wake
8 ISET1
FASTCHG
Disable
WAKE
PkILim
+
−
Charge
PRE−CHARGE
SYNCH
STAT1 2
Charge
0.1V
Discharge
SLEEP
SNS
+
1k
−
Vovp
OVP
BAT
OVP
STAT2 19
2.1V
TERM
VCC
0.25V
Vrch 30ms
Dgltch
DSABL_TERM
TIMER CLK
TTC 7
0.75V
TIMER
FF CHAIN
0.5V
PRE−CHG
TIMEOUT
VSS 10
RESET
FAST CHG
TIMEOUT
LowV 30ms
Dgltch
BAT_PRS_dischg
VSHORT
BAT
+
−
9 ISET2
PRE−CHG
Disable
+
−
FASTCHG
Disable
0.1V
30ms
dgltch
Term_Det
VTSB
12 TS
LTF
SUSPEND
TS
SPIN
TEMP
SUSPEND
HTF
TCO
bqSWITCHER
bq2412x
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OPERATIONAL FLOW CHART
POR
Check for battery
Presence
Battery
Detected?
No
Indicate BATTERY
ABSENT
Yes
Suspend charge
TS pin
in LTF to HTF
range?
No
Indicate CHARGE
SUSPEND
Yes
VBAT <VLOWV
Yes
Regulate
IPRECHG
Reset and Start
T30min timer
Indicate ChargeIn-Progress
No
Suspend charge
Reset and Start
FSTCHG timer
TS pin
in LTF to TCO
range?
Regulate
Current or Voltage
Yes
No
No
TS pin
in LTF to HTF
range?
Indicate ChargeIn-Progress
No
V BAT
<V LOWV
Suspend charge
TS pin
in LTF to TCO
range?
No
Yes
Yes
Indicate CHARGE
SUSPEND
Yes
No
T30min
Expired?
TS pin
in LTF to HTF
range?
FSTCHG timer
Expired?
Indicate CHARGE
SUSPEND
No
Yes
No
- Fault Condition
- Enable I DETECT
No
Indicate Fault
Yes
Yes
No
V BAT
<VLOWV
Yes
V BAT > VOREG
- VRCH ?
No
No
VBAT > VOREG V RCH ?
ITERM detection?
Yes
- Disable I DETECT
Indicate Fault
Yes
Yes
- Fault Condition
- Turn off charge
- Enable I DISCHG2
for tDISCHG2
Indicate Fault
No
Indicate ChargeIn-Progress
Battery
Replaced?
VBAT< VOREG V RCH ?
Charge Complete
VBAT < V OREG VRCH?
No
Indicate DONE
Battery Removed
Yes
Indicate BATTERY
ABSENT
Figure 10. Operational Flow Chart
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DETAIL DESCRIPTION
The bqSWITCHER™ supports a precision Li-ion or Li-polymer charging system for single cell or two cell
applications. See Figure 10 and Figure 11 for a typical charge profile.
The bq2412X has enhanced EMI performance that helps minimize the number of components needed to meet
the FCC-B Standard. The rise time of the OUT pin was slowed down to minimize the radiated EMI.
Precharge
Phase
Voltage Regulation and
Charge Termination Phase
Current Regulation Phase
Regulation V oltage
Regulation Current
Charge Voltage
VLOW
VSHORT
Charge Current
Precharge
and Termination
ISHORT
UDG-04037
Precharge
Timer
Programmable
Safety Timer
Figure 11. Typical Charging Profile
PWM Controller
The bq2412X provides an integrated fixed 1MHz frequency voltage-mode controller with Feed-Forward function
to regulate charge current or voltage. This type of controller is used to help improve line transient response,
thereby simplifying the compensation network used for both continuous and discontinuous current conduction
operation. The voltage and current loops are internally compensated using a Type-III compensation scheme that
provides enough phase boost for stable operation, allowing the use of small ceramic capacitors with very low
ESR. There is a 0.5V offset on the bottom of the PWM ramp to allow the device to operate between 0% to 100%
duty cycle.
The internal PWM gate drive can directly control the internal PMOS and NMOS power MOSFETs. The high-side
gate voltage swings from VCC (when off), to VCC-6 (when on and VCC is greater than 6V) to help reduce the
conduction losses of the converter by enhancing the gate an extra volt beyond the standard 5V. The low-side
gate voltage swings from 6V, to turn on the NMOS, down to PGND to turn it off. The bq2412X has two back to
back common-drain P-MOSFETs on the high side. An input P-MOSFET prevents battery discharge when IN is
lower than BAT. The second P-MOSFET behaves as the switching control FET, eliminating the need of a
bootstrap capacitor.
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DETAIL DESCRIPTION (continued)
Cycle-by-cycle current limit is sensed through the internal high-side sense FET. The threshold is set to a nominal
3.6A peak current. The low-side FET also has a current limit that decides if the PWM Controller will operate in
synchronous or non-synchronous mode. This threshold is set to 100mA and it turns off the low-side NMOS
before the current reverses, preventing the battery from discharging. Synchronous operation is used when the
current of the low-side FET is greater than 100mA to minimize power losses.
Temperature Qualification
The bqSWITCHER continuously monitors battery temperature by measuring the voltage between the TS pin and
VSS pin. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop
this voltage. The bqSWITCHER compares this voltage against its internal thresholds to determine if charging is
allowed. To initiate a charge cycle, the battery temperature must be within the V(LTF)-to-V(HTF) thresholds. If
battery temperature is outside of this range, the bqSWITCHER suspends charge and waits until the battery
temperature is within the V(LTF)-to-V(HTF) range. During the charge cycle (both precharge and fast charge), the
battery temperature must be within the V(LTF)-to-V(TCO) thresholds. If battery temperature is outside of this range,
the bqSWITCHER suspends charge and waits until the battery temperature is within the V(LTF)-to-V(HTF) range.
The bqSWITCHER suspends charge by turning off the PWM and holding the timer value (i.e., timers are not
reset during a suspend condition). Note that the bias for the external resistor divider is provided from the VTSB
output. Applying a constant voltage between the V(LTF)-to-V(HTF) thresholds to the TS pin disables the
temperature-sensing feature.
V O(VTSB) RTH COLD RTH HOT RT2 V
RTH HOT V
O(VTSB)
V
RT1 LTF
O(VTSB)
V
HTF
1
1
V
LTF
V
RTH COLD 1
V
HTF
O(VTSB)
V
LTF
1
1
1 1
RT2 RTH
COLD
(1)
VCC
Charge Suspend
Charge Suspend
V(LTF)
V(HTF)
V(TCO)
Temperature Range
to Initiate Charge
Charge Suspend
Temperature Range
During Charge Cycle
Charge Suspend
VSS
Figure 12. TS Pin Thresholds
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DETAIL DESCRIPTION (continued)
Battery Preconditioning (Precharge)
On power up, if the battery voltage is below the VLOWV threshold, the bqSWITCHER applies a precharge current,
IPRECHG, to the battery. This feature revives deeply discharged cells. The bqSWITCHER activates a safety timer,
tPRECHG, during the conditioning phase. If the VLOWV threshold is not reached within the timer period, the
bqSWITCHER turns off the charger and enunciates FAULT on the STATx pins. In the case of a FAULT
condition, the bqSWITCHER reduces the current to IDETECT. IDETECT is used to detect a battery replacement
condition. Fault condition is cleared by POR or battery replacement.
The magnitude of the precharge current, IO(PRECHG), is determined by the value of programming resistor, R(ISET2),
connected to the ISET2 pin.
K (ISET2) V (ISET2)
I O(PRECHG) R(ISET2) R(SNS)
(2)
where
RSNS is the external current-sense resistor
V(ISET2) is the output voltage of the ISET2 pin
K(ISET2) is the V/A gain factor
V(ISET2) and K(ISET2) are specified in the Electrical Characteristics table.
Battery Charge Current
The battery charge current, IO(CHARGE), is established by setting the external sense resistor, R(SNS), and the
resistor, R(ISET1), connected to the ISET1 pin.
In order to set the current, first choose R(SNS) based on the regulation threshold VIREG across this resistor. The
best accuracy is achieved whe the VIREG is between 100mV and 200mV.
V IREG
R (SNS) I OCHARGE
(3)
If the results is not a standard sense resistor value, choose the next larger value. Using the selected standard
value, solve for VIREG. Once the sense resistor is selected, the ISET1 resistor can be calculated using the
following equation:
K
V ISET1
R ISET1 ISET1
RSNS I CHARGE
(4)
Battery Voltage Regulation
The voltage regulation feedback occurs through the BAT pin. This input is tied directly to the positive side of the
battery pack. The bqSWITCHER monitors the battery-pack voltage between the BAT and VSS pins. The
bqSWITCHER is offered in a fixed single-cell voltage version (4.2 V) and as a one-cell or two-cell version
selected by the CELLS input. A low or floating input on the CELLS selects single-cell mode (4.2 V) while a
high-input through a resistor selects two-cell mode (8.4 V).
Charge Termination and Recharge
The bqSWITCHER monitors the charging current during the voltage regulation phase. Once the termination
threshold, ITERM, is detected, the bqSWITCHER terminates charge. The termination current level is selected by
the value of programming resistor, R(ISET2), connected to the ISET2 pin.
K (ISET2) V TERM
I TERM R(ISET2) R(SNS)
(5)
where
R(SNS) is the external current-sense resistor
VTERM is the output of the ISET2 pin
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DETAIL DESCRIPTION (continued)
K(ISET2) is the A/V gain factor
VTERM and K(ISET2) are specified in the Electrical Characteristics table
As a safety backup, the bqSWITCHER also provides a programmable charge timer. The charge time is
programmed by the value of a capacitor connected between the TTC pin and GND by the following formula:
t CHARGE C(TTC) K(TTC)
(6)
where
C(TTC) is the capacitor connected to the TTC pin
K(TTC) is the multiplier
A new charge cycle is initiated when one of the following conditions is detected:
• The battery voltage falls below the VRCH threshold.
• Power-on reset (POR), if battery voltage is below the VRCH threshold
• CE toggle
• TTC pin, described as follows.
In order to disable the charge termination and safety timer, the user can pull the TTC input below the VTTC_EN
threshold. Going above this threshold enables the termination and safety timer features and also resets the timer.
Tying TTC high disables the safety timer only.
Sleep Mode
The bqSWITCHER enters the low-power sleep mode if the VCC pin is removed from the circuit. This feature
prevents draining the battery during the absence of VCC.
Charge Status Outputs
The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in Table 1. These
status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates that the
open-drain transistor is turned off.
Table 1. Status Pins Summary
Charge State
STAT1
STAT2
Charge-in-progress
ON
OFF
Charge complete
OFF
ON
Charge suspend, timer fault, overvoltage, sleep mode, battery absent
OFF
OFF
PG Output
The open-drain PG (power good) indicates when the AC-to-DC adapter (i.e., VCC) is present. The output turns on
when sleep-mode exit threshold, VSLP-EXIT, is detected. This output is turned off in the sleep mode. The PG pin
can be used to drive an LED or communicate to the host processor.
CE Input (Charge Enable)
The CE digital input is used to disable or enable the charge process. A low-level signal on this pin enables the
charge and a high-level VCC signal disables the charge. A high-to-low transition on this pin also resets all timers
and fault conditions. Note that the CE pin should not be tied to VTSB. This may create power-up issues.
Timer Fault Recovery
As shown in Figure 10, bqSWITCHER provides a recovery method to deal with timer fault conditions. The
following summarizes this method.
Condition 1 VI(BAT) above recharge threshold (VOREG - VRCH) and timeout fault occurs.
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Recovery method: bqSWITCHER waits for the battery voltage to fall below the recharge threshold. This could
happen as a result of a load on the battery, self-discharge or battery removal. Once the battery falls below the
recharge threshold, the bqSWITCHER clears the fault and enters the battery absent detection routine. A POR or
CE toggle also clears the fault.
Condition 2 Charge voltage below recharge threshold (VOREG– VRCH) and timeout fault occurs
Recovery method: Under this scenario, the bqSWITCHER applies the IDETECT current. This small current is used
to detect a battery removal condition and remains on as long as the battery voltage stays below the recharge
threshold. If the battery voltage goes above the recharge threshold, then the bqSWITCHER disables the IDETECT
current and executes the recovery method described in Condition 1. Once the battery falls below the recharge
threshold, the bqSWITCHER clears the fault and enters the battery absent detection routine. A POR or CE toggle
also clears the fault.
Output Overvoltage Protection (Applies To All Versions)
The bqSWITCHER provides a built-in overvoltage protection to protect the device and other components against
damages if the battery voltage gets too high, as when the battery is suddenly removed. When an overvoltage
condition is detected, this feature turns off the PWM and STATx pins. The fault is cleared once VIBAT drops to the
recharge threshold (VOREG - VRCH).
Inductor, Capacitor, and Sense Resistor Selection Guidelines
The bqSWITCHER provides internal loop compensation. With this scheme, best stability occurs when LC
resonant frequency, fo is approximately 16 kHz (8 kHz to 32 kHz). Equation 7 can be used to calculate the value
of the output inductor and capacitor. Table 2 provides a summary of typical component values for various charge
rates.
1
f0 2 L OUT C OUT
(7)
Table 2. Output Components Summary
0.5 A
1A
2A
Output inductor, LOUT
CHARGE CURRENT
22 µH
10 µH
4.7 µH
Output capacitor, COUT
4.7 µF
10 µF
22 µF (or 2 × 10 µH) ceramic
Sense resistor, R(SNS)
0.2 Ω
0.1 Ω
0.05 Ω
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Battery Detection
For applications with removable battery packs, bqSWITCHER provides a battery absent detection scheme to
reliably detect insertion and/or removal of battery packs.
POR or VRCH
Detection routine runs on power up
and if VBAT drops below refresh
threshold due to removing battery
or discharging battery.
Yes
Enable
I(DETECT)
for t(DETECT)
VI(BAT)<V(SHORT)
No
BATTERY
PRESENT,
Begin Charge
No
BATTERY
PRESENT,
Begin Charge
Yes
Apply I(WAKE)
for t(WAKE)
VI(BAT) >
VO(REG)
−VRCH
Yes
BATTERY
ABSENT
Figure 13. Battery Detection for bq2412x ICs
The voltage at the BAT pin is held above the battery recharge threshold, VOREG– VRCH, by the charged battery
following fast charging. When the voltage at the BAT pin falls to the recharge threshold, either by a load on the
battery or due to battery removal, the bqSWITCHER begins a battery absent detection test. This test involves
enabling a detection current, IDISCHARGE1, for a period of tDISCHARGE1 and checking to see if the battery voltage is
below the short circuit threshold, VSHORT. Following this, the wake current, IWAKE is applied for a period of tWAKE
and the battery voltage is checked again to ensure that it is above the recharge threshold. The purpose of this
current is to attempt to close an open battery pack protector, if one is connected to the bqSWITCHER.
Passing both of the discharge and charge tests indicates a battery absent fault at the STAT pins. Failure of either
test starts a new charge cycle. For the absent battery condition, typically the voltage on the BAT pin rises and
falls between 0V and VOVPthresholds indefinitely.
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VBAT
Battery
Connected
VOREG
No
Battery
Detected
2V/cell
No
Battery
Detected
Yes
Battery
Detected
IWAKE
IBAT
- IDISCHRG1
t DISCHRG1
tWAKE
t DISCHRG1
Figure 14. Battery Detect Timing Diagram
Battery Detection Example
In order to detect a no battery condition during the discharge and wake tests, the maximum output capacitance
should not exceed the following:
a. Discharge (IDISCHRG1 = 400 µA, tDISCHRG1 = 1s, VSHORT = 2V)
I
t DISCHRG1
C MAX_DIS DISCHRG1
V OREG V SHORT
C MAX_DIS 400 A 1s
4.2 V 2 V
C MAX_DIS 182 F
(8)
b. Wake (IWAKE = 2 mA, tWAKE = 0.5 s, VOREG– VRCH = 4.1V)
I WAKE t WAKE
C MAX_WAKE VOREG VRCH 0 V
C MAX_WAKE 2 mA 0.5s
(4.2 V 0.1 V) 0V
C MAX_WAKE 244 F
(9)
Based on these calculations the recommended maximum output capacitance to ensure proper operation of the
battery detection scheme is 100 µF which will allow for process and temperature variations.
Figure 15 shows the battery detection scheme when a battery is inserted. Channel 3 is the output signal and
Channel 4 is the output current. The output signal switches between VOREG and GND until a battery is inserted.
Once the battery is detected, the output current increases from 0A to 1.3A, which is the programmed charge
current for this application.
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Figure 15. Battery Detection Waveform When a Battery is Inserted
Figure 16 shows the Battery Detection scheme when a battery is removed. Channel 3 is the output signal and
Channel 4 is the output current. When the battery is removed, the output signal goes up due to the stored energy
in the inductor and it crosses the VOREG– VRCH threshold. At this point the output current goes to 0A and the IC
terminates the charge process and turns on the IDISCHG2 for tDISCHG2. This causes the output voltage to fall down
below the VOREG– VRCHG threshold triggering a Battery Absent condition and starting the Battery Detection
scheme.
Figure 16. Battery Detection Waveform When a Battery is Removed
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Current Sense Amplifier
BQ2412X family offers a current sense amplifier feature that translates the charge current into a DC voltage.
Figure 17 is a block diagram of this feature.
OUT
ICHARGE
SNS
RSNS
+
KISET2
BAT
+
-
+
FASTCHG
Disable
ISET2
RISET2
Figure 17. Current Sense Amplifer
The voltage on the ISET2 pin can be used to calculate the charge current. Equation 10 shows the relationship
between the ISET2 voltage and the charge current:
VISET2 K(ISET2)
I CHARGE R SNS R ISET2
(10)
This feature can be used to monitor the charge current during the current regulation phase (Fastcharge only) and
the voltage regulation phase. The schematics for the application circuit for this waveform is shown in Figure 2
CH3 = Inductor Current
CH3
500 mA/div
CH1 = ISET2
CH3
0A
CH1
200 mV/div
CH2 = OUT
CH1
0V
CH2
16 V
CH2
10 V/div
t = Time = 200 ms/div
Figure 18. Current Sense Amplifier
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SYSTEM DESIGN EXAMPLE AND APPLICATIONS INFORMATION
The following section provides a detailed system design example for the bq24120.
System Design Specifications:
•
•
•
•
•
•
•
1.
VIN = 16V
VBAT = 4.2V (1-Cell)
ICHARGE = 1.33 A
IPRECHARGE = ITERM = 133 mA
Safety Timer = 5.0 hours
Inductor Ripple Current = 30% of Fast Charge Current
Initiate Charge Temperature = 0°C to 45°C
Determine the inductor value (LOUT) for the specified charge current ripple:
I L I CHARGE I CHARGERipple
L OUT L OUT VBAT VINMAX VBAT
V INMAX ƒ I L
4.2 (16 4.2)
16 (1.1 106) (1.33 0.3)
L OUT 7.06 H
(11)
Set the output inductor to standard 10 µH. Calculate the total ripple current with using the 10 µH inductor:
I L I L VBAT VINMAX VBAT
V INMAX ƒ LOUT
4.2 (16 4.2)
16 (1.1 106) (10 10 6)
I L 0.282 A
(12)
Calculate the maximum output current (peak current):
I
I LPK I OUT L
2
I LPK 1.33 0.282
2
I LPK 1.471 A
(13)
Use standard 10 µH inductor with a saturation current higher than 1.471A. (i.e., Sumida CDRH74-100)
2. Determine the output capacitor value (COUT) using 16 kHz as the resonant frequency:
1
ƒo 2 LOUT COUT
C OUT 1
4 2 ƒo 2 L OUT
C OUT 1
4 2 (16 10 3)2 (10 10 6)
C OUT 9.89 F
(14)
Use standard value 10 µF, 25V, X5R, ±20% ceramic capacitor (i.e., Panasonic 1206 ECJ-3YB1E106M
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SYSTEM DESIGN EXAMPLE AND APPLICATIONS INFORMATION (continued)
3. Determine the sense resistor using the following equation:
V
R SNS RSNS
I CHARGE
(15)
In order to get better current regulation accuracy (±10%), let VRSNS be between 100 mV and 200 mV. Use
VRSNS = 100 mV and calculate the value for the sense resistor.
R SNS 100 mV
1.33 A
R SNS 0.075 (16)
This value is not standard in resistors. If this happens, then choose the next larger value which in this case is
0.1Ω. Using the same equation (15) the actual VRSNS will be 133mV. Calculate the power dissipation on the
sense resistor:
2
P RSNS I CHARGE R SNS
P RSNS 1.332 0.1
P RSNS 176.9 mW
(17)
Select standard value 100 mΩ, 0.25W 0805, 1206 or 2010 size, high precision sensing resistor. (i.e., Vishay
CRCW1210-0R10F)
4. Determine ISET 1 resistor using the following equation:
K
V ISET1
R ISET1 ISET1
RSNS I CHARGE
R ISET1 1000 1.0
0.1 1.33
R ISET1 7.5 k
(18)
Select standard value 7.5 kΩ, 1/16W ±1% resistor (i.e., Vishay CRCWD0603-7501-F)
5. Determine ISET 2 resistor using the following equation:
KISET2 VISET2
R ISET2 RSNS I PRECHARGE
R ISET2 1000 0.1
0.1 0.133
R ISET2 7.5 k
(19)
Select standard value 7.5 kΩ, 1/16W ±1% resistor (i.e., Vishay CRCWD0603-7501-F)
6. Determine TTC capacitor (CTTC) for the 5.0 hours safety timer using the following equation:
t
C TTC CHARGE
K TTC
C TTC 300 m
2.6 mnF
C TTC 115.4 nF
(20)
Select standard value 100 nF, 16V, X7R, ±10% ceramic capacitor (i.e., Panasonic ECJ-1VB1C104K). Using
this capacitor the actual safety timer will be 4.3 hours.
7. Determine TS resistor network for an operating temperature range from 0°C to 45°C.
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SYSTEM DESIGN EXAMPLE AND APPLICATIONS INFORMATION (continued)
VTSB
RT1
TS
RTH
RT2
103AT
Figure 19. TS Resistor Network
Assuming a 103AT NTC Thermistor on the battery pack, determine the values for RT1 and RT2 using the
following equations:
V O(VTSB) RTH COLD RTH HOT RT2 V
RTH HOT V
O(VTSB)
V
RT1 LTF
O(VTSB)
V
HTF
1
1
V
LTF
V
RTH COLD 1
V
HTF
O(VTSB)
V
LTF
1
1
1 1
RT2 RTH
COLD
(21)
RTH COLD 27.28 k
RTH HOT 4.912 k
RT1 9.31 k
RT2 442 k
24
(22)
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APPLICATION INFORMATION
Charging Battery and Powering System Without Affecting Battery Charge and Termination
RSYS
LO
BQ24120
VIN
CIN
1.5 KW
10 mF
1.5 KW
Adapter
Present
1.5 KW
Done
Charge
3
IN
OUT 1
4
IN
OUT 20
6
VCC
2
STAT1 PGND 18
RSNS
10 mH
COUT
0.1W
10 mF
Battery
Pack
Pack+
Pack-
PGND 17
103AT
19 STAT2
5
PG
7
TTC
SNS 15
BAT 14
7.5 KW
ISET1 8
VTSB
7.5 KW
16 CE
9.31 KW
ISET2 9
0.1 mF
10 VSS
0.1 mF
13 NC
TS 12
VTSB 11
442 KW
0.1 mF
0.1 mF
Figure 20. Application circuit for charging a battery and powering a system without affecting termination
The bqSWITCHER was designed as a stand-alone battery charger but can be easily adapted to power a system
load, while considering a few minor issues.
Advantages:
1. The charger controller is based only on what current goes through the current-sense resistor (so precharge,
constant current, and termination all work well), and is not affected by the system load.
2. The input voltage has been converted to a usable system voltage with good efficiency from the input.
3. Extra external FETs are not needed to switch power source to the battery.
4. The TTC pin can be grounded to disable termination and keep the converter running and the battery fully
charged, or let the switcher terminate when the battery is full and then run off of the battery via the sense
resistor.
Other Issues:
1. If the system load current is large (≥ 1 A), the IR drop across the battery impedance causes the battery
voltage to drop below the refresh threshold and start a new charge. The charger would then terminate due to
low charge current. Therefore, the charger would cycle between charging and termination. If the load is
smaller, the battery would have to discharge down to the refresh threshold resulting in a much slower
cycling. Note that grounding the TTC pin keeps the converter on continuously.
2. If TTC is grounded, the battery is kept at 4.2 V (not much different than leaving a fully charged battery set
unloaded).
3. Efficiency declines 2-3% hit when discharging through the sense resistor to the system.
Submit Documentation Feedback
25
bq24120
bq24123
www.ti.com
SLUS688 – MARCH 2006
THERMAL CONSIDERATIONS
Thermal Considerations
The SWITCHER is packaged in a thermally enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the IC and the printed circuit board (PCB). Full PCB design
guidelines for this package are provided in the application report entitled: QFN/SON PCB Attachment
(SLUA271).
The most common measure of package thermal performance is thermal impedance (θJA) measured (or modeled)
from the chip junction to the air surrounding the package surface (ambient). The mathematical expression for θJA
is:
T TA
(JA) J
P
(23)
Where:
TJ = chip junction temperature
TA = ambient temperature
P = device power dissipation
Factors that can greatly influence the measurement and calculation of θJA include:
• Whether or not the device is board mounted
• Trace size, composition, thickness, and geometry
• Orientation of the device (horizontal or vertical)
• Volume of the ambient air surrounding the device under test and airflow
• Whether or not other surfaces are in close proximity to the device being tested
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power
FET. It can be calculated from the following equation:
P = [Vin × lin - Vbat × Ibat]
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. (See Figure 11.)
26
Submit Documentation Feedback
bq24120
bq24123
www.ti.com
SLUS688 – MARCH 2006
PCB LAYOUT CONSIDERATION
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed
as close as possible to the bqSWITCHER. The output inductor should be placed directly above the IC and
the output capacitor connected between the inductor and PGND of the IC. The intent is to minimize the
current path loop area from the OUT pin through the LC filter and back to the PGND pin. The sense resistor
should be adjacent to the junction of the inductor and output capacitor. Route the sense leads connected
across the RSNS back to the IC, close to each other (minimize loop area) or on top of each other on adjacent
layers. BAT and SNS traces should be away from high di/dt traces such as the OUT pin. Use an optional
capacitor downstream from the sense resistor if long (inductive) battery leads are used.
• Place all small-signal components (CTTC, RSET1/2 and TS) close to their respective IC pin (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias
(3 vias per capacitor for power-stage capacitors, 3 vias for the IC PGND, 1 via per capacitor for small-signal
components). A star ground design approach is typically used to keep circuit block currents isolated
(high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single
ground plane for this design gives good results. With this small layout and a single ground plane, there is not
a ground-bounce issue, and having the components segregated minimizes coupling between signals.
• The high-current charge paths into IN and from the OUT pins must be sized appropriately for the maximum
charge current in order to avoid voltage drops in these traces. The PGND pins should be connected to the
ground plane to return current through the internal low-side FET. The thermal vias in the IC PowerPAD™
provide the return-path connection.
• The bqSWITCHER is packaged in a thermally enhanced MLP package. The package includes a thermal pad
to provide an effective thermal contact between the IC and the PCB. Full PCB design guidelines for this
package are provided in the application report entitled: QFN/SON PCB Attachment (SLUA271). Six 10-13 mil
vias are a minimum number of recommended vias, placed in the IC's power pad, connecting it to a ground
thermal plane on the opposite side of the PWB. This plane must be at the same potential as VSS and PGND
of this IC.
• See user guide SLUU200 for an example of good layout.
Submit Documentation Feedback
27
PACKAGE OPTION ADDENDUM
www.ti.com
14-Mar-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ24120RHLR
ACTIVE
QFN
RHL
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24120RHLRG4
ACTIVE
QFN
RHL
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24120RHLT
ACTIVE
QFN
RHL
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24120RHLTG4
ACTIVE
QFN
RHL
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24123RHLR
ACTIVE
QFN
RHL
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24123RHLRG4
ACTIVE
QFN
RHL
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24123RHLT
ACTIVE
QFN
RHL
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24123RHLTG4
ACTIVE
QFN
RHL
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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