1/4 Structure Product Silicon monolithic Integrated circuit Clock Generator Type BU7346GUL Feature To generate clocks for digital still camera system To generate clocks by connecting reference 27.0000MHz SEL pin allowing for the selection of 38.0000MHz or 36.0000MHz Selection of PDB pin enabling Power-Down function ○Absolute Maximum Ratings (Ta=25℃) Symbol Ratings Unit Parameter Supply voltage VDD V -0.3 ～ 4.0 Input Voltage VIN V -0.3 ～ VDD+0.3 Storage Temperature range Tstg ℃ -55 ～ 125 ※1 mW Power dissipation PD 460 ※1 A measure value at mounting on 50mm×58mm×1.75mm glass epoxy substrate. In the case of exceeding Ta=25℃, 4.6mW should be reduced per 1℃. ※ Operation is not guaranteed. ※ The radiation-resistance design is not carried out. ○Operating Conditions (Ta=-5℃~+75℃) Parameter Symbol Supply voltage VDD Input ”H” Voltage VIH Input ”L” Voltage VIL Output load CL Min. 2.7 0.8VDD 0.0 0 REV. A Typ. 3.3 - Max. 3.6 VDD 0.2VDD 15 Unit V V V pF 2/4 ○Electrical Characteristics （VDD=3.3V, Ta=25℃, Input frequency=27.0000MHz, at No Load, unless otherwise specified） Parameter Output H voltage Output L voltage Standby current Consumption current1 Consumption current2 Pull-down load Min. Limit Typ. Max. VOH 2.8 - VDD V IOH=-3.0mA VOL 0.0 - 0.5 V IOL=3.0mA IDDst - - 1.0 A PDB=L IDD1 - 3.5 4.6 mA 38.0000MHz Output, SEL=L IDD2 - 3.5 4.6 mA 36.0000MHz Output, SEL=H Rpd 50 100 200 k Input PIN value Symbol Unit Conditions pull-down ○Output Frequency （VDD=3.3V, Ta=25℃, Input frequency=27.0000MHz, unless otherwise specified） Parameter Symbol Output Frequency Unit Conditions PDB=H, SEL=L OUT1 CLK38 38.0000 MHz XIN×(76/27)/2 PDB=H, SEL=H OUT2 CLK36 36.0000 MHz XIN×(8/3)/2 ○Package outline, Appearance of Marker AA8 LOT No. ○Block diagram, pin function REV. A load 3/4 B1: VDD A1: XIN PLL DATA1 B2: VSS B3: OUT A2: SEL DATA2 A3: PDB 1/2 VDD=3.3V, Ta=25℃, XIN＝27.0000MHz 38.0000MHz output (OUT＝XIN×(76/27)/2) as SEL=L 36.0000MHz output (OUT＝XIN×(8/3)/2) as SEL=H A1 PIN NAME XIN A2 SEL A3 PDB B1 VDD B2 VSS B3 OUT PIN No. Function Clock input pin (27.0000MHz input) SEL pin (L：38.0000MHz, H：36.0000MHz), Equipment with pull-down function (Typ.100k) Power down (L：disable, H：enable), Equipment with pull-down function (Typ.100k) Output fixed to L at disable Power supply GND Clock output terminal (SEL=L：38.0000MHz, SEL=H：36.0000MHz) ●Cautions on use（BU7346GUL） Basically, mount ICs to the printed circuit board for use. (If the ICs are not mounted to the printed circuit board, the characteristics of ICs may not be fully demonstrated.) Mount 0.1F capacitors in the vicinity of the IC PINs between B1 PIN(VDD) and B2 PIN(VSS), respectively. Depending on the conditions of the printed circuit board, mount an additional electrolytic capacitor between the power supply and GND terminal. For EMI protection, it is effective to put ferrite beads in the origin of power supply to be fed to BU7346GUL from the printed circuit board or to insert a capacitor (of 1 or less), which bypasses high frequency desired, between the power supply and the GND terminal. When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may flow instantaneously. Therefore, give special consideration to power coupling capacitance, power wiring, width of GND wiring, and routing of connections. REV. A 4/4 ●Cautions on use（common） （１）Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. （２）Operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. （３）Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal. （４）Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. （５）GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. （６）Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. （７）Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. （８）Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. （９）Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. （１０）Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. （１１）External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. REV. 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