Features • • • • • • • • • • • • • • 3.0V to 5.5V Operating Range Lowest Power in It Class Advanced Low-voltage, Zero-power, Electrically Erasable Programmable Logic Device “Zero” Standby Power (25 µA Maximum) (Input Transition Detection) Low-voltage Equivalent of ATF22V10CZ Ideal for Battery Powered Systems CMOS- and TTL-compatible Inputs and Outputs Inputs are 5V Tolerant Latch Feature Hold Inputs to Previous Logic States EE Technology – Reprogrammable – 100% Tested High-reliability CMOS Process – 20-year Data Retention – 10,000 Erase/Write Cycles – 2,000V ESD Protection – 200 mA Latch-up Immunity Commercial and Industrial Temperature Ranges Dual Inline and Surface Mount Standard Pinouts Green Package Options (Pb/Halide-free/RoHS Compliant) Available Highperformance EE PLD ATF22LV10CZ ATF22LV10CQZ 1. Description The ATF22LV10CZ/CQZ is a high-performance CMOS (electrically erasable) programmable logic device (PLD) that utilizes Atmel’s proven electrically erasable Flash memory technology and provides 25 ns speed with standby current of 25 µA maximum. All speed ranges are specified over the 3.0V to 5.5V range for industrial and commercial temperature ranges. The ATF22LV10CZ/CQZ provides a low-voltage and edge-sensing “zero” power CMOS PLD solution with “zero” standby power (5 µA typical). The ATF22LV10CZ/CQZ powers down automatically to the zero power mode through Atmel’s patented Input Transition Detection (ITD) circuitry when the device is idle. The ATF22LV10CZ/CQZ is capable of operating at supply voltages down to 3.0V. Pin “keeper” circuits on input and output pins hold pins to their previous logic levels when idle, which eliminate static power consumed by pull-up resistors. The “CQZ” combines this low high-frequency ICC of the “Q” design with the “Z” feature. The ATF22LV10CZ/CQZ macrocell incorporates a variable product term architecture. Each output is allocated from 8 to 16 product terms which allows highly complex logic functions to be realized. Two additional product terms are included to provide synchronous reset and asynchronous reset. These additional product terms are common to all 10 registers and are automatically cleared upon power-up. Register Preload simplifies testing. A security fuse prevents unauthorized copying of programmed fuse patterns. 0779L–PLD–12/05 Figure 1-1. Block Diagram 2. Pin Configurations Table 2-1. Pin Configurations (All Pinouts Top View) Pin Name Function CLK Clock IN Logic Inputs I/O Bi-directional Buffers GND Ground VCC (3 to 5.5V) Supply Figure 2-1. TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 CLK/IN IN IN IN IN IN IN IN IN IN IN GND Note: Figure 2-2. 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN DIP/SOIC CLK/IN IN IN IN IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN TSSOP is the smallest package of SPLD offering. PLCC 25 24 23 22 21 20 19 12 13 14 15 16 17 18 5 6 7 8 9 10 11 I/O I/O I/O GND* I/O I/O I/O IN IN GND GND* IN I/O I/O IN IN IN GND* IN IN IN 4 3 2 1 28 27 26 IN IN CLK/IN VCC* VCC I/O I/O Figure 2-3. Note: 2 For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22. ATF22LV10C(Q)Z 0779L–PLD–12/05 ATF22LV10C(Q)Z 3. Absolute Maximum Ratings* Temperature under Bias .................................. -40°C to +85°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground during Programming .....................................-2.0V to +14.0V(1) Note: Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns. 4. DC and AC Operating Conditions Commercial Industrial Operating Temperature (Ambient) 0°C - 70°C -40°C - 85°C VCC Power Supply 3.0V - 5.5V 3.0V - 5.5V 3 0779L–PLD–12/05 4.1 DC Characteristics Symbol Parameter Condition(2) IIL Input or I/O Low Leakage Current IIH Input or I/O High Leakage Current ICC ISB Clocked Power Supply Current Power Supply Current, Standby Max Units 0 ≤ VIN ≤ VIL (Max) -10.0 µA (VCC - 0.2)V ≤ VIN ≤ VCC 10.0 µA VCC = Max Outputs Open, f = 15 MHz VCC = Max VIN = Max Outputs Open Min Typ CZ-25 Com. 50.0 85.0 mA CZ-25 Ind. 55.0 90.0 mA CQZ-30 Com. 18.0 50.0 mA CQZ-30 Ind. 19.0 60.0 mA CZ-25 Com. 3.0 25.0 µA CZ-25 Ind. 4.0 50.0 µA CQZ-30 Com. 3.0 25.0 µA CQZ-30 Ind. 4.0 50.0 µA -130.0 mA IOS(1) Output Short Circuit Current VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.75 V VOL Output Low Voltage VIN = VIH or VIL VCC = Min, IOL = 16 mA 0.5 V VOH Output High Voltage VIN = VIH or VIL VCCIO = Min, IOH = -2.0 mA VOH Output High Voltage IOH = -100 µA Note: VOUT = 0.5V 2.4 V VCC - 0.2V V 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. For DC characterization, the test condition of VCC = Max corresponds to 3.6V. 4 ATF22LV10C(Q)Z 0779L–PLD–12/05 ATF22LV10C(Q)Z 4.2 AC Waveforms INPUTS, I/O REG. FEEDBACK SYNCH. PRESET tS tH tW tW CP tP tAW tAR ASYNCH. RESET tCO tAP REGISTERED OUTPUTS VALID tER 4.3 OUTPUT DISABLED VALID tPD COMBINATORIAL OUTPUTS tEA tER VALID VALID tEA OUTPUT DISABLED VALID VALID AC Characteristics(1) -25 -30 Symbol Parameter Min Max Min Max Units tPD Input or Feedback to Non-registered Output 3.0 25.0 10.0 30.0 ns tCF Clock to Feedback 13.0 10.0 15.0 ns tCO Clock to Output 2.0 15.0 4.0 20.0 ns tS Input or Feedback Setup Time 15.0 18.0 ns tH Input Hold Time 0 0 ns tP Clock Period 25.0 30.0 ns tW Clock Width 12.5 15.0 ns fMAX External Feedback 1/(tS + tCO) Internal Feedback 1/(tS + tCF) No Feedback 1/(tP) 33.3 35.7 40.0 tEA Input to Output Enable 3.0 25.0 tER Input to Output Disable 3.0 tAP Input or I/O to Asynchronous Reset of Register 3.0 tSP Setup Time, Synchronous Preset 15.0 20.0 ns tAW Asynchronous Reset Width 25.0 30.0 ns tAR Asynchronous Reset Recovery Time 25.0 30.0 ns tSPR Synchronous Preset to Clock Recovery Time 15.0 20.0 ns Note: 25.0 30.0 33.3 MHz MHz MHz 10.0 30.0 ns 25.0 10.0 30.0 ns 25.0 10.0 3.0 ns 1. See ordering information for valid part numbers. 5 0779L–PLD–12/05 4.4 Input Test Waveforms 4.4.1 Input Test Waveforms and Measurement Levels 4.4.2 Output Test Loads Note: 4.5 Similar competitors devices are specified with slightly different loads. These load differences may affect output signals’ delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification conditions. Pin Capacitance Table 4-1. Typ Max Units Conditions CIN 5 8 pF VIN = 0V CI/O 6 8 pF VOUT = 0V Note: 4.6 Pin Capacitance (f = 1 MHz, T = 25°C(1)) 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Power-up Reset The registers in the ATF22LV10CZ/CQZ are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic and start below 0.7V. 2. The clock must remain stable during TPR. 3. After TPR, all input and feedback setup times must be met before driving the clock pin high. 4.7 Preload of Register Outputs The ATF22LV10CZ/CQZ’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file 6 ATF22LV10C(Q)Z 0779L–PLD–12/05 ATF22LV10C(Q)Z with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. 5. Electronic Signature Word There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. 6. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF22LV10CZ/CQZ fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. 7. Programming/Erasing Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/ programming. Table 7-1. Programming/Erasing Parameter Description Typ Max Units TPR Power-up Reset Time 600 1000 ns VRST Power-up Reset Voltage 2.3 2.7 V 8. Input and I/O Pin Keepers All ATF22LV10CZ/CQZ family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic array inputs and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see input and I/O diagrams below). Figure 8-1. Input Diagram VCC 100K INPUT ESD PROTECTION CIRCUIT 7 0779L–PLD–12/05 Figure 8-2. I/O Diagram VCC OE DATA I/O VCC INPUT 100K 9. Functional Logic Diagram Description The Functional Logic Diagram describes the ATF22LV10CZ/CQZ architecture. The ATF22LV10CZ/CQZ has 12 inputs and 10 I/O macrocells. Each macrocell can be configured into one of four output configurations: active high/low or registered/combinatorial. The universal architecture of the ATF22LV10CZ/CQZ can be programmed to emulate most 24-pin PAL devices. Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF22LV10CZ/CQZ. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse. 8 ATF22LV10C(Q)Z 0779L–PLD–12/05 ATF22LV10C(Q)Z Figure 9-1. Functional Logic Diagram ATF22LV10CZ/CQZ 9 0779L–PLD–12/05 ATF22LV10CZ/CQZ STANDBY CURRENT VS. SUPPLY VOLTAGE (T A = 25°C) NORMALIZED I CC VS. TEMP 1.2 NORMALIZED ICC 3.500 3.000 ICC (uA) 2.500 2.000 1.500 1.000 0.500 0.000 3.00 3.30 1.1 1.0 0.9 0.8 -40.0 0.0 25.0 TEMPERATURE (C) 3.60 75.0 VCC (V) ATF22LV10CQZ SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 3.3V, T A = 25°C) ATF22LV10CZ SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 3.3V, T A = 25°C) 25.000 50.000 20.000 ICC (mA) 60.000 ICC (mA) 40.000 30.000 15.000 10.000 5.000 20.000 0.000 10.000 0.0 0.5 2.5 0.000 0 0.5 2.5 5 7.5 10 Frequency (MHz) 25 37.5 50 ATF22LV10CZ/CQZ SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V) 7.5 10.0 25.0 37.5 50.0 ATF22LV10C/CZ OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C) 0.0 0.0 -2.0 -2.0 -4.0 IOH (mA) Ioh (mA) 5.0 Frequency (MHz) -4.0 -6.0 -6.0 -8.0 -8.0 -10.0 -10.0 -12.0 -14.0 -12.0 3.0 3.2 3.3 3.5 2.0 3.6 2.2 2.4 2.6 2.8 VOH (V) 3.0 3.2 3.3 ATF22LV10CZ/CQZ OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V) 40.0 39.0 38.0 37.0 36.0 35.0 34.0 33.0 32.0 100.0 80.0 60.0 40.0 20.0 3.0 3.2 3.3 SUPPLY VOLTAGE (V) 10 ATF22LV10CZ/CQZ OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C) IOL (mA) IOL (mA) SUPPLY VOLTAGE (V) 3.5 3.6 0.0 0.00 0.50 1.00 1.50 2.00 VOL (V) 2.50 3.00 3.30 ATF22LV10C(Q)Z 0779L–PLD–12/05 ATF22LV10C(Q)Z ATF22LV10CZ/CQZ INPUT CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C) INPUT CURRENT (µA) INPUT CURRENT (mA) ATF22LV10CZ/CQZ INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C) 20.0 0.0 -20.0 -40.0 -60.0 -80.0 -100.0 -120.0 0.0 -0.2 -0.4 -0.6 INPUT VOLTAGE (V) -0.8 15.0 10.0 5.0 0.0 -5.0 0.0 -1.0 1.1 1.0 0.9 3.0 3.2 3.3 3.5 3.6 SUPPLY VOLTAGE (V) 3.0 3.5 4.0 1.1 1.0 0.9 0.8 -40.0 NORMALIZED TCO VS. VCC NORMALIZED TCO 1.1 1.0 0.9 0.8 3.0 3.2 3.3 SUPPLY VOLTAGE (V) 0.0 25.0 TEMPERATURE (C) 75.0 NORMALIZED TCO VS. TEMP 1.2 NORMALIZED TCO 1.5 2.0 2.5 INPUT VOLTAGE (V) NORMALIZED TPD VS. TEMP 0.8 3.5 3.6 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 25.0 75.0 TEMPERATURE (C) NORMALIZED TSU VS. VCC NORMALIZED TSU VS. TEMP 1.2 1.2 NORMALIZED TSU NORMALIZED TSU 1.0 1.2 1.2 NORMALIZED TPD NORMALIZED TPD NORMALIZED TPD VS. VCC 0.5 1.1 1.0 0.9 0.8 3.0 3.2 3.3 SUPPLY VOLTAGE (V) 3.5 3.6 1.1 1.0 0.9 0.8 -40.0 0.0 25.0 75.0 TEMPERATURE (C) 11 0779L–PLD–12/05 22LV10CZ/CQZ DELTA TPD VS. OUTPUT LOADING 22LV10CZ/CQZ DELTA TCO VS. OUTPUT LOADING 15.0 DELTA TCO (ns) DELTA TPD (ns) 15.0 10.0 5.0 0.0 -5.0 0.00 0.50 1.00 1.50 2.00 OUTPUT LOADING (PF) 2.50 10.0 5.0 0.0 -5.0 0.00 3.00 2.50 3.00 DELTA TCO VS. # OF OUTPUT SWITCHING -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.1 -0.1 -0.2 -0.2 -0.3 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 NUMBER OF OUTPUTS SWITCHING 12 1.00 1.50 2.00 OUTPUT LOADING (PF) 0.0 0.0 -0.1 DELTA TCO (ns) DELTA TPD (ns) DELTA TPD VS. # OF OUTPUT SWITCHING 0.50 9.0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING ATF22LV10C(Q)Z 0779L–PLD–12/05 ATF22LV10C(Q)Z 10. Ordering Information 10.1 Standard Package Options tPD (ns) tS (ns) 25 10.2 15 15 Ordering Code Package Operation Range ATF22LV10CZ-25JC ATF22LV10CZ-25PC ATF22LV10CZ-25SC ATF22LV10CZ-25XC 28J 24P3 24S 24X Commercial (0°C to 70°C) ATF22LV10CZ-25JI ATF22LV10CZ-25PI ATF22LV10CZ-25SI ATF22LV10CZ-25XI 28J 24P3 24S 24X Industrial (-40°C to +85°C) ATF22LV10CQZ-30JC ATF22LV10CQZ-30PC ATF22LV10CQZ-30SC ATF22LV10CQZ-30XC 28J 24P3 24S 24X ATF22LV10CQZ-30JI ATF22LV10CQZ-30PI ATF22LV10CQZ-30SI ATF22LV10CQZ-30XI 28J 24P3 24S 24X Commercial (0°C to 70°C) Industrial (-40°C to +85°C) ATF22LV10CQZ Green Package Options (Pb/Halide-free/RoHS Compliant) tPD (ns) tS (ns) 30 10.3 tCO (ns) 15 tCO (ns) Ordering Code Package Operating Range 15 ATF22LV10CQZ-30JU ATF22LV10CQZ-30PU ATF22LV10CQZ-30SU ATF22LV10CQZ-30XU 28J 24P3 24S 24X Industrial (-40°C to +85°C) Using “C” Product for Industrial To use commercial product for industrial temperature ranges, simply de-rate ICC by 15% on the “C” device. No speed de-rating is necessary. Package Type 28J 28-lead, Plastic J-leaded Chip Carrier (PLCC) 24P3 24-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24S 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 24X 24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP) 13 0779L–PLD–12/05 11. Packaging Information 11.1 28J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 12.319 – 12.573 D1 11.430 – 11.582 E 12.319 – 12.573 E1 11.430 – 11.582 D2/E2 9.906 – 10.922 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 14 2325 Orchard Parkway San Jose, CA 95131 TITLE 28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 28J B ATF22LV10C(Q)Z 0779L–PLD–12/05 ATF22LV10C(Q)Z 11.2 24P3 – PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. 2. This package conforms to JEDEC reference MS-001, Variation AF. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A – – 5.334 A1 0.381 – – D 31.623 – 32.131 E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.270 – 1.651 L 2.921 – 3.810 C 0.203 – 0.356 eB – – 10.922 eC 0.000 – 1.524 e NOTE Note 2 Note 2 2.540 TYP 6/1/04 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 24P3 REV. D 15 0779L–PLD–12/05 11.3 24S – SOIC B D1 D PIN 1 ID PIN 1 e E A COMMON DIMENSIONS (Unit of Measure = mm) A1 0º ~ 8º L1 L SYMBOL MIN NOM MAX A – – 2.65 A1 0.10 – 0.30 D 10.00 – 10.65 D1 7.40 – 7.60 E 15.20 – 15.60 B 0.33 – 0.51 L 0.40 – 1.27 L1 0.23 – 0.32 e NOTE 1.27 BSC 06/17/2002 R 16 2325 Orchard Parkway San Jose, CA 95131 TITLE 24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC) DRAWING NO. REV. 24S B ATF22LV10C(Q)Z 0779L–PLD–12/05 ATF22LV10C(Q)Z 11.4 24X – TSSOP Dimensions in Millimeter and (Inches)* JEDEC STANDARD MO-153 AD Controlling dimension: millimeters 0.30(0.012) 0.19(0.007) 4.48(0.176) 6.50(0.256) 4.30(0.169) 6.25(0.246) PIN 1 0.65(0.0256)BSC 7.90(0.311) 1.20(0.047)MAX 7.70(0.303) 0.15(0.006) 0.05(0.002) 0.20(0.008) 0º ~ 8º 0.09(0.004) 0.75(0.030) 0.45(0.018) 04/11/2001 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. REV. 24X A 17 0779L–PLD–12/05 12. Revision History Version No./Release Date History Revision L – November 2005 18 1. Added Green Package options ATF22LV10C(Q)Z 0779L–PLD–12/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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