ACPL-M21L, ACPL-021L and ACPL-024L Low Power, 5 MBd Digital CMOS Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features ACPL-M21L (single channel SO-5 package), ACPL-021L (single channel SO-8 package) and ACPL-024L (dual channel SO-8 package) are optically-coupled logic gates. The detector IC has CMOS output stage and optical receiver input stage with built-in Schmitt trigger to provide logic-compatible waveforms, eliminating the need for additional waveshaping. CMOS output An internal shield on the ACPL-M21L/021L/024L guarantees common mode transient immunity of 25 kV/μs at a common mode voltage of 1000 V. The ACPL-x2xL optocouplers' series operates from a 2.7 to 5.5 V supply with guaranteed AC and DC performance from an extended temperature range of -40° C to 105° C. Glitches free output upon power-up and power-down of optocoupler. Cathode 1 3 Shield Low power supply current IDD: ≤ 1.1 mA max Low forward current IF: 1.6 mA min Speed: 5 MBd typ Pulse width distortion (PWD): 200 ns max Propagation delay skew (tpsk): 220 max Propagation delay (tp): 250 ns max Common mode rejection: 25 kV/s min at VCM = 1000 V Hysteresis: 0.2 mA typ Temperature range: -40° C to 105° C Safety and regulatory approvals – UL 1577 recognized – 3750 Vrms for 1 minute for ACPL-M21L/021L/024L Functional Diagram Anode Wide supply voltage: 2.7 V – 5.5 V TRUTH TABLE (POSITIVE LOGIC) 6 VDD 5 VO LED VO 4 GND ON OFF HIGH LOW – CSA Approval – IEC/EN 60747-5-5, Approval for Reinforced Insulation Applications Low isolation of high speed logic systems ACPL-M21L Computer peripheral interface Anode1 1 8 VDD Microprocessor system interface VO Cathode1 2 7 V01 Ground loop elimination 6 NC Cathode2 3 6 V02 Pulse transformer replacement 5 GND Anode2 4 5 GND High speed line receiver NC 1 8 VDD Anode 2 7 Cathode 3 NC 4 Shield ACPL-021L Shield ACPL-024L A 0.1 F bypass capacitor must be connected between pins Vdd and GND Power control systems Ordering Information ACPL-M21L, ACPL-024L and ACPL-021L are UL Recognized with 3750 Vrms for 1 minute per UL1577. Option Part number RoHS Compliant Package Surface Mount ACPL-M21L -000E SO-5 X X -500E X X X X ACPL-021L -000E SO-8 X X 1500 per reel 100 per tube X -500E X X -560E X X SO-8 100 per tube 1500 per reel X -060E -000E IEC/EN 60747-5-5 Quantity 100 per tube -060E -560E ACPL-024L Tape & Reel UL1577 5000 Vrms / 1 Minute Rating X 100 per tube X 1500 per reel 1500 per reel X 100 per tube -060E X -500E X X -560E X X X 100 per tube X 1500 per reel 1500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-M21L-500E to order product of SO-5 package in Tape and Reel packaging with RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. 2 Package Outline Drawings ACPL-M21L SO-5 Package LAND PATTERN RECOMMENDATION 0.3 (0.01) MXXX XXX 4.4 ± 0.1 (0.173 ± 0.004) 7.0 ± 0.2 (0.276 ± 0.008) 4.4 (0.17) 8.27 (0.325) 1.8 (0.072) 0.4 ± 0.05 (0.016 ± 0.002) 2.5 (0.10) 3.6 ± 0.1* (0.142 ± 0.004) 2.5 ± 0.1 (0.098 ± 0.004) 0.5 (0.02) 1.3 (0.05) 0.102 ± 0.102 (0.004 ± 0.004) 0.15 ± 0.025 (0.006 ± 0.001) 7° MAX. 1.27 BSC (0.050) Dimensions in millimeters (inches). Note: Foating Lead Protrusion is 0.15 mm (6 mils) max. * Maximum Mold flash on each side is 0.15 mm (0.006). 3 0.71 MIN (0.028) MAX. LEAD COPLANARITY = 0.102 (0.004) ACPL-024L/021L SO-8 Package LAND PATTERN RECOMMENDATION 1.9 (0.075) 8 7 6 5 5.994 ± 0.203 (0.236 ± 0.008) XXXV YWW 3.937 ± 0.127 (0.155 ± 0.005) 0.64 (0.025) TYPE NUMBER (LAST 3 DIGITS) 3.95 (0.156) 7.49 (0.295) DATE CODE PIN ONE 1 2 3 0.406 ± 0.076 (0.016 ± 0.003) 4 1.270 BSC (0.050) 1.3 (0.5) 7° * 5.080 ± 0.127 (0.200 ± 0.005) 3.175 ± 0.127 (0.125 ± 0.005) 45° X 0.432 (0.017) 0 ~ 7° 0.228 ± 0.025 (0.009 ± 0.001) 1.524 (0.060) * Total package length (inclusive of mold flash) 5.207 ± 0.254 (0.205 ± 0.010) Dimensions in Millimeters (Inches). Note: Floating lead protrusion is 0.15 mm (6 mils) max. Lead coplanarity = 0.10 mm (0.004 inches) max. Option number 500 not marked. 0.305 MIN. (0.012) 0.203 ± 0.102 (0.008 ± 0.004) Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACPL-M21L/024L/021L is approved by the following organizations: UL Approval under UL 1577, component recognition program up to VISO = 3750 VRMS for ACPL-M21L/024L/021L CSA Approval under CSA Component Acceptance Notice #5. IEC/EN 60747-5-5 (Option 060 only) 4 Insulation and Safety Related Specifications Parameter Symbol ACPL-M21L ACPL-024L ACPL-021L Units Conditions Minimum External Air Gap (Clearance) L(101) 5 4.9 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 5 4.8 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. 175 175 Volts DIN IEC 112/VDE 0303 Part 1 IIIa IIIa Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group Material Group (DIN VDE 0110, 1/89, Table 1) IEC/EN 60747-5-5 Insulation Characteristics* (Option 060) Characteristic Description Symbol ACPL-M21L/ 024L/021L Unit Installation classification per DIN VDE 0110/39, Table 1 for rated mains voltage ≤ 150 Vrms I – IV for rated mains voltage ≤ 300 Vrms I – III for rated mains voltage ≤ 600 Vrms I – II for rated mains voltage ≤ 1000 Vrms Climatic Classification 55/105/21 Pollution Degree (DIN VDE 0110/39) 2 Maximum Working Insulation Voltage VIORM 567 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC VPR 1063 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial discharge < 5 pC VPR 896 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 6000 Vpeak TS 150 °C Input Current** IS, INPUT 150 mA Output Power** PS, OUTPUT 600 mW RS >109 Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature Insulation Resistance at TS, VIO = 500 V * Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figure for dependence of PS and IS on ambient temperature. 5 Absolute Maximum Ratings Parameter Symbol Min Max Units Storage Temperature TS -55 125 °C Operating Temperature TA -40 105 °C Reverse Input Voltage VR 5 V Supply Voltage VDD 6.5 V Average Forward Input Current IF 8 mA Peak Forward Input Current IF(TRAN) 1 A 10 mA VDD +0.5 V Output Current IO Output Voltage VO Lead Solder Temperature TLS -0.5 Condition ≤ 1 s Pulse Width, < 300 pulses per second 260° C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings section Recommended Operating Conditions Parameter Symbol Min Max Units Operating Temperature TA -40 105 °C Input Current, Low Level IFL 0 250 A Input Current, High Level IFH 1.6* 6 mA Power Supply Voltage VDD 2.7 5.5 V Forward Input Voltage VF (OFF) 0.8 V * The initial switching threshold is 1.6 mA or less. It is recommended that 2.2 mA be used to permit at least a 20% LED degradation guardband. Electrical Specifications (DC) Over recommended temperature (TA = -40° C to 105° C) and supply voltage (2.7 V ≤ VDD ≤ 5.5 V). All typical specifications are at VDD = 2.7 V, TA = 25° C, unless otherwise specified. Parameter Symbol Input Forward Voltage VF Input Reverse Breakdown Voltage BVR 8 Logic High Output Voltage VOH Logic Low Output Voltage VOL Part Number Min Typ Max Units Test Conditions 1.5 2.0 V IF = 2 mA (Figure 1 & 2) V IR = 10 A VDD - 0.1 V IF = 2.2 mA, IO = -20 A VDD - 1.0 V IF = 2.2 mA, IO = -3.2 mA (Figure 3) 11 0.001 0.1 V IF = 0 mA, IO = 20 A 0.15 0.4 V IF = 0 mA, IO = 3.2 mA (Figure 4) Input Threshold Current ITH 0.5 1.4 mA Figure 5 Logic Low Output Supply Current IDDL 0.6 1.1 mA VF = 0 V, VDD = 5.5 V, IO = Open (Figure 6) Logic High Output Supply Current IDDH 0.5 1.1 mA IF = 2.2 mA, VDD = 5.5 V, IO = Open (Figure 7) Input Capacitance CIN 77 pF f = 1 MHz, VF = 0 V Input Diode Temperature Coefficient VF/TA -1.9 mV/°C IF = 2.2 mA 6 Switching Specifications (AC) Over recommended temperature (TA = -40° C to +105° C), supply voltage (2.7 V ≤ VDD ≤ 5.5 V). All typical specifications are at VDD = 2.7 V, TA = 25° C Parameter Symbol Propagation Delay Time to Logic Low Output [1] Part Number Min Typ Max Units Test Conditions tPHL 130 250 ns Propagation Delay Time to Logic High Output [1] tPLH 115 250 ns IF = 2.2 mA, CL= 15 pF, CMOS Signal Levels (Figure 8, 9 & 12) Pulse Width Distortion [2] PWD 200 ns Propagation Delay Skew [3] tPSK 220 ns Output Rise Time (10% – 90%) tR 11 ns IF = 2.2 mA, CL= 15 pF, CMOS Signal Levels. Output Fall Time (90% – 10%) tF 11 ns IF = 2.2 mA, CL= 15 pF, CMOS Signal Levels. Static Common Mode Transient Immunity at Logic High Output [4] |CMH| 25 40 kV/s VCM = 1000 V, TA = 25° C, IF = 2.2 mA, CL= 15 pF, VI = 5 V (RT = 1.6 k) or VI = 3.3 V (RT = 840 ) CMOS Signal Levels Figure 13 Static Common Mode Transient Immunity at Logic Low Output [5] |CML| 25 40 kV/s VCM = 1000 V, TA = 25° C, IF = 0 mA, CL= 15 pF, VI = 0 V (RT = 1.6 k) or (RT = 840 ) CMOS Signal Levels Figure 13 Notes: 1. tPHL propagation delay is measured from the 50% (Vin or IF) on the falling edge of the input pulse to the 50% VDD of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% (Vin or IF) on the rising edge of the input pulse to the 50% level of the rising edge of the VO signal 2. PWD is defined as |tPHL - tPLH| 3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 5. CML is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a low logic state. 6. Use of a 0.1 F bypass capacitor connected between Vdd and ground is recommended. Package Characteristics All typical at TA = 25° C Parameter Symbol Part Number Min Input-Output Insulation VISO ACPL-M21L/ 024L/021L 3750 Input-Output Resistance RI-O Input-Output Capacitance CI-O 7 Typ Max Units Test Conditions Vrms RH < 50% for 1 min. TA = 25° C 1012 VI-O = 500 V 0.6 pF f = 1 MHz, TA = 25° C 100 1.7 IF - FORWARD CURRENT - mA VF - FORWARD VOLTAGE - V 1.8 1.6 1.5 1.4 1.3 1.2 -40 0 20 40 60 TA - TEMPERATURE - °C 80 0.1 1.3 100 VOL - LOW LEVEL OUTPUT VOLTAGE - V 6 5 1.7 1.8 4 3 2 1 0 1 2 3 4 5 VDD - SUPPLY VOLTAGE - V 6 0.2 0.15 0.1 0.05 -20 0 20 40 60 TA - TEMPERATURE - °C 80 100 Figure 4. Logic Low Output Voltage vs. Temperature 0.7 0.7 0.6 0.5 0.4 0.3 0.2 0.1 IDDL - LOGIC LOW OUTPUT SUPPLY CURRENT - mA ITH_3.3 V ITH_5.0 V 0.8 0 VDD = 3.3 V VF = 0 V IO = 3.2 mA 0 -40 7 0.9 Ith - INPUT THRESHOLD CURRENT - mA 1.5 1.6 VF - FORWARD VOLTAGE - V 0.25 IO = -3.2 mA Figure 3. Logic High Output voltage vs Supply Voltage 0.6 0.5 0.4 0.3 0.2 IDDL @ 3.3 V IDDL @ 5.0 V 0.1 0 -40 -20 0 20 40 60 TA - TEMPERATURE - °C Figure 5. Input Threshold Current vs. Temperature 8 1.4 Figure 2. Forward Current vs Forward Voltage 7 VOH - HIGH LEVEL OUTPUT VOLTAGE - V 1 0.01 -20 Figure 1. Forward Voltage vs. Temperature 0 10 80 100 -40 -20 0 20 40 60 TA - TEMPERATURE - °C Figure 6. Logic Low Output Supply Current vs. Temperature 80 100 0.6 0.5 0.4 0.3 0.2 IDDH_3.3 V IDDH_5.0 V 0.1 0 -40 -20 0 20 40 60 TA - TEMPERATURE - °C 80 100 TPLH - PROPAGATION DELAY - ns 150 140 130 120 110 100 90 80 70 60 50 -40 IF = 1.6, 2.2 and 6 mA VDD = 2.7 V -20 0 20 40 60 TA - TEMPERATURE - °C 80 100 Figure 8. Propagation Delay, tPHL vs. Temperature Figure 7. Logic High Output Supply Current vs. Temperature 150 140 130 120 110 100 90 80 70 60 VDD = 2.7 V 50 -40 -20 Tp - PROPAGATION DELAY - ns IDDH - LOGIC HIGH OUTPUT SUPPLY CURRENT - mA 0.7 IF = 1.6 mA IF = 2.2 mA IF = 6.0 mA 0 20 40 60 TA - TEMPERATURE - °C 80 100 Figure 9. Propagation Delay, tPLH vs. Temperature 6 4 5 Vo - OUTPUT VOLTAGE - V Vo - OUTPUT VOLTAGE - V 3.5 3 2.5 2 1.5 1 2 VDD = 5.0 V VDD = 3.3 V 0 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008 IF - INPUT CURRENT - A Figure 10. Output Voltage vs Input Current @ Vdd = 3.3 V 9 3 1 0.5 0 4 0 0 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008 IF - INPUT CURRENT - A Figure 11. Output Voltage vs Input Current @ Vdd = 5 V PULSE GEN tr = tf = 11 ns f = 1.0 MHz 50% DUTY CYCLE OUTPUT VO MONITORING NODE Vdd ACPL-M21L IF 6 1 IF (ON) 50% IF (ON) 0 mA INPUT IF * 5 tPLH CL = 15 pF INPUT MONITORING NODE 3 Shield tPHL VOH 50% VOL 4 OUTPUT VO Rm * 0.1 μF BYPASS — SEE NOTE 6 above. [6] PULSE GEN tr = tf = 11 ns f = 1.0 MHz 50% DUTY CYCLE IF INPUT MONITORING NODE Vdd 8 2 7 6 4 Shield Figure 12. Circuit for tPLH, tPHL, tr, tf 10 PULSE GEN tr = tf = 11 ns f = 1.0 MHz 50% DUTY CYCLE 5 IF OUTPUT VO MONITORING NODE Vdd ACPL-024L ACPL-021L 1 3 Rm OUTPUT VO MONITORING NODE 1 8 2 7 3 6 * CL = 15 pF INPUT MONITORING NODE Rm 4 Shield 5 CL = 15 pF ACPL-M21L, ACPL-021L, ACPL-024L: VI = 3.3 V: R1 = 510 ± 1%, R2 = 330 ± 1% VI = 5.0 V: R1 = 1 k ± 1%, R2 = 600 ± 1% RT = R1 + R2 R1/R2 ≈ 1.5 VI R 1 IF 1 VDD 6 XXX YWW C 5 Vo C = 0.1μF R2 3 GND1 4 GND2 ACPL-M21L 1 VI R1 IF 1 8 2 3 7 4 Vo1 GND1 C 2 7 6 5 Vo2 GND2 GND2 VI R2 R1 IF 3 XXX YWW R2 VI VDD R2 XXX YWW GND2 R1 IF VDD 8 4 ACPL-021L Vo1 C 6 5 Vo2 GND2 ACPL-024L Figure 13. Recommended printed circuit board layout and input current limiting resistor selection This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. AV02-3462EN - July 24, 2012