HI1396 8-Bit, 125 MSPS, Flash A/D Converter August 1997 Features • • • • • • • • • • • • Description Differential Linearity Error ±0.5 LSB (Typ) or Less Integral Linearity Error ±0.5 LSB (Typ) or Less Built-In Integral Linearity Compensation Circuit Ultra High Speed Operation with Maximum Conversion Rate of 125 MSPS (Min) Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . . 18pF Wide Analog Input Bandwidth (Min for Full Scale Input) . . . . . . . . . . . . . . . . . . 200MHz Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . .-5.2V Low Power Consumption (Typ) . . . . . . . . . . . . .870mW Low Error Rate Operable at 50% Clock Duty Cycle Capable of Driving 50Ω Loads Direct Replacement for Sony CXA1396 The HI1396 is an 8-bit, ultra high speed flash analog-to-digital converter IC capable of digitizing analog signals at the maximum rate of 125 MSPS. The digital I/O levels of the converter are compatible with ECL 100K/10KH/10K. Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. HI1396JCJ -20 to 75 42 Ld SBDIP D42.6 HI1396AIL -20 to 100 68 Ld CLCC J68.A Applications • Video Digitizing • Communication Systems • HDTV (High Definition TV) • Radar Systems • Direct RF Down-Conversion • Digital Oscilloscopes Pinouts 40 NC 39 AVEE DVEE 4 DGND1 5 38 AVEE DGND2 6 37 NC (LSB) D0 7 36 NC D1 D2 8 9 35 AGND 34 VIN D3 10 33 AGND D4 11 32 VRM D5 12 D6 13 (MSB) D7 14 31 AGND 30 VIN 29 AGND DGND2 15 28 NC DGND2 16 27 NC DVEE 17 26 AVEE MINV 18 25 AVEE NC 19 9 NC AVEE AVEE NC VRT NC AVEE NC NC NC LINV NC DVEE NC DGND1 DGND2 NC 23 VRB CLK 21 22 NC 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 NC 11 59 AVEE 12 58 AVEE 13 57 NC 14 56 VRB 15 55 NC 16 54 NC 17 53 NC 18 52 CLK 19 51 CLK 20 50 NC 21 49 MINV 22 48 NC 23 24 47 DVEE 46 NC 25 45 NC 44 NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 24 NC CLK 20 8 NC 41 VRT 3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 4-1156 NC 2 AGND NC NC NC NC NC LINV (MSB) D7 NC DGND2 DGND1 NC 42 NC NC NC (LSB) D0 D1 D2 D3 D4 D5 D6 1 NC NC AVEE NC NC NC AGND VIN AGND VRM AGND VIN HI1396 (CLCC) TOP VIEW NC NC HI1396 (SBDIP) TOP VIEW File Number 3576.3 HI1396 Functional Block Diagram MINV R1 COMPARATOR VRT R/2 R 1 R D7 (MSB) 2 R D6 63 D5 R 64 VIN R D4 65 OUTPUT D3 R 126 D2 R 127 R2 VRM ENCODE LOGIC R D1 128 R D0 (LSB) 129 R 191 R 192 VIN R 193 R 254 R 255 VRB CLK CLK R3 R/2 CLOCK DRIVER LINV 4-1157 HI1396 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (AVEE , DVEE) . . . . . . . . . . . . . . . . . . . . . . . . . . .-7V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V Reference Input Voltage VRT , VRB , VRM . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V |VRT - VRB | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage CLK, CLK, MINV, LINV . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V |CLK-CLK | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V VRM Pin Input Current (IVRM) . . . . . . . . . . . . . . . . . . -3mA to +3mA Digital Output Current (ID0 to ID7) . . . . . . . . . . . . . . . -30mA to 0mA Thermal Resistance (Typical, Note 1) θJAoC/W θJCoC/W SBDIP Package . . . . . . . . . . . . . . . . . . 45 7 CLCC Package . . . . . . . . . . . . . . . . . . 45 8 Maximum Junction Temperature Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range (TSTG) . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions (Note 1) Temperature Ranges (Note 4) SBDIP Package, TA . . . . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC CLCC Package, TC . . . . . . . . . . . . . . . . . . . . . . . . -20oC to 100oC Supply Voltage Ranges AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -4.95V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V AGND - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to 0.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to -1.8V Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . VRB to VRT Pulse Width of Clock tPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0ns (Min) tPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0ns (Min) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT - 8 - Bits SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL HI1396JCJ, HI1396AIL fC = 125 MSPS - ±0.3 ±0.5 LSB Differential Linearity Error, DNL HI1396JCJ, HI1396AIL fC = 125 MSPS - - ±0.5 LSB 200 - - MHz ANALOG INPUT Input Bandwidth VIN = 2VP-P Analog Input Capacitance, CIN VIN = 1V + 0.07VRMS - 17 - pF 50 190 - kΩ 20 130 400 µA 75 110 155 Ω VRT 8 19 32 mV VRB 0 15 24 mV Analog Input Resistance, RIN Input Bias Current, IIN VIN = -1V REFERENCE INPUTS Reference Resistance, RREF Offset Voltage EOT EOB DIGITAL INPUTS Logic H Level, VIH -1.13 - - V Logic L Level, VIL - - -1.50 V Logic H Current, IIH Input Connected to -0.8V 0 - 50 µA Logic L Current, IIL Input Connected to -1.6V 0 - 50 µA - 7 - pF Input Capacitance DIGITAL OUTPUTS Logic H Level, VOH RL = 50Ω to -2V -1.10 - - V Logic L Level, VOL RL = 50Ω to -2V - - -1.62 V 4-1158 HI1396 Electrical Specifications TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output Rise Time, tr RL = 50Ω to -2V, 20% to 80% 0.5 0.9 1.2 ns Output Fall Time, tf RL = 50Ω to -2V, 20% to 80% TIMING CHARACTERISTICS 0.5 1.0 1.3 ns Output Delay, tOD 3.0 3.6 4.2 ns H Pulse Width of Clock, tPW1 4.0 - - ns L Pulse Width of Clock, tPW0 4.0 - - ns 125 - - MSPS DYNAMIC CHARACTERISTICS Error Rate 10-9 TPS (Note 2) Maximum Conversion Rate, fC Aperture Jitter, tAJ - 10 - ps Sampling Delay, tDS - 1.5 - ns Input = 1MHz, Full Scale fC = 125 MSPS - 46 - dB Input = 31.5MHz, Full Scale fC = 125 MSPS - 40 - dB Error Rate Input = 31.249MHz, Full Scale Error > 16 LSB, fC = 125 MSPS - - 10-9 TPS (Note 2) Differential Gain Error, DG NTSC 40 IRE Mod. Ramp, fC = 125 MSPS - 1.0 - % - 0.5 - Degree -230 -160 - mA - 870 - mW Signal to Noise Ratio (SINAD) RMS Signal = -----------------------------------------------------------------RMS Noise + Distor tion Differential Phase Error, DP POWER SUPPLY CHARACTERISTICS Supply Current, IEE Power Consumption Note 3 NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. TPS: Times Per Sample. 2 3. ( V RT – V RB ) P D = I EE • V EE + ------------------------------------R REF 4. TA specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed. Timing Diagram ANALOG IN N+1 N N+2 tPW1 tPW0 CLK CLK DIGITAL OUT N-1 20% 80% tr tOD FIGURE 1. 4-1159 N 20% N+1 80% tf HI1396 Pin Descriptions and I/O Pin Equivalent Circuits PIN NUMBER DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 29, 31, 33, 35 49, 51, 53, 55 AGND - 0V Analog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND1, DGND2. 1, 25, 26, 38, 39 41, 42, 62, 63, 67 AVEE - -5.2V Analog VEE -5.2V (Typ). Internally connected to DVEE (Resistance: 4Ω to 6Ω). Bypass with 0.1µF to AGND. 21 35 CLK I ECL 20 34 CLK EQUIVALENT CIRCUIT CLK Input. DGND1 Input complementary to CLK. When left open pulled down to -1.3V. Device is operable without CLK input, but use of complementary inputs of CLK and CLK is recommended to obtain stable high speed operation. R R R CLK DESCRIPTION R CLK DVEE R R 5, 16 7, 24 DGND1 - 0V Digital GND for internal circuits. 6, 15 8, 23 DGND2 - 0V Digital GND for output transistors. 4, 17 5, 30 DVEE - -5.2V Digital VEE . Internally connected to AVEE (resistance: 4Ω to 6Ω). Bypass with 0.1µF to DGND 7 14 D0 O ECL 8 15 D1 9 16 D2 10 17 D3 11 18 D4 12 19 D5 13 20 D6 14 21 D7 DGND2 LSB of data outputs. External pull-down resistor is required. Data outputs. External pull-down resistors are required. DI DVEE 4-1160 MSB of data outputs. External pull-down resistor is required. HI1396 Pin Descriptions and I/O Pin Equivalent Circuits PIN NUMBER DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 3 3 LINV I ECL (Continued) EQUIVALENT CIRCUIT DESCRIPTION Input pin for D0 (LSB) to D6 output polarity inversion (see A/D Output Code Table). Pulled low when left open. DGND1 18 32 MINV I ECL Input pin for D7 (MSB) output polarity inversion (see A/D Output Code Table). Pulled low when left open. R R 30, 34 50, 54 VIN I LINV OR MINV R DVEE R -1.3V VRT to VRB AGND Analog input pins. These two pins must be connected externally, since they are not internally connected. VIN VIN AVEE 23 39 VRB I -2V 32 52 VRM I VRB/2 41 65 VRT I 0V VRT Reference voltage (bottom). Typically -2V. Bypass with a 0.1µF and 10µF to AGND. R1 R/2 R COMPARATOR 1 R COMPARATOR 2 R VRM COMPARATOR 127 R2 R COMPARATOR 128 R COMPARATOR 129 R COMPARATOR 130 R COMPARATOR 255 VRB R3 4-1161 R/2 Reference voltage mid point. Can be used as a pin for integral linearity compensation. Reference voltage (top) typically 0V. When a voltage different from AGND is applied to this pin, bypass with a 0.1µF and 10µF to AGND. HI1396 Pin Descriptions and I/O Pin Equivalent Circuits PIN NUMBER DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 2, 19, 22, 24, 27, 28, 36, 37, 40, 42 1, 2, 4, 6, 9-13, 25-29, 31, 33, 36-38, 40, 43-48, 56-61, 64, 66, 68 NC - - (Continued) EQUIVALENT CIRCUIT DESCRIPTION Unused pins. No internal connections have been made to these pins. Connecting them to AGND or DGND on PC board is recommended. A/D OUTPUT CODE TABLE MINV 1, LINV 1 VIN (Note 5) STEP D7 0V -1V D0 0, 1 D7 1, 0 D0 D7 0, 0 D0 D7 D0 000 • • • • • 00 100 • • • • • 00 011 • • • • • 11 111 • • • • • 11 0 000 • • • • • 00 100 • • • • • 00 011 • • • • • 11 111 • • • • • 11 1 000 • • • • • 01 100 • • • • • 01 011 • • • • • 10 111 • • • • • 10 • • • • • • • • • • • • 127 011 • • • • • 11 111 • • • • • 11 000 • • • • • 00 100 • • • • • 00 128 100 • • • • • 00 000 • • • • • 00 111 • • • • • 11 011 • • • • • 11 • • • • • • • • • • • • 111 • • • • • 10 011 • • • • • 10 100 • • • • • 01 000 • • • • • 01 254 255 -2V 111 • • • • • 11 011 • • • • • 11 100 • • • • • 00 000 • • • • • 00 111 • • • • • 11 011 • • • • • 11 100 • • • • • 00 000 • • • • • 00 NOTE: 5. VRT = 0V, VRB = -2V. Test Circuits SIGNAL SOURCE fCLK 4 VIN 8 HI1396 CLK A ECL LATCH B CLK -1kHz + ECL LATCH 2VP-P SINEWAVE DATA 16 SIGNAL SOURCE fCLK/4 fCLK FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT 4-1162 COMPARATOR A>B PULSE COUNTER HI1396 Test Circuits (Continued) HI20201 VIN 8 DUT HI1396 AMP CLK 8 ECL LATCH 10 BIT D/A CLK NTSC SIGNAL SOURCE DELAY SG (CW) 50 VBB VECTOR SCOPE DG/DP FIGURE 3. DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT +V S2 - S1 : A < B : ON S2 : A > B : ON S1 + -V A<B A>B COMPARATOR VIN DUT HI1396 8 “0” A8 B8 A1 A0 B1 B0 8 BUFFER “1” DVM 8 CLK (125 MSPS) 00000000 TO 11111110 CONTROLLER FIGURE 4. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT 4-1163 HI1396 Test Circuits (Continued) IIN 42 1 2 41 3 40 4 39 5 38 6 37 7 36 8 35 9 34 HI1396JCJ 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 32 12 31 13 30 14 29 15 28 16 27 17 26 18 25 19 24 20 23 21 22 -1V -2V A IIN 33 10 11 A -1V 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 HI1396AIL 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 -2V A IEE -5.2V A IEE -5.2V FIGURE 5A. FIGURE 5B. FIGURE 5. ANALOG INPUT BIAS AND POWER SUPPLY CURRENT TEST CIRCUITS 0V -1V VIN -2V 67.5MHz AMP OSC1 φ: VARIABLE CLK VIN fR HI1396 CLK LOGIC ANALYZER ∆υ ∆t t VIN OSC2 67.5MHz 8 1024 SAMPLES ECL BUFFER CLK 129 128 127 126 125 σ (LSB) APERTURE JITTER Aperture jitter is defined as follows: ∆υ 256 t AJ = σ ⁄ ------- = σ ⁄ ---------- × 2πf 2 ∆t Where σ (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. FIGURE 6A. FIGURE 6B. APERTURE JITTER TEST METHOD FIGURE 6. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT 4-1164 HI1396 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 4-1165 ASIA Intersil (Taiwan) Ltd. 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