Tiny I2C Programmable Linear Battery Charger with Power Path and USB Mode Compatibility ADP5061 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT ADP5061 VBUS C1 10µF ISO_S VIN CBP C2 10nF C3 47µF SCL SDA DIG_IO1 DIG_IO2 DIG_IO3 SYSTEM ISO_B CHARGER CONTROL BLOCK BAT_SNS + Li-ion C4 22µF THR SYS_EN ILED VLED AGND 10544-001 AC OR USB PROGRAMMABLE 2.6 mm × 2 mm WLCSP package Fully programmable via I2C Flexible digital control inputs Up to 2.1 A current from an ac charger in LDO mode Operating input voltage from 4.0 V to 6.7 V Tolerant input voltage from −0.5 V to +20 V (USB VBUS) Fully compatible with USB 3.0 and USB Battery Charging Specification 1.2 Built-in current sensing and limiting As low as 30 mΩ battery isolation FET between battery and charger output Thermal regulation prevents over heating Compliant with JEITA 1 and JEITA 2 Li-Ion battery charging temperature specifications SYS_EN flag permits the system to be disabled until battery is at minimum required level for guaranteed system start-up Figure 1. APPLICATIONS Digital still cameras Digital video cameras Single cell Li-Ion portable equipment PDAs, audio, and GPS devices Portable medical devices Mobile phones GENERAL DESCRIPTION The ADP5061 charger is fully compliant with USB 3.0 and the USB Battery Charging Specification 1.2 and enables charging via the mini USB VBUS pin from a wall charger, car charger, or USB host port. The ADP5061 operates from a 4 V to 6.7 V input voltage range but is tolerant of voltages up to 20 V. The 20 V voltage tolerance alleviates the concerns about the USB bus spiking during disconnect or connect scenarios. The ADP5061 features an internal FET between the linear charger output and the battery. This permits battery isolation and, hence, system powering under a dead battery or no battery scenario, which allows for immediate system function on connection to a USB power supply. Based on the type of USB source, which is detected by an external USB detection chip, the ADP5061 can be set to apply the correct current limit for optimal charging and USB compliance. The ADP5061 has three factory programmable digital input/output pins that provide maximum flexibility for different systems. These digital input/output pins permit combinations of features such as, input current limits, charging enable and disable, charging current limits, and a dedicated interrupt output pin. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. ADP5061 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Battery Isolation FET ................................................................. 20 Applications ....................................................................................... 1 Battery Detection ....................................................................... 20 Typical Application Circuit ............................................................. 1 Battery Pack Temperature Sensing .......................................... 21 General Description ......................................................................... 1 I2C Interface ................................................................................ 25 Revision History ............................................................................... 2 I2C Register Map......................................................................... 26 Specifications..................................................................................... 3 Register Bit Descriptions ........................................................... 27 Recommended Input and Output Capacitances ...................... 6 Applications Information .............................................................. 35 I C-Compatible Interface Timing Specifications ..................... 6 External Components ................................................................ 35 Absolute Maximum Ratings ....................................................... 7 PCB Layout Guidelines.............................................................. 37 Thermal Resistance ...................................................................... 7 Power Dissipation and Thermal Considerations ....................... 38 ESD Caution .................................................................................. 7 Charger Power Dissipation ....................................................... 38 Pin Configuration and Function Descriptions ............................. 8 Junction Temperature ................................................................ 38 Typical Performance Characteristics ............................................. 9 Factory Programmable Options ................................................... 39 Temperature Characteristics ..................................................... 11 Charger Options ......................................................................... 39 Typical Waveforms ..................................................................... 13 I2C Register Defaults .................................................................. 40 Theory of Operation ...................................................................... 14 Digital Input and Output Options ........................................... 40 Summary of Operation Modes ................................................. 14 Packaging and Ordering Information ......................................... 42 Introduction ................................................................................ 15 Outline Dimensions ................................................................... 42 Charger Modes............................................................................ 17 Ordering Guide .......................................................................... 42 2 Thermal Management ............................................................... 20 REVISION HISTORY 6/12—Revision 0: Initial Version Rev. 0 | Page 2 of 44 Data Sheet ADP5061 SPECIFICATIONS −40°C < TJ < +125°C, VVIN = 5.0 V, VHOT < VTHR < VCOLD, VBAT_SNS = 3.6 V, VISO_B = VBAT_SNS, CVIN = 10 µF, CISO_S = 22 µF, CISO_B = 22 µF, CCBP = 10 nF, all registers at default values, unless otherwise noted. Table 1. Parameter GENERAL PARAMETERS Undervoltage Lockout Hysteresis Total Input Current VINx Current Consumption Battery Current Consumption CHARGER Fast Charge Current CC Mode Symbol Min Typ Max Unit Test Conditions/Comments VUVLO 2.25 50 74 114 2.35 100 92 425 470 2.5 150 100 150 300 500 900 1500 5 V mV mA mA mA mA mA mA mA µA µA µA 0.5 0.9 mA Falling threshold, higher of VVIN and VBAT_SNS 1 Hysteresis, higher of VVIN and VBAT_SNS rising1 Nominal USB initialized current level 2 USB super speed USB enumerated current level (specification for China) USB enumerated current level Dedicated charger input Dedicated wall charger Charging or LDO mode DIS_IC1 = high, VISO_B < VINx < 5.5 V LDO mode, VISO_S > VBAT_SNS Standby, includes ISO_Sx pin leakage, VVIN = 0 V, TJ = −40°C to +85°C Standby, battery monitor active 750 775 mA +30 +30 +35 25 mA mA mA mA mA ILIM IQVIN IQVIN_DIS IQBATT ICHG Fast Charge Current Accuracy Trickle Charge Current2 Weak Charge Current2, 3 Trickle to Weak Charge Threshold Dead Battery Hysteresis Weak Battery Threshold Weak to Fast Charge Threshold Battery Termination Voltage Termination Voltage Accuracy Battery Overvoltage Threshold ITRK_DEAD ICHG_WEAK 715 −40 −50 −65 16 20 ITRK_DEAD + ICHG 450 VISO_B = 3.9 V; fast charge current accuracy is guaranteed at temperatures from TJ = −40°C to isothermal regulation limit (typically TJ = +115°C)2, 3 ICHG = 50 mA to 550 mA ICHG = 600 mA to 950 mA ICHG = 1000 mA to 1300 mA VTRK_DEAD ΔVTRK_DEAD 2.4 2.5 100 2.6 V mV VTRK_DEAD < VBAT_SNS < VWEAK2, 4 On BAT_SNS2 VWEAK ΔVWEAK VTRM 2.89 3.0 100 4.200 3.11 V mV V % % % V On BAT_SNS2, 4 On BAT_SNS, TJ = 25°C, IEND = 52.5 mA2 TJ = 0°C to 115°C2 TJ = −40°C to +125°C Relative to VINx voltage, BAT_SNS rising mA mA VBAT_SNS = VTRM IEND = 52.5 mA, TJ = 0°C to 115°C2 −0.25 −0.96 −1.15 VBATOV Charge Complete Current Charging Complete Current Threshold Accuracy IEND Recharge Voltage Differential Battery Node Short Threshold Voltage2 Battery Short Detection Current Charging Start Voltage Limit Charging Soft Start Current Charging Soft Start Timer BATTERY ISOLATION FET Bump to Bump Resistance Between ISO_Sx and ISO_Bx Regulated System Voltage: VBAT Low VRCH VBAT_SHR ITRK_SHORT VCHG_VLIM ICHG_START tCHG_START Battery Supplementary Threshold 2 280 20 15 17 59 160 2.2 3.6 185 RDSONISO VISO_SFC VTHISO 3.6 3.3 0 +0.25 +0.89 +1.20 VIN − 0.075 52.5 260 2.4 20 3.7 260 3 98 83 123 390 2.5 3.8 365 mV V mA V mA ms 30 49 mΩ 3.8 3.5 5 4.0 3.7 12 V Rev. 0 | Page 3 of 44 mV IEND = 92.5 mA, TJ = 0°C to 115°C Relative to VTRM, BAT_SNS falling2 ITRK_SHORT = ITRK_DEAD2 Voltage limit is not active by default VBAT_SNS > VTRK_DEAD On battery supplement mode, VINx = 0 V, VISO_B = 4.2 V, IISO_B = 500 mA VTRM[5:0] programming ≥ 4.00 V VTRM[5:0] programming < 4.00 V VISO_S < VISO_B, VSYS rising ADP5061 Parameter LDO AND HIGH VOLTAGE BLOCKING Regulated System Voltage Load Regulation High Voltage Blocking FET (LDO FET) On Resistance Maximum Output Current VINx Input Voltage, Good Threshold Rising VINx Falling VINx Input Overvoltage Threshold Hysteresis VINx Transition Timing THERMAL CONTROL Isothermal Charging Temperature Thermal Early Warning Temperature Thermal Shutdown Temperature THERMISTOR CONTROL Thermistor Current 10,000 NTC 100,000 NTC Thermistor Capacitance Cold Temperature Threshold Resistance Thresholds Cool to Cold Resistance Cold to Cool Resistance Hot Temperature Threshold Resistance Thresholds Hot to Typical Resistance Typical to Hot Resistance JEITA1 Li-ION BATTERY CHARGING SPECIFICATION DEFAULTS 5 JEITA Cold Temperature Resistance Thresholds Cool to Cold Resistance Cold to Cool Resistance JEITA Cool Temperature Resistance Thresholds Typical to Cool Resistance Cool to Typical Resistance JEITA Typical Temperature Resistance Thresholds Warm to Typical Resistance Typical to Warm Resistance JEITA Warm Temperature Resistance Thresholds Hot to Warm Resistance Warm to Hot Resistance JEITA Hot Temperature Data Sheet Symbol Min Typ Max Unit Test Conditions/Comments VISO_STRK 4.214 4.3 4.386 V −0.28 330 485 %/A mΩ VSYSTEM[2:0] = 000 (binary) = 4.3 V, IISO_S = 100 mA, LDO mode2 IISO_S = 0 m A to 1500 mA IVIN = 500 mA 2.1 3.9 4.0 A V RDS(ON)HV VVIN_OK_RISE VVIN_OK_FALL VVIN_OV ΔVVIN_OV TVIN_RISE TVIN_FALL 3.75 6.7 115 130 140 110 INTC_10k INTC_100k CNTC TNTC_COLD RHOT_FALL RHOT_RISE 3.7 7.2 10 10 TLIM TSDL TSD RCOLD_FALL RCOLD_RISE TNTC_HOT 3.6 6.9 0.1 400 40 100 0 20,500 2750 TJEITA_COLD 25,600 24,400 60 3700 3350 30,720 3950 0 RCOLD_FALL RCOLD_RISE TJEITA_COOL 20,500 RTYP_FALL RTYP_RISE TJEITA_TYP 13,200 RWARM_FALL RWARM_RISE TJEITA_WARM 4260 RHOT_FALL RHOT_RISE TJEITA_HOT 2750 25,600 24,400 10 30,720 16,500 15,900 19,800 5800 5200 45 6140 3700 3350 60 3950 Rev. 0 | Page 4 of 44 VISO_S = 4.3 V, LDO mode V V V µs µs Minimum rise time for VINx from 5 V to 20 V Minimum fall time for VINx from 4 V to 0 V °C °C °C °C TJ rising TJ falling μA μA pF °C No battery charging occurs Ω Ω °C No battery charging occurs Ω Ω °C No battery charging occurs Ω Ω °C Battery charging occurs at 50% of programmed level Ω Ω °C Normal battery charging occurs at default/programmed levels Ω Ω °C Battery termination voltage (VTRM) is reduced by 100 mV Ω Ω °C No battery charging occurs Data Sheet Parameter JEITA2 Li-ION BATTERY CHARGING SPECIFICATION DEFAULTS5 JEITA Cold Temperature Resistance Thresholds Cool to Cold Resistance Cold to Cool Resistance JEITA Cool Temperature Resistance Thresholds Typical to Cool Resistance Cool to Typical Resistance JEITA Typical Temperature Resistance Thresholds Warm to Typical Resistance Typical to Warm Resistance JEITA Warm Temperature Resistance Thresholds Hot to Warm Resistance Warm to Hot Resistance JEITA Hot Temperature BATTERY DETECTION Battery Detection Sink Current Source Current Battery Threshold Low High Battery Detection Timer TIMERS Clock Oscillator Frequency Start Charging Delay Trickle Charge Fast Charge Charge Complete Deglitch Watchdog2 Safety Battery Short2 ILED OUTPUT PINS Voltage Drop over ILED Maximum Operating Voltage over ILED SYS_EN OUTPUT PIN SYS_EN FET On Resistance LOGIC INPUT PIN Maximum Voltage on Digital Inputs Maximum Logic Low Input Voltage Minimum Logic High Input Voltage Pull-Down Resistance ADP5061 Symbol Min TJEITA_COLD Typ Max 0 RCOLD_FALL RCOLD_RISE TJEITA_COOL 20,500 RTYP_FALL RTYP_RISE TJEITA_TYP 13,200 RWARM_FALL RWARM_RISE TJEITA_WARM 4260 RHOT_FALL RHOT_RISE TJEITA_HOT 2750 ISINK ISOURCE 25,600 24,400 10 30,720 16,500 15,900 19,800 Unit Test Conditions/Comments °C No battery charging occurs Ω Ω °C Battery termination voltage (VTRM) is reduced by 100 mV Ω Ω °C 5800 5200 45 6140 3700 3350 60 3950 13 7 20 10 34 13 mA mA VBATL VBATH tBATOK 1.8 1.9 3.4 333 2.0 V V ms fCLK tSTART tTRK tCHG tEND tDG tWD tSAFE tBAT_SHR 2.7 3 1 60 600 7.5 31 32 40 30 3.3 MHz sec min min min ms sec min sec 36 VILED VMAXILED 200 RON_SYS_EN 10 VDIN_MAX VIL VIH 44 5.5 5.5 0.5 1.2 215 350 610 Normal battery charging occurs at default/programmed levels Ω Ω °C Battery termination voltage (VTRM) is reduced by 100 mV Ω Ω °C No battery charging occurs VBAT_SNS = VTRM, ICHG < IEND Applies to VTRK, VRCH, IEND, VDEAD, VVIN_OK mV V IILED = 20 mA Ω ISYS_EN = 20 mA V V V kΩ Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3 Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3 Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3 Applies to DIG_IO1, DIG_IO2, DIG_IO3 Undervoltage lockout generated normally from ISO_Sx or ISO_Bx; in certain transition cases, it can be generated from VINx. These values are programmable via I2C. Values are given with default register values. 3 The output current during charging may be limited by the input current limit or by the isothermal charging mode. 4 During weak charging mode, the charger provides at least 20 mA of charging current via the trickle charge branch to the battery unless trickle charging is disabled. Any residual current, which is not required by the system, is also used to charge the battery. 5 Either JEITA1 (default) or JEITA2 can be selected in I2C, or both JEITA functions can enabled or disabled in I2C. 1 2 Rev. 0 | Page 5 of 44 ADP5061 Data Sheet RECOMMENDED INPUT AND OUTPUT CAPACITANCES Table 2. Parameter CAPACITANCES VINx CBP ISO_Sx ISO_Bx Symbol Min Typ CVIN CBP CISO_S CISO_B 4 6 20 10 10 47 22 Max Unit Test Conditions/Comments 10 14 100 μF nF μF μF Effective capacitance Effective capacitance Effective capacitance Effective capacitance I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS Table 3. Parameter 1 I2C-COMPATIBLE INTERFACE 2 Capacitive Load for Each Bus Line SCL Clock Frequency SCL High Time SCL Low Time Data Setup Time Data Hold Time Setup Time for Repeated Start Hold Time for Start/Repeated Start Bus Free Time Between a Stop and a Start Condition Setup Time for Stop Condition Rise Time of SCL/SDA Fall Time of SCL/SDA Pulse Width of Suppressed Spike 1 2 Symbol CS fSCL tHIGH tLOW tSU, DAT tHD, DAT tSU, STA tHD, STA tBUF tSU, STO tR tF tSP Min 0.6 1.3 100 0 0.6 0.6 1.3 0.6 20 20 0 Typ Max Unit 400 400 pF kHz µs µs ns µs µs µs µs µs ns ns ns 0.9 300 300 50 Test Conditions/Comments Guaranteed by design. A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL (see Figure 2). Timing Diagram SDA tLOW tF tR tSU, DAT tSP tF tBUF tR tHD, STA SCL tHD, DAT tHIGH tBU, STO tBU, STA Sr P S 10544-002 S S = START CONDITION Sr = REPEATED START CONDITION P = STOP CONDITION Figure 2. I2C Timing Diagram Rev. 0 | Page 6 of 44 Data Sheet ADP5061 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Absolute Maximum Ratings θJA is specified for the worst-case conditions, that is, θJA is specified for a device soldered in a circuit board for surfacemount packages. Parameter VIN1, VIN2, VIN3 to AGND All Other Pins to AGND Continuous Drain Current, Battery Supplementary Mode, from ISO_Bx to ISO_Sx Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating –0.5 V to +20 V –0.3 V to +6 V 2.1 A –65°C to +150°C –40°C to +125°C JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Thermal Resistance Package Type 20-Lead WLCSP1 1 θJA 46.8 θJC 0.7 θJB 9.2 Unit °C/W 5 × 4 array, 0.5 mm pitch (2.6 mm × 2.0 mm); based on a JEDEC 2S2P, 4-layer board with 0 m/sec airflow. Maximum Power Dissipation The maximum safe power dissipation in the ADP5061 package is limited by the associated rise in junction temperature (TJ) on the die. At a die temperature of approximately 150°C (the glass transition temperature), the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, thereby permanently shifting the parametric performance of the ADP5061. Exceeding a junction temperature of 175°C for an extended period can result in changes in the silicon devices, potentially causing failure. ESD CAUTION Rev. 0 | Page 7 of 44 ADP5061 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 CORNER 1 2 3 4 ILED SYS_EN SDA SCL AGND THR CBP DIG_IO3 ISO_B3 ISO_S3 VIN3 DIG_IO2 ISO_B2 ISO_S2 VIN2 BAT_SNS ISO_B1 ISO_S1 VIN1 DIG_IO1 A B C D TOP VIEW (BALL SIDE DOWN) Not to Scale 10544-003 E Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. E2, D2, C2 Type 1 I/O A4 A3 E4 Name ISO_S1, ISO_S2, ISO_S3 VIN1, VIN2, VIN3 AGND ISO_B1, ISO_B2, ISO_B3 SCL SDA DIG_IO1 C4 DIG_IO2 GPIO B4 DIG_IO3 GPIO B2 THR I D4 A1 A2 BAT_SNS ILED SYS_EN I O O B3 CBP I/O E3, D3, C3 B1 E1, D1, C1 I/O G I/O I I/O GPIO Description Linear Charger Supply Side Input to the Internal Isolation FET/Battery Current Regulation FET. High current input/output. Power Connections to USB VBUS. These pins are high current inputs when in charging mode. Analog Ground. Battery Supply Side Input to Internal Isolation FET/Battery Current Regulation FET. I2C-Compatible Interface Serial Clock. I2C-Compatible Interface Serial Data. Set Input Current Limit. This pin sets the input current limit directly. When DIG_IO1 = low or high-Z, the input limit is 100 mA. When DIG_IO1 = high, the input limit is 500 mA. 2, 3 Disable IC1. This pin sets the charger to the low current mode. When DIG_IO2 = low or high-Z, the charger operates in normal mode. When DIG_IO2 = high, the LDO and the charger are disabled and VINx current consumption is 280 µA (typical). 20 V VINx input protection is disabled and VINx voltage level must be equal to or lower than 5.5 V.2, 3 Enable Charging. When DIG_IO3 = low or high-Z, charging is disabled. When DIG_IO3 = high, charging is enabled.2, 3 Battery Pack Thermistor Connection. If this pin is not used, connect a dummy 10 kΩ resistor from THR to GND. Battery Voltage Sense Pin. Open-Drain Output to Indicator LED. System Enable. This is the battery OK flag/open-drain pull-down FET pin to enable the system when the battery level reaches the VWEAK level. Bypass Capacitor Input. I is input, O is output, I/O is input/output, G is ground, and GPIO is factory programmable general-purpose input/output. See the Digital Input and Output Options section for details. 3 DIG_IOx setting defines the initial state of the ADP5061. When the parameter or the mode that is related to each DIG_IOx pin setting is changed (by programming the equivalent I2C register bit or bits), the I2C register setting dominates over the DIG_IOx pin setting. VINx connection or disconnection resets control to the DIG_IOx pin. 1 2 Rev. 0 | Page 8 of 44 Data Sheet ADP5061 TYPICAL PERFORMANCE CHARACTERISTICS 5.05 4.34 5.04 4.33 5.03 4.32 4.31 4.30 4.29 4.28 5.01 5.00 4.99 4.98 4.27 4.97 4.26 4.96 4.25 0.01 0.1 1 SYSTEM OUTPUT CURRENT (A) 4.95 0.01 4.4 Figure 7. System Voltage vs. System Output Current, LDO Mode, VVIN = 6.0 V, VSYSTEM[2:0] = 111 (Binary) = 5.0 V 5.4 LOAD = 100mA LOAD = 500mA LOAD = 1000mA 5.2 4.3 SYSTEM VOLTAGE (V) 4.1 4.0 3.9 3.8 4.8 4.6 4.4 4.2 4.0 3.7 3.8 3.6 3.6 4.8 5.2 5.6 6.0 6.4 3.4 4.0 10544-005 4.4 6.8 INPUT VOLTAGE (V) 4.4 4.8 5.2 5.6 6.0 6.4 6.8 INPUT VOLTAGE (V) Figure 5. Output Voltage vs. Input Voltage (In Dropout), LDO Mode, VSYSTEM[2:0] = 000 (Binary) = 4.3 V Figure 8. Output Voltage vs. Input Voltage (In Dropout), LDO Mode, VSYSTEM[2:0] = 111 (Binary) = 5.0 V 1000 700 900 600 700 CHARGE CURRENT (mA) 800 LIMIT = 900mA LIMIT = 500mA LIMIT = 100mA 600 500 400 300 WEAK CHARGE 500 FAST CHARGE 400 300 200 200 TRICKLE CHARGE 100 0 2.7 3.2 3.7 4.2 BATTERY VOLTAGE (V) Figure 6. Input Current-Limited Charge Current vs. Battery Voltage 0 2.3 2.8 3.3 BATTERY VOLTAGE (V) 3.8 4.3 10544-009 100 10544-006 CHARGE CURRENT (mA) LOAD = 100mA LOAD = 500mA LOAD = 1000mA 5.0 4.2 3.5 4.0 1 10544-008 4.5 0.1 SYSTEM OUTPUT CURRENT (A) Figure 4. System Voltage vs. System Output Current, LDO Mode, VSYSTEM[2:0] = 000 (Binary) = 4.3 V SYSTEM VOLTAGE (V) 5.02 10544-007 SYSTEM VOLTAGE (V) 4.35 10544-004 SYSTEM VOLTAGE (V) VVIN = 5.0 V, CVIN = 10 µF, CISO_S = 44 µF, CISO_B = 22 µF, CBP = 10 nF, all registers at default values, unless otherwise noted. Figure 9. Battery Charge Current vs. Battery Voltage, ICHG[4:0] = 01001 (Binary) = 500 mA, ILIM[3:0] = 1111 (Binary) = 2100 mA Rev. 0 | Page 9 of 44 Data Sheet 40 40 38 38 ISOLATION FET RESISTANCE (mΩ) 36 34 32 30 28 26 24 36 34 32 30 28 26 24 3.7 4.2 BATTERY VOLTAGE (V) 20 4.4 BATTERY VOLTAGE (A) 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 INPUT VOLTAGE (V) Figure 11. VINx Current vs. VINx Voltage 8 10544-011 VINx CURRENT (mA) 3.0 1.0 1.5 2.0 Figure 12. Ideal Diode RON vs. Load Current, VISO_B = 3.6 V DEFAULT STARTUP DIS_LDO = HIGH DIS_IC1 = HIGH 3.5 0.5 LOAD CURRENT (A) Figure 10. Ideal Diode RON vs. Battery Voltage, IISO_S = 500 mA, VINx Open 4.0 0 0.7 VBAT_SNS IISO_B 4.2 0.6 4.0 0.5 3.8 0.4 3.6 0.3 3.4 0.2 3.2 0.1 3.0 CHARGE CURRENT (A) 3.2 10544-010 20 2.7 10544-012 22 22 0 0 50 100 150 CHARGE TIME (min) Figure 13. Charge Profile, ILIM[3:0] = 0110 (Binary) = 500 mA, Battery Capacity = 925 mAh Rev. 0 | Page 10 of 44 10544-013 ISOLATION FET RESISTANCE (mΩ) ADP5061 Data Sheet ADP5061 TEMPERATURE CHARACTERISTICS 1.5 0.5 VISO_B = 3.6V VISO_B = 4.2V VISO_B = 5.5V 1.3 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.2 0.1 0 –0.1 –0.2 –0.3 –15 10 35 60 85 AMBIENT TEMPERATURE (°C) –0.5 –40 10544-014 0 –40 5 20 35 50 65 80 95 110 125 Figure 17. System Voltage vs. Temperature, Trickle Charge Mode, VISO_S = 4.3 V and VINx = 5.0 V, or VISO_S = 5.0 V and VINx = 6.0 V 5.0 VIN = 4.0V VIN = 5.0V VIN = 5.5V VIN = 4.0V VIN = 5.0V VIN = 6.7V 4.5 VINx QUIESCENT CURRENT (mA) 0.45 –10 AMBIENT TEMPERATURE (°C) Figure 14. Battery Leakage Current vs. Ambient Temperature 0.50 –25 10544-017 –0.4 0.1 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 –25 –10 5 20 35 50 65 80 95 110 125 AMBIENT TEMPERATURE (°C) 0 –40 10544-015 0 –40 Figure 15. VINx Quiescent Current vs. Ambient Temperature, DIS_IC1 = High 0.5 VTRM VOLTAGE ACCURACY (%) 0.1 0 –0.1 –0.2 –0.3 20 35 50 65 80 95 110 125 VTRM = 3.8V VTRM = 4.2V VTRM = 4.5V 0.4 0.2 5 Figure 18. VINx Quiescent Current vs. Ambient Temperature, LDO Mode VISO_S = 4.3V VISO_S = 5.0V 0.3 –10 AMBIENT TEMPERATURE (°C) 0.5 0.4 –25 10544-018 VINx QUIESCENT CURRENT (mA) 0.3 –0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.5 –40 –25 –10 5 20 35 50 65 80 95 110 AMBIENT TEMPERATURE (°C) 125 10544-016 –0.4 Figure 16. LDO Mode Voltage vs. Ambient Temperature, Load = 100 mA, VVIN = 5.5 V –0.5 –40 –25 –10 5 20 35 50 65 80 95 110 125 AMBIENT TEMPERATURE (°C) Figure 19. Termination Voltage vs. Ambient Temperature Rev. 0 | Page 11 of 44 10544-019 STANDBY CURRENT (µA) 1.2 SYSTEM VOLTAGE ACCURACY (%) VISO_S = 4.3V VISO_S = 5.0V 0.4 SYSTEM VOLTAGE ACCURACY (%) 1.4 Data Sheet 1.4 1.3 ICHG = 1300mA INPUT CURRENT LIMIT (A) CHARGE CURRENT (A) 1.2 1.1 1.0 0.9 0.8 0.7 ICHG = 750mA 0.6 ICHG = 500mA 0.4 –40 –15 10 35 60 85 110 AMBIENT TEMPERATURE (°C) 10544-020 0.5 6.95 6.90 6.85 –10 5 20 35 50 65 80 95 110 125 AMBIENT TEMPERATURE (°C) 10544-021 VIN OVERVOLTAGE THRESHOLD (V) 7.00 –25 20 35 50 65 80 95 110 AMBIENT TEMPERATURE (°C) Figure 22. Input Current Limit vs. Ambient Temperature Figure 20. Fast Charge CC Mode Current vs. Ambient Temperature 6.80 –40 1.6 1.5 ILIM = 1500mA 1.4 1.3 1.2 1.1 1.0 0.9 ILIM = 900mA 0.8 0.7 0.6 0.5 ILIM = 500mA 0.4 0.3 0.2 ILIM = 100mA 0.1 0 –40 –25 –10 5 Figure 21. VINx Overvoltage Threshold vs. Ambient Temperature Rev. 0 | Page 12 of 44 125 10544-022 ADP5061 Data Sheet ADP5061 TYPICAL WAVEFORMS VISO_S VISO_S VVIN VVIN IISO_B IISO_B 10544-026 10544-023 IVIN IVIN Figure 23. Charging Startup, VVIN = 5.0 V, ILIM[3:0] = 0110 (Binary) = 500 mA, ICHG[4:0] = 01110 (Binary) = 750 mA Figure 26. VBUS Disconnect VISO_S IISO_B VISO_S 10544-024 IISO_S Figure 24. Load Transient, IISO_Sx Load = 300 mA to 1500 mA to 300 mA 10544-027 IISO_S Figure 27. Load Transient. IISO_Sx Load = 300 mA to 1500 mA to 300 mA, EN_CHG = High, ILIM[3:0] = 0110 (Binary) = 500 mA VISO_S VVIN VISO_B IISO_B 10544-028 10544-025 IVIN IISO_B Figure 25. Input Current-Limit Transition from 100 mA to 900 mA, ISO_Sx Load = 66 Ω, Charging = 750 mA Figure 28. Battery Detection Waveform, VSYSTEM[2:0] = 000 (Binary) = 4.3 V, No Battery Rev. 0 | Page 13 of 44 ADP5061 Data Sheet THEORY OF OPERATION SUMMARY OF OPERATION MODES Table 7. Summary of the ADP5061 Operation Modes Battery Condition Any battery condition Trickle Charge Off LDO FET State Off Battery Isolation FET On/Off 5V 5V Any battery condition Any battery condition Off Off Off Off On On System Voltage ISO_Sx Battery voltage or 0 V Battery voltage Battery voltage 5V Any battery condition Off Off Off 0V 5V Any battery condition Off LDO Off 5.0 V Trickle Charge Mode 5V Battery < VTRK_DEAD On LDO Off 5.0 V Weak Charge Mode 5V VTRK_DEAD ≤ battery < VWEAK On CHG CHG 3.8 V Fast Charge Mode 5V Battery ≥ VWEAK Off CHG CHG 3.8 V (min) Charge Mode, No Battery 5V Open Off LDO Off 5.0 V Charge Mode, Battery (ISO_Bx) Short 5V Short On LDO Off 5.0 V Mode Name IC Off, Standby IC Off, Suspend LDO Mode Off, Isolation FET On LDO Mode Off, Isolation FET Off (System Off) LDO Mode, Charger Off 1 VINx Condition 0V Additional Conditions1 Disable IC1 Disable IC1 Disable LDO and enable isolation FET Enable battery charging Enable battery charging Enable battery charging Enable battery charging Enable battery charging Enable battery charging Enable battery charging See Table 8 for details. Table 8. Operation Mode Controls Pin Configuration Enable Battery Charging DIG_IOx DIG_IO3 Equivalent I2C Address, Data 0x07, D0 Disable IC1 DIG_IO2 0x07, D6 Disable LDO and Enable Isolation FET 1 0x07, D3, D0 Description Low = all charging modes disabled (fast, weak, trickle). High = all charging modes enabled (fast, weak, trickle). VINx 1 Supply Disable IC1 LDO_FET ISO_FET Connected Low No Off On Yes CHG CHG High No Off On Yes Off On Low = LDO enabled. High = LDO disabled. In addition, when EN_CHG = low, the battery isolation FET is on; when EN_CHG = high, the battery isolation FET is off. When disable IC1 mode is active and the VINx supply is connected, the supply voltage level must fulfill the following condition: VISO_B < VIN < 5.5 V. Rev. 0 | Page 14 of 44 Data Sheet ADP5061 INTRODUCTION The ADP5061 is a fully programmable I2C charger for single cell lithium-ion or lithium-polymer batteries suitable for a wide range of portable applications. The linear charger architecture enables up to 2.1 A output current at 4.3 V to 5.0 V (I2C programmable) on the system power supply, and up to 1.3 A charge current into the battery from a dedicated charger. The ADP5061 operates from an input voltage of 4 V up to 6.7 V but is tolerant of voltages of up to 20 V. The 20 V voltage tolerance alleviates the concerns of the USB bus spiking during disconnection or connection scenarios. The ADP5061 features an internal FET between the linear charger output and the battery. This feature permits battery isolation and, hence, system powering under a dead battery or no battery scenario, which allows for immediate system function upon connection to a USB power supply. The ADP5061 is fully compliant with USB 3.0 and the USB Battery Charging Specification 1.2. The ADP5061 is chargeable via the mini USB VBUS pin from a wall charger, car charger, or USB host port. Based on the type of USB source, which is detected by an external USB detection device, the ADP5061 can be set to apply the correct current limit for optimal charging and USB compliance. The USB charger permits correct operation under all USB-compliant sources such as wall chargers, host chargers, hub chargers, and standard host and hubs. A processor can control the USB charger using the I2C to program the charging current and numerous other parameters, including • • • • • • • • • • • • Rev. 0 | Page 15 of 44 Trickle charge current level Trickle charge voltage threshold Weak charge (constant current) current level Fast charge (constant current) current level Fast charge (constant voltage) voltage level at 1% accuracy Fast charge safety timer period Watchdog safety timer parameters Weak battery threshold detection Charge complete threshold Recharge threshold Charge enable/disable Battery pack temperature detection and automatic charger shutdown ADP5061 Data Sheet E3 TO USB VBUS OR WALL ADAPTER D3 C3 VIN1 ISO_S1 HIGH VOLTAGE BLOCKING LDO-FET ISO_S2 VIN2 VIN3 ISO_S3 + 6.85V + LDO-FET CONTROL – VIN LIMIT D3 TO SYSTEM LOAD E3 C3 – VIN OVERVOLTAGE CBP BATTERY ISOLATION FET B3 TRICKLE CURRENT SOURCE + 3.9V – 3MHz OSC ISO_B1 + VIN GOOD – A4 A3 C4 B4 ISO_B2 D1 SCL CHARGE CONTROL DIG_IO1 DIG_IO2 ISO_B3 + SDA – E4 EOC E1 I2C INTERFACE AND CONTROL LOGIC C1 CV-MODE RECHARGE + – DIG_IO3 WEAK BATTERY DETECTION SINK + – BATTERY: OPEN SHORT + TRICKLE BAT_SNS D4 3.4V – 1.9V BATTERY DETECTION – SYS_EN + A2 SYS_EN OUTPUT LOGIC + – VIN – 150mV BATTERY OVERVOLTAGE TSD 140°C WARNING 130°C ISOTHERMAL 115°C TSD DOWN 110°C WARM NTC CURRENT CONTROL HOT THR 0.5V B2 NTC THERMAL CONTROL AGND B1 SINGLE CELL Li-Ion Figure 29. Block Diagram Rev. 0 | Page 16 of 44 10544-029 ILED OUTPUT LOGIC COLD COOL – ILED + A1 Data Sheet ADP5061 The ADP5061 includes a number of significant features to optimize charging and functionality including Table 9. DIG_IO1 Operation Thermal regulation for maximum performance USB host current-limit accuracy: ±5%. Termination voltage accuracy: ±1%. Battery thermistor input with automatic charger shutdown in the event that the battery temperature exceeds limits (compliant with the JEITA Li-Ion battery charging temperature specification). Three external pins (DIG_IO1, DIG_IO2, and DIG_IO3) that directly control a number of parameters. These pins are factory programmable for maximum flexibility. They can be factory programmed for functions such as Enable/disable charging. Control of 100 mA or 500 mA input current limit. Control of 1500 mA input current limit. Control of the battery charge current. Interrupt output pin. See the Digital Input and Output Options section for details. CHARGER MODES Input Current Limit The VINx input current limit is controlled via the internal I2C ILIM bits. The input current limit can also be controlled via the DIG_IO1 pin (if factory programmed to do so) as outlined in Table 9. Any change in the I2C default from 100 mA dominates over the pin setting. DIG_IO1 0 1 Function 100 mA input current limit or I2C programmed value 500 mA input current limit or I2C programmed value (or reprogrammed I2C value from 100 mA default) USB Compatibility The ADP5061 features an I2C programmable input current limit to ensure compatibility with the requirements listed in Table 10. The current limit defaults to 100 mA to allow compatibility with a USB host or hub that is not configured. The I2C register default is 100 mA. An I2C write command to the ILIM bits override the DIG_IOx pins, and the I2C register default value can be reprogrammed for alternative requirements. When the input current-limit feature is used, the available input current may be too low for the charger to meet the programmed charging current, ICHG, thereby reducing the rate of charge and setting the VIN_ILIM flag. When connecting voltage to VINx without the proper voltage level on the battery side, the high voltage blocking mechanism is in a state wherein it draws only the current of <1 mA until VIN reaches the VIN_OK level. The ADP5061 charger provides support for the following connections through the single connector VINx pin (see Table 10). Table 10. Input Current Compatibility with Standard USB Limits Mode USB (China Only) USB 2.0 USB 3.0 Dedicated Charger Standard USB Limit 100 mA limit for standard USB host or hub 300 mA limit for Chinese USB specification 100 mA limit for standard USB host or hub 500 mA limit for standard USB host or hub 150 mA limit for superspeed USB 3.0 host or hub 900 mA limit for superspeed, high speed USB host or hub charger 1500 mA limit for dedicated charger or low/full speed USB host or hub charger Rev. 0 | Page 17 of 44 ADP5061 Function 100 mA input current limit or I2C programmed value 300 mA input current limit or I2C programmed value 100 mA input current limit or I2C programmed value 500 mA input current limit or I2C programmed value 150 mA input current limit or I2C programmed value 900 mA input current limit or I2C programmed value 1500 mA input current limit or I2C programmed value ADP5061 Data Sheet Trickle Charge Mode Fast Charge Mode (Constant Current) A deeply discharged Li-Ion cell can exhibit a very low cell voltage, making it unsafe to charge the cell at high current rates. The ADP5061 charger uses a trickle charge mode to reset the battery pack protection circuit and lift the cell voltage to a safe level for fast charging. A cell with a voltage below VTRK_DEAD is charged with the trickle mode current, ITRK_DEAD. During trickle charging mode, the CHARGER_STATUS bits are set. When the battery voltage exceeds VTRK_DEAD and VWEAK, the charger switches to fast charge mode, charging the battery with the constant current, ICHG. During fast charge mode (constant current), the CHARGER_STATUS bits are set to 010. During trickle charging, the ISO_Sx node is regulated to VISO_STRK by the LDO and the battery isolation FET is off, which means that the battery is isolated from the system power supply. During constant current mode, other features may prevent the current, ICHG, from reaching its full programmed value. Isothermal charging mode or input current limiting for USB compatibility can affect the value of ICHG under certain operating conditions. The voltage on ISO_Sx is regulated to stay at VISO_SFC by the battery isolation FET when VISO_B < VISO_SFC. Trickle Charge Mode Timer Fast Charge Mode (Constant Voltage) The duration of trickle charge mode is monitored to ensure that the battery is revived from its deeply discharged state. If trickle charge mode runs for longer than 60 minutes without the cell voltage reaching VTRK_DEAD, a fault condition is assumed and charging stops. The fault condition is asserted on the CHARGER_STATUS bits, allowing the user to initiate the fault recovery procedure specified in the Fault Recovery section. As the battery charges, its voltage rises and approaches the termination voltage, VTRM. The ADP5061 charger monitors the voltage on the BAT_SNS pin to determine when charging should end. However, the internal ESR of the battery pack, combined with the printed circuit board (PCB) and other parasitic series resistances creates a voltage drop between the sense point at the BAT_SNS pin and the cell terminal. To compensate for this and ensure a fully charged cell, the ADP5061 enters a constant voltage charging mode when the termination voltage is detected on the BAT_SNS pin. The ADP5061 reduces charge current gradually as the cell continues to charge, maintaining a voltage of VTRM on the BAT_SNS pin. During fast charge mode (constant voltage), the CHARGER_ STATUS register is set. Weak Charge Mode (Constant Current) When the battery voltage exceeds VTRK_DEAD but is less than VWEAK, the charger switches to intermediate charge mode. During the weak charge mode, the battery voltage is too low to allow the full system to power-up. Because of the low battery level, the USB transceiver cannot be powered and, therefore, cannot enumerate for more current from a USB host. Consequently, the USB limit remains at 100 mA. The system microcontroller may or may not be powered by the charger output voltage (VISO_SFC), depending upon the amount of current required by the microcontroller and/or the system architecture. When the ISO_Sx pins power the microcontroller, the battery charge current (ICHG_WEAK) cannot be increased above 20 mA to ensure the microcontroller operation (if doing so), nor can ICHG_WEAK be increased above the 100 mA USB limit. Thus, set the battery charging current as follows: • • Set the default 20 mA via the linear trickle charger branch (to ensure that the microprocessor remains alive if powered by the main charger output, ISO_Sx). Any residual current on the main charger output, ISO_Sx, is used to charge the battery. During weak current mode, other features may prevent the weak charging current from reaching its full programmed value. Isothermal charging mode or input current limiting for USB compatibility can affect the programmed weak charging current value under certain operating conditions. During weak charging, the ISO_Sx node is regulated to VISO_SFC by the battery isolation FET. Fast Charge Mode Timer The duration of fast charge mode is monitored to ensure that the battery is charging correctly. If the fast charge mode runs for longer than tCHG without the voltage at the BAT_SNS pin reaching VTRM, a fault condition is assumed and charging stops. The fault condition is asserted on the CHARGER_STATUS bits allowing the user to initiate the fault recovery procedure as specified in the Fault Recovery section. If the fast charge mode runs for longer than tCHG, and VTRM has been reached on the BAT_SNS pin but the charge current has not yet fallen below IEND, charging stops. No fault condition is asserted in this circumstance and charging resumes as normal if the recharge threshold is breached. Watchdog Timer The ADP5061 charger features a programmable watchdog timer function to ensure charging is under the control of the processor. The watchdog timer starts running when the ADP5061 charger determines that the processor should be operational, that is, when the processor sets the RESET_WD bit for the first time or when the battery voltage is greater than the weak battery threshold, VWEAK. When the watchdog timer has been triggered, it must be reset regularly within the watchdog timer period, tWD. While in charger mode, if the watchdog timer expires without being reset, the ADP5061 charger assumes that there is a software problem and triggers the safety timer, tSAFE. For more information, see the Safety Timer section. Rev. 0 | Page 18 of 44 Data Sheet ADP5061 Safety Timer Battery Voltage Limit to Prevent Charging While in charger mode, if the watchdog timer expires, the ADP5061 charger initiates the safety timer, tSAFE (see the Watchdog Timer section). If the processor has programmed charging parameters by the time the charger initiates the safety timer, the ILIM is set to the default value. Charging continues for a period of tSAFE, and then the charger switches off and sets the CHARGER_STATUS bits. The battery monitor of the ADP5061 charger can be configured to monitor battery voltage and prevent charging when the battery voltage is higher than VCHG_VLIM (typically 3.7 V) during charging start-up (enabled by EN_CHG or DIG_IO3). This function can prevent unnecessary charging of a half discharged battery and, as such, can extend the lifetime of the Li-Ion battery cell. Charging starts automatically when the battery voltage drops below VCHG_VLIM and continues through full charge cycle until the battery voltage reaches VTRM (typically 4.2 V). Charge Complete The ADP5061 charger monitors the charging current while in constant voltage fast charge mode. If the current falls below IEND and remains below IEND for tEND, charging stops and the CHDONE flag is set. If the charging current falls below IEND for less than tEND and then rises above IEND again, the tEND timer resets. Recharge After the detection of charge complete, and the cessation of charging, the ADP5061 charger monitors the BAT_SNS pin as the battery discharges through normal use. If the BAT_SNS pin voltage falls to VRCH, the charger reactivates charging. Under most circumstances, triggering the recharge threshold results in the charger starting directly into fast charge constant voltage mode. The recharge function can be disabled in I2C, but a status bit (Register 0x0C, Bit D3) informs the system that a recharge cycle is required. IC Enable/Disable The ADP5061 IC can be disabled by the DIG_IO2 digital input pin (if factory programmed to do so) or by the I2C registers. All internal control circuits are disabled when the IC is disabled. Disabling the IC1 option can also control the states of the LDO FET and the battery isolation FET. It is critical to note that during the disable IC1 mode, a high voltage at VINx passes to the internal supply voltage because all of the internal control circuits are disabled. The VINx supply voltage must fulfill the following condition: VISO_B < VINx < 5.5 V Battery Charging Enable/Disable The ADP5061 charging function can be disabled by setting the I2C EN_CHG bit to low. The LDO to the system still operates under this circumstance and can be set in I2C to the default or I2C programmed system voltage from 4.3 V to 5.0 V (see the relevant I2C register description for full details). The ADP5061 charging function can also be controlled via one of the external DIG_IOx pins (if factory programmed to do so). Any change in the I2C EN_CHG bit takes precedence over the pin setting. By default, the charging voltage limit is disabled and it can be enabled from I2C Register 0x08, Bit EN_CHG_VLIM. SYS_EN Output The ADP5061 features a SYS_EN open-drain FET to enable the system until the battery is at the minimum required level for guaranteed system start-up. When there are minimum battery voltage and/or minimum battery charge level requirements, the operation of SYS_EN can be set by I2C programming. The SYS_EN operation can be factory programmed to four different operating conditions as described in Table 11. Table 11. SYS_EN Mode Descriptions SYS_EN Mode Description Selection SYS_EN is activated when LDO is active and 00 system voltage is available. SYS_EN is activated by the ISO_Bx voltage, 01 battery charging mode. 10 11 SYS_EN is activated and the isolation FET is disabled when the battery drops below VWEAK. This option is active, when VINx = 0 V and the battery monitor is activated from Register 0x07, Bit D5 (EN_BMON). SYS_EN is active in LDO mode when the charger is disabled. SYS_EN is active in charging mode when ISO_Bx ≥ VWEAK. Indicator LED Output (ILED) The ILED is an open-drain output for indicator LED connection. Optionally, the ILED output can be used as a status output for a microcontroller. Indicator LED modes are shown in Table 12. Table 12. Indicator LED Operation Modes ADP5061 Mode IC Off LDO Mode Off LDO Mode On Charge Mode Timer Error (tTRK, tCHG, tSAFE) Overtemperature (TSD) Rev. 0 | Page 19 of 44 ILED Mode Off Off Off Continuously on Blinking Blinking On/Off Time 167 ms/833 ms 1 sec/1 sec ADP5061 Data Sheet THERMAL MANAGEMENT BATTERY ISOLATION FET Isothermal Charging The ADP5061 charger features an integrated battery isolation FET for power path control. The battery isolation FET isolates a deeply discharged Li-Ion cell from the system power supply in both trickle and fast charge modes, thereby allowing the system to be powered at all times. The ADP5061 includes a thermal feedback loop that limits the charge current when the die temperature exceeds TLIM (typically 115°C). As the on-chip power dissipation and die temperature increase, the charge current is automatically reduced to maintain the die temperature within the recommended range. As the die temperature decreases due to lower on-chip power dissipation or ambient temperature, the charge current returns to the programmed level. During isothermal charging, the THERM_LIM I2C flag is set to high. This thermal feedback control loop allows the user to set the programmed charge current based on typical rather than worst case conditions. The ADP5061 does not include a thermal feedback loop to limit ISO_Sx load current in LDO mode. If the power dissipated on chip during LDO mode causes the die temperature to exceed 130°C, an interrupt is generated. If the die temperature continues to rise beyond 140°C, the device enters into thermal shutdown. Thermal Shutdown and Thermal Early Warning The ADP5061 charger features a thermal shutdown threshold detector. If the die temperature exceeds TSD, the ADP5061 charger is disabled, and the TSD 140°C bit is set. The ADP5061 charger can be reenabled when the die temperature drops below the TSD falling limit and the TSD 140°C bit is reset. To reset the TSD 140°C bit, write to the I2C Fault Register 0x0D or cycle the power. Before die temperature reaches TSD, the early warning bit is set if TSDL is exceeded. This allows the system to accommodate power consumption before thermal shutdown occurs. Fault Recovery Before performing the following operation, it is important to ensure that the cause of the fault has been rectified. To recover from a charger fault (when the CHARGER_STATUS = 110), cycle power on VINx or write high to reset the I2C fault bits in the fault register. When VINx is below VVIN_OK, the battery isolation FET is in full conducting mode. The battery isolation FET is off during trickle charge mode. When the battery voltage exceeds VTRK, the battery isolation FET switches to the system voltage regulation mode. During system voltage regulation mode, the battery isolation FET maintains the VISO_SFC voltage on the ISO_Sx pins. When the battery voltage exceeds VISO_SFC, the battery isolation FET is in full conducting mode. The battery isolation FET supplements the battery to support high current functions on the system power supply. When voltage on ISO_Sx drops below ISO_Bx, the battery isolation FET enters into full conducting mode. When voltage on ISO_Sx rises above ISO_Bx, the isolation FET enters regulating mode or full conduction mode, depending on the Li-Ion cell voltage and the linear charger mode. BATTERY DETECTION Battery Voltage Level Detection The ADP5061 charger features a battery detection mechanism to detect an absent battery. The charger actively sinks and sources current into the ISO_Bx/BAT_SNS node, and voltage vs. time is detected. The sink phase is used to detect a charged battery, whereas the source phase is used to detect a discharged battery. The sink phase (see Figure 30) sinks ISINK current from the ISO_Bx/ BAT_SNS pins for a time period, tBATOK. If the BAT_SNS pin is below VBATL when the tBATOK timer expires, the charger assumes no battery is present, and starts the source phase. If the BAT_SNS exceeds the VBATL voltage when the tBATOK timer expires, the charger assumes the battery is present and begins a new charge cycle. The source phase sources ISOURCE current to ISO_Bx and the BAT_SNS pin for a time period, tBATOK. If BAT_SNS pin exceeds VBATH before the tBATOK timer expires, the charger assumes that no battery is present. If the BAT_SNS does not exceed the VBATH voltage when the tBATOK timer expires, the charger assumes that a battery is present and begins a new charge cycle. Rev. 0 | Page 20 of 44 Data Sheet ADP5061 SOURCE PHASE SINK PHASE VBATL VBATH ISOURCE LOGIC STATUS tBAT_OK LOGIC STATUS tBAT_OK OPEN OR SHORT OPEN ISO_Bx 10544-030 OPEN OPEN ISINK ISO_Bx Figure 30. Sink Phase ISO_Bx SHORT OR LOW BATTERY tBAT_SHR SHORT ISO_Bx 10544-031 tBAT_OK LOGIC STATUS SHORT OPEN OR SHORT SHORT SHORT ISINK tBAT_OK LOGIC STATUS ISOURCE LOGIC STATUS ISO_Bx TRICKLE CHARGE VBAT_SHR SOURCE PHASE VBATH VBATL ITRK_DEAD SINK PHASE Figure 31. Trickle Charge Battery (ISO_Bx) Short Detection A battery short occurs under a damaged battery condition or when the battery protection circuitry is enabled. On commencing trickle charging, the ADP5061 charger monitors the battery voltage. If this battery voltage does not exceed VBAT_SHR within the specified timeout period, tBAT_SHR, a fault is declared and the charger is stopped by turning the battery isolation FET off, but the system voltage is maintained at VISO_STRK by the linear regulator. The battery pack temperature sensing can be controlled by I2C, using the conditions shown in Table 13. Note that the I2C register default setting for EN_THR (Register 0x07) is 0 = temperature sensing off. Table 13. THR Input Function Conditions VINx Open or VIN = 0 V to 4.0 V Open or VIN = 0 V to 4.0 V 4.0 V to 6.7 V VISO_B <2.5 V >2.5 V Don't care THR Function Off Off, controlled by I2C Always on After source phase, if the ISO_Bx or BAT_SNS level remains below VBATH, either the battery voltage is low or the battery node can be shorted. Because the battery voltage is low, trickle charging mode is initiated (see Figure 31). If the BAT_SNS level remains below VBAT_SHR after tBAT_SHR has elapsed, the ADP5061 assumes that the battery node is shorted. If the battery pack thermistor is not connected directly to the THR pin, a 10 kΩ (tolerance ±20%) dummy resistor must be connected between the THR input and GND. Leaving the THR pin open results in a false detection of the battery temperature being <0°C and charging is disabled. The trickle charge branch is active during the battery short scenario, and trickle charge current to the battery is maintained until the 60-minute trickle charge mode timer expires. The ADP5061 charger monitors the voltage in the THR pin and suspends charging if the current is outside the range of less than 0°C or greater than 60°C. BATTERY PACK TEMPERATURE SENSING The ADP5061 charger is designed for use with an NTC thermistor in the battery pack with a nominal room temperature value of either 10 kΩ at 25°C or 100 kΩ at 25°C, which is selected by factory programming. Battery Thermistor Input The ADP5061 charger features battery pack temperature sensing that precludes charging when the battery pack temperature is outside the specified range. The THR pin provides an on and off switching current source that should be connected directly to the battery pack thermistor terminal. The activation interval of the THR current source is 167 ms. The ADP5061 charger is designed for use with an NTC thermistor in the battery pack with a temperature coefficient curve (beta). Factory programming supports eight beta values covering a range from 3150 to 4400 (see Table 44). Rev. 0 | Page 21 of 44 ADP5061 Data Sheet JEITA Li-Ion Battery Temperature Charging Specification I2C. Alternatively, the JEITA1 or JEITA2 can be set as enabled to default by factory programming. The ADP5061 is compliant with the JEITA1 and JEITA2 Li-Ion battery charging temperature specifications as outlined in Table 14 and in Table 16, respectively. When the ADP5061 identifies a hot or cold battery condition, the ADP5061 takes the following actions: JEITA function can be enabled via the I2C interface and, optionally, the JEITA1 or JEITA2 function can be selected in • • Stops charging the battery. Connects or enables the battery isolation FET such that the ADP5061 continues in LDO mode. Table 14. JEITA1 Specifications Parameter JEITA1 Cold Temperature Limits JEITA1 Cool Temperature Limits Symbol IJEITA_COLD IJEITA_COOL JEITA1 Typical Temperature Limits JEITA1 Warm Temperature Limits JEITA1 Hot Temperature Limits IJEITA_TYP IJEITA_WARM IJEITA_HOT Conditions No battery charging occurs Battery charging occurs at approximately 50% of programmed level— see Table 15 for specific charging current reduction levels Normal battery charging occurs at default/programmed levels Min 0 Max 0 10 Unit °C °C 10 45 °C Battery termination voltage (VTRM) is reduced by 100 mV from programmed value No battery charging occurs 45 60 °C 60 °C Table 15. JEITA1 Reduced Charge Current Levels, Battery Cool Temperature ICHG[4:0] (Default) 00000 = 50 mA 00001 = 100 mA 00010 = 150 mA 00011 = 200 mA 00100 = 250 mA 00101 = 300 mA 00110 = 350 mA 00111 = 400 mA 01000 = 450 mA 01001 = 500 mA 01010 = 550 mA 01011 = 600 mA ICHG JEITA1 50 mA 50 mA 50 mA 100 mA 100 mA 150 mA 150 mA 200 mA 200 mA 250 mA 250 mA 300 mA ICHG[4:0] (Default) 01100 = 650 mA 01101 = 700 mA 01110 = 750 mA 01111 = 800 mA 10000 = 850 mA 10001 = 900 mA 10010 = 950 mA 10011 = 1000 mA 10100 = 1050 mA 10101 = 1100 mA 10110 = 1200 mA 10111 = 1300 mA ICHG JEITA1 300 mA 350 mA 350 mA 400 mA 400 mA 450 mA 450 mA 500 mA 500 mA 550 mA 600 mA 650 mA Table 16. JEITA2 Specifications Parameter JEITA2 Cold Temperature Limits JEITA2 Cool Temperature Limits JEITA2 Typical Temperature Limits JEITA2 Warm Temperature Limits JEITA2 Hot Temperature Limits Symbol IJEITA_COLD Conditions No battery charging occurs Min Max 0 Unit °C IJEITA_COOL Battery termination voltage (VTRM) is reduced by 100 mV from programmed value Normal battery charging occurs at default/programmed levels 0 10 °C 10 45 °C Battery termination voltage (VTRM) is reduced by 100 mV from programmed value No battery charging occurs 45 60 °C IJEITA_TYP IJEITA_WARM IJEITA_HOT Rev. 0 | Page 22 of 44 60 °C Data Sheet ADP5061 POWER-ON RESET RESET ALL REGISTERS NO NO IC OFF VINOK SYSTEM OFF YES ENABLE CHARGER NO ENABLE LDO YES ENABLE CHARGER LDO MODE NO YES LOW BATTERY CHG YES VBAT_SNS < VCHG_VLIM NO YES NO TO CHARGING-MODE Figure 32. Simplified Battery and VIN Connect Flowchart Rev. 0 | Page 23 of 44 10544-032 YES ADP5061 Data Sheet TO CHARGING MODE TO IC OFF YES RUN BATTERY DETECTION tSTART NO EXPIRED YES VBAT_SNS < VTRK NO POWER-DOWN TRICKLE CHARGE VINOK FAST CHARGE NO VINOK YES VBAT_SNS < VTRK YES NO IVIN < ILIM YES NO IBUSLIM = HIGH IVIN = ILIM NO THERMLIM = HIGH TEMP = TLIM YES YES WATCHDOG EXPIRED START tSAFE IBUS = 100 mA NO tWD EXPIRED TEMP < TLIM NO YES TFAULT OR BAD BATTERY YES tSAFE OR tTRK EXPIRED tWD EXPIRED YES NO WATCHDOG EXPIRED START tSAFE IBUS = 100 mA NO tSAFE OR tCHG YES1 EXPIRED NO RUN BATTERY DETECTION VBAT_SNS = VTRM YES NO CC MODE CHARGING NO CV MODE CHARGING CHARGE COMPLETE YES IOUT < IEND Figure 33. Simplified Charging Mode Flowchart Rev. 0 | Page 24 of 44 10544-033 YES VBAT_SNS = VRCH NO TFAULT OR BAD BATTERY TIMER SPECS 1SEE Data Sheet ADP5061 I2C INTERFACE the master after the 8-bit data byte has been written (see Figure 34 for an example of the I2C write sequence to a single register). The ADP5061 increments the subaddress automatically and starts receiving a data byte at the next register until the master sends an I2C stop as shown in Figure 35. The ADP5061 includes an I2C-compatible serial interface for control of the charging and LDO functions, as well as for a readback of system status registers. The I2C chip address is 0x28 in write mode and 0x29 in read mode. Figure 36 shows the I2C read sequence of a single register. ADP5061 sends the data from the register denoted by the subaddress and increments the subaddress automatically, sending data from the next register until the master sends an I2C stop condition as shown in Figure 37. Registers values are reset to the default values when the VINx supply falls below the VVIN_OK falling voltage threshold. The I2C registers also reset when the battery is disconnected and VIN is 0 V. The subaddress content selects which of the ADP5061 registers is written to first. The ADP5061 sends an acknowledgement to MASTER STOP 0 = WRITE 0 1 0 0 0 0 0 SUBADDRESS 0 SP ADP5061 RECEIVES DATA 10544-034 1 CHIP ADDRESS ADP5061 ACK 0 ADP5061 ACK 0 ADP5061 ACK ST Figure 34. I2C Single Register Write Sequence MASTER STOP 0 = WRITE 0 0 0 0 CHIP ADDRESS 0 SUBADDRESS REGISTER N 0 0 ADP5061 RECEIVES DATA TO REGISTER N ADP5061 RECEIVES DATA TO REGISTER N + 1 0 SP ADP5061 RECEIVES DATA TO LAST REGISTER 10544-035 1 ADP5061 ACK 0 ADP5061 ACK 1 ADP5061 ACK 0 ADP5061 ACK 0 ADP5061 ACK ST Figure 35. I2C Multiple Register Write Sequence CHIP ADDRESS 0 1 SP MASTER ACK SUBADDRESS 0 ADP5061 ACK CHIP ADDRESS 0 ST 0 0 1 0 1 0 0 1 ADP5061 ACK 0 1 0 1 0 0 0 0 ADP5061 ACK ST 0 MASTER STOP 1 = READ ADP5061 SENDS DATA 10544-036 0 = WRITE Figure 36. I2C Single Register Read Sequence Figure 37. I2C Multiple Register Read Sequence Rev. 0 | Page 25 of 44 ADP5061 SENDS DATA OF REGISTER N+1 ADP5061 SENDS DATA OF LAST REGISTER 10544-037 ADP5061 SENDS DATA OF REGISTER N 1 SP MASTER ACK CHIP ADDRESS 0 MASTER ACK MASTER ACK SUBADDRESS REGISTER N 0 ADP5061 ACK CHIP ADDRESS 0 ST 0 0 1 0 1 0 0 1 0 0 ADP5061 ACK 1 0 1 0 0 0 0 ADP5061 ACK ST 0 0 MASTER STOP 1 = READ 0 = WRITE ADP5061 Data Sheet I2C REGISTER MAP See the Factory Programmable Options section for programming option details. Note that a blank cell indicates a bit that is not used. Table 17. I2C Register Map Register Addr. Name 0x00 Manufacturer and model ID 0x01 Silicon revision 0x02 VINx pins settings 0x03 Termination settings 0x04 Charging current 0x05 Voltage thresholds 0x06 Timer settings 0x07 Functional Settings 1 0x08 Functional Settings 2 0x09 Interrupt enable 0x0A Interrupt active 0x0B Charger Status 1 0x0C Charger Status 2 0x0D Fault register 0x10 Battery short 0x11 IEND D7 D6 D5 MANUF D4 D3 D2 D1 D0 Model REV ILIM 1 VTRM1, 2 CHG_VLIM[1:0] 1, 2 ICHG1, 2 DIS_RCH1, 3 VRCH1 DIS_IC11 EN_JEITA1, 3 JEITA_SELECT1, 3 VIN_OV ITRK_DEAD1 VTRK_DEAD1, 3 VWEAK1 EN_TEND1 EN_CHG_TIMER1 CHG_TMR_PERIOD1 EN_WD1, 3 EN_BMON1 EN_THR1 EN_CHG_VLIM1, 3 DIS_LDO1 WD_PERIOD1 RESET_WD EN_EOC1 IDEAL_DIODE[1:0]1, 3 EN_CHG1 VSYSTEM[2:0]1, 3 EN_THERM_LIM_INT EN_WD_INT EN_TSD_INT EN_THR_INT EN_BAT_INT EN_CHG_INT EN_VIN_INT THERM_LIM_INT WD_INT TSD_INT THR_INT BAT_INT VIN_OK VIN_ILIM THERM_LIM CHDONE CHARGER_STATUS RCH_LIM_INFO BATTERY_STATUS THR_STATUS BAT_SHR1 CHG_INT TSD 130°C1 TBAT_SHR1 VIN_INT TSD 140°C1 VBAT_SHR1 IEND1, 3 C/20 EOC1 These bits reset to default I2C values when VINx is connected or disconnected. The default I2C values of these bits are partially factory programmable. 3 The default I2C values of these bits are fully factory programmable. 1 2 Rev. 0 | Page 26 of 44 C/10 EOC1 C/5 EOC1 SYS_EN_SET1, 3 Data Sheet ADP5061 REGISTER BIT DESCRIPTIONS In Table 18 through Table 33, the following abbreviations are used: R is read only, W is write only, R/W is read/write, and N/A means not applicable. Table 18. Manufacturer and Model ID, Register Address 0x00 Bit No. [7:4] [3:0] Bit Name MANUF[3:0] MODEL[3:0] Access R R Default 0001 1001 Description The 4-bit manufacturer identification bus The 4-bit model identification bus Table 19. Silicon Revision Register, Register Address 0x01 Bit No. [7:4] [3:0] Bit Name Not used REV[3:0] Access R R Default Description 0100 The 4-bit silicon revision identification bus Table 20. VINx Settings Register, Register Address 0x02 Bit No. [7:5] 4 [3:0] Bit Name Not used RFU ILIM[3:0] Access R R/W R/W Default Description 0 0000 = 100 mA Reserved for future use. VINx input current-limit programming bus. The current into VINx can be limited to the following programmed values: 0000 = 100 mA. 0001 = 150 mA. 0010 = 200 mA. 0011 = 250 mA. 0100 = 300 mA. 0101 = 400 mA. 0110 = 500 mA. 0111 = 600 mA. 1000 = 700 mA. 1001 = 800 mA. 1010 = 900 mA. 1011 = 1000 mA. 1100 = 1200 mA. 1101 = 1500 mA. 1110 = 1800 mA. 1111 = 2100 mA. Rev. 0 | Page 27 of 44 ADP5061 Data Sheet Table 21. Termination Settings, Register Address 0x03 Bit No. [7:2] Bit Name VTRM[5:0] Access R/W Default 100011 = 4.20 V [1:0] CHG_VLIM[1:0] R/W 10 = 3.7 V Description Termination voltage programming bus. The values of the float voltage can be programmed to the following values: 001111 = 3.80 V. 010000 = 3.82 V. 010001 = 3.84 V. 010010 = 3.86 V. 010011 = 3.88 V. 010100 = 3.90 V. 010101 = 3.92 V. 010110 = 3.94 V. 010111 = 3.96 V. 011000 = 3.98 V. 011001 = 4.00 V. 011010 = 4.02 V. 011011 = 4.04 V. 011100 = 4.06 V. 011101 = 4.08 V. 011110 = 4.10 V. 011111 = 4.12 V. 100000 = 4.14 V. 100001 = 4.16 V. 100010 = 4.18 V. 100011 = 4.20 V. 100100 = 4.22 V. 100101 = 4.24 V. 100110 = 4.26 V. 100111 = 4.28 V. 101000 = 4.30 V. 101001 = 4.32 V. 101010 = 4.34 V. 101011 = 4.36 V. 101100 = 4.38 V. 101101 = 4.40 V. 101110 = 4.42 V. 101111 = 4.44 V. 110000 = 4.44 V. 110001 = 4.46 V. 110010 = 4.48 V. 110011 to 111111 = 4.50 V. Charging voltage limit programming bus. The values of the charging voltage limit can be programmed to the following values: 00 = 3.2 V. 01 = 3.4 V. 10 = 3.7 V. 11 = 3.8 V. Rev. 0 | Page 28 of 44 Data Sheet ADP5061 Table 22. Charging Current Settings, Register Address 0x04 Bit No. 7 6 [5:2] Bit Name Not used Not used ICHG[4:0] Access R R R/W Default Description 01110 = 750 mA [1:0] ITRK_DEAD[1:0] R/W 10 = 20 mA Fast charge current programming bus. The values of the constant current charge can be programmed to the following values: 00000 = 50 mA. 00001 = 100 mA. 00010 = 150 mA. 00011 = 200 mA. 00100 = 250 mA. 00101 = 300 mA. 00110 = 350 mA. 00111 = 400 mA. 01000 = 450 mA. 01001 = 500 mA. 01010 = 550 mA. 01011 = 600 mA. 01100 = 650 mA. 01101 = 700 mA. 01110 = 750 mA. 01111 = 800 mA. 10000 = 850 mA. 10001 = 900 mA. 10010 = 950 mA. 10011 = 1000 mA. 10100 = 1050 mA. 10101 = 1100 mA. 10110 = 1200 mA. 10111 to 11111 = 1300 mA. Trickle and weak charge current programming bus. The values of the trickle and weak charge currents can be programmed to the following values: 00 = 5 mA. 01 = 10 mA. 10 = 20 mA. 11 = 80 mA. Table 23. Voltage Thresholds, Register Address 0x05 Bit No. 7 Bit Name DIS_RCH Access R/W Default 0 = recharge enabled [6:5] VRCH[1:0] R/W 11 = 260 mV Description 0 = recharge enabled. 1 = recharge disabled. Recharge voltage programming bus. The values of the recharge threshold can be programmed to the following values (note that the recharge cycle can be disabled in I2C by the DIS_RCH bit): 00 = 80 mV. 01 = 140 mV. 10 = 200 mV. 11 = 260 mV. Rev. 0 | Page 29 of 44 ADP5061 Data Sheet Bit No. [4:3] Bit Name VTRK_DEAD[1:0] Access R/W Default 01 = 2.5 V [2:0] VWEAK[2:0] R/W 011 = 3.0 V Description Trickle to fast charge dead battery voltage programming bus. The values of the trickle to fast charge threshold can be programmed to the following values: 00 = 2.0 V. 01 = 2.5 V. 10 = 2.6 V. 11 = 2.9 V. Weak battery voltage rising threshold. 000 = 2.7 V. 001 = 2.8 V. 010 = 2.9 V. 011 = 3.0 V. 100 = 3.1 V. 101 = 3.2 V. 110 = 3.3 V. 111 = 3.4 V. Table 24. Timer Settings, Register Address 0x06 Bit No. [7:6] 5 Bit Name Not used EN_TEND Access Default Description R/W 1 0 = charge complete timer, tEND, disabled. A 31 ms deglitch timer remains on. 1 = charge complete timer enabled. 4 EN_CHG_TIMER R/W 1 3 CHG_TMR_PERIOD R/W 1 2 EN_WD R/W 0 1 WD_PERIOD R/W 0 0 RESET_WD W 0 0 = trickle/fast charge timer disabled. 1 = trickle/fast charge timer enabled. Trickle and fast charge timer period. 0 = 30 sec trickle charge timer and 300 minute fast charge timer. 1 = 60 sec trickle charge timer and 600 minute fast charge timer. 0 = watchdog timer is disabled even when BAT_SNS exceeds VDEAD. 1 = watchdog timer safety timer is enabled. Watchdog safety timer period. 0 = 32 sec watchdog timer and 40 minute safety timer. 1 = 64 sec watchdog timer and 40 minute safety timer. When RESET_WD is set to logic high by I2C, the watchdog safety timer is reset. Table 25. Functional Settings 1, Register Address 0x07 Bit No. 7 6 Bit Name Not used DIS_IC1 Access Default Description R/W 0 5 EN_BMON R/W 0 4 EN_THR R/W 0 3 DIS_LDO R/W 0 0 = normal operation. 1 = the ADP5061 is disabled, VVIN must be VISO_B < VVIN < 5.5 V. 0 = when VVIN < VVIN_OK, the battery monitor is disabled. When VVIN = 4.0 to 6.7 V, the battery monitor is enabled regardless of the EN_BMON state. 1 = the battery monitor is enabled even when the voltage at the VINx pins is below VVIN_OK. 0 = when VVIN < VVIN_OK, the THR current source is disabled. When VVIN = 4.0 V to 6.7 V, the THR current source is enabled regardless of the EN_THR state. 1 = THR current source is enabled even when the voltage at the VINx pins is below VVIN_OK. 0 = LDO is enabled. 1 = LDO is off. In addition, If EN_CHG = low, the battery isolation FET is on. If EN_CHG = high, the battery isolation FET is off. Rev. 0 | Page 30 of 44 Data Sheet ADP5061 Bit No. 2 Bit Name EN_EOC Access R/W Default 1 Description 0 = end of charge not allowed. 1 = end of charge allowed. 1 0 Not used EN_CHG R/W 0 0 = battery charging is disabled. 1 = battery charging is enabled. Table 26. Functional Settings 2, Register Address 0x08 Bit No. 7 Bit Name EN_JEITA Access R/W Default 0 = JEITA disabled 6 JEITA_SELECT R/W 0 = JEITA1 5 EN_CHG_VLIM R/W 0 [4:3] IDEAL_DIODE[1:0] R/W 00 [2:0] VSYSTEM[2:0] R/W 000 = 4.3 V Description 0 = JEITA compliance of the Li-Ion temperature battery charging specifications is disabled. 1 = JEITA compliance enabled. 0 = JEITA1 is selected. 1 = JEITA2 is selected. 0 = charging voltage limit disabled. 1 = voltage limit activated. The charger prevents charging until the battery voltage drops below the VCHG_VLIM threshold. 00 = ideal diode operates always when VISO_S < VISO_B. 01 = ideal diode operates when VISO_S < VISO_B and VBAT_SNS > VWEAK. 10 = ideal diode is disabled. 11 = ideal diode is disabled. System voltage programming bus. The values of the system voltage can be programmed to the following values: 000 = 4.3 V. 001 = 4.4 V. 010 = 4.5 V. 011 = 4.6 V. 100 = 4.7 V. 101 = 4.8 V. 110 = 4.9 V. 111 = 5.0 V. Table 27. Interrupt Enable Register, Register Address 0x09 Bit No. 7 6 Mnemonic Not used EN_THERM_LIM_INT Access Default Description R/W 0 5 EN_WD_INT R/W 0 4 EN_TSD_INT R/W 0 3 EN_THR_INT R/W 0 2 EN_BAT_INT R/W 0 1 EN_CHG_INT R/W 0 0 EN_VIN_INT R/W 0 0 = isothermal charging interrupt is disabled. 1 = isothermal charging interrupt is enabled. 0 = watchdog alarm interrupt is disabled. 1 = watchdog alarm interrupt is enabled. 0 = overtemperature interrupt is disabled. 1 = overtemperature interrupt is enabled. 0 = THR temperature thresholds interrupt is disabled. 1 = THR temperature thresholds interrupt is enabled. 0 = battery voltage thresholds interrupt is disabled. 1 = battery voltage thresholds interrupt is enabled. 0 = charger mode change interrupt is disabled. 1 = charger mode change interrupt is enabled. 0 = VINx pin voltage thresholds interrupt is disabled. 1 = VINx pin voltage thresholds interrupt is enabled. Rev. 0 | Page 31 of 44 ADP5061 Data Sheet Table 28. Interrupt Active Register, Register Address 0x0A Bit No. 7 6 5 Mnemonic Not used THERM_LIM_INT WD_INT Access Default Description R R 0 0 4 TSD_INT R 0 1 = indicates an interrupt caused by isothermal charging. 1 = indicates an interrupt caused by the watchdog alarm. The watchdog timer expires within 2 sec or 4 sec, depending on the watch dog period setting of 32 sec or 64 sec, respectively. 1 = indicates an interrupt caused by an overtemperature fault. 3 THR_INT R 0 1 = indicates an interrupt caused by THR temperature thresholds. 2 BAT_INT R 0 1 = indicates an interrupt caused by battery voltage thresholds. 1 0 CHG_INT VIN_INT R R 0 0 1 = indicates an interrupt caused by a charger mode change. 1 = indicates an interrupt caused by VIN voltage thresholds. Table 29. Charger Status Register 1, Register Address 0x0B Bit No. 7 6 5 Mnemonic VIN_OV VIN_OK VIN_ILIM Access R R R Default N/A N/A N/A 4 THERM_LIM R N/A 3 CHDONE R N/A [2:0] CHAGER_STATUS[2:0] R N/A Description 1 = indicates that the voltage at the VINx pins exceeds VVIN_OV. 1 = indicates that the voltage at the VINx pins exceeds VVIN_OK. 1 = indicates that the current into a VINx pin is limited by the high voltage blocking FET and the charger is not running at the full programmed ICHG. 1 = indicates that the charger is not running at the full programmed ICHG but is limited by the die temperature. 1 = indicates the end of charge cycle has been reached. This bit latches on, in that it does not reset to low when the VRCH threshold is breached. Charger status bus. 000 = off. 001 = trickle charge. 010 = fast charge (CC mode). 011 = fast charge (CV mode). 100 = charge complete. 101 = LDO mode. 110 = trickle or fast charge timer expired. 111 = battery detection. Rev. 0 | Page 32 of 44 Data Sheet ADP5061 Table 30. Charger Status Register 2, Register Address 0x0C Bit No. [7:5] Mnemonic THR_STATUS[2:0] Access R Default N/A 4 3 Not used RCH_LIM_INFO R R N/A N/A 2:0 BATTERY_STATUS[2:0] R Description THR pin status. 000 = off. 001 = battery cold. 010 = battery cool. 011 = battery warm. 100 = battery hot. 111 = thermistor OK. The recharge limit information function is activated when DIS_RCH is logic high and the CHARGER_STATUS[2:0] = 100 (binary). The status bit informs the system that a recharge cycle is required. 0 = VBAT_SNS > VRCH. 1 = VBAT_SNS < VRCH. Battery status bus. 000 = battery monitor off. 001 = no battery. 010 = VBAT_SNS < VTRK. 011 = VTRK ≤ VBAT_SNS < VWEAK. 100 = VBAT_SNS ≥ VWEAK. Table 31. Fault Register 1, Register Address 0x0D Bit No. [7:4] 3 2 1 0 1 Mnemonic Not used BAT_SHR Not used TSD 130°C TSD 140°C Access Default Description R/W R/W R/W R/W 0 1 = indicates detection of a battery short. 0 0 1 = indicates an overtemperature (lower) fault. 1 = indicates an overtemperature fault. To reset the fault bits in the fault register, cycle power on VINx or write high to the corresponding I2C bit. Table 32. Battery Short, Register Address 0x10 Bit No. [7:5] Mnemonic TBAT_SHR[2:0] Access R/W Default 100 = 30 sec Description Battery short timeout timer. 000 = 1 sec. 001 = 2 sec. 010 = 4 sec. 011 = 10 sec. 100 = 30 sec. 101 = 60 sec. 110 = 120 sec. 111 = 180 sec. [4:3] [2:0] Not used VBAT_SHR[2:0] R/W R/W 100 = 2.4 V Battery short voltage threshold level. 000 = 2.0 V. 001 = 2.1 V. 010 = 2.2 V. 011 = 2.3 V. 100 = 2.4 V. 101 = 2.5 V. 110 = 2.6 V. 111 = 2.7 V. Rev. 0 | Page 33 of 44 ADP5061 Data Sheet Table 33. IEND Register, Register Address 0x11 Bit No. [7:5] Mnemonic IEND[2:0] Access R/W 4 C/20 EOC R/W 3 C/10 EOC R/W 2 C/5 EOC R/W 1:0 SYS_EN_SET[1:0] R/W 1 Default 010 = 52.5 mA 0 Description Termination current programming bus. The values of the termination current can be programmed to the following values: 000 = 12.5 mA. 001 = 32.5 mA. 010 = 52.5 mA. 011 = 72.5 mA. 100 = 92.5 mA. 101 = 117.5 mA. 110 = 142.5 mA. 111 = 170.0 mA. The C/20 EOC bit has priority over the other settings (C/10 EOC, C/5 EOC, and IEND). 1 = the termination current is ICHG/20 with the following limitations: Minimum value = 12.5 mA. Maximum value = 170 mA. The C/10 EOC bit has priority over the other termination current settings (IEND), but does not have priority over the C/20 EOC setting. 1 = the termination current is ICHG/10 unless C/20 EOC is high. The termination current is limited to the following values: Minimum value = 12.5 mA. Maximum value = 170 mA. The C/5 bit has priority over the other termination current settings (IEND), but does not have priority over the C/20 EOC setting or the C/10 EOC setting. 1 = the termination current is ICHG / 5 unless the C/20 or the C/10 EOC is high. The termination current is limited to the following values: Minimum value = 12.5 mA. Maximum value = 170 mA. Selects the operation of the system enable pin (SYS_EN). 00 = SYS_EN is activated when LDO is active and the system voltage is available. 01 = SYS_EN activated by ISO_Bx voltage, the battery charging mode. 10 = SYS_EN is activated and the isolation FET is disabled when the battery drops below VWEAK. 1 11 = SYS_EN is active in LDO mode when the charger is disabled. SYS_EN is active in the charging mode when VISO_B ≥ VWEAK. This option is active when VINx = 0 V and the battery monitor is activated from Register 0x07, Bit D5 (EN_BMON). Rev. 0 | Page 34 of 44 Data Sheet ADP5061 APPLICATIONS INFORMATION Substituting these values in the equation yields EXTERNAL COMPONENTS CEFF = 34.3 μF × (1 − 0.15) × (1 − 0.2) ≈ 20.7 μF ISO_Sx (VOUT) Capacitor Selection To obtain stable operation of the ADP5061 in a safe way, the combined effective capacitance of the ISO_Sx capacitor and the system capacitance must not be less than 20 µF and must not exceed 100 µF at any point during operation. When choosing the capacitor value, it is also important to account for the loss of capacitance due to the output voltage dc bias. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric that is adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or higher are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. To guarantee the performance of the charger in various operation modes including trickle charge, constant current charge, and constant voltage charge, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. Splitting ISO_Sx Capacitance In many applications, the total ISO_Sx capacitance consists of a number of capacitors. The system voltage node (ISO_Sx) usually supplies a single regulator or a number of ICs and regulators, each of which requires a capacitor close to its power supply input (see Figure 39). The capacitance close to the ADP5061 ISO_Sx output should be at least 10 µF, as long as the total effective capacitance is at least 20 µF at any point during operation. The worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation: ISO_Sx CEFF = COUT × (1 − TEMPCO) × (1 − TOL) ADP5061 + SUM OF EFFECTIVE CAPACITANCES ON ISO_Sx NODE ≥ 20µF CISO_B ≥10µF IC2 10544-038 CIN2 Figure 39. Splitting ISO_Sx Capacitance ISO_Bx Capacitor Selection 60 The ISO_Bx effective capacitance (including temperature and dc bias effects) must not be less than 10 µF at any point during operation. Typically, a nominal capacitance of 22 µF is required to fulfill the condition at all points of operation. Suggestions for an ISO_Bx capacitor are listed in Table 35. 55 50 CAPACITANCE (µF) IC1 VIN2 In this example, the worst-case temperature coefficient (TEMPCO) over the −40°C to +85°C temperature range is assumed to be 15% for an X7R dielectric. The tolerance of the capacitor (TOL) is assumed to be 20%, and COUT is 30.4 μF at 5.0 V, as shown in Figure 38. 45 40 CBP Capacitor Selection 35 30 0 1 2 3 DC BIAS VOLTAGE (V) 4 5 10544-041 25 20 CIN1 ISO_Bx where: CEFF is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. VIN1 CISO_S ≥10µF The internal supply voltage of the ADP5061 is equipped with a noise suppressing capacitor at the CBP terminal. Do not allow CBP capacitance to exceed 14 nF at any point during operation. Do not connect any external voltage source, any resistive load, or any other current load to the CBP terminal. Suggestions for a CBP capacitor are listed in Table 36. Figure 38. Murata GRM32ER61A476ME20C Capacitance vs. Bias Voltage Rev. 0 | Page 35 of 44 ADP5061 Data Sheet VINx Capacitor Selection According to the USB 2.0 specification, USB peripherals have a detectable change in capacitance on VBUS when they are attached to a USB port. The peripheral device VBUS bypass capacitance must be at least 1 µF but not larger than 10 µF. The VINx input of the ADP5061 is tolerant of voltages as high as 20 V; however, if an application requires exposing the VINx input to voltages of up to 20 V, the voltage range of the capacitor must also be above 20 V. Suggestions for a VINx capacitor are given in Table 37. When using ceramic capacitors, a higher voltage range is usually achieved by selecting a component with larger physical dimensions. In applications where lower than 20 V at VINx input voltages can be guaranteed, smaller output capacitors can be used accordingly. Table 34. ISO_Sx Capacitor Suggestions Vendor Murata TDK Part Number GRM32ER61A476ME20 C3225X5R1A476M Value 47 µF 47 µF Voltage 10 V 10 V Size 1210 1210 Voltage 10 V 6.3 V 6.3 V 6.3 V Size 1206 1206 1206 1206 Voltage 16 V 16 V Size 0402 0402 Voltage 25 V 25 V Size 0805 0805 Table 35. ISO_Bx Capacitor Suggestions Vendor Murata Murata TDK TaiyoYuden Part Number GRM31CR61A226KE19 GRM31CR60J226ME19 C3216X5R0J226M JMK316ABJ226KL Value 22 μF 22 μF 22 µF 22 µF Table 36. CBP Capacitor Suggestions Vendor Murata TDK Part Number GRM15XR71C103KA86 C1005X7R1C103K Value 10 nF 10 nF Table 37. VINx Capacitor Suggestions Vendor Murata TDK Rev. 0 | Page 36 of 44 Part Number GRM21BR61E106MA73 C2012X5R1E106K Value 10 µF 10 µF Data Sheet ADP5061 PCB LAYOUT GUIDELINES VIN = 4V TO 6.7V C4 10µF GRM21BR61E106MA73 C3 E3 D3 VIN1:3 ISO_S1:3 B3 CBP C1 10nF C2 D2 GRM15XR71C103KA86 E2 C3 47µF GRM32ER61A476ME20 VDDIO R1 1.5kΩ R2 1.5kΩ CHARGER CONTROL BLOCK TO MCU A4 SCL TO MCU A3 SDA C1 TO MCU/NC E4 DIG_IO1 D1 TO MCU/NC C4 DIG_IO2 TO MCU/NC B4 DIG_IO3 E1 ISO_B1:3 BAT_SNS D4 VDDIO CONNECT CLOSE TO BATTERY + THR B2 R4 10kΩ TO MCU VLED A1 ILED C2 22µF R5 NTC 10kΩ (OPTIONAL) A2 SYS_EN AGND GRM31CR60J226ME19 ADP5061 WLCSP20 10544-039 B1 Figure 40. Reference Circuit Diagram ISO_S ISO_B CISO_B 22µF ADP5061 PGND CBP 10nF 5.5mm CVIN 10µF VIN 8mm Figure 41. Reference PCB Floor Plan Rev. 0 | Page 37 of 44 10544-042 PGND CISO_S 47µF ADP5061 Data Sheet POWER DISSIPATION AND THERMAL CONSIDERATIONS PISOFET = RDSON_ISO × ICHG CHARGER POWER DISSIPATION When the ADP5061 charger operates at high ambient temperatures and at maximum current charging and loading conditions, the junction temperature can reach the maximum allowable operating limit of 125°C. When the junction temperature exceeds 140°C, the ADP5061 turns off, allowing the device to cool down. When the die temperature falls below 110°C and the TSD 140°C fault bit in Register 0x0D is cleared by an I2C write, the ADP5061 resumes normal operation. This section provides guidelines to calculate the power dissipated in the device to ensure that the ADP5061 operates below the maximum allowable junction temperature. To determine the available output current in different operating modes under various operating conditions, the user can reference the following equations: PD = PLDOFET + PISOFET (1) where: PLDOFET is the power dissipated in the input LDO FET. PISOFET is the power dissipated in the battery isolation FET. where: RDSON_ISO is the on resistance of the battery isolation FET (typically 110 mΩ during charging). The thermal control loop of the ADP5061 automatically limits the charge current to maintain a die temperature below TLIM (typically 115°C). The most intuitive and practical way to calculate the power dissipation in the ADP5061 device is to measure the power dissipated at the input and all of the outputs. Perform the measurements at the worst-case conditions (voltages, currents, and temperature). The difference between input and output power is the power that is dissipated in the device. JUNCTION TEMPERATURE In cases where the board temperature, TA, is known, the thermal resistance parameter, θJA, can be used to estimate the junction temperature rise. TJ is calculated from TA and PD using the formula TJ = TA + (PD × θJA) Calculate the power dissipation in the LDO FET and the battery isolation FET using Equation 2 and Equation 3. PLDOFET = (VIN – VISO_S) × (ICHG + ILOAD) (2) PISOFET = (VISO_S – VISO_B) × ICHG (3) where: VIN is the input voltage at the VINx pins. VISO_S is the system voltage at the ISO_Sx pins. VISO_B is the battery voltage at the ISO_Bx pins. ICHG is the battery charge current. ILOAD is the system load current from the ISO_Sx pins. (4) (5) The typical θJA value for the 20-bump WLCSP is 46.8°C/W (see Table 5). A very important factor to consider is that θJA is based on a 4-layer, 4 in × 3 in, 2.5 oz. copper board as per JEDEC standard, and real applications may use different sizes and layers. It is important to maximize the copper to remove the heat from the device. Copper exposed to air dissipates heat better than copper used in the inner layers. If the case temperature can be measured, the junction temperature is calculated by TJ = TC + (PD × θJC) (6) where TC is the case temperature and θJC is the junction-to-case thermal resistance provided in Table 5. LDO Mode The system regulation voltage is user programmable from 4.3 V to 5.0 V. In LDO mode (charging disabled, EN_CHG = low), calculation of the total power dissipation is simplified, assuming that all current is drawn from the VINx pins and the battery is not shared with ISO_Sx. PD = (VIN – VISO_S) × ILOAD Charging Mode In charging mode, the voltage at the ISO_Sx pins depends on the battery level. When the battery voltage is lower than VISO_SFC (typically 3.8 V), the voltage drop over the battery isolation FET is higher and the power dissipation must be calculated using Equation 3. When the battery voltage level reaches VISO_SFC, the power dissipation can be calculated using Equation 4. For a WLCSP device, where possible, remove heat from every current carrying bump (VINx, ISO_Sx, and ISO_Bx). For example, thermal vias to the board power planes can be placed close to these pins, where available. The reliable operation of the charger can be achieved only if the estimated die junction temperature of the ADP5061 (Equation 5) is less than 125°C. Reliability and mean time between failures (MTBF) are greatly affected by increasing the junction temperature. Additional information about product reliability can be found in the ADI Reliability Handbook located at the following URL: www.analog.com/reliability_handbook. Rev. 0 | Page 38 of 44 Data Sheet ADP5061 FACTORY PROGRAMMABLE OPTIONS CHARGER OPTIONS Table 38 to Table 50 list the factory programmable options of the ADP5061. In each of these tables, the selection column represents the default setting of Model ADP5061ACBZ-2-R7. Table 38. Default Termination Voltage Table 42. Default System Voltage Option 000 = 4.20 V 010 = 3.70 V 011 = 3.80 V 100 = 3.90 V 101 = 4.00 V 110 = 4.10 V 111 = 4.40 V Option 000 = 4.3 V 001 = 4.4 V 010 = 4.5 V 011 = 4.6 V 100 = 4.7 V 101 = 4.8 V 110 = 4.9 V 111 = 5.0 V Selection 000 = 4.20 V Table 39. Default Fast Charge Current Option 000 = 500 mA 001 = 300 mA 010 = 550 mA 011 = 600 mA 100 = 750 mA 101 = 900 mA 110 = 1300 mA 111 = 1300 mA Selection 100 = 750 mA Table 40. Default End of Charge Current Option 000 = 52.5 mA 001 = 72.5 mA 010 = 12.5 mA 011 = 32.5 mA 100 = 142.5 mA 101 = 167.5 mA 110 = 92.5 mA 111 = 117.5 mA Selection 000 = 52.5 mA 111 = 5.0 V Table 43. Thermistor Resistance Option 0 = 10 kΩ 1 = 100 kΩ Selection 0 = 10 kΩ Table 44. Thermistor Beta Value Option 0100 = 3150 0101 = 3350 0110 = 3500 0111 = 3650 1000 = 3850 1001 = 4000 1010 = 4200 1011 = 4400 Selection 0100 = 3150 Table 45. DIS_IC1 Mode Select Option 0 = DIC_IC1 mode select, VINx current = 280 µA, ISO_B can float, no leak to ISO_Bx 1 = DIC_IC1 mode select, VINx current = 110 µA, supply switch leaks from VINx to ISO_Bx Table 41. Default Trickle to Fast Charge Threshold Option 00 = 2.5 V 01 = 2.0 V 10 = 2.9 V 11 = 2.6 V Selection Selection 00 = 2.5 V Selection 0 Table 46. Trickle or Fast Charge Timer Fault Operation Option 0 = after timeout LDO off, charging off 1 = after timeout LDO mode active, charging off Rev. 0 | Page 39 of 44 Selection 1 = LDO mode active ADP5061 Data Sheet I2C REGISTER DEFAULTS Table 47. I2C Register Default Settings Bit Name CHG_VLIM DIS_RCH I2C Register Address, Bit Location Address 0x03, Bits[D1:D0] Address 0x05, Bit D7 Option 0 = limit 3.2 V, 1 = limit 3.7 V 0 = recharge enabled, 1 = recharge disabled EN_WD DIS_IC1 EN_CHG Address 0x06, Bit D2 Address 0x07, Bit D6 Address 0x07, Bit D0 0 = watchdog disabled, 1 = watchdog enabled 0 = not activated, 1 = activated 0 = charging disabled, 1 = charging enabled EN_JEITA JEITA_SELECT Address 0x08, Bit D7 Address 0x08, Bit D6 0 = JEITA disabled, 1 = JEITA enabled 0 = JEITA1 charging, 1= JEITA2 charging EN_CHG_VLIM IDEAL_DIODE[1:0] Address 0x08, Bit D5 Address 0x08, Bits[D4:D3] 0 = limit disabled, 1 = limit enabled 00 = ideal diode operates when VISO_S < VISO_B 01 = ideal diode operates when VISO_S < VISO_B and VBAT_SNS > VWEAK 10 = ideal diode is disabled 11 = ideal diode is disabled Selection 0 = limit 3.2 V 0 = recharge enabled 0 = disabled 0 = not activated 0 = charging disabled 0 = JEITA disabled 0 = JEITA1 charging 0 = limit disabled 00 DIGITAL INPUT AND OUTPUT OPTIONS Table 48. I2C Address 0x11, Bits[D1:D0] SYS_EN Output Default Option 00 = SYS_EN is activated when LDO is active and system voltage is available 01 = SYS_EN is activated by ISO_Bx voltage; battery charging mode 10 = SYS_EN is activated and isolation FET is disabled when battery drops below VWEAK 1 11 = SYS_EN is active in LDO mode when charger is disabled. SYS_EN is active in charging mode when VISO_B ≥ VWEAK 1 This option is active when VINx = 0 V and battery monitor is activated from Register 0x07, Bit D5 (EN_BMON). Rev. 0 | Page 40 of 44 Selection 00 Data Sheet ADP5061 DIG_IO1, DIG_IO2, and DIG_IO3 Options Table 49. DIG_IO1 Polarity Option 0 = DIG_IO1 polarity, high active operation 1 = DIG_IO1 polarity, low active operation Selection 0 = high active Table 50. DIG_IOx Options Option 0000 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DIG_IO1 Function IVIN limit, low = 100 mA, high = 500 mA IVIN limit, low = 100 mA, high = 500 mA IVIN limit, low = 100 mA, high = 500 mA IVIN limit, low = 100 mA, high = 500 mA IVIN limit, low = 100 mA, high = 500 mA IVIN limit, low = 100 mA, high = 500 mA low = charging disabled, high = charging enabled IVIN limit, low = 100 mA, high = 500 mA IVIN limit, low = 100 mA, high = 500 mA IVIN limit, low = 100 mA, high = 500 mA IVIN limit, low = 100 mA, high = 500 mA IVIN limit, low = 100 mA, high = 500 mA IVIN limit, low = 100 mA, high = 500 mA High = IVIN limit 1500 mA Disable IC1, low = not activated, high = activated DIG_IO2 Function Disable IC1, low = not activated, high = activated High = IVIN limit 1500 mA High = IVIN limit 1500 mA High = IVIN limit 1500 mA High = IVIN limit 1500 mA Disable recharge Disable IC1, low = not activated, high = activated High = IVIN limit 1500 mA DIG_IO3 Function Low = charging disabled, high = charging enabled Disable IC1, low = not activated, high = activated Fast charge current, low = ICHG, high = ICHG/2 Low = LDO active, high = LDO disabled Low = charging disabled, high = charging enabled Low = charging disabled, high = charging enabled High = disable recharge Interrupt output Low = charging disabled, high = charging enabled Disable IC1, low = not activated, high = activated High = disable recharge Interrupt output Fast charge current, low = ICHG, high = ICHG/2 Low = LDO active, high = LDO disabled Low = charging disabled, high = charging enabled Low = charging disabled, high = charging enabled Interrupt output Rev. 0 | Page 41 of 44 Interrupt output Interrupt output Interrupt output Interrupt output Interrupt output Selection 0000 ADP5061 Data Sheet PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 2.035 1.995 1.955 4 3 2 1 A BALL A1 IDENTIFIER B 2.635 2.595 2.555 2.00 REF C D E 0.50 REF BOTTOM VIEW TOP VIEW (BALL SIDE UP) (BALL SIDE DOWN) SEATING PLANE SIDE VIEW 1.50 REF COPLANARITY 0.04 0.360 0.320 0.280 0.270 0.240 0.210 04-18-2012-A 0.660 0.600 0.540 0.390 0.360 0.330 Figure 42. 20-Ball Wafer Level Chip Scale Package [WLCSP] (CB-20-9) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 ADP5061ACBZ-2-R7 ADP5061CB-EVALZ 1 2 Temperature Range –40°C to +125°C Package Description 20-Ball WLCSP Evaluation Board Z = RoHS Compliant Part. For additional factory programmable options, contact a local Analog Devices, Inc., sales or distribution representative. Rev. 0 | Page 42 of 44 Package Option CB-20-9 Data Sheet ADP5061 NOTES Rev. 0 | Page 43 of 44 ADP5061 Data Sheet NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10544-0-6/12(0) www.analog.com/ADP5061 Rev. 0 | Page 44 of 44