ON NOIP1FN0500A-QTI Python 1.3/0.5/0.3 megapixels global shutter cmos image sensor Datasheet

NOIP1SN1300A
PYTHON 1.3/0.5/0.3 MegaPixels
Global Shutter CMOS
Image Sensors
FEATURES
• Size Options:
www.onsemi.com
PYTHON 300: 640 x 480 Active Pixels, 1/4” Optical Format
♦ PYTHON 500: 800 x 600 Active Pixels, 1/3.6” Optical Format
♦ PYTHON 1300: 1280 x 1024 Active Pixels, 1/2” Optical Format
• Data Output Options:
♦ P1: 4 LVDS Data Channels
♦ P2: 10 bit Parallel
♦ P3: 2 LVDS Data Channels
• 4.8 mm x 4.8 mm Low Noise Global Shutter Pixels with In-pixel CDS
• Monochrome (SN), Color (SE) and NIR (FN)
• Protective Foil Option Available
• Zero Row Overhead Time (ZROT) Mode Enabling Higher Frame
Rate
• Frame Rate at Full Resolution, 4 LVDS Data Channels (P1 only)
♦ 210/165 frames per second @ SXGA (ZROT/NROT)
Figure 1. PYTHON 1300
♦ 545/385 frames per second @ SVGA (ZROT/NROT)
♦ 815/545 frames per second @ VGA (ZROT/NROT)
DESCRIPTION
• Frames Rate at Full Resolution (CMOS)
The PYTHON 300, PYTHON 500, and PYTHON 1300
♦ 50/43 Frames per Second @ SXGA (ZROT/NROT)
image
sensors utilize high sensitivity 4.8 mm x 4.8 mm pixels
• On−chip 10−bit Analog−to−Digital Converter (ADC)
that support low noise “pipelined” and “triggered” global
• Four/Two/One LVDS High Speed Serial Outputs or
shutter readout modes. The sensors support correlated
Parallel CMOS Output
double sampling (CDS) readout, reducing noise and
• Random Programmable Region of Interest (ROI)
increasing dynamic range.
Readout
The image sensors have on−chip programmable gain
• Serial Peripheral Interface (SPI)
amplifiers and 10−bit A/D converters. The integration time
and gain parameters can be reconfigured without any visible
• Automatic Exposure Control (AEC)
image artifact. Optionally the on−chip automatic exposure
• Phase Locked Loop (PLL)
control loop (AEC) controls these parameters dynamically.
• High Dynamic Range (HDR) Modes Possible
The image’s black level is either calibrated automatically or
• Dual Power Supply (3.3 V and 1.8 V)
can be adjusted by adding a user programmable offset.
• −40°C to +85°C Operational Temperature Range
A high level of programmability using a four wire serial
• 48−pin LCC
peripheral interface enables the user to read out specific
regions of interest. Up to eight regions can be programmed,
• Power Dissipation:
♦ 620 mW (P1, 4 LVDS, ZROT)
achieving even higher frame rates.
♦ 420 mW (P1, P3, 2 LVDS, NROT)
The image data interface of the P1 devices consists of four
♦ 270 mW (P1, P3, 1 LVDS, NROT)
LVDS lanes, enabling frame rates up to 210 frames per
second in Zero ROT mode for the PYTHON 1300. Each
♦ 420 mW (P2, ZROT)
channel runs at 720 Mbps. A separate synchronization
• These Devices are Pb−Free and are RoHS Compliant
channel containing payload information is provided to
APPLICATIONS
facilitate the image reconstruction at the receiving end. The
• Machine Vision
P2 devices provide a parallel CMOS output interface at
• Motion Monitoring
reduced frame rate. The P3 devices are the same as the P1 but
with only two of the four LVDS data channels enabled,
• Security
facilitating frame rates of 90 frames per second in Normal
• Barcode Scanning (2D)
ROT for the PYTHON 1300.
♦
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 2
1
Publication Order Number:
NOIP1SN1300A/D
NOIP1SN1300A
The devices are provided in a 48−pin LCC package and are available in monochrome, Bayer color, and extended
near−infrared (NIR) configurations.
ORDERING INFORMATION
Part Number
Description
Package
PYTHON 1300
NOIP1SN1300A−QDI
1.3 Megapixel, Monochrome, LVDS Output
NOIP1SE1300A−QDI
1.3 Megapixel, Bayer Color, LVDS Output
NOIP1FN1300A−QDI
1.3 Megapixel, Monochrome with enhanced NIR, LVDS Output
NOIP2SN1300A−QDI
1.3 Megapixel, Monochrome, CMOS (parallel) Output
NOIP2SE1300A−QDI
1.3 Megapixel, Bayer Color, CMOS (parallel) Output
NOIP1SN1300A−QTI
1.3 Megapixel, Monochrome, LVDS Output, Protective Foil
NOIP1SE1300A−QTI
1.3 Megapixel, Bayer Color, LVDS Output, Protective Foil
NOIP1FN1300A−QTI
1.3 Megapixel, Monochrome with enhanced NIR, LVDS Output, Protective Foil
NOIP3SN1300A−QDI
1.3 Megapixel, 2 LVDS Outputs, Monochrome
NOIP3FN1300A−QDI
1.3 Megapixel, 2 LVDS Outputs, NIR enhanced Monochrome
NOIP3SE1300A−QDI
1.3 Megapixel, 2 LVDS Outputs, Color
NOIP3SN1300A−QTI
1.3 Megapixel, 2 LVDS Outputs, Monochrome, Protective Foil
NOIP3FN1300A−QTI
1.3 Megapixel, 2 LVDS Outputs, NIR enhanced Monochrome, Protective Foil
NOIP3SE1300A−QTI
1.3 Megapixel, 2 LVDS Outputs, Color, Protective Foil
48−pin LCC
PYTHON 500
NOIP1SN0500A−QDI
0.5 Megapixel, Monochrome, LVDS Output
NOIP1SE0500A−QDI
0.5 Megapixel, Bayer Color, LVDS Output
NOIP1FN0500A−QDI
0.5 Megapixel, Monochrome with enhanced NIR, LVDS Output
NOIP1SN0500A−QTI
0.5 Megapixel, Monochrome, LVDS Output, Protective Foil
NOIP1SE0500A−QTI
0.5 Megapixel, Bayer Color, LVDS Output, Protective Foil
NOIP1FN0500A−QTI
0.5 Megapixel, Monochrome with enhanced NIR, LVDS Output, Protective Foil
48−pin LCC
PYTHON 300
NOIP1SN0300A−QDI
0.3 Megapixel, Monochrome, LVDS Output
NOIP1SE0300A−QDI
0.3 Megapixel, Bayer Color, LVDS Output
NOIP1FN0300A−QDI
0.3 Megapixel, Monochrome with enhanced NIR, LVDS Output
NOIP1SN0300A−QTI
0.3 Megapixel, Monochrome, LVDS Output, Protective Foil
NOIP1SE0300A−QTI
0.3 Megapixel, Bayer Color, LVDS Output, Protective Foil
NOIP1FN0300A−QTI
0.3 Megapixel, Monochrome with enhanced NIR, LVDS Output, Protective Foil
48−pin LCC
The P1−SN/SE/FN base part references the mono, color and NIR enhanced versions of the 4 LVDS interface; the P2−SN/SE
base part references the mono and color versions of the CMOS interface; the P3−SN/SE/FN base part references the mono,
color and NIR enhanced version of the 2 LVDS interface. More details on the part number coding can be found at
http://www.onsemi.com/pub_link/Collateral/TND310−D.PDF
Production Package Mark
Line 1: NOI xxxx RRRRA where xxxx denotes LVDS−4 LVDS (P1) / CMOS (P2) / LVDS−2 LVDS (P3), mono micro lens
(SN) / color micro lens (SE) / NIR enhanced mono micro lens (FN) option,
RRRR is the resolution (1300), (0500), (0300)
Line 2: −QDI (without protective foil), −QTI (with protective foil)
Line 3: AWLYYWW where AWL is PRODUCTION lot traceability, YYWW is the 4−digit date code
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2
NOIP1SN1300A
SPECIFICATIONS
Key Specifications
Table 1. GENERAL SPECIFICATIONS
Parameter
Table 2. ELECTRO−OPTICAL SPECIFICATIONS
Specification
Parameter
Pixel type
In−pixel CDS. Global shutter pixel
architecture
Shutter type
Pipelined and triggered global shutter
Frame rate
Zero ROT/
Normal ROT
mode
P1−SN/SE/FN:
PYTHON 300: 815/545 fps
PYTHON 500: 545/385 fps
PYTHON 1300: 210/165 fps
P2−SN/SE: 50/43 fps
P3−SN/SE/FN: NA/90 fps
Master clock
Specification
Active pixels
PYTHON 300: 640 (H) x 480 (V)
PYTHON 500: 800 (H) x 600 (V)
PYTHON 1300: 1280 (H) x 1024 (V)
Pixel size
4.8 mm x 4.8 mm
Conversion gain
0.096 LSB10/e−
140 mV/e−
Dark temporal noise
< 9 e− (Normal ROT, 1x gain)
< 7 e− (Normal ROT, 2x gain)
P1,P3−SN/SE/FN:
72 MHz when PLL is used,
360 MHz (10−bit) / 288 MHz (8−bit)
when PLL is not used
P2−SN/SE: 72 MHz
Responsivity
at 550 nm
7.7 V/lux.s
Parasitic Light
Sensitivity (PLS)
<1/8000
8 Randomly programmable windows. Normal, sub−sampled and binned readout
modes
Full Well Charge
10000 e−
Quantum Efficiency
at 550 nm
56%
ADC resolution
10−bit, 8−bit (Note 1)
Pixel FPN
< 1.0 LSB10
LVDS outputs
P1−SN/SE/FN: 4/2/1 data + sync + clock
P3−SN/SE/FN: 2/1 data + sync + clock
PRNU
< 10 LSB10 on half scale response
of 525 LSB10
CMOS outputs
P2−SN/SE: 10−bit parallel output,
frame_valid, line_valid, clock
MTF
68% @ 535 nm − X−dir & Y−dir
PSNL at 20°C
120 LSB10/s, 1200 e−/s
Dark signal at 20°C
5 e−/s, 0.5 LSB10/s
Dynamic Range
> 60 dB in global shutter mode
Signal to Noise Ratio
(SNR max)
40 dB
Windowing
Data rate
P1−SN/SE/FN:
4 x 720 Mbps (10−bit) /
4 x 576 Mbps (8−bit)
P2−SN/SE: 72 Mhz
P3−SN/SE/FN: 2 x 720 Mbps (10−bit)
Power
dissipation
(10−bit mode)
P1−SN/SE/FN: 620 mW (4 data channels)
P1&P3−SN/SE/FN: 420 mW (2 data ch.)
P1&P3−SN/SE/FN: 270 mW (1 data ch.)
P2−SN/SE: 420 mW
Package type
48−pin LCC
Table 3. RECOMMENDED OPERATING RATINGS (Note 2)
Symbol
TJ
Description
Operating temperature range
Min
Max
Unit
−40
85
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 4. ABSOLUTE MAXIMUM RATINGS (Notes 3 and 4)
Min
Max
Unit
ABS (1.8 V supply group)
ABS rating for 1.8 V supply group
Parameter
–0.5
2.2
V
ABS (3.3 V supply group)
ABS rating for 3.3 V supply group
–0.5
4.3
V
ABS storage temperature range
−40
+150
°C
85
%RH
Symbol
TS
ABS storage humidity range at 85°C
Electrostatic discharge (ESD)
LU
Human Body Model (HBM): JS−001−2010
2000
Charged Device Model (CDM): JESD22−C101
500
Latch−up: JESD−78
100
V
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The ADC is 11−bit, down−scaled to 10−bit. The PYTHON uses a larger word−length internally to provide 10−bit on the output.
2. Operating ratings are conditions in which operation of the device is intended to be functional.
3. ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer
to Application Note AN52561. Long term exposure toward the maximum storage temperature will accelerate color filter degradation.
4. Caution needs to be taken to avoid dried stains on the underside of the glass due to condensation. The glass lid glue is permeable and can
absorb moisture if the sensor is placed in a high % RH environment.
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NOIP1SN1300A
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6, 7, 8 and 9)
Description
Parameter
Min
Typ
Max
Unit
3.4
V
Power Supply Parameters − P1 − SN/SE/FN LVDS (ZROT)
(NOTE: All ground pins (gnd_18, gnd_33, gnd_colpc) should be connected to an external 0 V ground reference.)
vdd_33
Supply voltage, 3.3 V
Idd_33
Current consumption 3.3 V supply
vdd_18
Supply voltage, 1.8 V
Idd_18
Current consumption 1.8 V supply
vdd_pix
Supply voltage, pixel
Idd_pix
Current consumption pixel supply
Ptot
Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V
P1, 4 LVDS, ZROT
Pstby_lp
Power consumption in low power standby mode
Popt
Power consumption at lower pixel rates
3.2
3.3
140
1.7
1.8
3.25
3.3
mA
1.9
80
V
mA
3.35
V
5
mA
620
mW
50
mW
3.4
V
Configurable
Power Supply Parameters − P3 − SN/SE/FN LVDS (NROT)
(NOTE: All ground pins (gnd_18, gnd_33, gnd_colpc) should be connected to an external 0 V ground reference.)
vdd_33
Supply voltage, 3.3 V
Idd_33
Current consumption 3.3 V supply (2 / 1 LVDS)
vdd_18
Supply voltage, 1.8 V
Idd_18
Current consumption 1.8 V supply (2 / 1 LVDS)
vdd_pix
Supply voltage, pixel
Idd_pix
Current consumption pixel supply (2 / 1 LVDS)
2/1
Ptot
Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V
P3, 2 LVDS, NROT
P3, 1 LVDS, NROT
420
270
Pstby_lp
Power consumption in low power standby mode
Popt
Power consumption at lower pixel rates
3.2
3.3
95 / 55
1.7
1.8
mA
1.9
55 / 45
3.25
3.3
V
mA
3.35
V
mA
mW
50
mW
3.4
V
Configurable
Power Supply Parameters − P2−SN/SE CMOS
vdd_33
Supply voltage, 3.3 V
Idd_33
Current consumption 3.3 V supply
vdd_18
Supply voltage, 1.8 V
Idd_18
Current consumption 1.8 V supply
vdd_pix
Supply voltage, pixel
Idd_pix
Current consumption pixel supply
Ptot
Total power consumption
Pstby_lp
Power consumption in low power standby mode
Popt
Power consumption at lower pixel rates
3.2
3.3
120
1.7
1.8
3.25
3.3
mA
1.9
10
V
mA
3.35
V
1
mA
420
mW
50
mW
Configurable
I/O − P1, P3 − SN/SE/FN LVDS (EIA/TIA−644): Conforming to standard/additional specifications and deviations listed
fserdata
Data rate on data channels
DDR signaling − 4 data channels, 1 synchronization channel
720
Mbps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All parameters are characterized for DC conditions after thermal equilibrium is established.
6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is
recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high
impedance circuit.
7. Minimum and maximum limits are guaranteed through test and design.
8. Refer to ACSPYTHON1300 available at the Image Sensor Portal for detailed acceptance criteria specifications.
9. For power supply management recommendations, please refer to Application Note AND9158.
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4
NOIP1SN1300A
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6, 7, 8 and 9)
Parameter
Description
Min
fserclock
Clock rate of output clock
Clock output for mesochronous signaling
Vicm
LVDS input common mode level
Tccsk
Channel to channel skew (Training pattern allows per channel
skew correction)
0.3
Typ
1.25
Max
Unit
360
MHz
1.8
V
50
ps
I/O − P2−SN/SE CMOS (JEDEC− JESD8C−01): Conforming to standard/additional specifications and deviations listed
fpardata
Data rate on parallel channels (10−bit)
72
Mbps
Cout
Output load (only capacitive load)
10
pF
tr
Rise time (10% to 90% of input signal)
2.5
4.5
6.5
ns
tf
Fall time (10% to 90% of input signal)
2
3.5
5
ns
Electrical Interface − P1 − SN/SE/FN LVDS
fin
Input clock rate when PLL used
72
MHz
fin
Input clock when LVDS input used
360
MHz
tidc
Input clock duty cycle when PLL used
tj
Input clock jitter
ratspi
(= fin/fspi)
10−bit (4 LVDS channels), PLL used (fin = 72 MHz)
6
10−bit (2 LVDS channels), PLL used (fin = 72 MHz)
12
10−bit (1 LVDS channel), PLL used (fin = 72 MHz)
24
10−bit (4 LVDS channels), LVDS input used (fin = 360 MHz)
30
45
10−bit (2 LVDS channels), LVDS input used (fin = 360 MHz)
60
10−bit (1 LVDS channel), LVDS input used (fin = 360 MHz)
120
8−bit (4 LVDS channels), PLL used (fin = 72 MHz)
6
8−bit (2 LVDS channels), PLL used (fin = 72 MHz)
12
8−bit (1 LVDS channel), PLL used (fin = 72 MHz)
24
8−bit (4 LVDS channels), LVDS input used (fin = 288 MHz)
24
8−bit (2 LVDS channels), LVDS input used (fin = 288 MHz)
48
8−bit (1 LVDS channel), LVDS input used (fin = 288 MHz)
96
50
55
%
20
ps
72
MHz
Electrical Interface − P2−SN/SE CMOS
fin
Input clock rate
tidc
Input clock duty cycle
tj
Input clock jitter
ratspi
(= fin/fspi)
10−bit, PLL bypassed (fin = 72 MHz)
45
50
55
%
20
ps
72
MHz
360
MHz
55
%
20
ps
24
Electrical Interface − P3 − SN/SE/FN LVDS
fin
Input clock rate when PLL used
fin
Input clock when LVDS input used
tidc
Input clock duty cycle when PLL used
tj
Input clock jitter
45
50
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All parameters are characterized for DC conditions after thermal equilibrium is established.
6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is
recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high
impedance circuit.
7. Minimum and maximum limits are guaranteed through test and design.
8. Refer to ACSPYTHON1300 available at the Image Sensor Portal for detailed acceptance criteria specifications.
9. For power supply management recommendations, please refer to Application Note AND9158.
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5
NOIP1SN1300A
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6, 7, 8 and 9)
Parameter
ratspi
(= fin/fspi)
Description
Min
10−bit (2 LVDS channels), PLL used (fin = 72 MHz)
12
10−bit (1 LVDS channel), PLL used (fin = 72 MHz)
24
10−bit (2 LVDS channels), LVDS input used (fin = 360 MHz)
60
10−bit (1 LVDS channel), LVDS input used (fin = 360 MHz)
120
Typ
Max
Unit
Max
Units
Frame Specifications − P1−SN/SE/FN−LVDS (ZROT)
Maximum
Normal ROT
Zero ROT
fps
Frame rate at full resolution
165
210
fps
fps_roi1
Xres x Yres = 1024 x 1024
195
260
fps
fps_roi2
Xres x Yres = 800 x 600
385
545
fps
fps_roi3
Xres x Yres = 640 x 480
545
815
fps
fps_roi4
Xres x Yres = 512 x 512
580
925
fps
fps_roi5
Xres x Yres = 256 x 256
1400
2235
fps
fpix
Pixel rate (4 channels at 72 Mpix/s)
288
Mpix/s
Max
Units
50 / 43
fps
Max
Units
Frame Specifications − P2−SN/SE CMOS
Min
fps
Typ
Frame rate at full resolution (ZROT / NROT)
Frame Specifications − P3−SN/SE/FN LVDS (NROT)
Maximum
2 LVDS
1 LVDS
fps
Frame rate at full resolution
90
45
fps
fps_roi1
Xres x Yres = 1024 x 1024
110
55
fps
fps_roi2
Xres x Yres = 800 x 600
230
120
fps
fps_roi3
Xres x Yres = 640 x 480
340
185
fps
fps_roi4
Xres x Yres = 512 x 512
375
205
fps
fps_roi5
Xres x Yres = 256 x 256
1110
660
fps
fpix
Pixel rate (4 channels at 72 Mpix/s)
144
Mpix/s
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All parameters are characterized for DC conditions after thermal equilibrium is established.
6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is
recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high
impedance circuit.
7. Minimum and maximum limits are guaranteed through test and design.
8. Refer to ACSPYTHON1300 available at the Image Sensor Portal for detailed acceptance criteria specifications.
9. For power supply management recommendations, please refer to Application Note AND9158.
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NOIP1SN1300A
Color Filter Array
The P1SE, P2SE and P3SE sensors are processed with a Bayer RGB color pattern as shown in Figure 2. Pixel (0,0) has a
red filter situated to the bottom left.
Y
Gb
Gr
X
pixel (0;0)
Figure 2. Color Filter Array for the Pixel Array
Quantum Efficiency
60.0%
Red
Gr
Gb
Blue
Mono
50.0%
QE [%]
40.0%
30.0%
20.0%
10.0%
0.0%
300
400
500
600
700
Wavelength [nm]
800
900
Figure 3. Quantum Efficiency Curve for Mono and Color
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1000
1100
NOIP1SN1300A
70
60
QE [%]
50
40
MONO
NIR
30
20
10
0
300
400
500
600
700
800
900
Wavelengths [nm]
Figure 4. Quantum Efficiency Curve for Standard and NIR Mono
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1000
1100
NOIP1SN1300A
Ray Angle and Microlens Array Information
regards to its photodiode. A shift in microlens position
versus photodiode position will cause a tilted angle of peak
photoresponse, here denoted Chief Ray Angle (CRA).
Microlenses and photodiodes are aligned with 0 shift and
CRA in the center of the array, while the shift and CRA
increases radially towards its edges, as illustrated by
Figure 7.
The purpose of the shifted microlenses is to improve the
uniformity of photoresponse when camera lenses with a
finite exit pupil distance are used. The CRA varies nearly
linearly with distance from the center as illustrated in Figure
8, with a corner CRA of approximately 2.7 degrees. This
edge CRA is matching a lens with exit pupil distance of
∼ 80 mm.
An array of microlenses is placed over the CMOS pixel
array in order to improve the absolute responsivity of the
photodiodes. The combined microlens array and pixel array
has two important properties:
1. Angular dependency of photoresponse of a pixel
The photoresponse of a pixel with microlens in the center
of the array to a fixed optical power with varied incidence
angle is as plotted in Figure 5, where definitions of angles fx
and fy are as described by Figure 6.
2. Microlens shift across array and CRA
The microlens array is fabricated with a slightly smaller
pitch than the array of photodiodes. This difference in pitch
creates a varying degree of shift of a pixel’s microlens with
1
0.9
Normalized Response
0.8
0.7
0.6
0.5
0.4
0.3
fx = 0
0.2
fy = 0
0.1
0
−30
−20
−10
0
10
20
30
Incidence Angle fx, fy
[degrees deviation from normal]
Figure 5. Central Pixel Photoresponse to a Fixed Optical Power with Incidence Angle varied along fx and fy.
Note that the Photoresponse peaks near Normal Incidence for Center Pixels.
Figure 6. Definition of Angles used in Figure 5.
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NOIP1SN1300A
Shift
CRA
Center pixel
Edge pixel
(aligned)
(with shift)
Figure 7. Principles of Microlens Shift. The Center Axes of the Microlens and the Photodiode Coincide for the
Center Pixels. For the Edge Pixels, there is a Shift between the Axes of the Microlens and the Photodiode causing
a Peak Response Incidence Angle (CRA) that deviates from the Normal of the Pixel Array.
3
2.7
2.5
CRA [degrees]
2.1
2
1.7
1.5
diagonal
1
x direction
0.5
0
y direction
0
1
2
3
4
Distance from Center [mm]
Figure 8. Variation of Peak Responsivity Angle (CRA) as a Function of Distance from the Center of the Array
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NOIP1SN1300A
OVERVIEW
Figures 9 and 10 give an overview of the major functional blocks of the P1, P3 − SN/SE/FN and P2−SN/SE sensor respectively.
Image Core
Image Core
Image Core Bias
Row Dec od er
Row Dec od er
Image Core Bias
Pixel Array
Column Structure
Automatic
Exposure
Control
(AEC)
Column Structure
Automatic
Exposure
Control
(AEC)
8 analog channels
8 analog channels
Analog Front End (AFE)
Analog Front End (AFE)
8 x 10 bit
digital channels
Control &
Registers
Clock
Distribution
Serializers & LVDS Interface
4 x 10 bit
digital channels
Output MUX
Re set
CMOS Clock
Input
4, 2, 1 Multiplexed LVDS Output Channels
1 LVDS Sync Channel
1 LVDS Clock Channel
SPI Interface
PLL
External Trigger s
Re set
SPI Interface
LVDS Clock
Input
External Trigger s
CMOS Clock
Input
Data Formatting
Clock
Distribution
4 x 10 bit
digital channels
LVDS
Receiver
PLL
8 x 10 bit
digital channels
Control &
Registers
Data Formatting
CMOS Clock
Pixel Array
CMOS Interface
10 bit Parallel Data
Frame Valid Indication
Line Valid Indication
Note: P3 part only has 2,1 Multiplexed LVDS Output Channels
Figure 9. Block Diagram − P1, P3 − SN/SE/FN
Figure 10. Block Diagram − P2−SN/SE
Image Core
Phase Locked Loop
The image core consists of:
• Pixel Array
• Address Decoders and Row Drivers
• Pixel Biasing
The PYTHON 1300 pixel array contains 1280 (H) x
1024 (V) readable pixels with a pixel pitch of 4.8 mm. The
PYTHON 300 and PYTHON 500 image arrays contain
672 (H) x 512 (V) and 832 (H) x 632 (V) readable pixels
respectively, inclusive of 16 pixel rows and 16 pixel
columns at every side to allow for reprocessing or color
reconstruction. The sensors use in−pixel CDS architecture,
which makes it possible to achieve a low noise read out of
the pixel array in global shutter mode with CDS.
The function of the row drivers is to access the image array
line by line, or all lines together, to reset or read the pixel
data. The row drivers are controlled by the on−chip
sequencer and can access the pixel array.
The pixel biasing block guarantees that the data on a pixel
is transferred properly to the column multiplexer when the
row drivers select a pixel line for readout.
The PLL accepts a (low speed) clock and generates the
required high speed clock. Optionally this PLL can be
bypassed. Typical input clock frequency is 72 MHz.
LVDS Clock Receiver
The LVDS clock receiver receives an LVDS clock signal
and distributes the required clocks to the sensor.
Typical input clock frequency is 360 MHz in 10−bit mode
and 288 MHz in 8−bit mode. The clock input needs to be
terminated with a 100 W resistor.
Column Multiplexer
All pixels of one image row are stored in the column
sample−and−hold (S/H) stages. These stages store both the
reset and integrated signal levels.
The data stored in the column S/H stages is read out
through 8 parallel differential outputs operating at a
frequency of 36 MHz. At this stage, the reset signal and
integrated signal values are transferred into an
FPN−corrected differential signal. A programmable gain of
1x, 2x, or 4x can be applied to the signal. The column
multiplexer
also
supports
read−1−skip−1
and
read−2−skip−2 mode. Enabling this mode increases the
frame rate, with a decrease in resolution.
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11
NOIP1SN1300A
Bias Generator
clock, which is skew aligned to the output data channels. The
second LVDS output contains frame format synchronization
codes to serve system−level image reconstruction.
The bias generator generates all required reference
voltages and bias currents used on chip. An external resistor
of 47 kW, connected between pin IBIAS_MASTER and
gnd_33, is required for the bias generator to operate
properly.
Output MUX (P2 only)
The output MUX multiplexes the four data channels to
one channel and transmits the data words using a 10−bit
parallel CMOS interface.
Frame synchronization information is communicated by
means of frame and line valid strobes.
Analog Front End
The AFE contains 8 channels, each containing a PGA and
a 10−bit ADC.
For each of the 8 channels, a pipelined 10−bit ADC is used
to convert the analog image data into a digital signal, which
is delivered to the data formatting block. A black calibration
loop is implemented to ensure that the black level is mapped
to match the correct ADC input level.
Channel Multiplexer
The P1−SN/SE/FN LVDS channel multiplexer provides
a 4:2 and 4:1 feature, in addition to utilizing all 4 output
channels.
The P3− SN/SE/FN LVDS channel multiplexer provides
a 2:1 feature, in addition to utilizing both the output
channels.
Data Formatting
The data block receives data from two ADCs and
multiplexes this data to one data stream. A cyclic
redundancy check (CRC) code is calculated on the passing
data.
A frame synchronization data block transmits
synchronization codes such as frame start, line start, frame
end, and line end indications.
The data block calculates a CRC once per line for every
channel. This CRC code can be used for error detection at the
receiving end.
Sequencer
The sequencer:
• Controls the image core. Starts and stops integration
•
•
•
Serializer and LVDS Interface (P1, P3−SN/SE/FN only)
The serializer and LVDS interface block receives the
formatted (10−bit or 8−bit) data from the data formatting
block. This data is serialized and transmitted by the LVDS
288 MHz output driver.
In 10−bit mode, the maximum output data rate is
720 Mbps per channel. In 8−bit mode, the maximum output
data rate is 576 Mbps per channel.
In addition to the LVDS data outputs, two extra LVDS
outputs are available. One of these outputs carries the output
•
and control pixel readout.
Operates the sensor in master or slave mode.
Applies the window settings. Organizes readouts so that
only the configured windows are read.
Controls the column multiplexer and analog core.
Applies gain settings and subsampling modes at the
correct time, without corrupting image data.
Starts up the sensor correctly when leaving standby
mode.
Automatic Exposure Control
The AEC block implements a control system to modulate
the exposure of an image. Both integration time and gains
are controlled by this block to target a predefined
illumination level.
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12
NOIP1SN1300A
OPERATING MODES
Global Shutter Mode
at the same period of time. The whole pixel core is reset
simultaneously and after the integration time all pixel values
are sampled together on the storage node inside each pixel.
The pixel core is read out line by line after integration. Note
that the integration and readout can occur in parallel or
sequentially. The integration starts at a certain period,
relative to the frame start.
The PYTHON 300, PYTHON 500, and PYTHON 1300
operate in pipelined or triggered global shuttering modes. In
this mode, light integration, light integration takes place on
all pixels in parallel, although subsequent readout is
sequential. Figure 11 shows the integration and readout
sequence for the global shutter. All pixels are light sensitive
Figure 11. Global Shutter Operation
Pipelined Global Shutter Mode
In pipelined global shutter mode, the integration and
readout are done in parallel. Images are continuously read
and integration of frame N is ongoing during readout of the
previous frame N−1. The readout of every frame starts with
a Frame Overhead Time (FOT), during which the analog
value on the pixel diode is transferred to the pixel memory
element. After the FOT, the sensor is read out line per line
and the readout of each line is preceded by the Row
Overhead Time (ROT). Figure 12 shows the exposure and
readout time line in pipelined global shutter mode.
Reset
N
Integration Time
Handling
Readout
Handling
Master Mode
The PYTHON 300, PYTHON 500, and PYTHON 1300
operate in pipelined or triggered global shuttering modes. In
this mode, light, the integration time is set through the
register interface and the sensor integrates and reads out the
images autonomously. The sensor acquires images without
any user interaction.
Exposure Time N
FOT
Reset
N+1
Exposure Time N+1
FOT
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
É
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
É
FOT
ROT
Readout Frame N-1
FOT
Readout Frame N
FOT
Line Readout
Figure 12. Integration and Readout for Pipelined Shutter
of reset and integration starts. The integration continues
until the user or system deasserts the external pin. Upon a
falling edge of the trigger input, the image is sampled and the
readout begins. Figure 13 shows the relation between the
external trigger signal and the exposure/readout timing.
Slave Mode
The slave mode adds more manual control to the sensor.
The integration time registers are ignored in this mode and
the integration time is instead controlled by an external pin.
As soon as the control pin is asserted, the pixel array goes out
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13
NOIP1SN1300A
External Trigger
Integration Time
Handling
Readout
Handling
Reset
N
FOT
Exposure Time N
FOT
Readout N−1
Reset
N+1
FOT
Exposure T im e N+1
Readout N
FOT
FOT
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉ
ROT
Line Readout
Figure 13. Pipelined Shutter Operated in Slave Mode
Triggered Global Shutter Mode
The triggered global mode can also be controlled in a
master or in a slave mode.
Master Mode
In this mode, a rising edge on the synchronization pin is
used to trigger the start of integration and readout. The
integration time is defined by a register setting. The sensor
autonomously integrates during this predefined time, after
which the FOT starts and the image array is readout
sequentially. A falling edge on the synchronization pin does
not have any impact on the readout or integration and
subsequent frames are started again for each rising edge.
Figure 14 shows the relation between the external trigger
signal and the exposure/readout timing.
If a rising edge is applied on the external trigger before the
exposure time and FOT of the previous frame is complete,
it is ignored by the sensor.
In this mode, manual intervention is required to control
both the integration time and the start of readout. After the
integration time, indicated by a user controlled pin, the
image core is read out. After this sequence, the sensor goes
to an idle mode until a new user action is detected.
The three main differences with the pipelined global
shutter mode are:
• Upon user action, one single image is read.
• Normally, integration and readout are done
sequentially. However, the user can control the sensor
in such a way that two consecutive batches are
overlapping, that is, having concurrent integration and
readout.
• Integration and readout is under user control through an
external pin.
This mode requires manual intervention for every frame.
The pixel array is kept in reset state until requested.
No effect on falling edge
External Trigger
Integration Time
Handling
Reset
N
Exposure Time N
FOT
Reset
N+1
Exposure Time N+1
FOT
Readout N
FOT
Register Controlled
Readout
Handling
FOT
Readout N-1
FOT
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
É
ROT
Line Readout
Figure 14. Triggered Shutter Operated in Master Mode
FOT starts. The analog value on the pixel diode is
transferred to the pixel memory element and the image
readout can start. A request for a new frame is started when
the synchronization pin is asserted again.
Slave Mode
Integration time control is identical to the pipelined
shutter slave mode. An external synchronization pin
controls the start of integration. When it is de−asserted, the
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14
NOIP1SN1300A
Normal and Zero Row Overhead Time (ROT) Modes
In Reduced/Zero ROT operation mode (refer to
Figure 16), the row blanking and kernel readout occur in
parallel. This mode is called reduced ROT as a part of the
ROT is done while the image row is readout. The actual ROT
can thus be longer, however the perceived ROT will be
shorter (‘overhead’ spent per line is reduced).
This operation mode can be used for two reasons:
• Reduced total line time.
• Lower power due of reduced clock−rate.
In pipelined global shutter mode, the integration and
readout are done in parallel. Images are continuously read
out and integration of frame N is ongoing during readout of
the previous frame N−1. The readout of every frame starts
with a Frame Overhead Time (FOT), during which the
analog value of the pixel diode is transferred to the pixel
memory element. After the FOT, the sensor is read out line
by line and the readout of each line is preceded by a Row
Overhead Time (ROT) as shown in Figure 15.
(
FOT
)
ROT
ys
Readout
ys
NOTE: Zero ROT is not supported on P3 devices.
ROT
ys+1
Readout
ys
ROT
ye
Readout
ye
Valid Data
Figure 15. Integration and Readout Sequence of the Sensor Operating in Pipelined Global Shutter Mode with
Normal ROT Readout.
(
FOT
)
ROT
ys
(blanked out)
ROT
ys+1
Readout
ys
ROT
ye
Readout
ye−1
ROT
dummy
Readout
ye
Valid Data
Figure 16. Integration and Readout Sequence of the Sensor Operating in Pipelined Global Shutter Mode with
Zero ROT Readout.
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15
NOIP1SN1300A
SENSOR OPERATION
Flowchart
Figure 17 shows the sensor operation flowchart. The sensor has six different ‘states’. Every state is indicated with the oval
circle. These states are Power off, Low power standby, Standby (1), Standby (2), Idle, Running.
Power Off
Power Down
Sequence
Power Up Sequence
Low-Power Standby
Disable Clock Management
Part 1
Poll Lock Indication
(only when PLL is enabled)
Standby (1)
Enable Clock Management - Part 2
(First Pass after Hard Reset)
Intermediate Standby
Required Register
Upload
Standby (2)
Sensor (re-)configuration
(optional)
Soft Power-Down
Soft Power-Up
Sensor (re-)configuration
(optional)
Idle
Disable Sequencer
Enable Sequencer
Running
Sensor (re-)configuration
(optional)
Figure 17. Sensor Operation Flowchart
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16
Assertion of reset_n Pin
Enable Clock Management - Part 2
(Not First Pass after Hard Reset)
Disable Clock Management
Part 2
Enable Clock Management - Part 1
NOIP1SN1300A
Sensor States
Running
Low Power Standby
In running state, the sensor is enabled and grabbing
images. The sensor can be operated in global master/slave
modes.
In low power standby state, all power supplies are on, but
internally every block is disabled. No internal clock is
running (PLL / LVDS clock receiver is disabled).
All register settings are unchanged.
Only a subset of the SPI registers is active for read/write
in order to be able to configure clock settings and leave the
low power standby state. The only SPI registers that should
be touched are the ones required for the ‘Enable Clock
Management’ action described in Enable Clock
Management − Part 1 on page 18
User Actions: Power Up Functional Mode Sequences
Power Up Sequence
Figure 18 shows the power up sequence of the sensor. The
figure indicates that the first supply to ramp−up is the
vdd_18 supply, followed by vdd_33 and vdd_pix
respectively. It is important to comply with the described
sequence. Any other supply ramping sequence may lead to
high current peaks and, as consequence, a failure of the
sensor power up.
The clock input should start running when all supplies are
stabilized. When the clock frequency is stable, the reset_n
signal can be de−asserted. After a wait period of 10 ms, the
power up sequence is finished and the first SPI upload can
be initiated.
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
Standby (1)
In standby state, the PLL/LVDS clock receiver is running,
but the derived logic clock signal is not enabled.
Standby (2)
In standby state, the derived logic clock signal is running.
All SPI registers are active, meaning that all SPI registers
can be accessed for read or write operations. All other blocks
are disabled.
Idle
In the idle state, all internal blocks are enabled, except the
sequencer block. The sensor is ready to start grabbing
images as soon as the sequencer block is enabled.
clock input
reset_n
vdd_18
vdd_33
vdd_pix
SPI Upload
> 10us
> 10us
> 10us
> 10us
> 10us
Figure 18. Power Up Sequence
Enable Clock Management − Part 1
customers under NDA at the ON Semiconductor Image
Sensor Portal:
https://www.onsemi.com/PowerSolutions/myon/erCispFol
der.do
In the serial modes, if the PLL is not used, the LVDS clock
input must be running.
In the P2−SN/SE 10−bit parallel mode, the PLL is
bypassed. The clk_pll clock is used as sensor clock.
It is important to follow the upload sequence listed in
Table 6.
The ‘Enable Clock Management’ action configures the
clock management blocks and activates the clock generation
and distribution circuits in a pre−defined way. First, a set of
clock settings must be uploaded through the SPI register.
These settings are dependent on the desired operation mode
of the sensor.
Table 6 shows the SPI uploads to be executed to configure
the sensor for P1, P3 − SN/SE/FN 10−bit serial mode, with
the PLL, and all available LVDS channels.
Note that the SPI uploads to be executed to configure the
sensor for other supported modes (P1−SN/SE/FN 8−bit
serial, P2−SN/SE 10−bit parallel, ...) are available to
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17
NOIP1SN1300A
Use of Phase Locked Loop
Check the PLL_lock flag 24[0] by reading the SPI
register. When the flag is set, the ‘Enable Clock
Management− Part 2’ action can be continued. When PLL
is not used, this step can be bypassed as shown in Figure 17
on page 16.
If PLL is used, the PLL is started after the upload of the
SPI registers. The PLL requires (dependent on the settings)
some time to generate a stable output clock. A lock detect
circuit detects if the clock is stable. When complete, this is
flagged in a status register.
NOTE: The lock detect status must not be checked for
the P2−SN/SE sensor.
Table 6. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 1
Upload #
Address
Data
Description
P1, P3 − SN/SE/FN 10−bit mode with PLL
1
2
2
8
3
0x0000
Monochrome sensor
0x0001
Color sensor
0x0000
Release PLL soft reset
16
0x0003
Enable PLL
4
17
0x2113
Configure PLL
5
20
0x0000
Configure clock management
6
26
0x2280
Configure PLL lock detector
7
27
0x3D2D
Configure PLL lock detector
8
32
0x7004
Configure clock management for P1 only
0x6014
Configure clock management for P3 only
0x0002
Monochrome sensor
0x0003
Color sensor
0x0007
Enable PLL bypass mode
P2−SN/SE 10−bit mode
1
2
2
16
3
20
0x0000
Configure clock management
4
32
0x700C
Configure clock management
Enable Clock Management − Part 2
The next step to configure the clock management consists
of SPI uploads which enables all internal clock distribution.
The required uploads are listed in Table 4. Note that it is
important to follow the upload sequence listed in Table 7.
Table 7. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 2
Upload #
Address
Data
Description
P1, P3 − SN/SE/FN 10−bit mode with PLL
1
9
0x0000
Release clock generator soft reset
2
32
0x7006
Enable logic clock for P1 only
0x6016
Enable logic clock for P3 only
34
0x0001
Enable logic blocks
1
9
0x0000
Release clock generator soft reset
2
32
0x700E
Enable logic clock
3
34
0x0001
Enable logic blocks
3
P2−SN/SE 10−bit mode
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18
NOIP1SN1300A
Required Register Upload
In this phase, the ‘reserved’ register settings are uploaded
through the SPI register. Different settings are not allowed
and may cause the sensor to malfunction. The required
uploads are listed in Table 8.
Table 8. REQUIRED REGISTER UPLOAD
Upload #
Address
P1−SN/SE/FN 10−bit
mode with PLL
(4 LVDS ZROT)
Address
P2−SN/SE 10−bit
mode (ZROT)
Address
P3−SN/SE/FN 10−bit
mode with PLL (2 LVDS
NROT)
1
41
0x085F
41
0x085F
41
0x085F
2
42
0x4110
42
0x4110
42
0x4110
3
43
0x0008
43
0x0008
43
0x0008
4
65
0x382B
65
0x382B
65
0x382B
5
66
0x53C8
66
0x53C8
66
0x53C4
6
67
0x0665
67
0x0344
67
0x0645
7
68
0x0085
68
0x0085
68
0x0085
8
69
0x0088
69
0x0088
69
0x0048
9
70
0x1111
70
0x1111
70
0x1111
10
72
0x0010
72
0x0010
72
0x0017
11
128
0x4714
128
0x4714
128
0x4714
12
129
0x8001
129
0xA001
129
0x8001
13
171
0x1002
130
0x0001
171
0x1002
14
175
0x0080
171
0x1002
175
0x0080
15
176
0x00E6
175
0x0080
176
0x00E6
16
177
0x0400
176
0x00E6
177
0x0400
17
192
0x080C
177
0x0400
192
0x0800
18
194
0x0224
192
0x080C
194
0x0224
19
197
0x0306
194
0x0224
197
0x0306
20
204
0x01E1
197
0x0103
204
0x01E3
21
207
0x0000
204
0x01E1
207
0x0000
22
211
0x0E49
207
0x0000
211
0x0E39
23
215
0x111F
211
0x0E49
215
0x111F
24
216
0x7F00
215
0x111F
216
0x7F00
25
219
0x0020
216
0x7F00
219
0x0020
26
220
0x3A28
219
0x0017
220
0x3728
27
221
0x624D
220
0x2C1C
221
0x6245
28
222
0x624D
221
0x623C
222
0x6230
29
224
0x3E5E
222
0x623C
224
0x3E5E
30
227
0x0000
224
0x3E02
227
0x0000
31
250
0x2081
227
0x0000
250
0x2081
32
384
0xC800
250
0x2081
384
0xC800
33
385
0xFB1F
384
0xC800
385
0xFB1F
34
386
0xFB1F
385
0xFB1F
386
0xFB1F
35
387
0xFB12
386
0xFB17
387
0xFB12
36
388
0xF903
387
0xF802
388
0xF903
37
389
0xF802
388
0xF003
389
0xF802
38
390
0xF30F
389
0xF30F
390
0xF30F
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19
NOIP1SN1300A
Table 8. REQUIRED REGISTER UPLOAD
Upload #
Address
P1−SN/SE/FN 10−bit
mode with PLL
(4 LVDS ZROT)
Address
P2−SN/SE 10−bit
mode (ZROT)
Address
P3−SN/SE/FN 10−bit
mode with PLL (2 LVDS
NROT)
39
391
0xF30F
390
0xF30F
391
0xF30F
40
392
0xF30F
391
0xF30F
392
0xF30F
41
393
0xF30A
392
0xF101
393
0xF30A
42
394
0xF101
393
0xF005
394
0xF101
43
395
0xF00A
394
0xF247
395
0xF00A
44
396
0xF24B
395
0xF226
396
0xF24B
45
397
0xF226
396
0xF002
397
0xF226
46
398
0xF001
397
0xF402
398
0xF001
47
399
0xF402
398
0xF001
399
0xF402
48
400
0xF001
399
0xF20F
400
0xF001
49
401
0xF402
400
0xF20F
401
0xF402
50
402
0xF001
401
0xF205
402
0xF001
51
403
0xF401
402
0xF002
403
0xF401
52
404
0xF007
403
0xC801
404
0xF007
53
405
0xF20F
404
0xCC01
405
0xF20F
54
406
0xF20F
405
0xC802
406
0xF20F
55
407
0xF202
406
0xC800
407
0xF202
56
408
0xF006
407
0xC800
408
0xF006
57
409
0xEC02
408
0xC801
409
0xEC02
58
410
0xE801
409
0xCC04
410
0xE801
59
411
0xEC02
410
0xC801
411
0xEC02
60
412
0xE801
411
0xC800
412
0xE801
61
413
0xEC02
412
0x0030
413
0xEC02
62
414
0xC801
413
0x0078
414
0xC801
63
415
0xC800
414
0x0072
415
0xC800
64
416
0xC800
415
0x1071
416
0xC800
65
417
0xCC02
416
0x3073
417
0xCC02
66
418
0xC801
417
0x1073
418
0xC801
67
419
0xCC02
418
0x0072
419
0xCC02
68
420
0xC801
419
0x0031
420
0xC801
69
421
0xCC02
420
0x00B1
421
0xCC02
70
422
0xC805
421
0x01B8
422
0xC805
71
423
0xC800
422
0x00B2
423
0xC800
72
424
0x0030
423
0x10B1
424
0x0030
73
425
0x207C
424
0x30B3
425
0x2073
74
426
0x2071
425
0x10B3
426
0x2071
75
427
0x0074
426
0x00B2
427
0x0071
76
428
0x107F
427
0x0030
428
0x1079
77
429
0x1072
428
0x0030
429
0x1072
78
430
0x1074
429
0x0178
430
0x0073
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NOIP1SN1300A
Table 8. REQUIRED REGISTER UPLOAD
Upload #
Address
P1−SN/SE/FN 10−bit
mode with PLL
(4 LVDS ZROT)
Address
P2−SN/SE 10−bit
mode (ZROT)
Address
P3−SN/SE/FN 10−bit
mode with PLL (2 LVDS
NROT)
79
431
0x0076
430
0x0072
431
0x0031
80
432
0x0031
431
0x1071
432
0x21B6
81
433
0x21BB
432
0x3073
433
0x20B1
82
434
0x20B1
433
0x1073
434
0x00B1
83
435
0x20B1
434
0x0072
435
0x10B9
84
436
0x00B1
435
0x0031
436
0x10B2
85
437
0x10BF
436
0x00B1
437
0x00B1
86
438
0x10B2
437
0x00B8
438
0x0030
87
439
0x10B4
438
0x00B2
439
0x0030
88
440
0x00B1
439
0x10B1
440
0x2176
89
441
0x0030
440
0x30B3
441
0x2071
90
442
0x0030
441
0x10B3
442
0x2071
91
443
0x217B
442
0x00B2
443
0x0071
92
444
0x2071
443
0x0030
444
0x1079
93
445
0x2071
444
0x0030
445
0x1072
94
446
0x0074
445
0x207C
446
0x0073
95
447
0x107F
446
0x2071
447
0x0031
96
448
0x1072
447
0x0073
448
0x20B3
97
449
0x1074
448
0x017A
449
0x00B1
98
450
0x0076
449
0x0078
450
0x10B9
99
451
0x0031
450
0x1074
451
0x10B2
100
452
0x20BB
451
0x0076
452
0x00B1
101
453
0x20B1
452
0x0031
453
0x0030
102
454
0x20B1
453
0x21BB
103
455
0x00B1
454
0x20B1
104
456
0x10BF
455
0x20B1
105
457
0x10B2
456
0x00B1
106
458
0x10B4
457
0x10BF
107
459
0x00B1
458
0x10B2
108
460
0x0030
459
0x10B4
109
461
0x0030
460
0x00B1
110
462
0x207C
461
0x0030
111
463
0x2071
112
464
0x0073
113
465
0x017A
114
466
0x0078
115
467
0x1074
116
468
0x0076
117
469
0x0031
118
470
0x21BB
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NOIP1SN1300A
Table 8. REQUIRED REGISTER UPLOAD
Upload #
Address
P1−SN/SE/FN 10−bit
mode with PLL
(4 LVDS ZROT)
119
471
0x20B1
120
472
0x20B1
121
473
0x00B1
122
474
0x10BF
123
475
0x10B2
124
476
0x10B4
125
477
0x00B1
126
478
0x0030
P2−SN/SE 10−bit
mode (ZROT)
Address
Address
P3−SN/SE/FN 10−bit
mode with PLL (2 LVDS
NROT)
NOTE: Register uploads for other supported operation modes can be accessed at the Image Sensor Portal on MyON.
Soft Power Up
During the soft power up action, the internal blocks are
enabled and prepared to start processing the image data
stream. This action exists of a set of SPI uploads. The soft
power up uploads are listed in Table 9.
Table 9. SOFT POWER UP REGISTER UPLOAD
Upload #
Address
Data
Description
P1, P3 − SN/SE/FN 10−bit mode with PLL (P1 in ZROT, P3 in NROT)
1
10
0x0000
Release soft reset state
2
32
0x7007
Enable analog clock for P1
0x6017
Enable analog clock for P3
3
40
0x0003
Enable column multiplexer
4
42
0x4113
Configure image core
5
48
0x0001
Enable AFE
6
64
0x0001
Enable biasing block
7
72
0x0017
Enable charge pump
8
112
0x0007
Enable LVDS transmitters
P2−SN/SE 10−bit mode (ZROT)
1
10
0x0000
Release soft reset state
2
32
0x700F
Enable analog clock
3
40
0x0003
Enable column multiplexer
4
42
0x4113
Configure image core
5
48
0x0001
Enable AFE
6
64
0x0001
Enable biasing block
7
72
0x0017
Enable charge pump
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NOIP1SN1300A
Enable Sequencer
During the ‘Enable Sequencer’ action, the frame grabbing
sequencer is enabled. The sensor starts grabbing images in
the configured operation mode. Refer to Sensor States on
page 17.
The ‘Enable Sequencer’ action consists of a set of register
uploads. The required uploads are listed in Table 10.
Table 10. ENABLE SEQUENCER REGISTER UPLOAD
Upload #
Address
Data
Description
1
192
0x080D
Enable Sequencer for P1 in ZROT
0x0801
Enable Sequencer for P3 in NROT
User Actions: Functional Modes to Power Down Sequences
Disable Sequencer
During the ‘Disable Sequencer’ action, the frame
grabbing sequencer is stopped. The sensor stops grabbing
images and returns to the idle mode.
The ‘Disable Sequencer’ action consists of a set of register
uploads. as listed in Table 11.
Table 11. DISABLE SEQUENCER REGISTER UPLOAD
Upload #
Address
Data
1
192
0x080C
Disable sequencer for P1 in ZROT
Description
0x0800
Disable sequencer for P3 in NROT
Soft Power Down
During the soft power down action, the internal blocks are
disabled and the sensor is put in standby state to reduce the
current dissipation. This action exists of a set of SPI uploads.
The soft power down uploads are listed in Table 12.
Table 12. SOFT POWER DOWN REGISTER UPLOAD
Upload #
Address
Data
Description
P1, P3−SN/SE/FN 10−bit mode with PLL (P1 in ZROT, P3 in NROT)
1
10
0x0999
Soft reset
2
32
0x7006
Disable analog clock for P1
0x6016
Disable analog clock for P3
3
40
0x0000
Disable column multiplexer
4
42
0x4110
Image core config
5
48
0x0000
Disable AFE
6
64
0x0000
Disable biasing block
7
72
0x0010
Disable charge pump
8
112
0x0000
Disable LVDS transmitters
P2−SN/SE 10−bit mode (ZROT)
1
10
0x0999
Soft reset
2
32
0x700E
Disable analog clock
3
40
0x0000
Disable column multiplexer
4
42
0x4110
Image core config
5
48
0x0000
Disable AFE
6
64
0x0000
Disable biasing block
7
72
0x0010
Disable charge pump
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NOIP1SN1300A
Disable Clock Management − Part 2
The ‘Disable Clock Management’ action stops the
internal clocking to further decrease the power dissipation.
This action can be implemented with the SPI uploads as
shown in Table 13.
Table 13. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 2
Upload #
Address
Data
Description
P1, P3 − SN/SE/FN 10−bit mode with PLL
1
9
0x0000
Soft reset clock generator
2
32
0x7004
Disable logic clock for P1
0x6014
Disable logic clock for P3
3
34
0x0000
Disable logic blocks
1
9
0x0000
Soft reset clock generator
2
32
0x700C
Disable logic clock
3
34
0x0000
Disable logic blocks
P2−SN/SE 10−bit mode
Disable Clock Management − Part 1
The ‘Disable Clock Management’ action stops the
internal clocking to further decrease the power dissipation.
This action can be implemented with the SPI uploads as
shown in Table 14.
Table 14. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 1
Upload #
Address
Data
Description
P1, P3 − SN/SE/FN 10−bit mode with PLL
1
8
0x0099
Soft reset PLL
2
16
0x0000
Disable PLL
Power Down Sequence
Figure 19 illustrates the timing diagram of the preferred
power down sequence. It is important that the sensor is in
reset before the clock input stops running. Otherwise, the
internal PLL becomes unstable and the sensor gets into an
unknown state. This can cause high peak currents.
The same applies for the ramp down of the power
supplies. The preferred order to ramp down the supplies is
first vdd_pix, second vdd_33, and finally vdd_18. Any other
sequence can cause high peak currents.
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
clock input
reset_n
vdd_18
vdd_33
vdd_pix
> 10us
> 10us
> 10us
> 10us
Figure 19. Power Down Sequence
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NOIP1SN1300A
Sensor Re−configuration
Sensor Configuration
During the standby, idle, or running state several sensor
parameters can be reconfigured.
• Frame Rate and Exposure Time: Frame rate and
exposure time changes can occur during standby, idle,
and running states by modifying registers 199 to 203.
Refer to page 30−32 for more information.
• Signal Path Gain: Signal path gain changes can occur
during standby, idle, and running states by modifying
registers 204/205. Refer to page 37 for more
information.
• Windowing: Changes with respect to windowing can
occur during standby, idle, and running states. Refer to
Multiple Window Readout on page 32 for more
information.
• Subsampling: Changes of the subsampling mode can
occur during standby, idle, and running states by
modifying register 192. Refer to Subsampling on
page 33 for more information.
• Shutter Mode: The shutter mode can only be changed
during standby or idle mode by modifying register 192.
Reconfiguring the shutter mode during running state is
not supported.
This device contains multiple configuration registers.
Some of these registers can only be configured while the
sensor is not acquiring images (while register 192[0] = 0),
while others can be configured while the sensor is acquiring
images. For the latter category of registers, it is possible to
distinguish the register set that can cause corrupted images
(limited number of images containing visible artifacts) from
the set of registers that are not causing corrupted images.
These three categories are described here.
Static Readout Parameters
Some registers are only modified when the sensor is not
acquiring images. Re−configuration of these registers while
images are acquired can cause corrupted frames or even
interrupt the image acquisition. Therefore, it is
recommended to modify these static configurations while
the sequencer is disabled (register 192[0] = 0). The registers
shown in Table 15 should not be reconfigured during image
acquisition. A specific configuration sequence applies for
these registers. Refer to the operation flow and startup
description.
Table 15. STATIC READOUT PARAMETERS
Group
Addresses
Description
Clock generator
32
Configure according to recommendation
Image core
40
Configure according to recommendation
AFE
48
Configure according to recommendation
Bias
64–71
Configure according to recommendation
LVDS
112
Configure according to recommendation
192 [6:1]
Operation modes are: • triggered_mode
• slave_mode
Sequencer mode selection
All reserved registers
Keep reserved registers to their default state, unless otherwise described in the
recommendation
Dynamic Configuration Potentially Causing Image Artifacts
The category of registers as shown in Table 16 consists of configurations that do not interrupt the image acquisition process,
but may lead to one or more corrupted images during and after the re−configuration. A corrupted image is an image containing
visible artifacts. A typical example of a corrupted image is an image which is not uniformly exposed.
The effect is transient in nature and the new configuration is applied after the transient effect.
Table 16. DYNAMIC CONFIGURATION POTENTIALLY CAUSING IMAGE ARTIFACTS
Group
Addresses
Description
Black level configuration
128–129
197[8]
Re−configuration of these registers may have an impact on the black−level
calibration algorithm. The effect is a transient number of images with incorrect black
level compensation.
Sync codes
129[13]
116–126
Incorrect sync codes may be generated during the frame in which these registers
are modified.
Datablock test configurations
144, 146–150
Modification of these registers may generate incorrect test patterns during
a transient frame.
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NOIP1SN1300A
Dynamic Readout Parameters
as shown in Table 17. Some re−configuration may lead to
one frame being blanked. This happens when the
modification requires more than one frame to settle. The
image is blanked out and training patterns are transmitted on
the data and sync channels.
It is possible to reconfigure the sensor while it is acquiring
images. Frame−related parameters are internally
re−synchronized to frame boundaries, such that the
modified parameter does not affect a frame that has already
started. However, there can be restrictions to some registers
Table 17. DYNAMIC READOUT PARAMETERS
Group
Addresses
Subsampling/binning
192[7]
192[8]
Description
Subsampling or binning is synchronized to a new frame start.
Black lines
197
No blanking in global shutter mode
Dummy lines
198
No blanking in global shutter mode.
ROI configuration
195
256–279
A ROI switch is only detected when a new window is selected as the active window
(re−configuration of register 195). Re−configuration of the ROI dimension of the active
window does not lead to a frame blank and can cause a corrupted image.
Exposure
re−configuration
199−203
Exposure re−configuration does not cause artifact. However, a latency of one frame is
observed unless reg_seq_exposure_sync_mode is set to ‘1’ in triggered global mode
(master).
Gain re−configuration
204
Gains are synchronized at the start of a new frame. Optionally, one frame latency can be
incorporated to align the gain updates to the exposure updates
(refer to register 204[13] − gain_lat_comp).
Freezing Active Configurations
registers and uses them for the coming frames. The freezing
of the active set of registers can be programmed in the
sync_configuration registers, which can be found at the SPI
address 206.
Figure 20 shows a re−configuration that does not use the
sync_configuration option. As depicted, new SPI
configurations are synchronized to frame boundaries.
Figure 21 shows the usage of the sync_configuration
settings. Before uploading a set of registers, the
corresponding sync_configuration is de−asserted. After the
upload is completed, the sync_configuration is asserted
again and the sensor resynchronizes its set of registers to the
coming frame boundaries. As seen in the figure, this ensures
that the uploads performed at the end of frame N+2 and the
start of frame N+3 become active in the same frame (frame
N+4).
Though the readout parameters are synchronized to frame
boundaries, an update of multiple registers can still lead to
a transient effect in the subsequent images, as some
configurations require multiple register uploads. For
example, to reconfigure the exposure time in master global
mode, both the fr_length and exposure registers need to be
updated. Internally, the sensor synchronizes these
configurations to frame boundaries, but it is still possible
that the re−configuration of multiple registers spans over
two or even more frames. To avoid inconsistent
combinations, freeze the active settings while altering the
SPI registers by disabling synchronization for the
corresponding functionality before re−configuration. When
all registers are uploaded, re−enable the synchronization.
The sensor’s sequencer then updates its active set of
Time Line
Frame NFrame N+1 Frame N+2 Frame N+3
Frame N+4
SPI Registers
Active Registers
Figure 20. Frame Synchronization of Configurations (no freezing)
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NOIP1SN1300A
Frame NFrame N+1 Frame N+2 Frame N+3 Frame N+4
Time Line
sync_configuration
This configuration is not taken into
account as sync_register is inactive.
SPI Registers
Active Registers
Figure 21. Re−configuration Using Sync_configuration
NOTE: SPI updates are not taken into account while sync_configuration is inactive. The active configuration is frozen
for the sensor. Table 18 lists the several sync_configuration possibilities along with the respective registers being
frozen.
Table 18. ALTERNATE SYNC CONFIGURATIONS
Group
sync_black_lines
sync_dummy_lines
sync_exposure
sync_gain
sync_roi
Affected Registers
black_lines
Description
Update of black line configuration is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
dummy_lines
Update of dummy line configuration is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
mult_timer
fr_length
exposure
Update of exposure configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
mux_gainsw
afe_gain
roi_active0[7:0]
subsampling
binning
Update of gain configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
Update of active ROI configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
Note: The window configurations themselves are not frozen. Re−configuration of
active windows is not gated by this setting.
Window Configuration
Global Shutter Mode
Black Calibration
Up to 8 windows can be defined in global shutter mode
(pipelined or triggered). The windows are defined by
registers 256 to 279. Each window can be activated or
deactivated separately using register 195. It is possible to
reconfigure the inactive windows while the sensor is
acquiring images.
Switching between predefined windows is achieved by
activation of the respective windows. This way a minimum
number of registers need to be uploaded when it is necessary
to switch between two or more sets of windows. As an
example of this, scanning the scene at higher frame rates
using multiple windows and switching to full frame capture
when the object is tracked. Switching between the two
modes only requires an upload of one register.
The sensor automatically calibrates the black level for
each frame. Therefore, the device generates a configurable
number of electrical black lines at the start of each frame.
The desired black level in the resulting output interface can
be configured and is not necessarily targeted to ‘0’.
Configuring the target to a higher level yields some
information on the left side of the black level distribution,
while the other end of the distribution tail is clipped to ‘0’
when setting the black level target to ‘0’.
The black level is calibrated for the 8 columns contained
in one kernel. This implies 8 black level offsets are generated
and applied to the corresponding columns. Configurable
parameters for the black−level algorithm are listed in
Table 19.
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NOIP1SN1300A
Table 19. CONFIGURABLE PARAMETERS FOR BLACK LEVEL ALGORITHM
Group
Addresses
Description
black_lines
This register configures the number of black lines that are generated at the start of a
frame. At least one black line must be generated. The maximum number is 255.
Note: When the automatic black−level calibration algorithm is enabled, make sure that this
register is configured properly to produce sufficient black pixels for the black−level filtering.
The number of black pixels generated per line is dependent on the operation mode and
window configurations:
Each black line contains 160 kernels.
gate_first_line
When asserting this configuration, the first black line of the frame is blanked out and is not
used for black calibration. It is recommended to enable this functionality, because the first
line can have a different behavior caused by boundary effects. When enabling, the number
of black lines must be set to at least two in order to have valid black samples for the
calibration algorithm.
auto_blackcal_enable
Internal black−level calibration functionality is enabled when set to ‘1’. Required black level
offset compensation is calculated on the black samples and applied to all image pixels.
When set to ‘0’, the automatic black−level calibration functionality is disabled. It is possible
to apply an offset compensation to the image pixels, which is defined by the registers
129[10:1].
Note: Black sample pixels are not compensated; the raw data is sent out to provide
external statistics and, optionally, calibrations.
129[9:1]
blackcal_offset
Black calibration offset that is added or subtracted to each regular pixel value when auto_blackcal_enable is set to ‘0’. The sign of the offset is determined by register 129[10]
(blackcal_offset_dec).
Note: All channels use the same offset compensation when automatic black calibration is
disabled. The calculated black calibration factors are frozen when this register is set to
0x1FF (all−‘1’) in auto calibration mode. Any value different from 0x1FF re−enables the
black calibration algorithm. This freezing option can be used to prevent eventual frame to
frame jitter on the black level as the correction factors are recalculated every frame. It is
recommended to enable the black calibration regularly to compensate for temperature
changes.
129[10]
blackcal_offset_dec
Sign of blackcal_offset. If set to ‘0’, the black calibration offset is added to each pixel. If set
to ‘1’, the black calibration offset is subtracted from each pixel.
This register is not used when auto_blackcal_enable is set to ‘1’.
black_samples
The black samples are low−pass filtered before being used for black level calculation. The
more samples are taken into account, the more accurate the calibration, but more samples
require more black lines, which in turn affects the frame rate.
The effective number of samples taken into account for filtering is 2^ black_samples.
Note: An error is reported by the device if more samples than available are requested
(refer to register 136).
Black Line Generation
197[7:0]
197[8]
Black Value Filtering
129[0]
128[10:8]
Black Level Filtering Monitoring
136
blackcal_error0
An error is reported by the device if there are requests for more samples than are available
(each bit corresponding to one data path). The black level is not compensated correctly if
one of the channels indicates an error. There are three possible methods to overcome this
situation and to perform a correct offset compensation:
• Increase the number of black lines such that enough samples are generated at the
cost of increasing frame time (refer to register 197).
• Relax the black calibration filtering at the cost of less accurate black level determination (refer to register 128).
• Disable automatic black level calibration and provide the offset via SPI register upload.
Note that the black level can drift in function of the temperature. It is thus recommended
to perform the offset calibration periodically to avoid this drift.
NOTE: The maximum number of samples taken into account for black level statistics is half the number of kernels.
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NOIP1SN1300A
Serial Peripheral Interface
The sck clock is passed through to the sensor as
indicated in Figure 22. The sensor samples this
data on a rising edge of the sck clock (mosi needs
to be driven by the system on the falling edge of
the sck clock).
5. The tenth bit sent by the master indicates the type
of transfer: high for a write command, low for a
read command.
6. Data transmission:
- For write commands, the master continues
sending the 16−bit data, most significant bit first.
- For read commands, the sensor returns the
requested address on the miso pin, most significant
bit first. The miso pin must be sampled by the
system on the falling edge of sck (assuming
nominal system clock frequency and maximum
10 MHz SPI frequency).
7. When data transmission is complete, the system
deselects the sensor one clock period after the last
bit transmission by pulling ss_n high.
Note that the maximum frequency for the SPI interface
scales with the input clock frequency, bit depth and LVDS
output multiplexing as described in Table 5.
Consecutive SPI commands can be issued by leaving at
least two SPI clock periods between two register uploads.
Deselect the chip between the SPI uploads by pulling the
ss_n pin high.
The sensor configuration registers are accessed through
an SPI. The SPI consists of four wires:
• sck: Serial Clock
• ss_n: Active Low Slave Select
• mosi: Master Out, Slave In, or Serial Data In
• miso: Master In, Slave Out, or Serial Data Out
The SPI is synchronous to the clock provided by the
master (sck) and asynchronous to the sensor’s system clock.
When the master wants to write or read a sensor’s register,
it selects the chip by pulling down the Slave Select line
(ss_n). When selected, data is sent serially and synchronous
to the SPI clock (sck).
Figure 22 shows the communication protocol for read and
write accesses of the SPI registers. The PYTHON 300,
PYTHON 500, and PYTHON 1300 image sensors use 9−bit
addresses and 16−bit data words.
Data driven by the system is colored blue in Figure 16,
while data driven by the sensor is colored yellow. The data
in grey indicates high−Z periods on the miso interface. Red
markers indicate sampling points for the sensor (mosi
sampling); green markers indicate sampling points for the
system (miso sampling during read operations).
The access sequence is:
3. Select the sensor for read or write by pulling down
the ss_n line.
4. One SPI clock cycle after selecting the sensor, the
9−bit data is transferred, most significant bit first.
SPI − WRITE
ss_n
t_sckss
tsck
t_sssck
sck
ts _mos i
mosi
A8
th_mosi
A7
..
..
..
A1
A0
`1'
D15
D14
..
..
..
..
D1
D0
miso
SPI − READ
ss_n
t_sssck
t_sckss
tsck
sck
ts_mosi
mosi
A8
th_mosi
A7
..
..
..
A1
A0
`0'
th_miso
ts _miso
miso
D15
D14
..
..
Figure 22. SPI Read and Write Timing Diagram
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..
..
D1
D0
NOIP1SN1300A
Table 20. SPI TIMING REQUIREMENTS
Group
Addresses
Description
Units
100 (*)
ns
ss_n low to sck rising edge
tsck
ns
tsckss
sck falling edge to ss_n high
tsck
ns
ts_mosi
Required setup time for mosi
20
ns
th_mosi
Required hold time for mosi
20
ns
ts_miso
Setup time for miso
tsck/2−10
ns
th_miso
Hold time for miso
tsck/2−20
ns
tspi
Minimal time between two consecutive SPI accesses (not shown in figure)
2 x tsck
ns
tsck
sck clock period
tsssck
*Value indicated is for nominal operation. The maximum SPI clock frequency depends on the sensor configuration (operation mode, input clock).
tsck is defined as 1/fSPI. See text for more information on SPI clock frequency restrictions.
IMAGE SENSOR TIMING AND READOUT
reset period, the global photodiode reset condition is
abandoned. This indicates the start of the integration or
exposure time. The length of the exposure time is defined by
the registers exposure and mult_timer.
NOTE: The start of the exposure time is synchronized to
the start of a new line (during ROT) if the
exposure period starts during a frame readout.
As a consequence, the effective time during
which the image core is in a reset state is
extended to the start of a new line.
• Make sure that the sum of the reset time and exposure
time exceeds the time required to readout all lines. If
this is not the case, the exposure time is extended until
all (active) lines are read out.
• Alternatively, it is possible to specify the frame time
and exposure time. The sensor automatically calculates
the required reset time. This mode is enabled by the
fr_mode register. The frame time is specified in the
register fr_length.
The following sections describe the configurations for
single slope reset mechanism. Dual and triple slope handling
during global shutter operation is similar to the single slope
operation. Extra integration time registers are available.
Global Shutter Mode
Pipelined Global Shutter (Master)
The integration time is controlled by the registers
fr_length[15:0] and exposure[15:0]. The mult_timer
configuration defines the granularity of the registers
reset_length and exposure. It is read as number of system
clock cycles (14.706 ns nominal at 68 MHz) for the
P1, P3−SN/SE/FN version and 18 MHz cycles (55.556 ns
nominal) for the P2−SN/SE version.
The exposure control for (Pipelined) Global Master mode
is depicted in Figure 23.
The pixel values are transferred to the storage node during
FOT, after which all photo diodes are reset. The reset state
remains active for a certain time, defined by the reset_length
and mult_timer registers, as shown in the figure. Note that
meanwhile the image array is read out line by line. After this
Frame N
Exposure State
FOT
Readout
FOT
Reset
Frame N+1
Integrating
FOT
Reset
Integrating
FOT
FOT
FOT
Image Array Global Reset
reset_length
x
mult_timer
exposure
x
mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 23. Integration Control for (Pipelined) Global Shutter Mode (Master)
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NOIP1SN1300A
Triggered Global Shutter (Master)
exposure and mult_timer, as in the master pipelined global
mode. The fr_length configuration is not used. This
operation is graphically shown in Figure 24.
In master triggered global mode, the start of integration
time is controlled by a rising edge on the trigger0 pin. The
exposure or integration time is defined by the registers
Frame N
Exposure State
FOT
Reset
Integrating
FOT
Reset
Integrating
FOT
(No effect on falling edge)
trigger0
Readout
Frame N+1
FOT
FOT
FOT
Image Array Global Reset
exposure x mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 24. Exposure Time Control in Triggered Shutter Mode (Master)
the pixel storage node and readout of the image array. In
other words, the high time of the trigger pin indicates the
integration time, the period of the trigger pin indicates the
frame time.
The use of the trigger during slave mode is shown in
Figure 25.
Notes:
• The falling edge on the trigger pin does not have any
impact. Note however the trigger must be asserted for
at least 100 ns.
• The start of the exposure time is synchronized to the
start of a new line (during ROT) if the exposure period
starts during a frame readout. As a consequence, the
effective time during which the image core is in a reset
state is extended to the start of a new line.
• If the exposure timer expires before the end of readout,
the exposure time is extended until the end of the last
active line.
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Notes:
• The registers exposure, fr_length, and mult_timer are
•
•
•
Triggered Global Shutter (Slave)
Exposure or integration time is fully controlled by means
of the trigger pin in slave mode. The registers fr_length,
exposure and mult_timer are ignored by the sensor.
A rising edge on the trigger pin indicates the start of the
exposure time, while a falling edge initiates the transfer to
not used in this mode.
The start of exposure time is synchronized to the start
of a new line (during ROT) if the exposure period starts
during a frame readout. As a consequence, the effective
time during which the image core is in a reset state is
extended to the start of a new line.
If the trigger is de−asserted before the end of readout,
the exposure time is extended until the end of the last
active line.
The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Frame N
Exposure State
FOT
Reset
Frame N+1
Integrating
FOT
Reset
Integrating
FOT
trigger0
Readout
FOT
FOT
FOT
Image Array Global Reset
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 25. Exposure Time Control in Global−Slave Mode
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NOIP1SN1300A
ADDITIONAL FEATURES
Multiple Window Readout
The PYTHON 300, PYTHON 500, and PYTHON 1300
image sensors support multiple window readout, which
means that only the user−selected Regions Of Interest (ROI)
are read out. This allows limiting data output for every
frame, which in turn allows increasing the frame rate. In
global shutter mode, up to eight ROIs can be configured.
y1_end
ROI 1
y0_end
y1_start
ROI 0
Window Configuration
Figure 26 shows the four parameters defining a region of
interest (ROI).
y0_start
y-end
x0_start
x0_end
x1_start
x1_end
Figure 27. Overlapping Multiple Window
Configuration
ROI 0
The sequencer analyses each line that need to be read out
for multiple windows.
y-start
Restrictions
The following restrictions for each line are assumed for
the user configuration:
• Windows are ordered from left to right, based on their
x−start address:
x-start x-end
Figure 26. Region of Interest Configuration
x_start_roi(i) v x_start_roi(j) AND
• x−start[7:0]
x_end_roi(i) vx_end_roi(j)
x−start defines the x−starting point of the desired window.
The sensor reads out 8 pixels in one single clock cycle. As
a consequence, the granularity for configuring the x−start
position is also 8 pixels for no sub sampling. The value
configured in the x−start register is multiplied by 8 to find
the corresponding column in the pixel array.
• x−end[7:0]
This register defines the window end point on the x−axis.
Similar to x−start, the granularity for this configuration is
one kernel. x−end needs to be larger than x−start.
• y−start[9:0]
The starting line of the readout window. The granularity
of this setting is one line, except with color sensors where it
needs to be an even number.
• y−end[9:0]
The end line of the readout window. y−end must be
configured larger than y−start. This setting has the same
granularity as the y−start configuration.
Up to eight windows can be defined, possibly (partially)
overlapping, as illustrated in Figure 27.
Where j > i
Processing Multiple Windows
The sequencer control block houses two sets of counters
to construct the image frame. As previously described, the
y−counter indicates the line that needs to be read out and is
incremented at the end of each line. For the start of the frame,
it is initialized to the y−start address of the first window and
it runs until the y−end address of the last window to be read
out. The last window is configured by the configuration
registers and it is not necessarily window #7.
The x−counter starts counting from the x−start address of
the window with the lowest ID which is active on the
addressed line. Only windows for which the current
y−address is enclosed are taken into account for scanning.
Other windows are skipped.
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NOIP1SN1300A
• The read pointer is not necessarily incremented by one,
Figure 28 illustrates a practical example of a
configuration with five windows. The current position of the
read pointer (ys) is indicated by a red line crossing the image
array. For this position of the read pointer, three windows
need to be read out. The initial start position for the x−kernel
pointer is the x−start configuration of ROI1. Kernels are
scanned up to the ROI3 x−end position. From there, the
x−pointer jumps to the next window, which is ROI4 in this
illustration. When reaching ROI4’s x−end position, the read
pointer is incremented to the next line and xs is reinitialized
to the starting position of ROI1.
Notes:
• The starting point for the readout pointer at the start of
a frame is the y−start position of the first active
window.
•
•
•
but depending on the configuration, it can jump in
y−direction. In Figure 28, this is the case when reaching
the end of ROI0 where the read pointer jumps to the
y−start position of ROI1
The x−pointer starting position is equal to the x−start
configuration of the first active window on the current
line addressed. This window is not necessarily window
#0.
The x−pointer is not necessarily incremented by one
each cycle. At the end of a window it can jump to the
start of the next window.
Each window can be activated separately. There is no
restriction on which window and how many of the 8
windows are active.
ROI 2
ys
ROI 3
ROI 4
ROI 1
ROI 0
Figure 28. Scanning the Image Array with Five Windows
Subsampling
Color Sensors
Subsampling is used to reduce the image resolution. This
allows increasing the frame rate. Two subsampling modes
are supported: for monochrome and NIR enhanced sensors
(P1−SN/FN, P2−SN and P3−SN/FN) and color sensors
(P1−SE / P2−SE / P3−SE).
For color sensors, the read−2−skip−2 subsampling
scheme is used. Subsampling occurs both in x− and y−
direction. Figure 29 shows which pixels are read and which
ones are skipped.
Monochrome and NIR Sensors
These sensors utilize the read−1−skip−1 subsampling
scheme. Subsampling occurs both in x− and y− direction.
Figure 29. Subsampling Scheme for Monochrome and Color Sensors
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NOIP1SN1300A
Binning
Reverse Readout in Y−direction
Pixel binning is a technique in which different pixels
belonging to a rectangular bin are averaged in the analog
domain. Two−by−two pixel binning is available with the
monochrome and NIR enhanced image sensors (P1−SN/FN,
P2−SN, P3−SN/FN). This implies that two adjacent pixels
are averaged both in column and row. Binning is
configurable using a register setting. Pixel binning is not
supported on PYTHON color option (P1−SE / P2−SE /
P3−SE) and in Zero ROT mode.
NOTES:
1. Register 194[13:12] needs to be configured to 0x0
for 2x2 pixel binning and to 0x1 for 2x1 binning.
Binning occurs only in x direction.
2. Binning in y-direction cannot be used in
combination with pipelined integration and
readout. The integration time and readout time
should be separated in time (do not coincide).
Reverse readout in y−direction can be done by toggling
reverse_y (reg 194[8]). The reference for y_start and y_stop
pointers is reversed.
Channel Multiplexing
The PYTHON 300, PYTHON 500, and PYTHON 1300
image sensors contains a function for channel multiplexing
the output channels. Using this function, one may for
instance use the device with sync+clock+4 data channels.
Enabling the channel multiplexing is done through
register 32[5:4]. The default value of 0 disables all channel
multiplexing. Higher values sets higher degree of channel
multiplexing, The channels that are used per degree of
multiplexing are shown in Table 5. The unused data
channels are powered down and will not send any data.
Table 21. LVDS DATA OUTPUT CHANNELS USED WITH CHANNEL MULTIPLEXING
P1300
PYTHON 1300 − LVDS Channels
4 channels
Ch 0
2 channels
Ch 0
1 channel
Ch 0
Ch 1
Ch 2
Ch 3
Ch 2
Register
Address
Data
Register
Address
Data
32[5:4]
0
211
0x0E49
32[5:4]
1, 2
211
0x0E39
32[5:4]
3
211
0x0E29
1. P1 supports 4 LVDS channels, while P1, P3 support 2 and 1 channels.
2. Use P3 bias uploads for P1 in mux mode.
Table 22. BIAS UPLOADS FOR P1 AND P3
Bias Uploads
Address
mux 4:4
mux 4:2
mux 4:1
reg_mux_image_core_config1
41
0x085F
0x085F
0x085F
reg_mux_image_core_config2
42
0x4110
0x4110
0x4110
reg_mux_image_core_config3
43
0x0008
0x0008
0x0008
reg_bias_configuration
65
0x382B
0x382B
0x382B
reg_bias_afe_bias
66
0x53C8
0x53C4
0x53C2
reg_bias_mux_bias
67
0x0665
0x0645
0x0522
reg_bias_lvds_bias
68
0x0085
0x0085
0x0085
reg_bias_adc_bias
69
0x0088
0x0048
0x0028
reg_bias_imc_bias
70
0x1111
0x1111
0x1111
reg_cp_configuration
72
0x0010
0x0010
0x0010
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NOIP1SN1300A
Multiple Slope Integration
To increase the dynamic range of the sensor, a second
slope is applied in the dual slope mode (green curve). The
sensor has the same responsivity in the black as for a single
slope, but from ‘knee point 1’ on, the sensor is less
responsive to incoming light. The result is that the saturation
point is at a higher light power level.
To further increase the dynamic range, a third slope can be
applied, resulting in a second knee point.
The multiple slope function is only available in global
shutter modes. Refer to section Global Shutter Mode on
page 30 for general notes applicable to the global shutter
operation and more particular to the use of the trigger0 pin.
‘Multiple Slope Integration’ is a method to increase the
dynamic range of the sensor. The PYTHON 300,
PYTHON 500, and PYTHON 1300 support up to three
slopes.
Figure 30 shows the sensor response to light when the
sensor is used with one slope, two slopes, and three slopes.
The X−axis represents the light power; the Y−axis shows the
sensor output signal. The kneepoint of the multiple slope
curves are adjustable in both position and voltage level.
It is clear that when using only one slope (red curve), the
sensor has the same responsivity over the entire range, until
the output saturates at the point indicated with ‘single slope
saturation point’.
output
1023
slope 3
`kneepoint 2'
slope 1 slope 2
`kneepoint 1'
0
single slope
saturation point
dual slope
saturation point
Figure 30. Multiple Slope Operation
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35
light
triple slope
saturation point
NOIP1SN1300A
Kneepoint Configuration (Multiple Slope Reset Levels)
dual_slope_enable and triple_slope_enable and their values
are defined by the registers exposure_ds and exposure_ts.
NOTE: Dual and triple slope sequences must start after
readout of the previous frame is fully completed.
Figure 31 shows the frame timing for pipelined master
mode with dual and triple slope integration and
fr_mode = ‘0’ (fr_length representing the reset length).
In triggered master mode, the start of integration is
initiated by a rising edge on trigger0, while the falling edge
does not have any relevance. Exposure duration and
dual/triple slope points are defined by the registers.
The kneepoint reset levels are configured by means of
DAC configurations in the image core. The dual slope
kneepoint is configured with the dac_ds configuration,
while the triple slope kneepoint is configured with the
dac_ts register setting. Both are located on address 41.
Multiple Slope Integration in “Master Mode” (Pipelined
or Triggered)
In master mode, the time stamps for the double and triple
slope resets are configured in a similar way as the exposure
time. They are enabled through the registers
Figure 31. Multiple Slope Operation in Master Mode for fr_mode = ‘0’ (Pipelined)
Slave Mode
In slave mode, the register settings for integration control are ignored. The user has full control through the trigger0, trigger1
and trigger2 pins. A falling edge on trigger1 initiates the dual slope reset while a falling edge on trigger2 initiates the triple
slope reset sequence. Rising edges on trigger1 and trigger2 do not have any impact.
NOTE: Dual and triple slope sequences must start after readout of the previous frame is fully completed.
Figure 32. Multiple Slope Operation in Slave Mode
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NOIP1SN1300A
Black Reference
Signal Path Gain
The sensor reads out one or more black lines at the start of
every new frame. The number of black lines to be generated
is programmable and is minimal equal to 1. The length of the
black lines depends on the operation mode. The sensor
always reads out the entire line (160 kernels), independent
of window configurations.
The black references are used to perform black calibration
and offset compensation in the data channels. The raw black
pixel data is transmitted over the usual output interface,
while the regular image data is compensated (can be
bypassed).
On the output interface, black lines can be seen as a
separate window, however without Frame Start and Ends
(only Line Start/End). The Sync code following the Line
Start and Line End indications (“window ID”) contains the
active window number, which is 0. Black reference data is
classified by a BL code.
Analog Gain Stages
Referring to Table 23, three gain settings are available in
the analog data path to apply gain to the analog signal before
it is digitized. The gain amplifier can apply a gain of
approximately 1x to 4x to the analog signal.
The moment a gain re−configuration is applied and
becomes valid can be controlled by the gain_lat_comp
configuration.
With ‘gain_lat_comp’ set to ‘0’, the new gain
configurations are applied from the very next frame.
With ‘gain_lat_comp’ set to ‘1’, the new gain settings are
postponed by one extra frame. This feature is useful when
exposure time and gain are reconfigured together, as an
exposure time update always has one frame latency.
Table 23. SIGNAL PATH GAIN STAGES
Gain Stage 1 (204[4:0])
Gain Stage 2 (204[12:5])
Overall Gain
Address
Gain Setting
Normal ROT
Zero ROT
Normal
ROT
Zero ROT
Normal ROT
Zero ROT
204[12:0]
0x01E3
1
NA
1
NA
1
NA
204[12:0]
0x01E1
1.9
1
1
1
1.9
1
204[12:0]
0x01E4
3.5
1.8
1
1
3.5
1.8
204[12:0]
0x01E8
14
8
1
1
14
8
Digital Gain Stage
The digital gain stage allows fine gain adjustments on the
digitized samples. The gain configuration is an absolute 5.7
unsigned number (5 digits before and 7 digits after the
decimal point).
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NOIP1SN1300A
Automatic Exposure Control
AEC
Statistics
Requested Illumination Level
(Target)
Total Gain
Requested Gain
Changes
The exposure control mechanism has the shape of a
general feedback control system. Figure 33 shows the high
level block diagram of the exposure control loop.
AEC
Filter
AEC
Enforcer
Integration Time
Analog Gain (Coarse Steps)
Digital Gain (Fine Steps)
Image Capture
Figure 33. Automatic Exposure Control Loop
AEC Statistics Block
Three main blocks can be distinguished:
• The statistics block compares the average of the
current image’s samples to the configured target value
for the average illumination of all pixels
• The relative gain change request from the statistics
block is filtered through the AEC Filter block in the
time domain (low pass filter) before being integrated.
The output of the filter is the total requested gain in the
complete signal path.
• The enforcer block accepts the total requested gain and
distributes this gain over the integration time and gain
stages (both analog and digital)
The statistics block calculates the average illumination of
the current image. Based on the difference between the
calculated illumination and the target illumination the
statistics block requests a relative gain change.
Statistics Subsampling and Windowing
For average calculation, the statistics block will
sub−sample the current image or windows by taking every
fourth sample into account. Note that only the pixels read out
through the active windows are visible for the AEC. In the
case where multiple windows are active, the samples will be
selected from the total samples. Samples contained in a
region covered by multiple (overlapping) window will be
taking into account only once.
It is possible to define an AEC specific sub−window on
which the AEC will calculate it’s average. For instance, the
sensor can be configured to read out a larger frame, while the
illumination is measured on a smaller region of interest, e.g.
center weighted as shown in Table 24.
The automatic exposure control loop is enabled by asserting
the aec_enable configuration in register 160.
NOTE: Dual and Triple slope integration is not
supported in conjunction with the AEC.
Table 24. AEC SAMPLE SELECTION
Register
Name
192[10]
roi_aec_enable
When 0x0, all active windows are selected for statistics calculation.
When 0x1, the AEC samples are selected from the active pixels contained in the region of interest defined
by roi_aec
Description
253−255
roi_aec
These registers define a window from which the AEC samples will be selected when roi_aec_enable is
asserted. Configuration is similar to the regular region of interests.
The intersection of this window with the active windows define the selected pixels. It is important that this
window at least overlaps with one or more active windows.
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NOIP1SN1300A
AEC Filter Block
Target Illumination
The target illumination value is configured by means of
register desired_intensity as shown in Table 25.
The filter block low−pass filters the gain change requests
received from the statistics block.
The filter can be restarted by asserting the restart_filter
configuration of register 160.
Table 25. AEC TARGET ILLUMINATION
CONFIGURATION
AEC Enforcer Block
Register
Name
Description
161[9:0]
desired_intensity
Target intensity value, on 10−bit scale.
For 8−bit mode, target value is configured on desired_intensity[9:2]
The enforcer block calculates the four different gain
parameters, based on the required total gain, thereby
respecting a specific hierarchy in those configurations.
Some (digital) hysteresis is added so that the (analog) sensor
settings don’t need to change too often.
Exposure Control Parameters
The several gain parameters are described below, in the
order in which these are controlled by the AEC for large
adjustments. Small adjustments are regulated by digital gain
only.
• Exposure Time
The exposure is the time between the global image array
reset de−assertion and the pixel charge transfer. The
granularity of the integration time steps is configured by the
mult_timer register.
NOTE: The exposure_time register is ignored when the
AEC is enabled. The register fr_length defines
the frame time and needs to be configured
accordingly.
• Analog Gain
The sensor has two analog gain stages, configurable
independently from each other. Typically the AEC shall only
regulate the first stage.
• Digital Gain
The last gain stage is a gain applied on the digitized
samples. The digital gain is represented by a 5.7 unsigned
number (i.e. 7 bits after the decimal point). While the analog
gain steps are coarse, the digital gain stage makes it possible
to achieve very fine adjustments.
Color Sensor
The weight of each color can be configured for color
sensors by means of scale factors. Note these scale factor are
only used to calculate the statistics in order to compensate
for (off−chip) white balancing and/or color matrices. The
pixel values itself are not modified.
The scale factors are configured as 3.7 unsigned numbers
(0x80 = unity). Refer to Table 26 for color scale factors. For
mono sensors, configure these factors to their default value.
Table 26. COLOR SCALE FACTORS
Register
Name
Description
162[9:0]
red_scale_factor
Red scale factor for AEC
statistics
163[9:0]
green1_scale_fa
ctor
Green1 scale factor for AEC
statistics
164[9:0]
green2_scale_fa
ctor
Green2 scale factor for AEC
statistics
165[9:0]
blue_scale_factor
Blue scale factor for AEC
statistics
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NOIP1SN1300A
AEC Control Range
AEC Update Frequency
The control range for each of the exposure parameters can
be pre−programmed in the sensor. Table 27 lists the relevant
registers.
Table 27. MINIMUM AND MAXIMUM EXPOSURE
CONTROL PARAMETERS
As an integration time update has a latency of one frame,
the exposure control parameters are evaluated and updated
every other frame.
Note: The gain update latency must be postpone to match
the integration time latency. This is done by asserting the
gain_lat_comp register on address 204[13].
Register
Exposure Control Status Registers
Name
Description
168[15:0]
min_exposure
Lower bound for the integration
time applied by the AEC
169[1:0]
min_mux_gain
Lower bound for the first stage
analog amplifier.
This stage has three
configurations with the following
approximative gains:
0x0 = 1x
0x1 = 2x
0x2 = 4x
169[3:2]
min_afe_gain
Lower bound for the second
stage analog amplifier.
This stage has one
configuration with the following
approximative gain:
0x0 = 1.00x
169[15:4]
min_digital_gain
Lower bound for the digital gain
stage. This configuration
specifies the effective gain in 5.7
unsigned format
170[15:0]
max_exposure
Upper bound for the integration
time applied by the AEC
171[1:0]
171[3:2]
171[15:4]
max_mux_gain
max_afe_gain
max_digital_gain
Configured integration and gain parameters are reported
to the user by means of status registers. The sensor provides
two levels of reporting: the status registers reported in the
AEC address space are updated once the parameters are
recalculated and requested to the internal sequencer. The
status registers residing in the sequencer’s address space on
the other hand are updated once these parameters are taking
effect on the image readout. Refer to Table 28 reflecting the
AEC and Sequencer Status registers.
Table 28. EXPOSURE CONTROL STATUS REGISTERS
Register
Name
Description
AEC Status Registers
Upper bound for the first stage
analog amplifier.
This stage has three
configurations with the following
approximative gains:
0x0 = 1x
0x1 = 2x
0x2 = 4x
Upper bound for the second
stage analog amplifier
This stage has one
configuration with the following
approximative gain:
0x0 = 1.00x
184[15:0]
total_pixels
Total number of pixels taken into
account for the AEC statistics.
186[9:0]
average
Calculated average illumination
level for the current frame.
187[15:0]
exposure
AEC calculated exposure.
Note: this parameter is updated at
the frame end.
188[1:0]
mux_gain
AEC calculated analog gain
(1st stage)
Note: this parameter is updated at
the frame end.
188[3:2]
afe_gain
AEC calculated analog gain
(2st stage)
Note: this parameter is updated at
the frame end.
188[15:4]
digital_gain
AEC calculated digital gain
(5.7 unsigned format)
Note: this parameter is updated at
the frame end.
Upper bound for the digital gain
stage. This configuration
specifies the effective gain in 5.7
unsigned format
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NOIP1SN1300A
Table 28. EXPOSURE CONTROL STATUS REGISTERS
Register
Name
Description
Register
Sequencer Status Registers
242[15:0]
mult_timer
mult_timer for current frame (global
shutter only).
Note: this parameter is updated
once it takes effect on the image.
243[15:0]
reset_length
Image array reset length for the
current frame (global shutter only).
Note: this parameter is updated
once it takes effect on the image.
244[15:0]
exposure
Exposure for the current frame.
Note: this parameter is updated
once it takes effect on the image.
245[15:0]
exposure_ds
Dual slope exposure for the current
frame. Note this parameter is not
controlled by the AEC.
Note: this parameter is updated
once it takes effect on the image.
246[15:0]
exposure_ts
Triple slope exposure for the
current frame. Note this parameter
is not controlled by the AEC.
Note: this parameter is updated
once it takes effect on the image.
247[4:0]
mux_gainsw
1st stage analog gain for the current
frame.
Note: this parameter is updated
once it takes effect on the image.
Description
afe_gain
2st stage analog gain for the current
frame.
Note: this parameter is updated
once it takes effect on the image.
248[11:0]
db_gain
Digital gain configuration for the
current frame (5.7 unsigned
format).
Note: this parameter is updated
once it takes effect on the image.
248[12]
dual_slope
Dual slope configuration for the
current frame
Note 1: this parameter is updated
once it takes effect on the image.
Note 2: This parameter is not
controlled by the AEC.
248[13]
triple_slope
Triple slope configuration for the
current frame.
Note 1: this parameter is updated
once it takes effect on the image.
Note 2: This parameter is not
controlled by the AEC.
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41
Name
247[12:5]
NOIP1SN1300A
Mode Changes and Frame Blanking
summarized in the following table for the sensor’s image
related modes.
NOTE: Major mode switching (i.e. switching between
master, triggered or slave mode) must be
performed while the sequencer is disabled
(reg_seq_enable = 0x0).
Dynamically reconfiguring the sensor may lead to
corrupted or non-uniformilly exposed frames. For some
reconfigurations, the sensor automatically blanks out the
image data during one frame. Frame blanking is
Table 29. DYNAMIC SENSOR RECONFIGURATION AND FRAME BLANKING
Configuration
Corrupted
Frame
Blanked Out
Frame
Notes
Shutter Mode and Operation
triggered_mode
Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.
slave_mode
Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.
subsampling
Enabling: No
Disabling: Yes
Configurable
Configurable with blank_subsampling_ss register.
binning
No
Configurable
Configurable with blank_subsampling_ss register
No
No
mult_timer
No
No
Latency is 1 frame
fr_length
No
No
Latency is 1 frame
exposure
No
No
Latency is 1 frame
mux_gainsw
No
No
Latency configurable by means of gain_lat_comp register
afe_gain
No
No
Latency configurable by means of gain_lat_comp register.
db_gain
No
No
Latency configurable by means of gain_lat_comp register.
roi_active
See Note
No
Windows containing lines previously not read out may lead to corrupted
frames.
roi*_configuration*
See Note
No
Reconfiguring the windows by means of roi*_configuration* may lead to
corrupted frames when configured close to frame boundaries.
It is recommended to (re)configure an inactive window and switch the
roi_active register.
See Notes on roi_active.
black_samples
No
No
If configured within range of configured black lines
auto_blackal_enable
See Note
No
Manual correction factors become instantly active when
auto_blackcal_enable is deasserted during operation.
blackcal_offset
See Note
No
Manual blackcal_offset updates are instantly active.
No
No
Impacts the transmitted CRC
bl_0
No
No
Impacts the Sync channel information, not the Data channels.
img_0
No
No
Impacts the Sync channel information, not the Data channels.
crc_0
No
No
Impacts the Sync channel information, not the Data channels.
tr_0
No
No
Impacts the Sync channel information, not the Data channels.
Frame Timing
black_lines
Exposure Control
Gain
Window/ROI
Black Calibration
CRC Calculation
crc_seed
Sync Channel
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NOIP1SN1300A
Temperature Sensor
low respectively. The temperature sensor is reset or disabled
when the input reg_tempd_enable is set to a digital low state.
The PYTHON 300, PYTHON 500, and PYTHON 1300
image sensors have an on−chip temperature sensor which
returns a digital code (Tsensor) of the silicon junction
temperature. The Tsensor output is a 8−bit digital count
between 0 and 255, proportional to the temperature of the
silicon substrate. This reading can be translated directly to
a temperature reading in °C by calibrating the 8−bit readout
at 0°C and 85°C to achieve an output accuracy of ±2°C. The
Tsensor output can also be calibrated using a single
temperature point (example: room temperature or the
ambient temperature of the application), to achieve an
output accuracy of ±5°C.
Note that any process variation will result in an offset in
the bit count and that offset will remain within ±5°C over the
temperature range of 0°C and 85°C. Tsensor output digital
code can be read out through the SPI interface.
Calibration using one temperature point
The temperature sensor resolution is fixed for a given type
of package for the operating range of 0°C to +85°C and
hence devices can be calibrated at any ambient temperature
of the application, with the device configured in the mode of
operation.
Interpreting the actual temperature for the digital code
readout:
The formula used is
TJ = R (Nread − Ncalib) + Tcalib
TJ = junction die temperature
R = resolution in degrees/LSB (typical 0.75 deg/LSB)
Nread = Tsensor output (LSB count between 0 and 255)
Tcalib = Tsensor calibration temperature
Ncalib = Tsensor output reading at Tcalib
Output of the temperature sensor to the SPI:
tempd_reg_temp<7:0>: This is the 8−bit N count readout
proportional to temperature.
Monitor Pins
The internal sequencer has two monitor outputs (Pin 44
and Pin 45) that can be used to communicate the internal
states from the sequencer. A three−bit register configures the
assignment of the pins as shown in Table 30.
Input from the SPI:
The reg_tempd_enable is a global enable and this enables
or disables the temperature sensor when logic high or logic
Table 30. REGISTER SETTING FOR THE MONITOR SELECT PIN
monitor_select [2:0]
192 [13:11]
monitor pin
0x0
monitor0
monitor1
‘0’
‘0’
0x1
monitor0
monitor1
Integration Time
ROT Indication (‘1’ during ROT, ‘0’ outside)
0x2
monitor0
monitor1
Integration Time
Dual/Triple Slope Integration (asserted during DS/TS FOT sequence)
0x3
monitor0
monitor1
Start of x−Readout Indication
Black Line Indication (‘1’ during black lines, ‘0’ outside)
0x4
monitor0
monitor1
Frame Start Indication
Start of ROT Indication
0x5
monitor0
monitor1
First Line Indication (‘1’ during first line, ‘0’ for all others)
Start of ROT Indication
0x6
monitor0
monitor1
ROT Indication (‘1’ during ROT, ‘0’ outside)
Start of X−Readout Indication
0x7
monitor0
monitor1
Start of X−readout Indication for Black Lines
Start of X−readout Indication for Image Lines
Description
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NOIP1SN1300A
DATA OUTPUT FORMAT
Frame Format
The PYTHON 300, PYTHON 500, and PYTHON 1300
image sensors are available in two LVDS output
configuration, P1 and P3.
The P1 configuration utilizes four LVDS output channels
together with an LVDS clock output and an LVDS
synchronization output channel.
The P3 configuration consists of two LVDS output
channels together with an LVDS clock output and an LVDS
synchronization output channel.
The PYTHON 1300 is also available in a CMOS output
configuration − P2, which includes a 10−bit parallel CMOS
output together with a CMOS clock output and ‘frame valid’
and ‘line valid’ CMOS output signals.
The frame format in 8−bit mode is identical to the 10−bit
mode with the exception that the Sync and data word depth
is reduced to eight bits.
The frame format in 10−bit mode is explained by example
of the readout of two (overlapping) windows as shown in
Figure 34(a).
The readout of a frame occurs on a line−by−line basis. The
read pointer goes from left to right, bottom to top.
Figure 34 indicates that, after the FOT is completed, the
sensor reads out a number of black lines for black calibration
purposes. After these black lines, the windows are
processed. First a number of lines which only includes
information of ‘ROI 0’ are sent out, starting at position
y0_start. When the line at position y1_start is reached, a
number of lines containing data of ‘ROI 0’ and ‘ROI 1’ are
sent out, until the line position of y0_end is reached. From
there on, only data of ‘ROI 1’ appears on the data output
channels until line position y1_end is reached
During read out of the image data over the data channels,
the sync channel sends out frame synchronization codes
which give information related to the image data that is sent
over the four data output channels.
Each line of a window starts with a Line Start (LS)
indication and ends with a Line End (LE) indication. The
line start of the first line is replaced by a Frame Start (FS);
the line end of the last line is replaced with a Frame End
indication (FE). Each such frame synchronization code is
followed by a window ID (range 0 to 7). For overlapping
windows, the line synchronization codes of the overlapping
windows with lower IDs are not sent out (as shown in the
illustration: no LE/FE is transmitted for the overlapping part
of window 0).
NOTE: In Figure 34, only Frame Start and Frame End
Sync words are indicated in (b). CRC codes are
also omitted from the figure.
P1, P3−SN/SE/FN: LVDS Interface Version
LVDS Output Channels
The image data output occurs through four LVDS data
channels where a synchronization LVDS channel and an
LVDS output clock signal synchronizes the data. Referring
to Table 21, the four data channels on the P1 option are used
to output the image data only, while on the P3 option, two
data channel channels are utilized. The sync channel
transmits information about the data sent over these data
channels (includes codes indicating black pixels, normal
pixels, and CRC codes).
8−bit / 10−bit Mode
The sensor can be used in 8−bit or 10−bit mode.
In 10−bit mode, the words on data and sync channel have
a 10−bit length. The output data rate is 720 Mbps.
In 8−bit mode, the words on data and sync channel have
an 8−bit length, the output data rate is 576 Mbps.
Note that the 8−bit mode can only be used to limit the data
rate at the consequence of image data word depth. It is not
supported to operate the sensor in 8−bit mode at a higher
clock frequency to achieve higher frame rates.
The P1 option supports 10−bit/8−bit in ZROT/NROT
mode, while the P3 option supports 10−bit NROT mode
only.
For additional information on the
synchronization codes, please refer to
Application Note AND5001.
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44
NOIP1SN1300A
y1_end
ROI 1
y0_end
y1_start
ROI 0
y0_start
x0_start
x0_end
x1_start
x1_end
(a)
Integration Time
Handling
Readout
Handling
FOT
Reset
N
É
É
Exposure Time N
FOT
Readout Frame N-1
B
L
ROI
1
ROI 0
FS0
FS1
FOT
FE1
Reset
N+1
É
É
B
L
Exposure Time N+1
FOT
Readout Frame N
ROI
1
ROI 0
FS0
FS1
FOT
FE1
(b)
Figure 34. P1&P3−SN/SE/FN: Frame Sync Codes
Figure 35 shows the detail of a black line readout during global or full−frame readout.
Sequencer
Internal State
FOT
ROT
ROT
black
line Ys
ROT
ROT
line Ys+1
line Ye
data channels
sync channel
data channels
sync channel
Training
TR
Training
LS
BL
timeslot
0
timeslot
1
BL
BL
BL
timeslot
157
BL
timeslot
158
BL
LE
timeslot
159
CRC
TR
CRC
timeslot
Figure 35. P1&P3−SN/SE/FN: Time Line for Black Line Readout
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45
NOIP1SN1300A
Figure 36 shows shows the details of the readout of a number of lines for single window readout, at the beginning of the frame.
Sequencer
Internal State
FOT
ROT
black
ROT
line Ys+1
ROT
line Ys
line Ye
ROT
data channels
sync channel
Training
data channels
TR
sync channel
Training
FS
ID
timeslot
Xstart
IMG
IMG
IMG
timeslot
Xstart + 1
IMG
timeslot
Xend - 2
IMG
IMG
timeslot
Xend - 1
ID
LE
CRC
timeslot
Xend
TR
CRC
timeslot
Figure 36. P1&P3−SN/SE/FN: Time Line for Single Window Readout (at the start of a frame)
Figure 37 shows the detail of the readout of a number of lines for readout of two overlapping windows.
Sequencer
Internal State
FOT
ROT
ROT
black
line Ys
ROT
ROT
line Ys+1
line Ye
data channels
sync channel
data channels
sync channel
Training
Training
TR
LS
IDM
IMG
IMG
LS
timeslot
XstartM
IDN
IMG
IMG
IMG LE
timeslot
XstartN
IDN
CRC
TR
timeslot
XendN
Figure 37. P1&P3−SN/SE/FN: Time Line Showing the Readout of Two Overlapping Windows
Frame Synchronization for 10−bit Mode
Table 31 shows the structure of the frame synchronization
code. Note that the table shows the default data word
(configurable) for 10−bit mode. If more than one window is
active at the same time, the sync channel transmits the frame
synchronization codes of the window with highest index
only.
Table 31. FRAME SYNCHRONIZATION CODE DETAILS FOR 10−BIT MODE
Sync Word Bit
Position
Register
Address
Default
Value
9:7
N/A
0x5
Frame start indication
9:7
N/A
0x6
Frame end indication
9:7
N/A
0x1
Line start indication
Line end indication
9:7
N/A
0x2
6:0
117[6:0]
0x2A
Description
These bits indicate that the received sync word is a frame synchronization code. The
value is programmable by a register setting
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NOIP1SN1300A
• Window Identification
• Data Classification Codes
Frame synchronization codes are always followed by a
3−bit window identification (bits 2:0). This is an integer
number, ranging from 0 to 7, indicating the active window.
If more than one window is active for the current cycle, the
highest window ID is transmitted.
For the remaining cycles, the sync channel indicates the
type of data sent through the data links: black pixel data
(BL), image data (IMG), or training pattern (TR). These
codes are programmable by a register setting. The default
values are listed in Table 32.
Table 32. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 10−BIT MODE
Sync Word Bit
Position
Register
Address
Default
Value
9:0
118 [9:0]
0x015
Black pixel data (BL). This data is not part of the image. The black pixel data is used
internally to correct channel offsets.
9:0
119 [9:0]
0x035
Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the
image).
9:0
125 [9:0]
0x059
CRC value. The data on the data output channels is the CRC code of the finished image
data line.
9:0
126 [9:0]
0x3A6
Training pattern (TR). The sync channel sends out the training pattern which can be
programmed by a register setting.
Description
Frame Synchronization in 8−bit Mode
and not sent out. Table 32 shows the structure of the frame
synchronization code, together with the default value, as
specified in SPI registers. The same restriction for
overlapping windows applies in 8−bit mode.
The frame synchronization words are configured using
the same registers as in 10−bit mode. The two least
significant bits of these configuration registers are ignored
Table 33. FRAME SYNCHRONIZATION CODE DETAILS FOR 8−BIT MODE
Sync Word Bit
Position
Register
Address
Default
Value
7:5
N/A
0x5
Frame start (FS) indication
7:5
N/A
0x6
Frame end (FE) indication
7:5
N/A
0x1
Line start (LS) indication
7:5
N/A
0x2
Line end (LE) indication
4:0
117 [6:2]
0x0A
Description
These bits indicate that the received sync word is a frame synchronization code.
The value is programmable by a register setting.
• Window Identification
• Data Classification Codes
Similar to 10−bit operation mode, the frame
synchronization codes are followed by a window
identification. The window ID is located in bits 4:2 (all other
bit positions are ‘0’). The same restriction for overlapping
windows applies in 8−bit mode.
BL, IMG, CRC, and TR codes are defined by the same
registers as in 10−bit mode. Bits 9:2 of the respective
configuration registers are used as classification code with
default values shown in Table 34.
Table 34. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 8−BIT MODE
Sync Word Bit
Position
Register
Address
Default
Value
7:0
118 [9:2]
0x05
Black pixel data (BL). This data is not part of the image. The black pixel data is used
internally to correct channel offsets.
7:0
119 [9:2]
0x0D
Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of
the image).
7:0
125 [9:2]
0x16
CRC value. The data on the data output channels is the CRC code of the finished image
data line.
7:0
126 [9:2]
0xE9
Training Pattern (TR). The sync channel sends out the training pattern which can be
programmed by a register setting.
Description
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NOIP1SN1300A
Training Patterns on Data Channels
a TR code. These training patterns are configurable
independent of the training code on the sync channel as
shown in Table 35.
In 10−bit mode, during idle periods, the data channels
transmit training patterns, indicated on the sync channel by
Table 35. TRAINING CODE ON SYNC CHANNEL IN 10−BIT MODE
Sync Word Bit
Position
Register
Address
Default
Value
[9:0]
116 [9:0]
0x3A6
Description
Data channel training pattern. The data output channels send out the training pattern,
which can be programmed by a register setting. The default value of the training pattern
is 0x3A6, which is identical to the training pattern indication code on the sync channel.
In 8−bit mode, the training pattern for the data channels is
defined by the same register as in 10−bit mode, where the
lower two bits are omitted; see Table 36.
Table 36. TRAINING PATTERN ON DATA CHANNEL IN 8−BIT MODE
Data Word Bit
Position
Register
Address
Default
Value
[7:0]
116 [9:2]
0xE9
Description
Data Channel Training Pattern (Training pattern).
In 8−bit mode, the polynomial is x8 + x6 + x3 + x2 + 1.
The CRC seed is configured by means of the crc_seed
register.
NOTE: The CRC is calculated for every line. This
implies that the CRC code can protect lines from
multiple windows.
Cyclic Redundancy Code
At the end of each line, a CRC code is calculated to allow
error detection at the receiving end. Each data channel
transmits a CRC code to protect the data words sent during
the previous cycles. Idle and training patterns are not
included in the calculation.
The sync channel is not protected. A special character
(CRC indication) is transmitted whenever the data channels
send their respective CRC code.
The polynomial in 10−bit operation mode is
x10 + x9 + x6 + x3 + x2 + x + 1. The CRC encoder is seeded
at the start of a new line and updated for every (valid) data
word received. The CRC seed is configurable using the
crc_seed register. When ‘0’, the CRC is seeded by all−‘0’;
when ‘1’ it is seeded with all−‘1’.
Data Order for P1&P3−SN/SE/FN: LVDS Interface
Version
To read out the image data through the output channels,
the pixel array is organized in kernels. The kernel size is
eight pixels in x−direction by one pixel in y−direction. The
data order in 8−bit mode is identical to the 10−bit mode.
Figure 38 indicates how the kernels are organized. The first
kernel (kernel [0, 0]) is located in the bottom left corner. The
data order of this image data on the data output channels
depends on the subsampling mode.
kernel
(159,1023)
pixel array
ROI
kernel
(x_start,y_start)
kernel
(0,0)
0
1
2
3
5
6
7
Figure 38. Kernel Organization in Pixel Array
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NOIP1SN1300A
• P1&P3−SN/SE/FN: Subsampling disabled
Figure 39 shows how a kernel is read out over the four
output channels. For even positioned kernels, the kernels are
read out ascending, while for odd positioned kernels the data
order is reversed (descending).
4 LVDS output channels (P1 only)
The image data is read out in kernels of eight pixels in
x−direction by one pixel in y−direction. One data channel
output delivers two pixel values of one kernel sequentially.
♦
kernel N−2
kernel N−1
kernel N
kernel N+1
3
4
5
6
7
pixel # (odd kernel)
7
6
5
4
3
2
1
0
MSB
LSB
MSB
channel #3
2
channel #2
1
channel #1
0
channel #0
pixel # (even kernel)
LSB
Note: The bit order is always MSB first
10−bit / 8−bit
10−bit / 8−bit
Figure 39. P1−SN/SE/FN: 4 LVDS Data Output Order when Subsampling is Disabled
♦ 2 LVDS output channels
Figure 40 shows how a kernel is read out over 2 output
channels. Each pair of adjacent channels is multiplexed into
one channel. For even positioned kernels, the kernels are
kernel N−2
read out ascending but in pair of even and odd pixels, while
for odd positioned kernels the data order is reversed
(descending) but in pair of even and odd pixels.
kernel N−1
kernel N
kernel N+1
2
1
3
4
6
5
7
pixel # (odd kernel)
7
5
6
4
3
1
2
0
MSB
LSB
MSB
channel #2
0
channel #0
pixel # (even kernel)
LSB
Note: The bit order is always MSB first
10−bit / 8−bit
10−bit / 8−bit
Figure 40. P1, P3 −SN/SE/FN: 2 LVDS Data Output Order when Subsampling is Disabled
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NOIP1SN1300A
♦ 1 LVDS output channel
Figure 41 shows how a kernel is read out over 1 output
channel. Each bunch of four adjacent channels is
multiplexed into one channel. For even positioned kernels,
kernel N−2
the kernels are read out ascending but in sets of 4 even and
4 odd pixels, while for odd positioned kernels the data order
is reversed (descending) but in sets of 4 odd and 4 even
pixels.
kernel N−1
kernel N
kernel N+1
0
2
4
6
1
3
5
7
pixel # (odd kernel)
7
5
3
1
6
4
2
0
channel #0
pixel # (even kernel)
MSB
LSB
MSB
LSB
Note: The bit order is always MSB first
10−bit / 8−bit
10−bit / 8−bit
Figure 41. P1, P3 −SN/SE/FN: 1 LVDS Data Output Order when Subsampling is Disabled
• P1&P3−SN/FN: Subsampling on Monochrome Sensor
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout.
♦ 4 LVDS output channels (P1 only)
Figure 42 shows the data order for 4 LVDS output
channels. Note that there is no difference in data order for
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
During subsampling on a monochrome sensor, every
other pixel is read out and the lines are read in a
read-1-skip-1 manner. To read out the image data with
subsampling enabled on a monochrome sensor, two
neighboring kernels are combined to a single kernel of
16 pixels in the x−direction and one pixel in the y−direction.
Only the pixels at the even pixel positions inside that kernel
are read out. Note that there is no difference in data order for
2
12
4
10
kernel N+1
6
8
channel #3
14
kernel N
channel #2
0
channel #0
pixel #
kernel N−1
channel #1
kernel N−2
Figure 42. P1−SN/FN: Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a
Monochrome Sensor
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NOIP1SN1300A
♦ 2 LVDS output channels
Figure 43 shows the data order for 2 LVDS output
channels. Note that there is no difference in data order for
0
2
kernel N
14
12
4
channel #0
pixel #
kernel N−1
6
kernel N+1
10
8
channel #2
kernel N−2
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 43. P1, P3 −SN/FN: Data Output Order for 2 LVDS Output Channels in Subsampling Mode on a
Monochrome Sensor
♦ 1 LVDS output channel
Figure 44 shows the data order for 1 LVDS output
channel. Note that there is no difference in data order for
kernel N−2
kernel N−1
0
2
kernel N
4
6
14
12
kernel N+1
10
8
channel #0
pixel #
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 44. P1, P3 −SN/FN: Data Output Order for 1 LVDS Output Channels in Subsampling Mode on a
Monochrome Sensor
• P1&P3−SN/FN: Binning on Monochrome Sensor
x−direction and one pixel in the y−direction. Only the pixels
0, 1, 4, 5, 8, 9, 12 and 13 are read out. Note that there is no
difference in data order for even/odd kernel numbers, as
opposed to the ‘no−subsampling’ readout.
♦ 4 LVDS output channels (P1 only)
Figure 45 shows the data order for 4 LVDS output
channels. Note that there is no difference in data order for
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
The output order in binning mode is identical to the
subsampled mode.
• P1&P3−SE: Subsampling on Color Sensor
During subsampling on a color sensor, lines are read in a
read-2-skip−2 manner. To read out the image data with
subsampling enabled on a color sensor, two neighboring
kernels are combined to a single kernel of 16 pixels in the
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51
NOIP1SN1300A
13
12
4
5
9
8
channel #3
1
kernel N+1
channel #2
0
kernel N
channel #0
pixel #
kernel N−1
channel #1
kernel N−2
Figure 45. P1−SE: Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a Color Sensor
♦ 2 LVDS output channels
Figure 46 shows the data order for 2 LVDS output
channels. Note that there is no difference in data order for
0
13
kernel N
1
12
4
channel #0
pixel #
kernel N−1
9
kernel N+1
5
8
channel #2
kernel N−2
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 46. P1, P3 −SE: Data Output Order for 2 LVDS Output Channels in Subsampling Mode on a Color Sensor
♦ 1 LVDS output channel
Figure 47 shows the data order for 1 LVDS output
channel. Note that there is no difference in data order for
kernel N−2
kernel N−1
0
13
kernel N
4
9
1
12
kernel N+1
5
8
channel #0
pixel #
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 47. P1, P3 −SE: Data Output Order for 1 LVDS Output Channel in Subsampling Mode on a Color Sensor
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52
NOIP1SN1300A
• The frame_valid indication is asserted at the start of a
P2−SN/SE: CMOS Interface Version
CMOS Output Signals
The image data output occurs through a single 10−bit
parallel CMOS data output, operating at 62 MSps. A CMOS
clock output, ‘frame valid’ and ‘line valid’ signal
synchronizes the output data.
No windowing information is sent out by the sensor.
•
8−bit/10−bit Mode
The 8−bit mode is not supported when using the parallel
CMOS output interface.
Frame Format
Frame timing is indicated by means of two signals:
frame_valid and line_valid.
Sequencer
Internal State
FOT
ROT
black
ROT
line Ys
ROT
new frame and remains asserted until the last line of the
frame is completely transmitted.
The line_valid indication serves the following needs:
♦ While the line_valid indication is asserted, the data
channels contain valid pixel data.
♦ The line valid communicates frame timing as it is
asserted at the start of each line and it is de−asserted
at the end of the line. Low periods indicate the idle
time between lines (ROT).
♦ The data channels transmit the calculated CRC code
after each line. This can be detected as the data
words right after the falling edge of the line valid.
line Ys+1
ROT
line Ye
data channels
frame_valid
line_valid
Figure 48. P2−SN/SE/FN: Frame Timing Indication
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53
FOT
ROT
black
NOIP1SN1300A
starting at position y0_start. When the line at position
y1_start is reached, a number of lines containing data of
‘ROI 0’ and ‘ROI 1’ are sent out, until the line position of
y0_end is reached. Then, only data of ‘ROI 1’ appears on the
data output until line position y1_end is reached. The
line_valid strobe is not shown in Figure 49.
The frame format is explained with an example of the
readout of two (overlapping) windows as shown in
Figure 49 (a).
The readout of a frame occurs on a line−by−line basis. The
read pointer goes from left to right, bottom to top. Figure 49
(a) and (b) indicate that, after the FOT is finished, a number
of lines which include information of ‘ROI 0’ are sent out,
1280 pixels
1024 pixels
y1_end
ROI1
y0_end
y1_start
ROI0
y0_start
x0_start
x0_end
x1_start
x1_end
(a)
Reset
Exposure Time N
N
Readout Frame N -1
Integration Time
Handling
Readout
Handling
FOT
ROI1
ROI0
Reset
Exposure Time N +1
N+1
Readout Frame N
FOT
FOT
ROI0
ROI1
FOT
FOT
Frame valid
(b)
Figure 49. P2−SN/SE: Frame Format to Read Out Image Data
Black Lines
possible to ‘mute’ the frame and/or line valid indications for
the black lines. Refer to Table 37 for black line, frame_valid
and line_valid settings.
Black pixel data is also sent through the data channels. To
distinguish these pixels from the regular image data, it is
Table 37. BLACK LINE FRAME_VALID AND LINE_VALID SETTINGS
bl_frame
_valid_enable
bl_line
_valid_enable
0x1
0x1
The black lines are handled similar to normal image lines. The frame valid indication is asserted
before the first black line and the line valid indication is asserted for every valid (black) pixel.
0x1
0x0
The frame valid indication is asserted before the first black line, but the line valid indication is not
asserted for the black lines. The line valid indication indicates the valid image pixels only. This
mode is useful when one does not use the black pixels and when the frame valid indication needs
to be asserted some time before the first image lines (for example, to precondition ISP pipelines).
0x0
0x1
In this mode, the black pixel data is clearly unambiguously indicated by the line valid indication,
while the decoding of the real image data is simplified.
0x0
0x0
Black lines are not indicated and frame and line valid strobes remain de−asserted. Note however
that the data channels contains the black pixel data and CRC codes (Training patterns are
interrupted).
Description
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54
NOIP1SN1300A
• P2−SN/SE: No Subsampling
Data order for P2−SN/SE: CMOS Interface Version
To read out the image data through the parallel CMOS
output, the pixel array is divided in kernels. The kernel size
is eight pixels in x−direction by one pixel in y−direction.
Figure 38 on page 48 indicates how the kernels are
organized.
The data order of this image data on the data output
channels depends on the subsampling mode.
kernel 12
kernel 13
The image data is read out in kernels of eight pixels in
x−direction by one pixel in y−direction.
Figure 50 shows the pixel sequence of a kernel which is
read out over the single CMOS output channel. The pixel
order is different for even and odd kernel positions.
kernel 14
kernel 15
time
pixel # (even kernel)
0
2
4
6
1
3
pixel # (odd kernel)
5
7
7
5
3
1
6
4
2
0
time
Figure 50. P2−SN/SE: Data Output Order without Subsampling
• P2−SN: Subsampling On Monochrome Sensor
pixel positions inside that kernel are read out. Figure 51
shows the data order
Note that there is no difference in data order for even/odd
kernel numbers, as opposed to the ‘no−subsampling’
readout.
To read out the image data with subsampling enabled on
a monochrome sensor, two neighboring kernels are
combined to a single kernel of 16 pixels in the x−direction
and one pixel in the y−direction. Only the pixels at the even
kernel 12
kernel 13
kernel 14
kernel 15
time
pixel #
0
2
4
6
14
12
10
8
time
Figure 51. P2−SN: Data Output Order with Subsampling on a Monochrome Sensor
• P2−SE: Subsampling On Color Sensor
the y−direction. Only the pixels 0, 1, 4, 5, 8, 9, 12, and 13 are
read out. Figure 52 shows the data order.
Note that there is no difference in data order for even/odd
kernel numbers, as opposed to the ‘no−subsampling’
readout.
To read out the image data with subsampling enabled on
a color sensor, two neighboring kernels are combined to a
single kernel of 16 pixels in the x−direction and one pixel in
kernel 12
kernel 13
kernel 14
kernel 15
time
pixel #
0
13
4
9
1
12
5
8
time
Figure 52. P2−SE: Data Output Order with Subsampling on a Color Sensor
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55
NOIP1SN1300A
REGISTER MAP
The table below represents the register map for the
NOIP1xx1300A part. Deviating default values for the
NOIP1xx0500A and NOIP1xx0300A are mentioned
between brackets (“[ ]”).
Table 38. REGISTER MAP
Address
Offset
Address
Default
(Hex)
Default
chip_id
0x50D0
20688
Chip ID
id
0x50D0
20688
Chip ID
reserved
0x0000
[0x0200,
0x0100]
0 [512,
256]
Reserved
[3:0]
reserved
0x1
1
Reserved
[9:8]
Resolution
0x0
[0x2,
0x1]
0 [2, 1]
0x0: PYTHON1300,
0x1: PYTHON300
0x2: PYTHON500
reserved
0x0
0
Reserved
chip_configuration
0x0000
0
Chip General Configuration
[0]
color
0x0
0
Color/Monochrome Configuration
‘0’: Monochrome
‘1’: Color
[1]
parallel
0x0
0
LVDS/Parallel Mode Selector
‘0’: LVDS
‘1’: Parallel
soft_reset_pll
0x0099
153
PLL Soft Reset Configuration
[3:0]
pll_soft_reset
0x9
9
PLL Reset
0x9: Soft Reset State
others: Operational
[7:4]
pll_lock_soft_reset
0x9
9
PLL Lock Detect Reset
0x9: Soft Reset State
others: Operational
soft_reset_cgen
0x0009
9
Clock Generator Soft Reset
cgen_soft_reset
0x9
9
Clock Generator Reset
0x9: Soft Reset State
others: Operational
soft_reset_analog
0x0999
2457
Analog Block Soft Reset
[3:0]
mux_soft_reset
0x9
9
Column MUX Reset
0x9: Soft Reset State
others: Operational
[7:4]
afe_soft_reset
0x9
9
AFE Reset
0x9: Soft Reset State
others: Operational
[11:8]
ser_soft_reset
0x9
9
Serializer Reset
0x9: Soft Reset State
others: Operational
Bit Field
Register Name
Description
Type
Chip ID [Block Offset: 0]
0
0
[15:0]
1
1
[11:10]
2
2
Status
Status
RW
Reset Generator [Block Offset: 8]
0
1
8
9
[3:0]
2
10
RW
RW
RW
PLL [Block Offset: 16]
0
16
power_down
0x0004
4
PLL Configuration
[0]
pwd_n
0x0
0
PLL Power Down
’0’: Power Down,
’1’: Operational
[1]
enable
0x0
0
PLL Enable
’0’: disabled,
’1’: enabled
[2]
bypass
0x1
1
PLL Bypass
’0’: PLL Active,
’1’: PLL Bypassed
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56
RW
NOIP1SN1300A
Table 38. REGISTER MAP
Address
Offset
Address
Default
(Hex)
Default
config1
0x0000
0
IO Configuration
clock_in_pwd_n
0x0
0
Power down Clock Input
pll_lock
0x0000
0
PLL Lock Indication
lock
0x0
0
PLL Lock Indication
config0
0x0004
4
Clock Generator Configuration
[0]
enable_analog
0x0
0
Enable analogue clocks
‘0’: disabled,
‘1’: enabled
[1]
enable_log
0x0
0
Enable logic clock
‘0’: disabled,
‘1’: enabled
[2]
select_pll
0x1
1
Input Clock Selection
‘0’: Select LVDS clock input,
‘1’: Select PLL clock input
[3]
adc_mode
0x0
0
Set operation mode of CGEN block
mux
0x0
0
Multiplex Mode
config0
0x0000
0
Clock Generator Configuration
enable
0x0
0
Logic General Enable Configuration
‘0’: Disable
‘1’: Enable
Bit Field
Register Name
Description
Type
I/O [Block Offset: 20]
0
20
[0]
RW
PLL Lock Detector [Block Offset: 24]
0
24
[0]
Status
Clock Generator [Block Offset: 32]
0
32
[5:4]
RW
‘0’: divide by 5 mode (10-bit mode),
‘1’: divide by 4 mode (8-bit mode)
General Logic [Block Offset: 34]
0
34
[0]
RW
Image Core [Block Offset: 40]
0
1
40
image_core_config0
0x0000
0
Image Core Configuration
[0]
imc_pwd_n
0x0
0
Image Core Power Down
‘0’: powered down,
‘1’: powered up
[1]
mux_pwd_n
0x0
0
Column Multiplexer Power Down
‘0’: powered down,
‘1’: powered up
[2]
colbias_enable
0x0
0
Bias Enable
‘0’: disabled
‘1’: enabled
41
image_core_config1
0x0B5A
2906
Image Core Configuration
[3:0]
dac_ds
0xA
10
Double Slope Reset Level
[7:4]
dac_ts
0x5
5
Triple Slope Reset Level
power_down
0x0000
0
AFE Configuration
pwd_n
0x0
0
Power down for AFE’s
‘0’: powered down,
‘1’: powered up
power_down
0x0000
0
Bias Power Down Configuration
pwd_n
0x0
0
Power down bandgap
‘0’: powered down,
‘1’: powered up
configuration
0x888B
34955
Bias Configuration
extres
0x1
1
External Resistor Selection
‘0’: internal resistor,
‘1’: external resistor
RW
RW
AFE [Block Offset: 48]
0
48
[0]
RW
Bias [Block Offset: 64]
0
64
[0]
1
65
[0]
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57
RW
RW
NOIP1SN1300A
Table 38. REGISTER MAP
Address
Offset
Address
Bit Field
3
4
5
Default
(Hex)
Default
Description
[7:4]
imc_colpc_ibias
0x8
8
Column Precharge ibias Configuration
[11:8]
imc_colbias_ibias
0x8
8
Column Bias ibias Configuration
cp_ibias
0x8
8
Charge Pump Bias
[15:12]
2
Register Name
66
afe_bias
0x53C8
21448
AFE Bias Configuration
[3:0]
afe_ibias
0x8
8
AFE ibias Configuration
[7:4]
afe_adc_iref
0xC
12
ADC iref Configuration
[14:8]
afe_pga_iref
0x53
83
PGA iref Configuration
mux_bias
0x8888
34952
Column Multiplexer Bias Configuration
[3:0]
mux_25u_stage1
0x8
8
Column Multiplexer Stage 1 Bias Configuration
[7:4]
mux_25u_stage2
0x8
8
Column Multiplexer Stage 2 Bias Configuration
[11:8]
mux_25u_delay
0x8
8
Column Multiplexer Delay Bias Configuration
67
68
lvds_bias
0x0088
136
LVDS Bias Configuration
[3:0]
lvds_ibias
0x8
8
LVDS Ibias
[7:4]
lvds_iref
0x8
8
LVDS Iref
adc_bias
0x0088
136
LVDS Bias Configuration
[3:0]
imc_vsfdmed_ibias
0x8
8
VSFD Medium Bias
[7:4]
adcref_ibias
0x8
8
ADC Reference Bias
configuration
0x2220
8736
Charge Pump Configuration
[0]
trans_pwd_n
0x0
0
PD Trans Charge Pump Enable
‘0’: disabled,
‘1’: enabled
[1]
resfd_calib_pwd_n
0x0
0
FD Charge Pump Enable
‘0’: disabled,
‘1’: enabled
[2]
sel_sample_pwd_n
0x0
0
Select/Sample Charge Pump Enable
‘0’: disabled
‘1’: enabled
[6:4]
trans_trim
0x2
2
PD Trans Charge Pump Trim
[10:8]
resfd_calib_trim
0x2
2
FD Charge Pump Trim
[14:12]
sel_sample_trim
0x2
2
Select/Sample Charge Pump Trim
69
Type
RW
RW
RW
RW
Charge Pump [Block Offset: 72]
0
72
RW
Temperature Sensor [Block Offset: 96]
0
1
96
enable
0x0000
0
Temperature Sensor Configuration
[0]
enable
0x0
0
Temperature Diode Enable
‘0’: disabled,
‘1’: enabled
[13:8]
offset
0x0
0
Temperature Offset (signed)
temp
0x0000
0
Temperature Sensor Status
temp
0x00
0
Temperature Readout
power_down
0x0000
0
LVDS Power Down Configuration
[0]
clock_out_pwd_n
0x0
0
Power down for Clock Output.
‘0 ’: powered down,
‘1’: powered up
[1]
sync_pwd_n
0x0
0
Power down for Sync channel
‘0’: powered down,
‘1’: powered up
[2]
data_pwd_n
0x0
0
Power down for data channels (4 channels)
‘0’: powered down,
‘1’: powered up
97
[7:0]
RW
Status
Serializers/LVDS/IO [Block Offset: 112]
0
112
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58
RW
NOIP1SN1300A
Table 38. REGISTER MAP
Address
Offset
Address
Default
(Hex)
Default
trainingpattern
0x03A6
934
Data Formating - Training Pattern
trainingpattern
0x3A6
934
Training pattern sent on Data channels during
idle mode. This data is used to perform word
alignment on the LVDS data channels.
sync_code0
0x002A
42
LVDS Power Down Configuration
frame_sync_0
0x02A
42
Frame Sync Code LSBs - Even kernels
sync_code1
0x0015
21
Data Formating - BL Indication
bl_0
0x015
21
Black Pixel Identification Sync Code - Even
kernels
sync_code2
0x0035
53
Data Formating - IMG Indication
img_0
0x035
53
Valid Pixel Identification Sync Code - Even
kernels
sync_code3
0x0025
37
Data Formating - IMG Indication
ref_0
0x025
37
Reference Pixel Identification Sync Code Even kernels
sync_code4
0x002A
42
LVDS Power Down Configuration
frame_sync_1
0x02A
42
Frame Sync Code LSBs - Odd kernels
sync_code5
0x0015
21
Data Formating - BL Indication
bl_1
0x015
21
Black Pixel Identification Sync Code Odd kernels
sync_code6
0x0035
53
Data Formating - IMG Indication
img_1
0x035
53
Valid Pixel Identification Sync Code Odd kernels
sync_code7
0x0025
37
Data Formating - IMG Indication
ref_1
0x025
37
Reference Pixel Identification Sync Code Odd kernels
sync_code8
0x0059
89
Data Formating - CRC Indication
crc
0x059
89
CRC Value Identification Sync Code
sync_code9
0x03A6
934
Data Formating - TR Indication
tr
0x3A6
934
Training Value Identification Sync Code
blackcal
0x4008
16392
Black Calibration Configuration
[7:0]
black_offset
0x08
8
Desired black level at output
[10:8]
black_samples
0x0
0
Black pixels taken into account for black
calibration.
Total samples = 2**black_samples
crc_seed
0x0
0
CRC Seed
‘0’: All-0
‘1’: All-1
general_configuration
0x0001
1
Black Calibration and Data Formating
Configuration
auto_blackcal_enable
0x1
1
Automatic blackcalibration is enabled when 1,
bypassed when 0
[9:1]
blackcal_offset
0x00
0
Black Calibration offset used when auto_black_cal_en = ‘0’.
[10]
blackcal_offset_dec
0x0
0
blackcal_offset is added when 0, subtracted
when 1
[13]
8bit_mode
0x0
0
Shifts window ID indications by 4 cycles.
‘0’: 10 bit mode,
‘1’: 8 bit mode
Bit Field
Register Name
Description
Type
Sync Words [Block Offset: 116]
4
116
[9:0]
5
117
6
118
[6:0]
[9:0]
7
119
[9:0]
8
120
[9:0]
9
121
[6:0]
10
122
[9:0]
11
123
[9:0]
12
124
[9:0]
13
125
14
126
[9:0]
[9:0]
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Data Block [Block Offset: 128]
0
128
[15]
1
129
[0]
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59
RW
RW
NOIP1SN1300A
Table 38. REGISTER MAP
Address
Offset
2
Address
Bit Field
Register Name
Default
(Hex)
Default
[14]
ref_mode
0x0
0
Data contained on reference lines:
‘0’: reference pixels
‘1’: black average for the corresponding data
channel
[15]
ref_bcal_enable
0x0
0
Enable black calibration on reference lines
‘0’: Disabled
‘1’: Enabled
trainingpattern
0x000F
15
Data Formating - Training Pattern
bl_frame_valid_enable
0x1
1
Assert frame_valid for black lines when ‘1’,
gate frame_valid for black lines when ‘0’.
Parallel output mode only.
bl_line_valid_enable
0x1
1
Assert line_valid for black lines when ‘1’, gate
line_valid for black lines when ‘0’.
Parallel output mode only.
ref_frame_valid_enable
0x1
1
Assert frame_valid for ref lines when ‘1’, gate
frame_valid for black lines when ‘0’.
Parallel output mode only.
[3]
ref_line_valid_enable
0x1
1
Assert line_valid for ref lines when ‘1’, gate
line_valid for black lines when ‘0’.
Parallel output mode only.
[4]
frame_valid_mode
0x0
0
Behaviour of frame_valid strobe between
overhead lines when [0] and/or [1] is
deasserted:
‘0’: retain frame_valid deasserted between
lines
‘1’: assert frame_valid between lines
blackcal_error0
0x0000
0
Black Calibration Status
blackcal_error[15:0]
0x0000
0
Black Calibration Error. This flag is set when
not enough black samples are availlable.
Black Calibration shall not be valid.
Channels 0-16
(channels 0-7 for PYTHON1300)
test_configuration
0x0000
0
Data Formating Test Configuration
[0]
testpattern_en
0x0
0
Insert synthesized testpattern when ‘1’
[1]
inc_testpattern
0x0
0
Incrementing testpattern when ‘1’, constant
testpattern when ’0’
[2]
prbs_en
0x0
0
Insert PRBS when ‘1’
[3]
frame_testpattern
0x0
0
Frame test patterns when ‘1’, unframed
testpatterns when ‘0’
130
[0]
[1]
[2]
8
136
[15:0]
16
18
19
22
Description
144
146
test_configuration0
0x0100
256
Data Formating Test Configuration
[7:0]
testpattern0_lsb
0x00
0
Testpattern used on datapath #0 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
[15:8]
testpattern1_lsb
0x01
1
Testpattern used on datapath #1 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
147
test_configuration1
0x0302
770
Data Formating Test Configuration
[7:0]
testpattern2_lsb
0x02
2
Testpattern used on datapath #2 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
[15:8]
testpattern3_lsb
0x03
3
Testpattern used on datapath #3 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
test_configuration16
0x0000
0
Data Formating Test Configuration
[1:0]
testpattern0_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
[3:2]
testpattern1_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
150
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60
Type
RW
Status
RW
RW
RW
RW
NOIP1SN1300A
Table 38. REGISTER MAP
Address
Offset
Address
Bit Field
Register Name
Default
(Hex)
Default
Description
[5:4]
testpattern2_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
[7:6]
testpattern3_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
configuration
0x0010
16
AEC Configuration
[0]
enable
0x0
0
AEC Enable
[1]
restart_filter
0x0
0
Restart AEC filter
[2]
freeze
0x0
0
Freeze AEC filter and enforcer gains
[3]
pixel_valid
0x0
0
Use every pixel from channel when 0, every
4th pixel when 1
[4]
amp_pri
0x1
1
Column amplifier gets higher priority than AFE
PGA in gain distribution if 1. Vice versa if 0
intensity
0x60B8
24760
AEC Configuration
desired_intensity
0xB8
184
Target average intensity
red_scale_factor
0x0080
128
Red Scale Factor
red_scale_factor
0x80
128
Red Scale Factor
3.7 unsigned
green1_scale_factor
0x0080
128
Green1 Scale Factor
green1_scale_factor
0x80
128
Green1 Scale Factor
3.7 unsigned
green2_scale_factor
0x0080
128
Green2 Scale Factor
green2_scale_factor
0x80
128
Green2 Scale Factor
3.7 unsigned
blue_scale_factor
0x0080
128
Blue Scale Factor
blue_scale_factor
0x80
128
Blue Scale Factor
3.7 unsigned
min_exposure
0x0001
1
Minimum Exposure Time
min_exposure
0x0001
1
Minimum Exposure Time
min_gain
0x0800
2048
Minimum Gain
[1:0]
min_mux_gain
0x0
0
Minimum Column Amplifier Gain
[3:2]
min_afe_gain
0x0
0
Minimum AFE PGA Gain
[15:4]
min_digital_gain
0x080
128
Minimum Digital Gain
5.7 unsigned
max_exposure
0x03FF
1023
Maximum Exposure Time
max_exposure
0x03FF
1023
Maximum Exposure Time
Type
AEC [Block Offset: 160]
0
1
160
161
[9:0]
2
162
[9:0]
3
163
[9:0]
4
164
[9:0]
5
165
[9:0]
8
168
9
169
[15:0]
10
170
[15:0]
11
24
171
max_gain
0x100D
4109
Maximum Gain
[1:0]
max_mux_gain
0x1
1
Maximum Column Amplifier Gain
[3:2]
max_afe_gain
0x3
3
Maximum AFE PGA Gain
[15:4]
max_digital_gain
0x100
256
Maximum Digital Gain
5.7 unsigned
total_pixels0
0x0000
0
AEC Status
total_pixels[15:0]
0x0000
0
Total number of pixels sampled for Average,
LSB
total_pixels1
0x0000
0
AEC Status
total_pixels[23:16]
0x0
0
Total number of pixels sampled for Average,
MSB
average_status
0x0000
0
ASE Status
[9:0]
average
0x000
0
AEC Average Status
[12]
avg_locked
0x0
0
AEC Average Lock Status
184
[15:0]
25
185
[7:0]
26
186
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61
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Status
Status
Status
NOIP1SN1300A
Table 38. REGISTER MAP
Address
Offset
Address
27
187
28
188
Default
(Hex)
Default
exposure_status
0x0000
0
ASE Status
exposure
0x0000
0
AEC Exposure Status
gain_status
0x0000
0
ASE Status
[1:0]
mux_gain
0x0
0
AEC MUX Gain Status
[3:2]
afe_gain
0x0
0
AEC AFE Gain Status
[15:4]
digital_gain
0x000
0
AEC Digital Gain Status
5.7 unsigned
general_configuration
0x0000
0
Sequencer General Configuration
[0]
enable
0x0
0
Enable sequencer
‘0’: Idle,
‘1’: enabled
[1]
operation selection
0x0
0
‘0’: Global Shutter
[2]
zero_rot_enable
0x0
0
Zero ROT mode Selection.
‘0’: Normal ROT,
‘1’: Zero ROT’
[3]
reserved
0x0
0
Reserved
[4]
triggered_mode
0x0
0
Triggered Mode Selection
‘0’: Normal Mode,
‘1’: Triggered Mode
[5]
slave_mode
0x0
0
Master/Slave Selection
‘0’: master,
‘1’: slave
[6]
nzrot_xsm_delay_enable
0x0
0
Insert delay between end of ROT and start of
readout in normal ROT readout mode if ‘1’.
ROT delay is defined by register xsm_delay
[7]
subsampling
0x0
0
Subsampling mode selection
‘0’: no subsampling,
‘1’: subsampling
[8]
binning
0x0
0
Binning mode selection
‘0’: no binning,
‘1’: binning
[10]
roi_aec_enable
0x0
0
Enable windowing for AEC Statistics.
‘0’: Subsample all windows
‘1’: Subsample configured window
[13:11]
monitor_select
0x0
0
Control of the monitor pins
delay_configuration
0x0000
0
Sequencer Delay Configuration
xsm_delay
0x00
0
Delay between ROT start and X-readout (Zero
ROT mode)
Delay between ROT end and X-readout
(Normal ROT mode with
nzrot_xsm_delay_enable=‘1’)
integration_control
0x00E4
228
Integration Control
[0]
dual_slope_enable
0x0
0
Enable Dual Slope
[1]
triple_slope_enable
0x0
0
Enable Triple Slope
[2]
fr_mode
0x1
1
Representation of fr_length.
‘0’: reset length
‘1’: frame length
[4]
int_priority
0x0
0
Integration Priority
‘0’: Frame readout has priority over integration
‘1’: Integration End has priority over frame
readout
[5]
halt_mode
0x1
1
The current frame will be completed when the
sequencer is disabled and halt_mode = ‘1’.
When ‘0’, the sensor stops immediately when
disabled, without finishing the current frame.
Bit Field
[15:0]
Register Name
Description
Type
Status
Status
Sequencer [Block Offset: 192]
0
1
192
193
[15:8]
2
194
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62
RW
RW
RW
NOIP1SN1300A
Table 38. REGISTER MAP
Address
Offset
3
Address
Bit Field
7
1
Generation of Frame Sequence Start Sync
code (FSS)
‘0’: No generation of FSS
‘1’: Generation of FSS
[7]
fse_enable
0x1
1
Generation of Frame Sequence End Sync
code (FSE)
‘0’: No generation of FSE
‘1’: Generation of FSE
[8]
reverse_y
0x0
0
Reverse readout
‘0’: bottom to top readout
‘1’: top to bottom readout
[11:10]
subsampling_mode
0x0
0
Subsampling mode
“00”: Subsampling in x and y (VITA
compatible)
“01”: Subsampling in x, not y
“10”: Subsampling in y, not x
“11”: Subsampling in x an y
[13:12]
binning_mode
0x0
0
Binning mode
“00”: Binning in x and y (VITA compatible)
“01”: Binning in x, not y
“10”: Binning in y, not x
“11”: Binning in x an y
roi_active0_0
0x0001
1
Active ROI Selection
roi_active0[7:0]
0x01
1
Active ROI Selection
[0] Roi0 Active
[1] Roi1 Active
...
[7] Roi7 Active
195
197
black_lines
0x0102
258
Black Line Configuration
[7:0]
black_lines
0x02
2
Number of black lines. Minimum is 1.
Range 1-255
[12:8]
gate_first_line
0x1
1
Blank out first lines
0: no blank
1-31: blank 1-31 lines
mult_timer0
0x0001
1
Exposure/Frame Rate Configuration
mult_timer0
0x0001
1
Mult Timer
Defines granularity (unit = 1/PLL clock) of
exposure and reset_length
fr_length0
0x0000
0
Exposure/Frame Rate Configuration
fr_length0
0x0000
0
Frame/Reset length
Reset length when fr_mode = ‘0’, Frame
Length when fr_mode = ‘1’
Granularity defined by mult_timer
exposure0
0x0000
0
Exposure/Frame Rate Configuration
exposure0
0x0000
0
Exposure Time
Granularity defined by mult_timer
exposure_ds0
0x0000
0
Exposure/Frame Rate Configuration
exposure_ds0
0x0000
0
Exposure Time (Dual Slope)
Granularity defined by mult_timer
exposure_ts0
0x0000
0
Exposure/Frame Rate Configuration
exposure_ts0
0x0000
0
Exposure Time (Triple Slope)
Granularity defined by mult_timer
199
200
201
[15:0]
10
202
[15:0]
11
203
[15:0]
12
Description
0x1
[15:0]
9
Default
fss_enable
[15:0]
8
Default
(Hex)
[6]
[7:0]
5
Register Name
204
gain_configuration0
0x01E3
483
Gain Configuration
[4:0]
mux_gainsw0
0x03
3
Column Gain Setting
[12:5]
afe_gain0
0xF
15
AFE Programmable Gain Setting
gain_lat_comp
0x0
0
Postpone gain update by 1 frame when ‘1’ to
compensate for exposure time updates latency.
Gain is applied at start of next frame if ‘0’
[13]
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Type
RW
RW
RW
RW
RW
RW
RW
RW
NOIP1SN1300A
Table 38. REGISTER MAP
Address
Offset
Address
13
205
14
206
Default
(Hex)
Default
digital_gain
_configuration0
0x0080
128
Gain Configuration
db_gain0
0x080
128
Digital Gain
sync_configuration
0x037F
895
Synchronization Configuration
[0]
sync_rs_x_length
0x1
1
Update of rs_x_length will not be sync’ed at
start of frame when ‘0’
[1]
sync_black_lines
0x1
1
Update of black_lines will not be sync’ed at start
of frame when ‘0’
[2]
sync_dummy_lines
0x1
1
Update of dummy_lines will not be sync’ed at
start of frame when ‘0’
[3]
sync_exposure
0x1
1
Update of exposure will not be sync’ed at start of
frame when ‘0’
[4]
sync_gain
0x1
1
Update of gain settings (gain_sw, afe_gain) will
not be sync’ed at start of frame when ‘0’
[5]
sync_roi
0x1
1
Update of roi updates (active_roi) will not be
sync’ed at start of frame when ‘0’
[6]
sync_ref_lines
0x1
1
Update of ref_lines will not be sync’ed at start of
frame when ‘0’
[8]
blank_roi_switch
0x1
1
Blank first frame after ROI switching
[9]
blank
_subsampling_ss
0x1
1
Blank first frame after subsampling/binning
mode.
[10]
exposure_sync_mode
0x0
0
When ‘0’, exposure configurations are sync’ed
at the start of FOT. When ‘1’, exposure
configurations sync is disabled (continuously
syncing). This mode is only relevant for Triggered snapshot - master mode, where the exposure configurations are sync’ed at the start
of exposure rather than the start of FOT. For
all other modes it should be set to ‘0’.
Note: Sync is still postponed if
sync_exposure=‘0’.
ref_lines
0x0000
0
Reference Line Configuration
ref_lines
0x00
0
Number of Reference Lines
0-255
Bit Field
[11:0]
15
207
[7:0]
28
36
220
Register Name
reserved
0x301F
12319
Reserved
[6:0]
reserved
0x1F
31
Reserved
[14:8]
reserved
0x30
48
Reserved
roi_active0_1
0x0001
1
Active ROI Selection
roi_active1[7:0]
0x01
1
ROI Configuration
x_resolution
0x00A0
[0x0068,
0x0054]
160
[104, 84]
Sequencer Status
x_resolution
0x00A0
[0x0068,
0x0054]
160
[104, 84]
Sensor x resolution
y_resolution
0x0400
[0x0268,
0x01F0]
1024
[616,
496]
Sequencer Status
y_resolution
0x0400
[0x0268,
0x01F0]
1024
[616,
496]
Sensor y resolution
mult_timer_status
0x0000
0
Sequencer Status
mult_timer
0x0000
0
Mult Timer Status (Master Snapshot Shutter
only)
reset_length_status
0x0000
0
Sequencer Status
reset_length
0x0000
0
Current Reset Length (not in Slave mode)
228
[7:0]
240
48
[7:0]
241
49
[12:0]
50
242
[15:0]
51
Description
243
[15:0]
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Type
RW
RW
RW
RW
RW
Status
Status
Status
Status
NOIP1SN1300A
Table 38. REGISTER MAP
Address
Offset
Address
52
244
53
245
54
246
Bit Field
[15:0]
[15:0]
[15:0]
55
56
247
62
exposure_status
0x0000
0
Sequencer Status
exposure
0x0000
0
Current Exposure Time (not in Slave mode)
exposure_ds_status
0x0000
0
Sequencer Status
exposure_ds
0x0000
0
Current Exposure Time (not in Slave mode)
exposure_ts_status
0x0000
0
Sequencer Status
exposure_ts
0x0000
0
Current Exposure Time (not in Slave mode)
Description
gain_status
0x0000
0
Sequencer Status
mux_gainsw
0x00
0
Current Column Gain Setting
[12:5]
afe_gain
0x00
0
Current AFE Programmable Gain
digital_gain_status
0x0000
0
Sequencer Status
db_gain
0x000
0
Digital Gain
[12]
dual_slope
0x0
0
Dual Slope Enabled
[13]
triple_slope
0x0
0
Triple Slope Enabled
roi_aec_configuration0
0x0000
0
AEC ROI Configuration
[7:0]
x_start
0x00
0
AEC ROI X Start Configuration (used for AEC
statistics when roi_aec_enable=‘1’)
[15:8]
x_end
0x00
0
AEC ROI X End Configuration (used for AEC
statistics when roi_aec_enable=‘1’)
roi_aec_configuration1
0x0000
0
AEC ROI Configuration
y_start
0x0000
0
AEC ROI Y Start Configuration (used for AEC
statistics when roi_aec_enable=‘1’)
roi_aec_configuration2
0x0000
0
AEC ROI Configuration
y_end
0x0000
0
AEC ROI Y End Configuration (used for AEC
statistics when roi_aec_enable=‘1’)
roi0_configuration0
0x9F00
40704
ROI Configuration
For the P1300: 0x09F00
P500: 0x5100
P300: 0x6500
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0x9F
159
X End Configuration
roi0_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi0_configuration2
0x03FF
1023
ROI Configuration
y_end
0x3FF
1023
Y End Configuration
roi1_configuration0
0x9F00
40704
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0x9F
159
X End Configuration
roi1_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi1_configuration2
0x03FF
1023
ROI Configuration
y_end
0x3FF
1023
Y End Configuration
248
253
254
[12:0]
63
Default
[4:0]
[11:0]
61
Default
(Hex)
Register Name
255
[12:0]
Type
Status
Status
Status
Status
Status
RW
RW
RW
Sequencer ROI [Block Offset: 256]
0
256
1
257
2
258
3
259
[12:0]
[12:0]
4
260
5
261
[12:0]
[12:0]
6
262
roi2_configuration0
0x9F00
40704
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0x9F
159
X End Configuration
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65
RW
RW
RW
RW
RW
RW
RW
NOIP1SN1300A
Table 38. REGISTER MAP
Address
Offset
Address
7
263
8
264
9
265
Default
(Hex)
Default
roi2_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi2_configuration2
0x03FF
1023
ROI Configuration
y_end
0x3FF
1023
Y End Configuration
roi3_configuration0
0x9F00
40704
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0x9F
159
X End Configuration
roi3_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi3_configuration2
0x03FF
1023
ROI Configuration
y_end
0x3FF
1023
Y End Configuration
Bit Field
[12:0]
[12:0]
10
266
11
267
[12:0]
[12:0]
12
13
268
roi4_configuration0
0x9F00
40704
ROI Configuration
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0x9F
159
X End Configuration
roi4_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi4_configuration2
0x03FF
1023
ROI Configuration
y_end
0x3FF
1023
Y End Configuration
269
270
[12:0]
15
16
271
roi5_configuration0
0x9F00
40704
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0x9F
159
X End Configuration
roi5_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi5_configuration2
0x03FF
1023
ROI Configuration
y_end
0x3FF
1023
Y End Configuration
roi6_configuration0
0x9F00
40704
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0x9F
159
X End Configuration
roi6_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi6_configuration2
0x03FF
1023
ROI Configuration
y_end
0x3FF
1023
Y End Configuration
roi7_configuration0
0x9F00
40704
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0x9F
159
X End Configuration
roi7_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi7_configuration2
0x03FF
1023
ROI Configuration
y_end
0x3FF
1023
Y End Configuration
272
[12:0]
17
273
[12:0]
18
19
274
275
[12:0]
20
276
21
277
[12:0]
22
278
23
279
Description
[7:0]
[12:0]
14
Register Name
[12:0]
[12:0]
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66
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOIP1SN1300A
PACKAGE INFORMATION
Pin List
The PYTHON 300, PYTHON 500, and PYTHON 1300 image sensors are available in an LVDS output configuration
(P1&P3−SN/SE/FN), with the PYTHON 1300 also available in a CMOS output configuration (P2−SN/SE). The LVDS I/Os
comply to the TIA/EIA−644−A Standard and the CMOS I/Os have a 3.3 V signal level. Tables 39 and 40 show the pin list for
both versions.
Table 39. PIN LIST FOR P1, P3 −SN/SE/FN LVDS INTERFACE
Pack Pin
No.
Pin Name
I/O Type
Direction
Description
1
vdd_33
Supply
2
mosi
CMOS
Input
3.3 V Supply
SPI Master Out − Slave In
3
miso
CMOS
Output
SPI Master In − Slave Out
4
sck
CMOS
Input
5
gnd_18
Supply
1.8 V Ground
6
vdd_18
Supply
1.8 V Supply
7
clock_outn
LVDS
Output
LVDS Clock Output (Negative)
8
clock_outp
LVDS
Output
LVDS Clock Output (Positive)
9
doutn0
LVDS
Output
LVDS Data Output Channel #0 (Negative)
10
doutp0
LVDS
Output
LVDS Data Output Channel #0 (Positive)
11
doutn1
LVDS
Output
LVDS Data Output Channel #1 (Negative). Not connected for P3
12
doutp1
LVDS
Output
LVDS Data Output Channel #1 (Positive). Not connected for P3
13
doutn2
LVDS
Output
LVDS Data Output Channel #2 (Negative)
14
doutp2
LVDS
Output
LVDS Data Output Channel #2 (Positive)
15
doutn3
LVDS
Output
LVDS Data Output Channel #3 (Negative). Not connected for P3
16
doutp3
LVDS
Output
LVDS Data Output Channel #3 (Positive). Not connected for P3
17
syncn
LVDS
Output
LVDS Sync Channel Output (Negative)
18
syncp
LVDS
Output
LVDS Sync Channel Output (Positive)
19
vdd_33
Supply
3.3 V Supply
20
gnd_33
Supply
3.3 V Ground
21
gnd_18
Supply
1.8 V Ground
22
vdd_18
Supply
1.8 V Supply
23
lvds_clock_inn
LVDS
Input
LVDS Clock Input (Negative)
24
lvds_clock_inp
LVDS
Input
LVDS Clock Input (Positive)
25
clk_pll
CMOS
Input
Reference Clock Input for PLL
26
vdd_18
Supply
1.8 V Supply
27
gnd_18
Supply
1.8 V Ground
28
ibias_master
Analog
29
vdd_33
Supply
3.3 V Supply
30
gnd_33
Supply
3.3 V Ground
31
vdd_pix
Supply
Pixel Array Supply
32
gnd_colpc
Supply
Pixel Array Ground
33
vdd_pix
Supply
Pixel Array Supply
34
gnd_colpc
Supply
Pixel Array Ground
35
gnd_33
Supply
3.3 V Ground
SPI Clock
I/O
Master Bias Reference. Connect with 47k to gnd_33.
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67
NOIP1SN1300A
Table 39. PIN LIST FOR P1, P3 −SN/SE/FN LVDS INTERFACE
Pack Pin
No.
Pin Name
I/O Type
Direction
Description
36
vdd_33
Supply
3.3 V Supply
37
gnd_colpc
Supply
Pixel Array Ground
38
vdd_pix
Supply
Pixel Array Supply
39
gnd_colpc
Supply
Pixel Array Ground
40
vdd_pix
Supply
Pixel Array Supply
41
trigger0
CMOS
Input
Trigger Input #0
42
trigger1
CMOS
Input
Trigger Input #1
43
trigger2
CMOS
Input
Trigger Input #2
44
monitor0
CMOS
Output
Monitor Output #0
45
monitor1
CMOS
Output
Monitor Output #1
46
reset_n
CMOS
Input
Sensor Reset (Active Low)
47
ss_n
CMOS
Input
SPI Slave Select (Active Low)
48
gnd_33
Supply
3.3 V Ground
Table 40. PIN LIST FOR P2−SN/SE CMOS INTERFACE
Pack Pin
No.
Pin Name
I/O Type
Direction
Description
1
vdd_33
Supply
2
mosi
CMOS
Input
3.3 V Supply
SPI Master Out − Slave In
3
miso
CMOS
Output
SPI Master In − Slave Out
4
sck
CMOS
Input
5
gnd_18
Supply
1.8 V Ground
6
vdd_18
Supply
1.8 V Supply
7
dout9
CMOS
Output
Data Output Bit #9
8
dout8
CMOS
Output
Data Output Bit #8
9
dout7
CMOS
Output
Data Output Bit #7
10
dout6
CMOS
Output
Data Output Bit #6
11
dout5
CMOS
Output
Data Output Bit #5
12
dout4
CMOS
Output
Data Output Bit #4
13
dout3
CMOS
Output
Data Output Bit #3
14
dout2
CMOS
Output
Data Output Bit #2
15
dout1
CMOS
Output
Data Output Bit #1
16
dout0
CMOS
Output
Data Output Bit #0
17
frame_valid
CMOS
Output
Frame Valid Output
18
line_valid
CMOS
Output
Line Valid Output
19
vdd_33
Supply
3.3 V Supply
20
gnd_33
Supply
3.3 V Ground
21
clk_out
CMOS
Clock output
22
vdd_18
Supply
1.8 V Supply
23
lvds_clock_inn
LVDS
Input
LVDS Clock Input (Negative)
24
lvds_clock_inp
LVDS
Input
LVDS Clock Input (Positive)
25
clk_pll
CMOS
Input
CMOS Clock Input
SPI Clock
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68
NOIP1SN1300A
Table 40. PIN LIST FOR P2−SN/SE CMOS INTERFACE
Pack Pin
No.
Pin Name
I/O Type
Direction
Description
26
vdd_18
Supply
1.8 V Supply
27
gnd_18
Supply
1.8 V Ground
28
ibias_master
Analog
29
vdd_33
Supply
3.3 V Supply
30
gnd_33
Supply
3.3 V Ground
31
vdd_pix
Supply
Pixel Array Supply
32
gnd_colpc
Supply
Pixel Array Ground
33
vdd_pix
Supply
Pixel Array Supply
34
gnd_colpc
Supply
Pixel Array Ground
35
gnd_33
Supply
3.3 V Ground
36
vdd_33
Supply
3.3 V Supply
37
gnd_colpc
Supply
Pixel Array Ground
38
vdd_pix
Supply
Pixel Array Supply
39
gnd_colpc
Supply
Pixel Array Ground
40
vdd_pix
Supply
Pixel Array Supply
41
trigger0
CMOS
Input
Trigger Input #0
42
trigger1
CMOS
Input
Trigger Input #1
43
trigger2
CMOS
Input
Trigger Input #2
44
monitor0
CMOS
Output
Monitor Output #0
45
monitor1
CMOS
Output
Monitor Output #1
46
reset_n
CMOS
Input
Sensor Reset (Active Low)
47
ss_n
CMOS
Input
SPI Slave Select (Active Low)
48
gnd_33
Supply
I/O
Master Bias Reference. Connect with 47k to gnd_33.
3.3 V Ground
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69
NOIP1SN1300A
Mechanical Specification
Parameter
Die
(Refer to Figure 54
showing Pin 1
reference as left
center)
Glass Lid
Specification
Description
Min
Die thickness
Die Size
Typ
Max
Units
725
mm
9.0 X 7.95
mm2
Die center, X offset to the center of package
−50
0
50
Die center, Y offset to the center of the package
mm
−225
−175
−125
mm
Die position, tilt to the Die Attach Plane
−1
0
1
deg
Die rotation accuracy (referenced to die scribe and lead fingers on package on all four sides)
−1
0
1
deg
Optical center referenced from the die/package center (X−dir)
−179
mm
Optical center referenced from the die center (Y−dir)
1542
mm
Optical center referenced from the package center (Y−dir)
1367
mm
Distance from bottom of the package to top of the die surface
1.165
1.260
1.405
mm
Distance from top of the die surface to top of the glass lid
0.655
0.990
1.305
mm
XY size
mm2
13.6 X 13.6
Thickness
0.5
Spectral response range
400
Transmission of glass lid (refer to Figure 53)
0.55
0.6
mm
1000
nm
92
%
Glass Lid Material
D263 Teco
Mechanical Shock
JESD22−B104C; Condition G
2000
g
Vibration
JESD22−B103B; Condition 1
2000
Hz
Mounting Profile
Reflow profile according to J−STD−020D.1
260
°C
Recommended
Socket
Andon Electronics Corporation
http://www.andonelect.com
680−48−SM−G10−R14−X
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70
NOIP1SN1300A
Package Drawing
R.19
GLASS
Cross section view
0.55
Side view
1.65
1.08
2.28
A
1.26
A
SECTION A−A
Figure 53. Package Drawing for the 48−pin LCC Package
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71
NOIP1SN1300A
• Active Area outer dimensions
Optical Center Information
The center of the die (CD) is exactly at 50% between the
outsides of the two outer seal rings
The center of the cavity (CC) is exactly at 50% between
the insides of the finger pads and is equivalent to the center
of the package.
• Die outer dimensions:
♦ D4 is the reference for the Die (0,0) in mm
♦ D3 is at (7950,0) mm
♦ D2 is at (7950,9000) mm
♦ D1 is at (0,9000) mm
A1 is the at (707, 8517) mm
A2 is at (6885, 8517) mm
♦ A3 is at (6885, 3568) mm
♦ A4 is at (707, 3568) mm
Center of the Active Area
♦ AA is at (3796, 6042) mm
Center of the Die
♦ CD is at (3975, 4500) mm
Center of Cavity
♦ CC is at (3975,4675) mm
♦
♦
•
•
•
Top view
6.93
7.29
5.74
Center of
optical area
Center of
package
Optical area
Die
1.37
8.48
0.18
Pixel 0,0
Pin 1
Pin 2
DETAIL E
0.51
5.917
Pin 1
0.51
E
R0.19
Pin 2
1.02
7.464
6.275
SCALE 10:1
1.27
4.728
Center of
optical area
1.27
DETAIL D
D
SCALE 10:1
View from bottom side
Figure 54. Graphical Representation of the Optical Center
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72
NOIP1SN1300A
Packing and Tray Specification
The PYTHON packing specification with ON Semiconductor packing labels is packed as follows:
Table 41.
CLCC
Package (mm)
Tray
Restraint
Box
Leads
Length
Width
Thickness
Tray Spec#
Quantity / Tray
Strap
Bag
Tray Quantity
48
14.22
14.22
2.2
KS−87233
64
Rubber
band
Double bagged
using MBB and
pink ESD bag
5 trays + 1
cover tray
Figure 55. Packing and Tray Configuration
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73
NOIP1SN1300A
Glass Lid
As shown in Figure 52, no infrared attenuating color filter
glass is used. Use of an IR cut filter is recommended in the
optical path when color devices are used. (source:
http://www.pgo−online.com).
The PYTHON 300, PYTHON 500, and PYTHON 1300
image sensors use a glass lid without any coatings. Figure 44
shows the transmission characteristics of the glass lid.
Figure 56. Transmission Characteristics of the Glass Lid
Protective Foil
removed after assembly The dimensions of the foil are as
illustrated in Figure 57 with the tab aligned towards pin 1 of
the package.
For certain size and speed options, the sensor can be
delivered with a protective foil that is intended to be
(units in mm)
Figure 57. Dimensions of the Protective Foil
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NOIP1SN1300A
SPECIFICATIONS AND USEFUL REFERENCES
Image Sensor Handling and Best Practices Application
Note (AN52561/D) from www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on acronyms and a glossary of terms
used, please download Image Sensor Terminology
(TND6116/D) from www.onsemi.com.
The following references are available to customers
under NDA at the ON Semiconductor Image Sensor Portal:
https://www.onsemi.com/PowerSolutions/myon/erCispFol
der.do
• Product Acceptance Criteria
• Product Qualification Report
• PYTHON Developer’s Guide AND9362/D
Material Composition is available at
http://www.onsemi.com/PowerSolutions/MaterialCompos
ition.do?searchParts=PYTHON1300
Return Material Authorization (RMA)
Useful References
Refer to the ON Semiconductor RMA policy procedure at
http://www.onsemi.com/site/pdf/CAT_Returns_FailureAn
alysis.pdf
For information on ESD handling, cover glass care and
cleanliness, mounting information, please download the
ON Semiconductor and
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NOIP1SN1300A/D