16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC AD7723 16-bit Σ-∆ ADC 1.2 MSPS output word rate 32×/16× oversampling ratio Low-pass and band-pass digital filter Linear phase On-chip 2.5 V voltage reference Standby mode Flexible parallel or serial interface Crystal oscillator Single 5 V supply GENERAL DESCRIPTION The AD7723 is a complete 16-bit, sigma-delta ADC. The part operates from a 5 V supply. The analog input is continuously sampled, eliminating the need for an external sample-and-hold. The modulator output is processed by a finite impulse response (FIR) digital filter. The on-chip filtering combined with a high oversampling ratio reduces the external antialias requirements to first order in most cases. The digital filter frequency response can be programmed to be either low-pass or band-pass. The AD7723 provides 16-bit performance for input bandwidths up to 460 kHz at an output word rate up to 1.2 MHz. The sample rate, filter corner frequencies, and output word rate are set by the crystal oscillator or external clock frequency. Data can be read from the device in either serial or parallel format. A stereo mode allows data from two devices to share a single serial data line. All interface modes offer easy, high speed connections to modern digital signal processors. FUNCTIONAL BLOCK DIAGRAM AVDD 2.5V REFERENCE AD7723 AGND VIN(+) VIN(–) MODULATOR FIR FILTER UNI HALF_PWR STBY MODE 1 MODE 2 SYNC DVDD/ CS CFMT/RD DGND/DRDY DGND/DB0 REF2 REF1 DVDD DGND XTAL CLOCK XTAL_OFF XTAL CLKIN DGND/DB15 DGND/DB14 CONTROL LOGIC SCR/DB13 SLDR/DB12 SLP/DB11 TSI/DB10 FSO/DB9 DGND/ DGND/ DGND/ DOE/ SFMT/ FSI/ SCO/ SDO/ DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 Figure 1. The part provides an on-chip 2.5 V reference. Alternatively, an external reference can be used. A power-down mode reduces the idle power consumption to 200 µW. The AD7723 is available in a 44-lead MQFP package and is specified over the industrial temperature range from –40°C to +85°C. Two input modes are provided, allowing both unipolar and bipolar input ranges. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved. 01186-001 FEATURES AD7723 TABLE OF CONTENTS Specifications..................................................................................... 3 System Synchronization ................................................................ 23 Timing Specifications....................................................................... 6 Data Interfacing .............................................................................. 24 Absolute Maximum Ratings.......................................................... 10 Parallel Interface......................................................................... 24 ESD Caution................................................................................ 10 Serial Interface ................................................................................ 25 Pin Configuration And Function Descriptions.......................... 11 Two-Channel Multiplexed Operation ..................................... 25 Terminology .................................................................................... 14 Serial Interface to DSPs ................................................................. 27 Typical Performance Characteristics ........................................... 15 AD7723 to ADSP-21xx Interface ............................................. 27 Circuit Description......................................................................... 18 AD7723 to SHARC Interface.................................................... 27 Applying the AD7723 .................................................................... 20 AD7723 to DSP56002 Interface ............................................... 27 Analog Input Range ................................................................... 20 AD7723 to TMS320C5x Interface............................................ 27 Analog Input ............................................................................... 20 Grounding and Layout .................................................................. 28 Driving the Analog Inputs ........................................................ 20 Outline Dimensions ....................................................................... 29 Applying the Reference.............................................................. 21 Ordering Guide .......................................................................... 29 Clock Generation ....................................................................... 22 REVISION HISTORY 5/05—Rev. B to Rev. C Changes to Format .............................................................Universal Changes to Figure 6.......................................................................... 8 Changes to System Synchronization ............................................ 23 Updated Outline Dimensions ....................................................... 29 Changes to the Ordering Guide.................................................... 29 9/02—Data Sheet changed from Rev. 0 to Rev. A New TPCs 1 and 2 Added ............................................................. 13 Edits to Figures 17 and 18 ............................................................. 18 Outline Dimensions Updated....................................................... 23 10/03—Rev. A to Rev. B Changes to Ordering Guide ............................................................ 8 Outline Dimensions Updated ....................................................... 23 Rev. C | Page 2 of 32 AD7723 SPECIFICATIONS1 AVDD = DVDD = 5 V ± 5%; AGND = AGND1 = AGND2 = DGND = 0 V; fCLKIN = 19.2 MHz; REF2 = 2.5 V; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter DYNAMIC SPECIFICATIONS2, 3 Decimate by 32 Bipolar Mode Signal to Noise Full Power Half Power Total Harmonic Distortion4 Spurious-Free Dynamic Range4 Unipolar Mode Signal to Noise Total Harmonic Distortion4 Spurious-Free Dynamic Range4 Band-Pass Filter Mode Bipolar Mode Signal to Noise Decimate by 16 Bipolar Mode Signal to Noise Signal to Noise Total Harmonic Distortion4 Spurious-Free Dynamic Range4 Unipolar Mode Signal to Noise Signal to Noise Total Harmonic Distortion4 DIGITAL FILTER RESPONSE Low-Pass Decimate by 32 0 kHz to fCLKIN/83.5 fCLKIN/66.9 fCLKIN/64 fCLKIN/51.9 to fCLKIN/2 Group Delay Settling Time Test Conditions/Comments HALF_PWR = 0 to 1 fCLKIN = 10 MHz when HALF_PWR = 1 Min 2.5 V reference 3 V reference 87 88.5 86.5 B Version Typ Max 90 91 89 −96 2.5 V reference 3 V reference Measurement bandwidth = 0.383 × FO 2.5 V reference 3 V reference Measurement bandwidth = 0.5 × FO 2.5 V reference 3 V reference 2.5 V reference 3 V reference −90 −92 −90 dB dB dB dB dB dB 87 −89 −90 dB dB dB 76 79 dB 82 83 78 86 87 81.5 dB dB dB dB dB dB dB −88 −86 −90 −88 Measurement bandwidth = 0.383 × FO Measurement bandwidth = 0.5 × FO 84 81 −89 dB dB dB ±0.001 −3 −6 −90 1293/2 fCLKIN 1293/fCLKIN Rev. C | Page 3 of 32 Unit dB dB dB dB AD7723 Parameter Low-Pass Decimate by 16 0 kHz to fCLKIN/41.75 fCLKIN/33.45 fCLKIN/32 fCLKIN/25.95 to fCLKIN/2 Group Delay Settling Time Band-Pass Decimate by 32 fCLKIN/51.90 to fCLKIN/41.75 fCLKIN/62.95, fCLKIN/33.34 fCLKIN/64, fCLKIN/32 0 kHz to fCLKIN/83.5, fCLKIN/25.95 to fCLKIN/2 Group Delay Settling Time Output Data Rate, FO Decimate by 32 Decimate by 166 ANALOG INPUTS Full-Scale Input Span Bipolar Mode Unipolar Mode Absolute Input Voltage Input Sampling Capacitance Input Sampling Rage, fCLKIN CLOCK CLKIN Duty Ratio REFERENCE REF1 Output Resistance Using Internal Reference REF2 Output Voltage REF2 Output Voltage Drift Using External Reference REF2 Input Impedance REF2 External Voltage Range STATIC PERFORMANCE Resolution Differential Nonlinearity Integral Nonlinearity DC CMRR Offset Error Gain Error5 LOGIC INPUTS (EXCLUDING CLKIN) VINH, Input High Voltage VINL, Input High Voltage CLOCK INPUT (CLKIN) VINH, Input High Voltage VINL, Input High Voltage ALL LOGIC INPUTS IIN, Input Current CIN, Input Capacitance Test Conditions/Comments Min B Version Typ Max ±0.001 −3 −6 −90 Unit dB dB dB dB 541/2 fCLKIN 541/fCLKIN ±0.001 −3 −6 −90 dB dB dB dB 1293/2 fCLKIN 1293/fCLKIN fCLKIN/32 fCLKIN/16 VIN(+) − VIN(−) VIN(+) − VIN(−) ±4/5 × VREF2 8/5 × VREF2 AVDD 0 AGND 19.2 V V V pF MHz 55 % 2 45 3 2.39 REF1 = AGND 1.2 2.54 60 4 2.5 kΩ 2.69 3.15 16 Guaranteed monotonic ±0.5 ±2 80 ±20 ±0.5 ±1 2.0 Rev. C | Page 4 of 32 kΩ V Bits LSB LSB dB mV % FSR 0.8 V V 0.4 V V ±10 10 µA pF 3.8 VIN = 0 V to DVDD V ppm/°C AD7723 Parameter LOGIC OUPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD IAVDD DVDD IDVDD Power Consumption6 Test Conditions/Comments Min |IOUT| = 200 µA |IOUT| = 1.6 mA 4.0 B Version Typ Max 4.75 HALF_PWR = Logic Low HALF_PWR = Logic High 50 25 4.75 HALF_PWR = Logic Low HALF_PWR = Logic High Standby Mode 1 25 15 Unit 0.4 V V 5.25 60 33 5.25 35 20 200 V mA mA V mA mA µW Operating temperature range is −40°C to +85°C (B: Version). Typical values for SNR apply for parts soldered directly to the PCB ground plane. 3 Dynamic specifications apply for input signal frequencies from dc to 0.0240 × fCLKIN in decimate by 16 mode and from dc to 0.0120 × fCLKIN in decimate by 32 mode. 4 When using the internal reference, THD and SFDR specifications apply only to input signals above 10 kHz with a 10 µF decoupling capacitor between REF2 and AGND2. At frequencies below 10 kHz, THD degrades to 84 dB and SFDR degrades to 86 dB. 5 Gain error excludes reference error. 6 CLKIN and digital inputs static and equal to 0 or DVDD. 2 Rev. C | Page 5 of 32 AD7723 TIMING SPECIFICATIONS AVDD = DVDD = 5 V ± 5%; AGND = AGND1 = DGND = 0 V; fCLKIN = 19.2 MHz; CL = 50 pF; SFMT = logic low or high, CFMT = logic low or high; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter CLKIN Frequency CLKIN Period (tCLK – 1/fCLK) CLKIN Low Pulse Width CLKIN High Pulse Width CLKIN Rise Time CLKIN Fall Time FSI Setup Time FSI Hold Time FSI High Time1 CLKIN to SCO Delay SCO Period2, SCR = 1 SCO Period2, SCR = 0 SCO Transition to FSO High Delay SCO Transition to FSO Low Delay SCO Transition to SDO Valid Delay SCO Transition from FSI3 SDO Enable Delay Time SDO Disable Delay Time DRDY High Time2 Conversion Time2 (Refer to Table 3 and Table 4) CLKIN to DRDY Transition CLKIN to DATA Valid CS/RD Setup Time to CLKIN CS/RD Hold Time to CLKIN Data Access Time Bus Relinquish Time SYNC Input Pulse Width SYNC Low Time before CLKIN Rising DRDY High Delay after Rising SYNC DRDY Low Delay after SYNC Low Symbol fCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 Min 1 0.052 0.45 × t1 0.45 × t1 5 5 0 0 25 2 1 0 0 5 60 5 5 IOL 1.6mA 01186-002 1.6V Figure 2. Load Circuit for Timing Specifications Rev. C | Page 6 of 32 5 5 12 tCLK + t2 20 20 35 20 50 35 20 20 35 35 25 35 2049 1 0 FSO pulses are gated by the release of FSI (going low). Guaranteed by design. 3 Frame sync is initiated on the falling edge of CLKIN. IOH 200µA 5 5 1 40 0 20 2 CL 50pF Max 19.2 1 0.55 × t1 0.55 × t1 2 16/32 1 TO OUTPUT PIN Typ Unit MHz µs ns ns ns ns tCLK ns tCLK tCLK ns ns ns ns ns tCLK tCLK ns ns ns ns ns ns tCLK ns ns tCLK AD7723 t5 t4 t2 2.3V CLKIN 0.8V t3 t1 t7 t6 FSI t8 t9 01186-003 SCO t9 t10 Figure 3. Serial Mode Timing for Clock Input, Frame Sync Input, and Serial Clock Output 32 CLKIN CYCLES CLKIN t8 FSI (SFMT = 1) t14 SCO (CFMT = 0) t11 FSO (SFMT = 0) t11 t12 FSO (SFMT = 1) D15 SDO D14 D13 D2 D1 D0 D15 01186-004 t13 D14 Figure 4. Serial Mode 1: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE) 32 CLKIN CYCLES CLKIN t8 FSI t14 SCO (CFMT = 0) t11 t12 FSO SDO D2 D1 D0 D15 D14 D13 D12 D11 D5 D4 D3 D2 D1 D0 D15 D14 01186-005 t13 Figure 5. Serial Mode 2: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE) Rev. C | Page 7 of 32 AD7723 32 CLKIN CYCLES CLKIN t8 FSI t14 SCO (CFMT = 0) t12 t11 16 CLKIN CYCLES 16 CLKIN CYCLES FSO SDO D3 D2 D1 D0 D15 D14 D13 D3 D2 D1 D0 D15 D14 D13 D3 D2 D1 D0 D15 01186-006 t13 Figure 6. Serial Mode 3: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE) Table 3. Serial Interface (MODE1 = 0, MODE2 = 0) Serial Mode 1 1 2 2 3 Decimation Ratio (SLDR) 32 32 32 32 16 Digital Filter Mode (SLP) Low Pass Band Pass Low Pass Band Pass Low Pass SCO Frequency (SCR) fCLKIN fCLKIN fCLKIN/2 fCLKIN/2 fCLKIN Output Data Rate fCLKIN/32 fCLKIN/32 fCLKIN/32 fCLKIN/32 fCLKIN/16 Control Inputs SLDR SLP SCR 1 1 0 1 0 0 1 1 1 1 0 1 0 1 0 Table 4. Parallel Interface Decimation Ratio 32 32 16 Output Data Rate fCLKIN/32 fCLKIN/32 fCLKIN/16 MODE1 0 1 1 DOE t16 t15 01186-007 Digital Filter Mode Band Pass Low Pass Low Pass SDO Figure 7. Serial Mode Timing for Data Output Enable and Serial Data Output Rev. C | Page 8 of 32 Control Inputs MODE2 1 0 1 AD7723 t18 CLKIN t19 t19 t17 DRDY DB0–DB15 WORD N WORD N – 1 WORD N + 1 01186-008 t20 Figure 8. Parallel Mode Read Timing, CS and RD Tied Logic Low CLKIN t 18 t 19 DRDY t 19 t22 RD/CS t 21 t 21 t 24 DB0–DB15 VALID DATA 01186-009 t 22 t 23 Figure 9. Parallel Mode Read Timing, CS = RD t 28 CLKIN t 26 SYNC 01186-010 t 25 DRDY t 27 Figure 10. SYNC Timing Rev. C | Page 9 of 32 AD7723 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter DVDD to DGND AVDD, AVDD1 to AGND AVDD, AVDD1 to DVDD AGND, AGND1 to DGND Digital Inputs to DGND Digital Outputs to DGND VIN (+), VIN(−) to AGND REF1 to AGND REF2 to AGND Operating Temperature Range Storage Temperature Range Junction Temperature θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating −0.3 V to +7 V −0.3 V to +7 V −1 V to +1 V −0.3 V to +0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −40°C to +85°C −65°C to +150°C 150°C 95°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 215°C 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 10 of 32 AD7723 SLDR/DB12 SLP/DB11 TSI/DB10 FSO/DB9 SDO/DB8 DVDD SCO/DB7 FSI/DB6 DOE/DB4 SFMT/DB5 DGND/DB3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 DGND/DB2 1 DGND/DB1 2 33 SCR/DB13 PIN 1 IDENTIFIER 32 DGND/DB14 DGND/DB0 3 31 DGND/DB15 CFMT/RD 4 DGND/DRDY 5 AD7723 DGND 6 MODE2 7 TOP VIEW (Not to Scale) MODE1 8 26 AVDD AGND1 9 25 AGND 30 DVDD/CS 29 SYNC 28 DGND 27 STBY AGND1 10 24 UNI AVDD1 11 23 REF2 01186-011 AGND2 REF1 VIN(+) VIN(–) AGND AVDD AGND HALF_PWR XTAL_OFF XTAL CLKIN 12 13 14 15 16 17 18 19 20 21 22 Figure 11. 44-Lead MQFP Table 6. Pin Function Descriptions Pin No. 6, 28 8, 7 Mnemonic DGND MODE1/MODE2 9, 10 11 12 AGND1 AVDD1 CLKIN 13 14 XTAL XTAL_OFF 15 HALF_PWR 16, 18, 25 17, 26 19 20 21 AGND AVDD VIN(−) VIN(+) REF1 22 23 AGND2 REF2 24 UNI 27 STBY Description Ground Reference for Digital Circuitry. Mode Control Inputs. The MODE1 and MODE2 pins choose either parallel or serial data interface operation and select the operating mode for the digital filter in parallel mode. See Table 3 and Table 4. Digital Logic Power Supply Ground for the Analog Modulator. Digital Logic Power Supply Voltage for the Analog Modulator. Clock Input. An external clock source can be applied directly to this pin with XTAL_OFF tied high. Alternatively, a parallel resonant fundamental frequency crystal, in parallel with a 1 MΩ resistor, can be connected betweenthe XTAL pin and the CLKIN pin with XTAL_OFF tied low. External capacitors are then required from the CLKIN and XTAL pins to ground. Consult the crystal manufacturer’s recommendation for the load capacitors. Input to Crystal Oscillator Amplifier. If an external clock is used, XTAL should be tied to AGND1. Oscillator Enable Input. A logic high disables the crystal oscillator amplifier to allow use of an external clock source. Set low when using an external crystal between the CLKIN and XTAL pins. When set high, the power dissipation is reduced by approximately one-half, and a maximum CLKIN frequency of 10 MHz applies. Power Supply Ground for the Analog Modulator. Positive Power Supply Voltage for the Analog Modulator. Negative Terminal of the Differential Analog Input. Positive Terminal of the Differential Analog Input. Reference Output. REF1 connects through 3 kΩ to the output of the internal 2.5 V reference and to a buffer amplifier that drives the Σ-∆ modulator. Power Supply Ground Return to the Reference Circuitry, REF2, of the Analog Modulator. Reference Input. REF2 connects to the output of an internal buffer amplifier that drives the Σ-∆ modulator. When REF2 is used as an input, REF1 must be connected to AGND to disable the internal buffer amplifier. Analog Input Range Select Input. The UNI pin selects the analog input range for either bipolar or unipolar operation. A logic high input selects unipolar operation and a logic low selects bipolar operation. Standby Logic Input. A logic high sets the AD7723 into the power-down state. Rev. C | Page 11 of 32 AD7723 Pin No. 29 Mnemonic SYNC 39 DVDD Description Synchronization Logic Input. When using more than one AD7723 operated from a common master clock, SYNC allows each ADC to simultaneously sample its analog input and update its output register. A rising edge resets the AD7723 digital filter sequencer counter to 0. When the rising edge of CLKIN senses a logic low on SYNC, the reset state is released. Because the digital filter and sequencer are completely reset during this action, SYNC pulses cannot be applied continuously. Digital Power Supply Voltage; 5 V ± 5%. Table 7. Parallel Mode Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic DGND/DB2 DGND/DB1 DGND/DB0 CFMT/RD 5 DGND/DRDY 30 31 32 33 34 35 36 37 38 40 41 42 43 44 DVDD/CS DGND/DB15 DGND/DB14 SCR/DB13 SLDR/DB12 SLP/DB11 TSI/DB10 FSO/DB9 SDO/DB8 SCO/DB7 FSI/DB6 SFMT/DB5 DOE/DB4 DGND/DB3 Description Data Output Bit. Data Output Bit. Data Output Bit (LSB). Read Logic Input. Used in conjunction with CS to read data from the parallel bus. The output data bus is enabled when the rising edge of CLKIN senses a logic low level on RD if CS is also low. When RD is sensed high, the output data bits, DB15 to DB0, are high impedance. Data Ready Logic Output. A falling edge indicates a new output word is available to be read from the output data register. DRDY returns high upon completion of a read operation. If a read operation does not occur between output updates, DRDY pulses high for two CLKIN cycles before the next output update. DRDY also indicates when conversion results are available after a SYNC sequence. Chip Select Logic Input. Data Output Bit (MSB). Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Rev. C | Page 12 of 32 AD7723 Table 8. Serial Mode Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic DGND/DB2 DGND/DB1 DGND/DB0 CFMT/RD 5 30 31 32 33 DGND/DRDY DVDD/CS DGND/DB15 DGND/DB14 SCR/DB13 34 SLDR/DB12 35 SLP/DB11 36 TSI/DB10 37 FSO/DB9 38 SDO/DB8 40 41 SCO/DB7 FSI/DB6 42 SFMT/DB5 43 DOE/DB4 44 DGND/DB3 Description Tie to DGND. Tie to DGND. Tie to DGND. Serial Clock Format Logic Input. The clock format pin selects whether the serial data, SDO, is valid on the rising or falling edge of the serial clock, SCO. When CFMT is logic low, serial data is valid on the falling edge of the serial clock, SCO. If CFMT is logic high, SDO is valid on the rising edge of SCO. Tie to DGND. Tie to DVDD. Tie to DGND. Tie to DGND. Serial Clock Rate Select Input. With SCR set logic low, the serial clock output frequency, SCO, is equal to the CLKIN frequency. A logic high sets it equal to one-half the CLKIN frequency. Serial Mode Low/High Output Data Rate Select Input. With SLDR set logic high, the low data rate is selected. A logic low selects the high data rate. The high data rate corresponds to data at the output of the fourth decimation filter (decimate by 16). The low data rate corresponds to data at the output of the fifth decimation filter (decimate by 32). Serial Mode Low-Pass/Band-Pass Filter Select Input. With SLP set logic high, the low-pass filter response is selected. A logic low selects band-pass. Time Slot Logic Input. The logic level on TSI sets the active state of the DOE pin. With TSI set logic high, DOE enables the SDO output buffer when it is a logic high and vice versa. TSI is used when two AD7723s are connected to the same serial data bus. When this function is not needed, TSI and DOE should be tied low. Frame Sync Output. FSO indicates the beginning of a word transmission on the SDO pin. Depending on the logic level of the SFMT pin, the FSO signal is either a positive pulse approximately one SCO period wide or a frame pulse that is active low for the duration of the 16-data bit transmission. Serial Data Output. The serial data is shifted out MSB first, synchronous with the SCO. Serial Mode 1 data transmissions last 32 SCO cycles. After the LSB is output, trailing zeros are output for the remaining 16 SCO cycles. Serial Modes 2 and 3 data transmissions last 16 SCO cycles. Serial Clock Output. Frame Synchronization Logic Input. The FSI input is used to synchronize the AD7723 serial output data register to an external source and to allow more than one AD7723, operated from a common master clock, to simultaneously sample its analog input and update its output register. Serial Data Format Logic Input. The logic level on the SFMT pin selects the format of the FSO signal for Serial Mode 1. A logic low makes the FSO output a pulse one SCO cycle wide at the beginning of a serial data transmission. With SFMT set to a logic high, the FSO signal is a frame pulse that is active low for the duration of the 16-bit transmission. For Serial Modes 2 and 3, SFMT should be tied high. Data Output Enable Logic Input. The DOE pin controls the three-state output buffer of the SDO pin. The active state of DOE is determined by the logic level on the TSI pin. When the DOE logic level equals the level on the TSI pin, the serial data output, SDO, is active. Otherwise, SDO is high impedance. SDO can be three-state after a serial data transmission by connecting DOE to FSO. In normal operations, TSI and DOE should be tied low. Tie to DGND. Rev. C | Page 13 of 32 AD7723 TERMINOLOGY Signal-to-Noise Ratio (SNR) SNR is the measured signal-to-noise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all of the nonfundamental signals up to half the output data rate (FO/2), excluding dc. The ADC is evaluated by applying a low noise, low distortion sine wave signal to the input pins. By generating a fast fourier transform (FFT) plot, the SNR data can then be obtained from the output spectrum. Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are minus full scale, a point 0.5 LSB below the first code transition (100 . . . 00 to 100 . . . 01 in bipolar mode, 000 . . . 00 to 000 . . . 01 in unipolar mode), and plus full scale, a point 0.5 LSB above the last code transition (011 . . . 10 to 011 . . . 11 in bipolar mode, 111 . . . 10 to 111 . . . 11 in unipolar mode). The error is expressed in LSBs. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the harmonics to the rms value of the fundamental. THD is defined as Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between two adjacent codes in the ADC. THD = 20log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1 where V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through sixth harmonics. The THD is also derived from the FFT plot of the ADC output spectrum. Spurious-Free Dynamic Range (SFDR) Defined as the difference, in dB, between the peak spurious or harmonic component in the ADC output spectrum (up to FO/2 and excluding dc) and the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the output spectrum of the FFT. For input signals whose second harmonics occur in the stop-band region of the digital filter, the spur in the noise floor limits the SFDR. Pass-Band Ripple The frequency response variation of the AD7723 in the defined pass-band frequency range. Pass-Band Frequency The frequency up to which the frequency response variation is within the pass-band ripple specification. Common-Mode Rejection Ratio The ability of a device to reject the effect of a voltage applied to both input terminals simultaneously—often through variation of a ground level—is specified as a common–mode rejection ratio. CMRR is the ratio of gain for the differential signal to the gain for the common-mode signal. Unipolar Offset Error Unipolar offset error is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal differential voltage (VIN(+) – VIN(–)+ 0.5 LSB) when operating in the unipolar mode. Bipolar Offset Error This is the deviation of the midscale transition code (111 . . . 11 to 000 . . . 00) from the ideal differential voltage (VIN(+) – VIN(–) – 0.5 LSB) when operating in the bipolar mode. Gain Error The first code transition should occur at an analog value ½ LSB above –full scale. The last transition should occur for an analog value 1 ½ LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Cutoff Frequency The frequency below which the AD7723’s frequency response will not have more than 3 dB of attenuation. Stop-Band Frequency The frequency above which the AD7723’s frequency response will be within its stop-band attenuation. Stop-Band Attenuation The AD7723’s frequency response will not have less than 90 dB of attenuation in the stated frequency band. Rev. C | Page 14 of 32 AD7723 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 5 V; TA = 25°C; CLKIN = 19.2 MHz; external 2.5 V reference, unless otherwise noted. 106 110 SIGNAL FREQUENCY = 98kHz MEASUREMENT BANDWIDTH = 460kHz 104 100 SIGNAL FREQUENCY = 98kHz MEASUREMENT BANDWIDTH = 300kHz 3RD 102 90 100 THD (dB) (dB) 80 SFDR 98 96 70 2ND 94 SNR THD 60 92 90 01186-012 40 –50 –40 –30 –20 ANALOG INPUT LEVEL (dB) –10 88 –50 0 Figure 12. SNR, THD, and SFDR vs. Analog Input Level Relative to Full Scale (Output Data Rate = 1.2 MHz) 0 25 50 TEMPERATURE (°C) 75 100 106 SIGNAL FREQUENCY = 98kHz MEASUREMENT BANDWIDTH = 300kHz 104 SFDR 100 102 100 90 THD (dB) (dB) THD 98 80 SFDR 96 INPUT SIGNAL = 10kHz MEASUREMENT BANDWIDTH = 0.383 × OWR 94 70 SNR 92 60 90 88 –40 –30 –20 ANALOG INPUT LEVEL (dB) –10 SNR 01186-016 40 –50 01186-013 50 86 84 100 0 Figure 13. SNR, THD, and SFDR vs. Analog Input Level Relative to Full Scale (Output Data Rate = 600 kHz) 100 –25 Figure 15. SNR and THD vs. Temperature (Output Data Rate = 600 kHz) 110 102 01186-015 SNR 50 500 1000 1500 OUTPUT WORD RATE (kHz) 2150 Figure 16. SNR, THD, and SFDR vs. Sampling Frequency (Decimate by 16) 115 SIGNAL FREQUENCY = 98kHz MEASUREMENT BANDWIDTH = 460kHz INPUT SIGNAL = 10kHz MEASUREMENT BANDWIDTH = 0.5 × OWR 3RD 110 98 SFDR 2ND 105 94 (dB) (dB) 96 THD 92 100 90 THD 88 01186-014 84 –50 –25 0 25 50 TEMPERATURE (°C) 75 01186-017 95 SNR 86 SNR 90 100 50 Figure 14. SNR and THD vs. Temperature (Output Data Rate = 1.2 MHz) 150 300 600 450 OUTPUT WORD RATE (kHz) 750 900 Figure 17. SNR, THD, and SFDR vs. Sampling Frequency (Decimate by 32) Rev. C | Page 15 of 32 AD7723 RFB 220Ω 2000 AIN = ±2V BIASED ABOUT GROUND 1600 27Ω RBALANCE1 220Ω 1200 AD8047 20 VIN(+) A1 1400 RBALANCE2 220Ω 220pF RBALANCE2 1000 AD7723 220Ω 800 RREF1 10kΩ 600 RREF2 20kΩ 01186-018 400 200 32702 32704 32706 32708 CODE 32710 32712 32713 0.4 INL ERROR (LSB) 0.6 3500 3000 2500 2000 21 REF1 1µF 0.2 0 –0.2 1500 –0.4 1000 –0.6 01186-019 500 32706 32707 CODE 32708 –0.8 –1.0 32709 32710 0 16384 32768 49152 65535 CODE Figure 22. Integral Nonlinearity (Output Data Rate =1.2 MHz) Figure 19. Histogram of Output Codes with DC Input (Output Data Rate = 600 kHz) 1.0 1.0 67108864 SAMPLES TAKEN DIFFERENTIAL MODE 0.8 67108864 SAMPLES TAKEN DIFFERENTIAL MODE 0.8 0.6 0.4 0.4 INL ERROR (LSB) 0.6 0.2 0 –0.2 0.2 0 –0.2 –0.4 –0.4 –0.6 01186-020 –0.6 –0.8 –1.0 0 16384 32768 49152 65535 01186-023 FREQUENCY OF OCCURRENCE 23 REF2 10nF 67108864 SAMPLES TAKEN DIFFERENTIAL MODE 0.8 4000 32705 220nF 1.0 VIN(+) = V IN(–) 8192 SAMPLES TAKEN 32704 AD8047 Figure 21. Differential Nonlinearity (Output Data Rate = 600 kHz) 5000 0 32703 19 VIN(–) A2 GAIN = 2 × RFB/(RIN + RSOURCE) RBALANCE1 = RBALANCE2 × (RIN + RSOURCE)/(2 × RFB) RREF2 = RREF1 × (RIN + RSOURCE)/RFB Figure 18. Histogram of Output Codes with DC Input (Output Data Rate = 1.2 MHz) 4500 27Ω 01186-022 0 32700 DNL ERROR (LSB) RSOURCE RIN 50Ω 390Ω 01186-021 FREQUENCY OF OCCURRENCE 1800 VIN(+) = V IN(–) 8192 SAMPLES TAKEN –0.8 –1.0 0 16384 32768 CODE 49152 65535 CODE Figure 23. Integral Nonlinearity (Output Data Rate = 600 kHz) Figure 20. Differential Nonlinearity (Output Data Rate = 1.2 MHz) Rev. C | Page 16 of 32 AD7723 0 AIDD (HALF_POWER = 0) 175 POWER (mW) 150 125 100 AIDD (HALF_POWER = 1) 75 DIDD 01186-024 50 25 0 0 5 10 15 CLOCK FREQUENCY (MHz) 20 25 –75 –100 –125 01186-025 POWER LEVEL RELATIVE TO FULL SCALE (dB) SNR = –86.19dB SNR + D = –85.9dB THD = –96.42dB SFDR = –99.61dB 2ND HARMONIC = –100.98dB 3RD HARMONIC = –99.61dB AIN = 100kHz MEASURED BW = 460kHz –150 0 100k 300k 400k 200k FREQUENCY (Hz) –60 –80 –100 –120 –140 –160 500k 50k 150k 200k 100k FREQUENCY (Hz) 250k Figure 26. 16 K Point FFT (Output Data Rate = 600 kHz) 0 –50 –40 0 Figure 24. Power Consumption vs. CLKIN Frequency –25 SNR = –89.91dB SNR + D = –89.7dB THD = –101.16dB SFDR = –102.1dB 2ND HARMONIC = –102.1dB 3RD HARMONIC = –110.3dB AIN = 50kHz MEASURED BW = 300kHz –20 01186-026 200 POWER LEVEL RELATIVE TO FULL SCALE (dB) 225 600k Figure 25. 16 K Point FFT (Output Data Rate = 1.2 MHz) Rev. C | Page 17 of 32 300k AD7723 CIRCUIT DESCRIPTION The AD7723 ADC employs a Σ-Δ conversion technique to convert the analog input into an equivalent digital word. The modulator samples the input waveform and outputs an equivalent digital word at the input clock frequency, fCLKIN. Due to the high oversampling rate that spreads the quantization noise from 0 to fCLKIN/2, the noise energy contained in the band of interest is reduced (Figure 27A). To further reduce the quantization noise, a high-order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the band of interest (Figure 27B). The digital filter that follows the modulator removes the large out-of-band quantization noise (Figure 27C) while also reducing the data rate from fCLKIN at the input of the filter to fCLKIN/32 or fCLKIN/16 at the output of the filter, depending on the state on the MODE1/MODE2 pins in parallel interface mode or the SLDR pin in serial interface mode. The AD7723 output data rate is a little over twice the signal bandwidth, which guarantees that there is no loss of data in the signal band. Digital filtering has certain advantages over analog filtering. First, since digital filtering occurs after the A/D conversion, it can remove noise injected during the conversion process. Analog filtering cannot remove noise injected during conversion. Second, the digital filter combines low pass-band ripple with a steep roll-off while also maintaining a linear phase response. the converter is 16. Data fed to the interface from the output of the fifth filter results in an output data rate of fCLKIN/32 and a corresponding OSR for the converter of 32. When an output data rate (ODR) of fCLKIN/32 is selected, the digital filter response can be set to either low-pass or band-pass. The bandpass response is useful when the input signal is band limited because the resulting output data rate is half that required to convert the band when the low-pass operating mode is used. To illustrate the operation of this mode, consider a band-limited signal, as shown in Figure 28A. This signal band can be correctly converted by selecting the (low-pass) ODR = fCLKIN/16 mode, as shown in Figure 28B. Note that the output data rate is a little over twice the maximum frequency in the frequency band. Alternatively, the band-pass mode can be selected, as shown in Figure 28C. The band-pass filter removes unwanted signals from dc to just below fCLKIN/64. Rather than outputting data at fCLKIN/16, the output of the band-pass filter is sampled at fCLKIN/32. This effectively translates the wanted band to a maximum frequency of a little less than fCLKIN/64, as shown in Figure 28D. Halving the output data rate reduces the workload of any following signal processor and also allows a lower serial clock rate to be used. BAND LIMITED SIGNAL 0dB fCLKIN/16 A LOW-PASS FILTER RESPONSE 0dB QUANTIZATION NOISE ODR SAMPLE IMAGE fCLKIN/2 BAND OF INTEREST fCLKIN/16 A LOW-PASS FILTER. OUTPUT DATA RATE = fCLKIN/16 B BAND-PASS FILTER RESPONSE NOISE SHAPING SAMPLE IMAGE 0dB fCLKIN/2 BAND OF INTEREST B BAND-PASS FILTER fCLKIN/16 C DIGITAL FILTER CUTOFF FREQUENCY C SAMPLE IMAGE ODR fCLKIN/16 LOW-PASS FILTER. OUTPUT DATA RATE = fCLKIN/32 Figure 27. Sigma-Delta ADC D The AD7723 employs four or five finite impulse response (FIR) filters in series. Each individual filter’s output data rate is half that of the filter’s input data rate. When data is fed to the interface from the output of the fourth filter, the output data rate is fCLKIN/16 and the resulting oversampling ratio (OSR) of 01186-028 fCLKIN/2 BAND OF INTEREST FREQUENCY TRANSLATED INPUT SIGNAL 01186-027 0dB Figure 28. Band-Pass Operation The frequency response of the three digital filter operating modes is shown in Figure 29, Figure 30, and Figure 31. Rev. C | Page 18 of 32 AD7723 0dB 01186-029 –100dB 0 0.5 1.0 fCLKIN Figure 29. Low-Pass Filter Decimate by 16 Figure 32 shows the frequency response of the digital filter in both low-pass and band-pass modes. Due to the sampling nature of the converter, the pass-band response is repeated about the input sampling frequency, fCLKIN, and at integer multiples of fCLKIN. Out-of-band noise or signals coincident with any of the filter images are aliased down to the pass band. However, due to the AD7723’s high oversampling ratio, these bands occupy only a small fraction of the spectrum, and most broadband noise is attenuated by at least 90 dB. In addition, as shown in Figure 33, with even a low-order filter, there is significant attenuation at the first image frequency. This contrasts with a normal Nyquist rate converter where a very high-order antialias filter is required to allow most of the bandwidth to be used while ensuring sufficient attenuation at multiples of fCLKIN. 01186-032 0dB 0dB 1fCLKIN 2fCLKIN 3fCLKIN Figure 32. Digital Filter Frequency Response –100dB ANTIALIAS FILTER RESPONSE REQUIRED ATTENUATION 0dB 01186-030 fCLKIN/32 0 0.5 Figure 33. Frequency Response of Antialias Filter 1.0 fCLKIN Figure 30. Low-Pass Filter Decimate by 32 0dB 01186-031 –100dB 0 0.5 fCLKIN 1.0 fCLKIN Figure 31. Band-Pass Filter Decimate by 32 Rev. C | Page 19 of 32 01186-033 OUTPUT DATA RATE AD7723 APPLYING THE AD7723 ANALOG INPUT RANGE ANALOG INPUT The AD7723 has differential inputs to provide common-mode noise rejection. In unipolar mode, the analog input range is 0 to 8/5 × VREF2, while in bipolar mode, the analog input range is ±4/5 × VREF2. The output code is twos complement binary in both modes with 1 LSB = 61 µV. The ideal input/output transfer characteristics for the two modes are shown in Figure 34. In both modes, the absolute voltage on each input must remain within the supply range AGND to AVDD. The bipolar mode allows either single-ended or complementary input signals. The analog input of the AD7723 uses a switched capacitor technique to sample the input signal. For the purpose of driving the AD7723, an equivalent circuit of the analog inputs is shown in Figure 36. For each half clock cycle, two highly linear sampling capacitors are switched to both inputs, converting the input signal into an equivalent sampled charge. A signal source driving the analog inputs must be able to source this charge while also settling to the required accuracy by the end of each half-clock phase. 011…111 ΦA 011…110 AD7723 500Ω VIN(+) 20 000…010 000…001 VIN(–) 19 111…110 CLKIN 01186-034 100…000 –4/5 × VREF2 0V (0V) (+4/5 × VREF2) Figure 34. Bipolar (Unipolar) Mode Transfer Function The AD7723 accepts full-scale, in-band signals. However, large scale out-of-band signals can overload the modulator inputs. Figure 35 shows the maximum input signal level as a function of frequency. A minimal single-pole, RC, antialias filter set to fCLKIN/24 allows full-scale input signals over the entire frequency spectrum. 2.2 2.1 1.9 1.8 1.7 1.6 1.5 VREF = 2.5V 01186-035 PEAK INPUT (V p-p) 2.0 1.4 1.3 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 INPUT SIGNAL FREQUENCY RELATIVE TO fCLKIN Figure 35. Peak Input Signal Level vs. Signal Frequency 0.5 2pF ΦB AC GROUND Φ Φ Φ Φ A A B B Figure 36. Analog Input Equivalent Circuit +4/5 × VREF2 – 1LSB BIPOLAR (+8/5 × VREF2 – 1LSB) UNIPOLAR ΦA 500Ω 111…111 100…001 2pF 01186-036 000…000 ΦB DRIVING THE ANALOG INPUTS To interface the signal source to the AD7723, at least one op amp is generally required. Choice of op amp is critical to achieving the full performance of the AD7723. The op amp not only has to recover from the transient loads that the ADC imposes on it, but it must also have good distortion characteristics and very low input noise. Resistors in the signal path can also add to the overall thermal noise floor, necessitating the choice of low value resistors. Placing an RC filter between the drive source and the ADC inputs, as shown in Figure 37, has a number of beneficial effects. Transients on the op amp outputs are significantly reduced because the external capacitor now supplies the instantaneous charge required when the sampling capacitors are switched to the ADC input pins and input circuit noise at the sample images is now significantly attenuated, resulting in improved overall SNR. The external resistor serves to isolate the external capacitor from the ADC output, thus improving op amp stability while also isolating the op amp output from any remaining transients on the capacitor. By experimenting with different filter values, the optimum performance can be achieved for each application. As a guideline, the RC time constant (R × C) should be less than a quarter of the clock period to avoid nonlinear currents from the ADC inputs being stored on the external capacitor and degrading distortion. This restriction means that this filter cannot form the main antialias filter for the ADC. Rev. C | Page 20 of 32 AD7723 RFB 220Ω R AIN = ±2V BIASED ABOUT GROUND VIN(+) AD7723 VIN(–) VIN(+) 220Ω RBALANCE2 220pF AD7723 220Ω With the unipolar input mode selected, just one op amp is required to buffer single-ended input signals. However, driving the AD7723 with complementary signals and with the bipolar input range selected has some distinct advantages: even-order harmonics in both the drive circuits and the AD7723 front end are attenuated and the peak-to-peak input signal range on both inputs is halved. Halving the input signal range allows some op amps to be powered from the same supplies as the AD7723. Although a complementary driver requires the use of two op amps per ADC, it may avoid the need to generate additional supplies just for these op amps. Figure 38 and Figure 39 show two such circuits for driving the AD7723. Figure 38 is intended for use when the input signal is biased about 2.5 V, while Figure 39 is used when the input signal is biased about ground. While both circuits convert the input signal into a complementary signal, the circuit in Figure 39 also level shifts the signal so that both outputs are biased about 2.5 V. Suitable op amps include the AD8047, AD8044, AD8041, and its dual equivalent, the AD8042. The AD8047 has lower input noise than the AD8041/AD8042 but has to be supplied from a +7.5 V/−2.5 V supply. The AD8041/AD8042 typically degrades SNR from 90 dB to 88 dB but can be powered from the same single 5 V supply as the AD7723. RREF1 10kΩ 27Ω A2 RREF2 20kΩ AD8047 220nF GAIN = 2 × RFB/(RIN + RSOURCE) RBALANCE1 = RBALANCE2 × (RIN + RSOURCE)/(2 × RFB) RREF2 = RREF1 × (RIN + RSOURCE)/RFB 19 VIN(–) 23 REF2 21 REF1 10nF 1µF Figure 39. Single-Ended-to-Differential Input Circuit for Bipolar Mode Operation (Analog Input Biased About Ground) APPLYING THE REFERENCE The reference circuitry used in the AD7723 includes an on-chip 2.5 V band-gap reference and a reference buffer circuit. The block diagram of the reference circuit is shown in Figure 40. The internal reference voltage is connected to REF1 through a 3 kΩ resistor and is internally buffered to drive the analog modulator’s switched cap DAC (REF2). When using the internal reference, a 1 µF capacitor is required between REF1 and AGND to decouple the band-gap noise. If the internal reference is required to bias external circuits, use an external precision op amp to buffer REF1. 1V COMPARATOR AD7723 REFERENCE BUFFER REF1 SWITCHED-CAP DAC REFERENCED 21 1µF RFB 220Ω 3kΩ 2.5V REFERENCE REF2 23 AD8047 27Ω 20 A1 01186-040 AIN = ±2V BIASED ABOUT 2.5V 20 RBALANCE2 Figure 37. Input RC Network RSOURCE RIN 50Ω 390Ω 27Ω RBALANCE1 220Ω 01186-037 R AD8047 A1 01186-039 C RSOURCE RIN 50Ω 390Ω VIN(+) Figure 40. Reference Circuit Block Diagram 220Ω 220pF AD7723 220Ω 27Ω A2 AD8047 220nF GAIN = 2 × RFB/(RSOURCE + RIN) 19 VIN(–) 23 REF2 21 REF1 10nF 1µF 01186-038 10kΩ Figure 38. Single-Ended-to-Differential Input Circuit for Bipolar Mode Operation (Analog Input Biased About 2.5 V) Where gain error or gain error drift requires the use of an external reference, the reference buffer in Figure 40 can be turned off by grounding the REF1 pin and the external reference can be applied directly to REF2 pin. The AD7723 accepts an external reference voltage between 1.2 V to 3.15 V. By applying a 3 V rather than a 2.5 V reference, SNR is typically improved by about 1 dB. Where the output common-mode range of the amplifier driving the inputs is restricted, the fullscale input signal span can be reduced by applying a lower than 2.5 V reference. For example, a 1.25 V reference would make the bipolar input span ±1 V but would degrade SNR. Rev. C | Page 21 of 32 AD7723 In all cases, since the REF2 voltage connects to the analog modulator, a 220 nF and 10 nF capacitor must connect directly from REF2 to AGND. The external capacitor provides the charge required for the dynamic load presented at the REF2 pin (see Figure 41). Φ Φ When an external clock source is being used, the internal oscillator circuit can be disabled by tying XTAL_OFF high. A low phase noise clock should be used to generate the ADC sampling clock because sampling clock jitter effectively modulates the input signal and raises the noise floor. The sampling clock generator should be isolated from noisy digital circuits, grounded, and heavily decoupled to the analog ground plane. B 23 Φ 4pF Φ B A 01186-041 SWITCHED-CAP DAC REFERENCED CLKIN ΦA Φ Φ B A ΦB Figure 41. REF2 Equivalent Input Circuit The AD780 is ideal to use as an external reference with the AD7723. Figure 42 shows a suggested connection diagram. Grounding Pin 8 on the AD780 selects the 3 V output mode. O/P 8 SELECT 2 +VIN NC 7 2.5V REF2 1 NC 1µ F 3 TEMP 22nF VOUT 6 4 GND TRIM 5 AD780 220nF 22µ F 10nF AD7723 REF1 NC = NO CONNECT 01186-042 5V 01186-043 Figure 43. Crystal Oscillator Connection 4pF 10nF CLKIN 1MΩ A REF2 220nF AD7723 XTAL Figure 42. External Reference Circuit Connection CLOCK GENERATION The AD7723 contains an oscillator circuit to allow a crystal or an external clock signal to generate the master clock for the ADC. The connection diagram for use with a crystal is shown in Figure 43. Consult the manufacturer’s recommendation for the load capacitors. To enable the oscillator circuit on board the AD7723, XTAL_OFF should be tied low. The sampling clock generator should be referenced to the analog ground in a split ground system. However, this is not always possible because of system constraints. In many applications, the sampling clock must be derived from a higher frequency multipurpose system clock that is generated on the digital ground plane. If the clock signal is passed between its origin on a digital ground plane to the AD7723 on the analog ground plane, the ground noise between the two planes adds directly to the clock and produces excess jitter. The jitter can cause degradation in the signal-to-noise ratio and also produce unwanted harmonics. This can be remedied somewhat by transmitting the sampling signal as a differential one, using either a small RF transformer or a high speed differential driver and a receiver such as PECL. In either case, the original master system clock should be generated from a low phase noise crystal oscillator. Rev. C | Page 22 of 32 AD7723 SYSTEM SYNCHRONIZATION The SYNC input provides a synchronization function for use in parallel or serial mode. SYNC allows the user to begin gathering samples of the analog input from a known point in time. This allows a system using multiple AD7723s, operated from a common master clock, to be synchronized so that each ADC simultaneously updates its output register. In a system using multiple AD7723s, a common signal to their sync inputs synchronizes their operation. On the rising edge of SYNC, the digital filter sequencer is reset to 0. The filter is held in a reset state until a rising edge on CLKIN senses SYNC low. A SYNC pulse, one CLKIN cycle long, can be applied synchronous to the falling edge of CLKIN. This way, on the next rising edge of CLKIN, SYNC is sensed low, the filter is taken out of its reset state, and multiple parts begin to gather input samples. Following a SYNC, the modulator and filter need time to settle before data can be read from the AD7723. DRDY goes high following a synchronization and it remains high until valid data is available at the interface. When operating in any of the serial modes, either SYNC or frame sync input (FSI) may be used to synchronize multiple AD7723 devices to a common master clock. The functionality of FSI is detailed in the Serial Interface section. Rev. C | Page 23 of 32 AD7723 DATA INTERFACING cycles, the rising edge of DRDY is used to latch the conversion data before a new conversion result is loaded into the output data register. The falling edge of DRDY then sends an appropriate interrupt signal for interface control. Alternatively, if buffers are used instead of latches, the falling edge of DRDY provides the necessary interrupt when a new output word is available from the AD7723. AD7723 DSP DB15 16 74XX16374 16 ADDR DECODE PARALLEL INTERFACE When using the AD7723, place a buffer/latch adjacent to the converter to isolate the converter’s data lines from any noise that may be on the data bus. Even though the AD7723 has three state outputs, use of an isolation latch represents good design practice. Figure 44 shows how the parallel interface of the AD7723 can be configured to interface with the system data bus of a microprocessor or a microcontroller, such as the MC68HC16 or 8XC251. With CS and RD tied permanently low, the data output bits are always active. When DRDY goes high for two clock Rev. C | Page 24 of 32 D15 ADDR DRDY OE RD CS RD INTERRUPT Figure 44. Parallel Interface Connection 01186-044 The AD7723 offers a choice of serial or parallel data interface options to meet the requirements of a variety of system configurations. In parallel mode, multiple AD7723s can easily be configured to share a common data bus. Serial mode is ideal when it is required to minimize the number of data interface lines connected to a host processor. In either case, careful attention to the system configuration is required to realize the high dynamic range available with the AD7723. Consult the recommendations in the Grounding and Layout section. The following recommendations for parallel interfacing also apply for the system design when using the serial mode. AD7723 SERIAL INTERFACE Serial data shifts out of the SDO pin synchronous with SCO. The FSO is used to frame the output data transmission to an external device. An output data transmission is either 16 or 32 SCO cycles in duration (see Table 3). Serial data shifts out of the SDO pin, MSB first, LSB last, for a duration of 16 SCO cycles. In Serial Mode 1, SDO outputs 0s for the last 16 SCO cycles of the 32-cycle data transmission frame. The clock format pin, CFMT, selects the active edge of SCO. With CFMT tied logic low, the serial interface outputs FSO and SDO change state on the SCO rising edge and are valid on the falling edge of SCO. With CFMT set high, FSO and SDO change state on the falling SCO edge and are valid on the SCO rising edge. The frame sync input, FSI, can be used if the AD7723 conversion process must be synchronized to an external source. FSI allows the conversion data presented to the serial interface to be a filtered and decimated result derived from a known point in time. A common frame sync signal can be applied to two or more AD7723s to synchronize them to a common master clock. When FSI is applied for the first time, the digital filter sequencer counter is reset to 0, the AD7723 interrupts the current data transmission, reloads the output shift register, resets SCO, and transmits the conversion result. Synchronization starts immediately and the following conversions are invalid while the digital filter settles. FSI can be applied once after power-up, or it can be a periodic signal, synchronous to CLKIN, occurring every 32 CLKIN cycles. Subsequent FSI inputs applied every 32 CLKIN cycles do not alter the serial data transmission and do not reset the digital filter sequencer counter. FSI is an optional signal; if synchronization is not required, FSI can be tied to a logic low and the AD7723 generates FSO outputs. In Serial Mode 1, the control input, SFMT, can be used to select the format for the serial data transmission (see Figure 4). FSO is either a pulse, approximately one SCO cycle in duration, or a square wave with a period of 32 SCO cycles. With a logic low level on SFMT, FSO pulses high for one SCO cycle at the beginning of a data transmission frame. With a logic high level on SFMT, FSO goes low at the beginning of a data transmission frame and returns high after 16 SCO cycles. Note that in Serial Mode 1, FSI can be used to synchronize the AD7723 if SFMT is set to a logic high. If SFMT is set low, the FSI input has no effect on synchronization. In Serial Mode 2 and Serial Mode 3, SFMT should be tied high. TSI and DOE should be tied low in these modes. The FSO is a pulse, approximately one SCO cycle in duration, occurring at the beginning of the serial data transmission. TWO-CHANNEL MULTIPLEXED OPERATION Two additional serial interface control pins, DOE and TSI, are provided to allow the serial data outputs of two AD7723s, to easily share one serial data line when operating in Serial Mode 1. Figure 45 shows the connection diagram. Since a serial data transmission frame lasts 32 SCO cycles, two ADCs can share a single data line by alternating transmission of their 16bit output data onto one SDO pin. AD7723 DVDD DGND MASTER SFMT SDO CFMT SCO TSI FSO FSI DOE TO HOST PROCESSOR CLKIN FROM CONTROL LOGIC AD7723 SLAVE DV DD DGND FSI DOE CLKIN SDO SFMT SCO TSI FSO CFMT 01186-045 The AD7723’s serial data interface can operate in three modes, depending on the application requirements. The timing diagrams in Figure 4, Figure 5, and Figure 6 show how the AD7723 may be used to transmit its conversion results. Table 3 shows the control inputs required to select each serial mode and the digital filter operating mode. The AD7723 operates solely in the master mode, providing three serial data output pins for transfer of the conversion results. The serial data clock output, SCO, serial data output, SDO, and frame sync output, FSO, are all synchronous with CLKIN. FSO is continuously output at the conversion rate of the ADC. Figure 45. Serial Mode 1 Connection for Two-Channel Multiplexed Operation The data output enable pin, DOE, controls the SDO output buffer. When the logic level on DOE matches the state of the TSI pin, the SDO output buffer drives the serial data line; otherwise, the output of the buffer goes high impedance. The serial format pin, SFMT, is set high to choose the frame sync output format. The clock format pin, CFMT, is set low so that serial data is made available on SDO after the rising edge of SCO and can be latched on the SCO falling edge. Rev. C | Page 25 of 32 AD7723 The master device is selected by setting TSI to a logic low and connecting its FSO to DOE. The slave device is selected with its TSI pin tied high and both its FSI and DOE controlled from the master’s FSO. Since the FSO of the master controls the DOE input of both the master and slave, one ADC’s SDO is active while the other is high impedance (Figure 46). When the master transmits its conversion result during the first 16 SCO cycles of a data transmission frame, the low level on DOE sets the slave’s SDO high impedance. Once the master completes transmitting its conversion data, its FSO goes high and triggers the slave’s FSI to begin its data transmission frame. Since FSO pulses are gated by the release of FSI (going low) and the FSI of the slave device is held high during its data transmission, the FSO from the master device must be used for connection to the host processor. CLKIN FSI t9 SCO t11 t12 t13 t16 t15 D15 SDO (MASTER) D14 D1 D0 t16 SDO (SLAVE) D1 D0 t15 D15 Figure 46. Serial Mode 1 Timing for Two-Channel Multiplexed Operation Rev. C | Page 26 of 32 D14 01186-046 FSO (MASTER) FSI (SLAVE) DOE (MASTER AND SLAVE) AD7723 SERIAL INTERFACE TO DSPs AD7723 TO ADSP-21xx INTERFACE Figure 47 shows the interface between the ADSP-21xx and the AD7723. The AD7723 is operated in Mode 2 so that SCO = CLKIN/2. For the ADSP-21xx, the bits in the serial port control register should be set up as RFSR = 1 (a frame sync is needed for each transfer), SLEN = 15 (16-bit word lengths), RFSW = 0 (normal framing mode for receive operations), INVRFS = 0 (active high RFS), IRFS = 0 (external RFS), and ISCLK = 0 (external serial clock). ADSP-21xx (the DSP begins reading the 16-bit word after the DSP has identified the frame sync signal rather than the DSP reading the word at the same instant as the frame sync signal is identified), and LRFS = 0 (RFS is active high). The AD7723 can be used in Mode 1, Mode 2, or Mode 3 when interfaced to the ADSP2106x SHARC DSP. AD7723 TO DSP56002 INTERFACE Figure 48 shows the AD7723 to DSP56002 interface. To interface the AD7723 to the DSP56002, the ADC is operated in Mode 2 when the ADC is operated with a 19.2 MHz clock. The DSP56002 is configured as follows: SYN = 1 (synchronous mode), SCD1 = 0 (RFS is an input), GCK = 0 (a continuous serial clock is used), SCKD = 0 (the serial clock is external), WL1 = l, WL0 = 0 (transfers is 16 bits wide), FSL1 = 0, and FSL0 = 1 (the frame sync is active at the beginning of each transfer). Alternatively, the DSP56002 can be operated in asynchronous mode (SYN = 0). In this mode, the serial clock for the receive section is input to the SCO pin. This is accomplished by setting Bit SCDO to 0 (external Rx clock). DSP56002 AD7723 SDR SDO SC1 FSO SCK SCO 01186-048 In serial mode, the AD7723 can be directly interfaced to several industry-standard digital signal processors. In all cases, the AD7723 operates as the master with the DSP operating as the slave. The AD7723 provides its own serial clock (SCO) to transmit the digital word on the SDO pin to the DSP. The AD7723 also generates the frame synchronization signal that synchronizes the transfer of the 16-bit word from the AD7723 to the DSP. Depending on the serial mode used, SCO has a frequency equal to CLKIN or equal to CLKIN/2. When SCO equals 19.2 MHz, the AD7723 can be interfaced to the Analog Devices ADSP-2106x SHARC DSP. With a 19.2 MHz master clock and SCO equal to CLKIN/2, the AD7723 can be interfaced with the ADSP-21xx family of DSPs, the DSP56002, and the TMS320C5x-57. When the AD7723 is used in the HALF_PWR Mode, that is, CLKIN is less than 10 MHz, then the AD7723 can be used with DSPs, such as the TMS320C20/TMS320C25 and the DSP56000/DSP56001. Figure 48. AD7723 to DSP56002 Interface AD7723 SDO AD7723 TO TMS320C5x INTERFACE RFS FSO SCLK SCO Figure 49 shows the AD7723 to TMS320C5x interface. For the TMS320C5x, FSR and CLKR are automatically configured as inputs. The serial port is configured as follows: FO = 0 (16-bit word transfers) and FSM = 1 (a frame sync occurs for each transfer). Figure 47. AD7723 to ADSP-21xx Interface AD7723 TO SHARC INTERFACE The interface between the AD7723 and the ADSP-2106x SHARC DSP is the same as shown in Figure 47, but the DSP is configured as follows: SLEN = 15 (16-bit word transfers), SENDN = 0 (the MSB of the 16-bit word is received by the DSP first), ICLK = 0 (an external serial clock is used), RFSR = 0 (a frame sync is required for every word transfer), IRFS = 0 (the receive frame sync signal is external), CKRE = 0 (the receive data is latched into the DSP on the falling clock edge), LAFS = 0 Rev. C | Page 27 of 32 TMS320C5x AD7723 DR SDO FSR FSO CLKR SCO 01186-049 01186-047 DR Figure 49. AD7723 to TMS320C5x Interface AD7723 GROUNDING AND LAYOUT The analog and digital power supplies to the AD7723 are independent and separately pinned out to minimize coupling between the analog and digital sections within the device. The AD7723 AGND and DGND pins should be soldered directly to a ground plane to minimize series inductance. In addition, the ac path from any supply pin or reference pin (REF1 and REF2) through its decoupling capacitors to its associated ground must be made as short as possible (Figure 50). To achieve the best decoupling, place surface-mount capacitors as close as possible to the device, ideally right up against the device pins. All ground planes must not overlap to avoid capacitive coupling. The AD7723’s digital and analog ground planes must be connected at one place by a low inductance path, preferably right under the device. Typically, this connection is either a trace on the printed circuit board of 0.5 cm wide when the ground planes are on the same layer, or 0.5 cm wide minimum plated through holes when the ground planes are on different layers. Any external logic connected to the AD7723 should use a ground plane separate from the AD7723’s digital ground plane. These two digital ground planes should also be connected at just one place. Avoid running digital lines under the device as these couple noise onto the die. The analog ground plane should be allowed to run under the AD7723 to shield it from noise coupling. The power supply lines to the AD7723 should use as large a trace as possible (preferably a plane) to provide a low impedance path and reduce the effects of glitches on the power supply line. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. 23 REF2 10nF 220nF 22 AGND2 1µ F 21 REF1 10nF 11 AV 1 DD 10 AGND1 5V 9 AGND1 17 AVDD 10µ F 100nF 10nF 100nF 18 AGND 26 AVDD A minimum etch technique is generally best for ground planes because it gives the best shielding. Noise can be minimized by paying attention to the system layout and preventing different signals from interfering with each other. High level analog signals should be separated from low level analog signals, and both should be kept away from digital signals. In waveform sampling and reconstruction systems, the sampling clock (CLKIN) is as vulnerable to noise as any analog signal. CLKIN should be isolated from the analog and digital systems. Fast switching signals like clocks should be shielded with their associated ground to avoid radiating noise to other sections of the board, and clock signals should never be routed near the analog inputs. Rev. C | Page 28 of 32 10nF AD7723 ANALOG GROUND PLANE AD7723 DIGITAL GROUND PLANE 10µ F 100nF 10nF 10nF 25 AGND 39 DV DD 6 DGND 28 DGND Figure 50. Reference and Power Supply Decoupling 01186-050 Separate power supplies for AVDD and DVDD are also highly desirable. The digital supply pin DVDD should be powered from a separate analog supply, but if necessary, DVDD may share its power connection to AVDD, as shown in the connection diagram in Figure 50. The ferrites are also recommended to filter high frequency signals from corrupting the analog power supply. AD7723 OUTLINE DIMENSIONS 1.03 0.88 0.73 13.90 BSC SQ 2.45 MAX 23 33 SEATING PLANE 22 34 10.00 BSC SQ TOP VIEW 10° 6° 2° 2.10 2.00 1.95 (PINS DOWN) 0.23 0.11 VIEW A 7° 0° 0.25 MIN PIN 1 44 12 11 1 0.10 COPLANARITY VIEW A 0.80 BSC LEAD PITCH ROTATED 90° CCW 0.45 0.30 LEAD WIDTH COMPLIANT TO JEDEC STANDARDS MO-112-AA-1 Figure 51. 44-Lead Metric Quad Flat Package [MQFP] (S-44-2) Dimensions shown in millimeters ORDERING GUIDE Model AD7723BS AD7723BS-REEL AD7723BSZ1 AD7723BSZ-REEL1 EVAL-AD7723CB 1 Temperature Package –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 44-Lead Metric Quad Flat Package (MQFP) 44-Lead Metric Quad Flat Package (MQFP) 44-Lead Metric Quad Flat Package (MQFP) 44-Lead Metric Quad Flat Package (MQFP) Evaluation Board Z = Pb-free part. Rev. C | Page 29 of 32 Package Outline S-44-2 S-44-2 S-44-2 S-44-2 AD7723 NOTES Rev. C | Page 30 of 32 AD7723 NOTES Rev. C | Page 31 of 32 AD7723 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01186–0–5/05(C) Rev. C | Page 32 of 32