bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 3A, 30V, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger with Power Path Management and USB-OTG Support Check for Samples: bq24260, bq24261, bq24262A FEATURES – Thermal Regulation Protection for Input Current Control – Thermal Shutdown and Protection 1 • Charge Time Optimizer (Enhanced CC/CV Transition) for Faster Charging • Integrated FETs for Up to 3A Charge Rate at 5% Accuracy and 93% Peak Efficiency • Boost Capability to Supply 5V at 1A at IN for USB OTG Supply • Integrated 17mΩ Power Path MOSFET and optional BGATE control to Maximize Battery Life and Instantly Startup From a Deeply Discharged Battery or No Battery • 30V Input Rating with Over-Voltage Protection Supports 5V USB2.0/3.0 and 12V USB Power Delivery (bq24261) • Small Solution Size In a 2.4mm x 2.4mm 36ball WCSP or 4mm x 4mm QFN-24 Package – Total Charging Solution Can be 50mm2 or less with WCSP • Safe and Accurate Battery Management Functions Programmed Using I2C Interface – Charge Voltage, Current, Termination Threshold, Input Current Limit, VIN_DPM Threshold – Voltage-based, JEITA Compatible NTC Monitoring Input Application Schematic APPLICATIONS • • • • • Smartphone and Tablets Handheld Products Power Banks and External Battery Packs Small Power Tools Portable Media Players and Gaming DESCRIPTION The bq24260/bq24261/bq24262A are highly integrated single cell Li-Ion battery charger and system power path management devices targeted for space-limited, portable applications with high capacity batteries. The single cell charger has a single input that supports operation from either a USB port or wall adapter supply for a versatile solution. (Continued on page 2) Charge Time Optimizer Effect Charge Cycle 4000mAh Battery 2A Charge Rate 3 4.4 IN SW VBUS 4.2 D+ 2.5 System Load GND PGND 4 BOOT 3.8 Voltage (V) ` PMID SYS ` D+ More Energy Delivered to the Battery in the Same Time 3.6 3.4 2 1.5 3.2 D- 1 3 BAT CD 2.8 SDA SCL Charge Current (A) / Efficiency D- 0.5 bq24260 2.6 HOST INT PACK+ TS TEMP V I/O 0 10000 11000 2.4 VDRV 0 PACK- 2000 VBAT_CTO 4000 6000 Time (sec) VBAT_Traditional 8000 IBAT_CTO IBAT_Traditional 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013–2014, Texas Instruments Incorporated bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com DESCRIPTION (CONTINUED) The power path management feature allows the bq2426x to power the system from a high efficiency DC to DC converter while simultaneously and independently charging the battery. The charger monitors the battery current at all times and reduces the charge current when the system load requires current above the input current limit or the adapter cannot support the required load, causing the adapter voltage to fall (VIN_DPM). This allows for proper charge termination and timer operation. The system voltage is regulated to the battery voltage but will not drop below 3.5V (VMINSYS). This minimum system voltage support enables the system to run with a defective or absent battery pack and enables instant system turn-on even with a totally discharged battery or no battery. The powerpath management architecture also permits the battery to supplement the system current requirements when the adapter cannot deliver the peak system currents. The power-path feature coupled with VIN-DPM, enables the use of many adapters with no hardware change. The charge parameters are programmable using the I2C interface. To Support USB OTG applications, the bq2426x is configurable to boost the battery voltage to 5V at the input. In this mode, the bq2426x supplies up to 1A and operates with battery voltages down to 3.3V. The battery is charged using a standard Li-Ion charge profile with three phases: precharge, constant current and constant voltage. In all charge phases, an internal control loop monitors the IC junction temperature and reduces the input current to prevent the junction temperature from rising above 125°C. Additionally, a voltage-based, JEITA compatible battery pack thermistor monitoring input (TS) is included that monitors battery temperature and automatically changes charge parameters to prevent the battery from charging outside of its safe temperature range. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Available Options PART NUMBER OVP CE BIT DEFAULT D+/D– DETECTION TIMERS (SAFETY and WATCHDOG) NTC MONITORING OTG BOOST I2C ADDRESS bq24260 10.5 0 (Charge Enabled) YES YES JEITA YES 6B bq24261 14 1 (Charge Disabled) NO YES JEITA YES 6B bq24262A 6.5 0 (Charge Enabled) NO NO JEITA YES 6B Ordering Information PART NUMBER bq24260 bq24261 bq24262A 2 IC MARKING bq24260 bq24261 bq24262A Submit Documentation Feedback PACKAGE ORDERABLE NUMBER QUANTITY DSBGA - YFF (PREVIEW) bq24260YFFR 3000 DSBGA - YFF (PREVIEW) bq24260YFFT 250 QFN – RGE (PREVIEW) bq24260RGER 3000 QFN – RGE (PREVIEW) bq24260RGET 250 DSBGA - YFF bq24261YFFR 3000 DSBGA - YFF bq24261YFFT 250 QFN – RGE bq24261RGER 3000 QFN – RGE bq24261RGET 250 DSBGA - YFF (PREVIEW) bq24262AYFFR 3000 DSBGA - YFF (PREVIEW) bq24262AYFFT 250 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VALUE Pin Voltage Range (with respect to PGND) MIN MAX IN –1.3 30 BOOT, PMID –0.3 30 SW –0.7 20 BAT, BGATE, CD, D+, D-, DRV, INT, PSEL, SDA, SCL, STAT, SYS, TS –0.3 5 –0.3 5 BOOT to SW Output Current (Continuous) SW 4.5 SYS, BAT (charging/ discharging) 3.5 Input Current (Continuous) Output Sink Current STAT, INT V V A 2.75 A 10 mA Operating free-air temperature range –40 85 Junction temperature, TJ –40 125 Storage temperature, TSTG (1) UNIT °C 300 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. THERMAL INFORMATION THERMAL METRIC (1) bq2426x YFF (36 PINS) RGE (24 PINS) θJA Junction-to-ambient thermal resistance 55.8 32.6 θJCtop Junction-to-case (top) thermal resistance 0.5 30.5 θJB Junction-to-board thermal resistance 10 3.3 ψJT Junction-to-top characterization parameter 2.6 0.4 ψJB Junction-to-board characterization parameter 9.9 9.3 θJCbot Junction-to-case (bottom) thermal resistance N/A 2.6 (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. spacer Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIN NOM MAX UNIT 28 (1) IN voltage range 4.2 IN operating voltage range (bq24260) 4.2 10 IN operating voltage range (bq24261) 4.2 13.2 IN operating voltage range (bq24262A) 4.2 6.0 V IIN Input current, IN input 2.5 A ISW Output Current from SW, DC 3 A IBAT, ISYS Charging 3 Discharging, using internal battery FET 3 TJ (1) Operating junction temperature range 0 125 A °C The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight layout minimizes switching noise. Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 3 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com ELECTRICAL CHARACTERISTICS Circuit of Figure 1, VUVLO < VIN < VOVP AND VIN > VBAT+ VSLP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT YFF Package: VUVLO < VIN < VOVP and VIN>VBAT+VSLP PWM NOT switching 6.5 mA RGE Package: VUVLO < VIN < VOVP and VIN>VBAT+VSLP PWM NOT switching 6.65 0°C< TJ < 85°C, VIN = 5V, High-Z Mode 250 0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 5V, SCL, SDA = 0V or 1.8V, High-Z Mode 15 YFF Package: 0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 0V, SCL, SDA = 0V or 1.8V 77 RGE Package: 0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 0V, SCL, SDA = 0V or 1.8V 80 INPUT CURRENTS VUVLO < VIN < VOVP and VIN>VBAT+VSLP PWM switching IIN Supply current for control Battery discharge current in High Impedance mode, (BAT, SW, SYS) IBAT_HIZ 15 μA μA POWER-PATH MANAGEMENT VSYSREG(LO) System Regulation Voltage VBAT < VMINSYS VMINSYS + 80mV VMINSYS + 100mV VMINSYS + 120mV V VSYSREG(HI) System Regulation Voltage Battery FET turned off, no charging, VBAT > 3.5V VBATREG +2.2% VBATREG +2.5% VBATREG +2.77% V VMINSYS Minimum System Voltage Regulation Threshold VBAT + VDO(SYS_BAT) < 3.5V 3.44 3.5 3.55 V tDGL(MINSYS_C Deglitch time, VMINSYS comparator rising MP) 8 ms VBSUP1 Enter supplement mode threshold VBAT > VBUVLO VBAT – 20mV V VBSUP2 Exit supplement mode threshold VBAT > VBUVLO VBAT – 5mV V ILIM(DISCH) Current Limit, Discharge or Supplement Mode VLIM(BGATE) = VBAT – VSYS 6 A tDGL(SC1) Deglitch Time, OUT Short Circuit during Discharge or Supplement Mode Measured from IBAT = 7A to FET off 250 μs tREC(SC1) Recovery time, OUT Short Circuit during Discharge or Supplement Mode 2 s 4 Battery Range for BGATE Operation 2.5 4.5 V BATTERY CHARGER RON(BAT-SYS) VBATREG ICHARGE VBATSHRT VBATSHRT_HY S 4 YFF 17 25 RGE 32 47 Internal battery charger MOSFET on-resistance Measured from BAT to SYS, VBAT = 4.2V, High-Z mode Charge Voltage Operating in voltage regulation, Programmable Range RGE Package Voltage Regulation Accuracy 3.5 4.44 TJ = 0°C to 50°C -0.5% 0.5% RGE Package Voltage Regulation Accuracy TJ = 0°C to 85°C -0.7% 0.7% RGE Package Voltage Regulation Accuracy TJ = 0°C to 125°C -1.0% 1.0% YFF Package Voltage Regulation Accuracy TJ = 0°C to 125°C –1.7% 0.8% Fast Charge Current Range VBATSHRT ≤ VBAT < VBAT(REG) 500 3000 Fast Charge Current Accuracy 500 mA ≤ ICHARGE ≤ 1A –10% 10% ICHARGE > 1000 mA –5% 5% Battery short circuit threshold Hysteresis for VBATSHRT 1.9 Battery voltage falling Submit Documentation Feedback 2 100 2.1 mΩ V mA V mV Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS (continued) Circuit of Figure 1, VUVLO < VIN < VOVP AND VIN > VBAT+ VSLP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS Deglitch time for battery short to fastcharge transition VBAT rising or falling IBATSHRT Battery short circuit charge current VBAT < VBATSHRT ITERM Termination charge current MIN ITERM 33.5 < 200 mA ITERM ≥ 200 mA tDGL(TERM) Deglitch time for charge termination Both rising and falling, 2-mV over-drive, tRISE, tFALL=100ns VRCH Recharge threshold voltage Below VBATREG tDGL(RCH) Deglitch time VBAT falling below VRCH, tFALL=100ns VDET(SRC1) Battery detection voltage threshold (TE = 1) VDET(SRC2) VDET(SNK) MAX 1 ITERM ≤ 50 mA 50 mA < TYP 50 ms 66.5 –30% 30% –15% 15% –15% 10% 32 100 120 UNIT mA ms 150 mV 32 ms During current source (Turn IBATSHRT off) VRCH V During current source (Turn IBATSHRT on) VRCH – 200mV V During current sink VBATSHRT V IDETECT Battery detection current before charge done (sink current) Termination enabled (TE = 1) 7 mA tDETECT(SRC) Battery detection time (sourcing current) Termination enabled (TE = 1) 2 s tDETECT(SNK) Battery detection time (sinking current) Termination enabled (TE = 1) 250 ms INPUT CURRENT LIMITING IINLIM VIN_DPM Input current limiting threshold Input based DPM threshold range USB charge mode, VIN = 5V, Current pulled from SW IINLIM=USB100 90 95 100 IINLIM=USB500 450 475 500 IINLIM=USB150 125 140 150 IINLIM=USB900 800 850 900 IINLIM=1.5A 1425 1500 1575 IINLIM=2A, YFF Package 1850 2000 2150 IINLIM=2A, RGE Package 1850 2000 2200 IINLIM=2.5A, YFF Package 2300 2500 2700 IINLIM=2.5A, RGE Package 2225 2500 2825 Charge mode, programmable via I2C VIN_DPM threshold Accuracy 4.2 11.6 –3% 3% mA V VDRV BIAS REGULATOR VDRV Internal bias regulator voltage IDRV DRV Output Current VDO_DRV DRV Dropout Voltage (VIN – VDRV) VIN>5V 4.3 4.8 5.3 V 10 mA IIN = 1A, VIN = 4.2V, IDRV = 10mA 450 mV 0.4 V 1 µA 0.4 V 0 STATUS OUTPUT (STAT, INT) VOL Low-level output saturation voltage IO = 10 mA, sink current IIH High-level leakage current V STAT = VINT = 5V INPUT PINS (CD, PSEL) VIL Input low threshold VIH Input high threshold RPULLDOWN CD pull-down resistance 1.4 CD Only Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A V 100 Submit Documentation Feedback kΩ 5 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Circuit of Figure 1, VUVLO < VIN < VOVP AND VIN > VBAT+ VSLP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise noted) PARAMETER Deglitch for CD and PSEL TEST CONDITIONS MIN CD or PSEL rising/falling TYP MAX 100 UNIT µs PROTECTION VUVLO IC active threshold voltage VIN rising VUVLO_HYS IC active hysteresis VIN falling from above VUVLO 3.2 300 VBATUVLO Battery Undervoltage Lockout threshold VBAT falling, 100mV Hysteresis 2.4 2.6 V VSLP Sleep-mode entry threshold, VIN-VBAT 2.0 V < VBAT < VBATREG, VIN falling 40 120 mV tDGL(BAT) Deglitch time, BAT above VBATUVLO before SYS starts to rise VSLP_HYS Sleep-mode exit hysteresis VIN rising above VSLP tDGL(VSLP) Deglitch time for supply rising above VSLP+VSLP_HYS Rising voltage, 2-mV over drive, tRISE=100ns VOVP Input supply OVP threshold voltage IN rising, 100mV hysteresis 0 40 10.5 10.9 13.6 14 14.4 bq24262 6.25 6.5 6.75 3.51 3.7 3.89 Battery OVP threshold voltage VBAT threshold over VOREG to turn off charger during charge VBOVP_HYS VBOVP hysteresis Lower limit for VBAT falling from above VBOVP tDGL(BOVP) BOVP Deglitch Battery entering/exiting BOVP ICbCLIMIT Cycle-by-cycle current limit VSYS shorted TSHTDWN Thermal trip 30 1.03 × VBATREG 1.05 × VBATREG 1.07 × VBATREG V ms 4.9 150 Thermal hysteresis V % of VBATREG 8 4.5 V ms 1 4.1 mV ms 10.1 VBOVP Thermal regulation threshold 190 bq24261 IN falling below VOVP TREG ms bq24260 Deglitch time, VIN OVP in Buck Mode P) 100 V mV 30 VIN Rising tDGL(BUCK_OV 3.4 1.2 Good Battery Monitor Threshold (BQ24260/1 only) VBATGD 3.3 A °C 10 Input current begins to cut off 125 Safety Timer Accuracy –20% °C 20% PWM Internal top MOSFET onresistance YFF Package: Measured from IN to SW 75 120 mΩ RGE Package: Measured from IN to SW 80 135 mΩ RDSON_Q2 Internal bottom N-channel MOSFET on-resistance YFF Package: Measured from SW to PGND 75 115 mΩ RGE Package: Measured from SW to PGND 80 135 mΩ fOSC Oscillator frequency 1.5 1.65 MHz DMAX Maximum duty cycle DMIN Minimum duty cycle RDSON_Q1 1.35 95 % 0 BATTERY-PACK NTC MONITOR (1) VHOT High temperature threshold VTS falling, 2% VDRV Hysteresis 27.3 30 32.6 %VDRV VWARM Warm temperature threshold VTS falling, 2% VDRV Hysteresis 36.0 38.3 41.2 %VDRV VCOOL Cool temperature threshold VTS rising, 2% VDRV Hysteresis 54.7 56.4 58.1 %VDRV VCOLD Low temperature threshold VTS rising, 2% VDRV Hysteresis 58.2 60 61.8 %VDRV TSOFF TS Disable threshold VTS rising, 4% VDRV Hysteresis 80 85 %VDRV tDGL(TS) Deglitch time on TS change Applies to VHOT, VWARM, VCOOL and VCOLD 50 ms I2C COMPATIBLE INTERFACE VIH Input low threshold level VPULL-UP=1.8V, SDA and SCL VIL Input low threshold level VPULL-UP=1.8V, SDA and SCL 1.3 0.4 VOL Output low threshold level IL=5mA, sink current 0.4 V IBIAS High-Level leakage current VPULL-UP=1.8V, SDA and SCL 1 μA tWATCHDOG 6 Submit Documentation Feedback 30 V 50 V s Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS (continued) Circuit of Figure 1, VUVLO < VIN < VOVP AND VIN > VBAT+ VSLP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN tI2CRESET TYP MAX 700 UNIT ms OTG BOOST SUPPLY Quiescent current during boost mode (BAT pin) 3.3V<VBAT<4.5V, no switching Battery voltage range for specified boost operation VBAT falling 3.3 VIN_BOOST Boost output voltage (to pin VBUS) 3.3V<VBAT<4.5V over line and load 4.95 IBO Maximum output current for boost 3.3V<VBAT<4.5V IBLIMIT Cycle by cycle current limit for boost (measured at lowside FET) 3.3V<VBAT<4.5V VBOOSTOVP Over voltage protection threshold for boost (IN pin) Signals fault and exits boost mode IQBAT_ BOOST tDGL(BOOST_O VP) BOOST_ILIM = 1 1000 BOOST_ILIM = 0 500 5.05 4 BOOST_ILIM = 0 2 Deglitch Time, VIN OVP in Boost Mode µA 4.5 V 5.2 V mA BOOST_ILIM = 1 5.8 100 6 A 6.2 170 V µs VBURST(ENT) Upper VIN voltage threshold to enter burst mode (stop switching) 5.1 5.2 5.3 V VBURST(EXIT) Lower VBUS voltage threshold to exit burst mode (start switching) 4.9 5 5.1 V Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 7 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com Block Diagrams PMID 4.8V Reference DRV IN ICbCLimit + BOOT IINLIM Q1 DC-DC CONVERTER PWM LOGIC, COMPENSATION AND BATTERY FET CONTROL VINDPM VSYS(REG) IBAT(REG) VBAT(REG) SW DIE Temp Regulation Q2 PGND VSUPPLY SYS References OVP Comparator VIN Termination Reference + Q3 VINOVP + Termination Comparator Sleep Comparator VIN + IBAT BAT Recharge Comparator VBAT +VSLP Start Recharge Cycle + VBATREG ± 0.12V VBAT Hi-Impedance Mode Hi-Z Mode CD Enable Linear Charge VSYSREG Comparator + VSYS VMINSYS + Enable HiZ in DEFAULT mode SDA I2C Interface BGATE VBATGD VBATSC Comparator SCL Enable IBATSHRT + VBAT VBATSHRT Supplement COMPARATOR + D+ D- VSYS VBAT bq24260 USB Adapter Detection Circuitry VBSUP VDRV VBOVP Comparator + 1.5A / USB100 VBAT VBATOVP + DISABLE bq24261/2 TS COLD PSEL 1C/ 0.5C + TS COOL + VBATREG ± 0.14V STAT TS WARM + DISABLE INT CHARGE CONTROLLER TS HOT TS w/ Timers Figure 1. Block Diagram in Charging Mode 8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 PMID 4.8-V Reference DRV IN BOOT VBOOST Amp + Q1 VIN_BOOST Burst Mode Enter Comparator DC-DC Low Side Current CONVERTER Limit Comparator PWM LOGIC AND IBLIMITI COMPENSATION + VBURST_EXT SW + + VBURST_ENT VDRV Q2 Burst Mode Exit Comparator PGND Boost Short Circuit Comparator VBOOSTSHRT + VBOOSTOVP + VBOOST OVP Comparator SYS Battery SC Comparator VBAT CD SDA VBIAS Battery Short Circuit Q3 + ILIM(DISCH) BAT Hi-Z Mode 2 I C interface SCL BGATE Digital Control STAT INT TS Figure 2. Block Diagram in Boost Mode Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 9 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com PIN CONFIGURATION 36-Ball 2.4mm x 2.4mm WCSP bq24260 (Top View) bq24261/2 (Top View) 1 2 4 5 A PGND PGND PGND PGND PGND PGND SW B PMID SW SW SW SW SW CD BOOT C IN IN IN IN CD BOOT D+ TS DRV D SDA SCL N.C. PSEL TS DRV SYS SYS SYS SYS E STAT INT SYS SYS SYS SYS BAT BAT BAT BAT F AGND BGATE BAT BAT BAT BAT 1 2 3 4 5 6 A PGND PGND PGND PGND PGND PGND B PMID SW SW SW SW C IN IN IN IN D SDA SCL D– E STAT INT F AGND BGATE 3 6 24-Pin 4mm × 4mm QFN AGND IN IN PGND AGND PGND PGND SW PGND 3 SW SW 19 DRV 19 20 2 20 21 BOOT 21 22 18 IN 22 23 1 23 24 PMID 24 SW (Top View) PMID 1 18 IN 17 SDA BOOT 2 17 SDA 16 SCL DRV 3 16 SCL bq24261 bq24262 bq24260 14 PSEL SYS 6 13 STAT 13 STAT SYS BAT BAT INT BGATE AGND 12 12 11 11 10 10 9 9 8 8 Submit Documentation Feedback 7 7 10 AGND TS 5 BGATE 14 D+ INT TS 5 SYS 6 15 N.C. BAT CD 4 BAT 15 D– SYS CD 4 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 Pin Configurations PIN NUMBER bq24260 PIN NUMBER bq24261/2 YFF RGE YFF RGE F1 12, 20 F1 12, 20 F3-F6 8, 9 F3-F6 8, 9 I/O Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at least 1μF of ceramic capacitance. See Applicaton section for additional details. F2 11 F2 11 O External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFET to provide a very low resistance discharge path. Connect BGATE to the gate of the external MOSFET. BGATE is low during high impedance mode or when no input is connected. If no external FET is required, leave BGATE disconnected. Do not connect BGATE to GND. C6 2 C6 2 I High Side MOSFET Gate Driver Supply. Connect 0.033µF of ceramic capacitance (voltage rating > 10V) from BOOT to SW to supply the gate drive for the high side MOSFET. C5 4 C5 4 I IC Hardware Disable Input. Drive CD high to place the bq24260 in high-z mode. Drive CD low for normal operation. CD is pulled low internally with 100kΩ D+ D4 14 – – I D– D3 15 – – I D6 3 D6 3 O Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass DRV to PGND with at least 1μF of ceramic capacitance. DRV may be used to drive external loads up to 10mA. DRV is active whenever the input is connected and VIN > VUVLO and VIN > (VBAT + VSLP). C1-C4 19 C1-C4 19 I DC Input Power Supply. IN is connected to the external DC supply (AC adapter or USB port). Bypass IN to PGND with at least a 4.7μF of ceramic capacitance. PIN NAME AGND BAT I/O Analog Ground. Connect to the thermal pad (for QFN only) and the ground plane of the circuit. BGATE BOOT CD DRV IN DESCRIPTION INT D+ and D– Connections for USB Input Adapter Detection. When a source is initially connected to the input during DEFAULT mode, and a short is detected between D+ and D–, the input current limit is set to 1.5A. If a short is not detected, the USB100 mode is selected. E2 10 E2 10 O Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT pulls low during charging. INT is high impedance when charging is complete, disabled or the charger is in high impedance mode. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. INT is enabled /disabled using the EN_STAT bit in the control register. Connect INT to a logic rail through a 100kΩ resistor to communicate with the host processor. A1-A6 21,22 A1-A6 21,22 – Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit. B1 1 B1 1 I High Side Bypass Connection. Connect at least 1µF of ceramic capacitance from PMID to PGND as close to the PMID and PGND pins as possible. – – D4 14 I Hardware Input Current Limit. In DEFAULT mode, PSEL selects the input current limit. Drive PSEL high to select USB100 (bq24261) or USB500 (bq24262A) mode, drive PSEL low to select 1.5A mode. SCL D2 16 D2 16 I I2C Interface Clock. Connect SCL to the logic rail through a 10kΩ resistor. SDA D1 17 D1 17 I/O I2C Interface Data. Connect SDA to the logic rail through a 10kΩ resistor. PGND PMID PSEL STAT SW E1 13 E1 13 O Status Output. STAT is an open-drain output that signals charging status and fault interrupts. STAT pulls low during charging. STAT is high impedance when charging is complete, disabled or the charger is high impedance mode. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. STAT is enabled /disabled using the EN_STAT bit in the control register. Connect STAT to a logic rail using an LED for visual indication or through a 100kΩ resistor to communicate with the host processor. B2-B6 23, 24 B2-B6 23, 24 O Inductor Connection. Connect to the switched side of the external inductor. The inductance must be between 1.5µH and 2.2µH. E3-E6 6, 7 E3-E6 6, 7 I System Voltage Sense and Charger FET Connection. Connect SYS to the system output at the output bulk capacitors. Bypass SYS locally with at least 10μF of ceramic capacitance. The SYS rail must have at least 20µF of total capacitance for stable operation. See Application section for additional details. SYS TS Thermal PAD D5 5 D5 5 I Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND. The NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA compatibility. TS faults are reported by the I2C interface. Pull TS high to VDRV to disable the TS function if unused. See the NTC Monitor section for more details on operation and selecting the resistor values. – – – – – There is an internal electrical connection between the exposed thermal pad and the PGND pin of the device. The thermal pad must be connected to the same potential as the PGND pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. PGND pin must be connected to ground at all times. Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 11 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com Typical Application Circuit Typical Application Circuit 1 – bq24261, No External Discharge FET 1 .5 uH PMID SW 47 uF 1 uF 0 .033 uF System Load BOOT SYS IN VBUS D+ 10 uF DGND 4 .7 uF BGATE DRV BAT VDRV 1 uF 1 uF PGND STAT PACK + TS TEMP V I/O ( 1 .8 V ) PSEL USB PHY PACK– HOST bq 24261 INT GPIO 1 SDA SDA SCL SCL CD Typical Application Circuit 2 – bq24260, External Discharge FET 1 .5 uH PMID SW 1 uF System Load 47 uF 0 .033 uF BOOT 10 uF SYS IN VBUS D+ D- PGND GND 4 .7 uF BGATE DRV BAT VDRV 1 uF 1 uF STAT PACK + TS TEMP V SYS ( 1 .8 V ) D+ DPACK - bq 24260 INT HOST GPIO 1 SDA SDA SCL SCL CD 12 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 Typical Characteristics Figure 3. Startup With No Battery Figure 4. Battery Detection Figure 5. Battery Removal Figure 6. Default Start-up - bq24260 (D+/D– shorted) Figure 7. Default Start-up - bq24260 (D+/D– not shorted) Figure 8. VSYS Transient Without Supplement Mode Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 13 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com Typical Characteristics (continued) 14 Figure 9. VSYS Transient With Supplement Mode Figure 10. VSYS Transient With Supplement Mode Figure 11. Boost Startup No Load Figure 12. Boost Burst Mode During Light Load Figure 13. Boost Startup 1A Load Figure 14. Boost Transient Response Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 Typical Characteristics (continued) Figure 15. Input OVP Event with INT Figure 16. Startup, 4.2V 10 95 VIN=5V 8 ICHG=1.2A Charge Current Accuracy (%) 6 90 Efficiency (%) 4 2 0 -2 TA=25ºC -4 85 80 VIN=5V VIN=7V TA=0ºC -6 TA=85ºC -8 TA=60ºC -10 2.9 3.1 3.3 3.5 3.7 3.9 VBAT (V) 4.1 VIN=12V 4.3 70 4.5 0 Figure 17. Charge Current vs Battery Voltage 90 -0.5 VBAT Accuracy (%) 0.0 80 Efficiency (%) 0.5 1 1.5 2 Load Current (A) 2.5 3 Figure 18. Efficiency vs Output Current 100 70 60 ICHG=2A VIN=5V VREG=4.44V TA=25ºC 50 VIN=10V 75 -1.0 -1.5 -2.0 TA=25ºC TA=60ºC TA=0ºC -2.5 40 2 2.5 3 3.5 4 VBAT (V) Figure 19. Efficiency vs Battery Voltage 4.5 -3.0 0 0.5 1 1.5 IBAT (A) Figure 20. VBAT Accuracy vs IBAT – 4.2V Setting Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 2 15 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com 700 14 600 12 500 Input Current (μA) Input Current - mA Typical Characteristics (continued) 16 10 8 6 4 400 300 200 Input Current (μA) 100 2 TA=25°C 0 0 -100 3 -2 0 2 4 6 8 10 12 14 Input Voltage - V Figure 21. Input IQ - No Battery, No System 5 7 16 9 11 13 15 Input Voltage (V) Figure 22. Input IQ with Hi-Z Enabled Detailed Description High Impedance Mode High Impedance mode (Hi-Z mode) is the low quiescent current state for the bq2426x. During Hi-Z mode, the buck converter is off, and the battery FET and BGATE are on. SYS is powered by BAT. The bq2426x is in Hi-Z mode when VIN < VUVLO, the HZ_MODE bit in the I2C is '1' or the CD pin is driven high. Hi-Z mode resets the safety timer. The bq2426x contains a CD input that is used to disable the IC and place the bq2426x into high-impedance mode. Drive CD low to enable the bq2426x and enter normal operation. Drive CD high to disable charge and place the bq2426x into high-impedance mode. CD is internally pulled down to PGND with a 100kΩ resistor. When exiting Hi-Z mode, charging resumes in approximately 110ms. Battery Only Connected When the battery is connected with no input source, the battery FET is turned on. After the battery rises above VBATUVLO and the deglitch time, tDGL(BAT), the SYS output starts to rise. In this mode, the current is not regulated; however, there is a short circuit current limit. If the short circuit limit (ILIM(DISCHG)) is reached for the deglitch time (tDGL(SC)), the battery FET is turned off for the recovery time (tREC(SC)). After the recovery time, the battery FET is turned on to test and see if the short has been removed. If it has not, the FET turns off and the process repeats until the short is removed. This process protects the internal FET from over current. If an external FET is used for discharge, the body diode prevents the load on SYS from being disconnected from the battery and tDGL(BAT) is not applicable. Input Connected Input Voltage Protection in Charge Mode Sleep Mode The bq2426x enters the low-power sleep mode if the voltage on VIN falls below sleep-mode entry threshold, VBAT+VSLP, and VIN is higher than the undervoltage lockout threshold, VUVLO. In sleep mode, the input is isolated from the battery. This feature prevents draining the battery during the absence of VIN. When VIN < VBAT+ VSLP, the bq2426x turns off the PWM converter, turns the battery FET and BGATE on, sends a single 128μs pulse on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I2C. Once VIN > VBAT+ VSLP, the STATx bits are cleared and the device initiates a new charge cycle. The FAULT_x bits are not cleared until they are read in the I2C and the sleep condition no longer exists. Input Voltage Based Dynamic Power Management (VIN-DPM) 16 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 During normal charging process, if the input power source is not able to support the programmed or default charging current, the supply voltage deceases. Once the supply drops to VIN_DPM (default 4.2V), the charge current limit is reduced to prevent the further drop of the supply. When the IC enters this mode, the charge current is lower than the set value and the DPM_STATUS bit is set. This feature ensures IC compatibility with adapters with different current capabilities without a hardware change. Figure 23 shows the VIN-DPM behavior to a current limited source. In this figure the input source has a 2A current limit and the device is charging at 1A. A 2.5A load transient then occurs on VSYS causing the adapter to hit its current limit and collapse, while VSYS goes from VSYSREG(LO) to VMINSYS. If the 2X timer is set, the safety timer is extended while VIN-DPM is active. Additionally, termination is disabled. VIN 1V/div Input voltage regulated to VIN_DPM (5V Offset) Input current limit reduced to avoid crashing adapter 2A/div IIN 500mV/div VSYS (3.6V Offset) IBAT Normal Charging (1A) SYS enters supplement mode to ensure SYS load is supported SYS load removed, normal charging resumes 2A/div 2A/div ISYS 800us/div Figure 23. bq24260 VIN-DPM Input Over-Voltage Protection The built-in input over-voltage protection protects the bq2426x and downstream components connected to SYS and/or BAT against damage from overvoltage on the input supply (Voltage from VIN to PGND). When VIN > VOVP, the bq2426x turns off the PWM converter immediately. After the deglitch time tDGL(BUCK_OVP), an OVP fault is determined to exist. During the OVP fault, the bq2426x turns the battery FET and BGATE on, sends a single 128μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits are updated in the I2C. Once the OVP fault is removed, the STATx bits are cleared and the device returns to normal operation. The FAULT_x bits are not cleared until they are read in the I2C after the OVP condition no longer exists. The OVP threshold for the bq24260 is 10.5V for operation from standard adapters while the bq24261 is set to 14V to enable operation from 12V sources. The bq24262A OVP is set to 6.5V to operate from standard USB sources. Charge Profile When a valid input source is connected (VIN>VUVLO and VBAT+VSLP<VIN<VOVP), the CE bit in the control register determines whether a charge cycle is initiated. By default, the bq24260 and bq24262A enable the charge cycle when a valid input source is connected while the bq24261 does not (CE=1 by default). When the CE bit is 1 and a valid input source is connected, the battery FET is turned off and the SYS output is regulated to VSYSREG(HI). A charge cycle is initiated when the CE bit is written to a 0. Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 17 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com The bq2426x supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. Charging is done through the internal battery MOSFET. There are 6 loops that influence the charge current; constant current loop (CC), constant voltage loop (CV), thermal regulation loop, minimum system voltage loop (MINSYS), input current limit and VIN-DPM. During the charging process, all six loops are enabled and the one that is dominant takes control. The minimum system output feature regulates the system voltage to VSYSREG(LO), so that startup is enabled even for a missing or deeply discharged battery. Figure 24 shows a typical charge profile including the minimum system output voltage feature. Precharge Phase Current Regulation Phase Voltage Regulation Phase Regulation Voltage Regulation Current System Voltage VSYS (3.6V) VBATSHORT (2.0V) Battery Voltage Charge Current Termination IBATSHORT 50mA Linear Charge to Close Pack Protector Linear Charge to Maintain Minimum System Voltage Battery FET (Q3) is ON Battery FET is OFF Figure 24. Typical Charging Profile of bq2426x with Termination Enabled Battery Charging Process When the battery is deeply discharged or shorted, the bq2426x applies a IBATSHRT current to close the battery protector switch and bring the battery voltage up to acceptable charging levels. During this time, the battery FET is off and the system output is regulated to VSYSREG(LO). Once the battery rises above VBATSHRT, the charge current is regulated to the value set in the I2C register. The battery FET is linearly regulated to maintain the system voltage at VSYSREG(LO). Under normal conditions, the time spent in this region is a very short percentage of the total charging time, so the linear regulation of the charge current does not affect the overall charging efficiency for very long. If the die temperature does heat up, the thermal regulation loop reduces the input current to maintain a die temperature at 125°C. If the current limit for the SYS output is reached (limited by the input current limit, VIN-DPM, or 100% duty cycle), the SYS output drops to the VMINSYS output voltage. When this happens, the charge current is reduced to ensure the system is supplied with all the current that is needed while maintaining the minimum system voltage. If the charge current is reduced to 0mA, pulling further current from SYS causes the output to fall to the battery voltage and enter supplement mode (see the “Dynamic Power Path Management” section for more details). 18 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 Once the battery is charged enough that the system voltage rises above VSYSREG(LO) (approximately 3.5V), the battery FET is turned on fully and the battery is charged with the full programmed charge current set by the I2C interface, ICHARGE. The charge current is regulated to ICHARGE until the voltage between BAT and PGND reaches the regulation voltage. The voltage between BAT and PGND is regulated to VBATREG (CV mode) while the charge current naturally tapers down as shown in Figure 24. During CV mode, the SYS output remains connected to the battery. The impedance of the battery FET is increased to 4x of the fully on value when IBAT falls below ~350mA to provide increased accuracy during termination. This will show a small rise in the SYS voltage when the RDSON increases below ~350mA. When termination is enabled (TE bit is '1'), the bq2426x monitors the charging current during the CV mode. Once the charge current tapers down to the termination threshold, ITERM, and the battery voltage is above the recharge threshold, the bq2426x terminates charge, turns off the battery charging FET and enters battery detection (see Battery Detection section for more details). The system output is regulated to the VSYSREG(HI) and supports the full current available from the input. The battery supplement mode is available to supply any SYS load that cannot be supported by the input source (see the “Dynamic Power Path Management” section for more details). The termination current level is programmable. To disable the charge current termination, the host sets the charge termination bit (TE) of charge control register to 0. Refer to I2C section for details. When termination is disabled, VBAT is continuously regulated to VBATREG. Termination is also disabled when any loop is active other than CC or CV. This includes VINDPM, input current limit, or thermal regulation. Termination is also disabled during TS warm/cool conditions and when the LOW_CHG bit is set to '1'. A charge cycle is initiated when one of the following conditions is detected: 1. The battery voltage falls below the VBATREG-VRCH threshold. 2. IN Power-on reset (POR) 3. CE bit toggle or RESET bit is set (Host controlled) 4. CD pin is toggled Charge Time Optimizer The CC to CV transition is enhanced in the bq2426x architecture. The "knee" between CC and CV is very sharp. This enables the charger to remain in CC mode as long as possible before beginning to taper the charge current (CV mode). This provides a decrease in charge time as compared to older topologies. Battery Detection When termination conditions are met, a battery detection cycle is started. During battery detection, IDETECT is pulled from VBAT for tDETECT(SNK) to verify there is a battery. If the battery voltage remains above VDETECT for the full duration of tDETECT(SNK), a battery is determined to present and the IC enters “Charge Done”. If VBAT falls below VDETECT, a “Battery Not Present” fault is signaled, the charge parameters are reset (VBATREG, ICHARGE and ITERM) and battery detection continues. The next cycle of battery detection, the bq2426x turns on IBATSHRT for tDETECT(SRC). If VBAT rises to VDET(SRC1), the current source is turned off and a “No Battery” condition is registered. In order to keep VBAT high enough to close the battery protector, the current source turns on if VBAT falls to VDET(SRC2). The source cycle continues for tDETECT(SRC). After tDETECT(SRC), the battery detection continues through another current sink cycle. Battery detection continues until charge is disabled, the bq2426x enters high-z mode or a battery is detected. Once a battery is detected, the fault status clears and a new charge cycle begins. With no battery connected, the BAT output will transition from VRCH to PGND with a high period of tDETECT(SRC) and a low period of tDETECT(SNK). See Figure 4 in the Typical Operating Characteristics. Battery detection is not performed when termination is disabled. Battery Overvoltage Protection (BOVP) If the battery is ever above the battery OVP threshold (VBOVP), the battery OVP circuit shuts the PWM converter off and the battery FET is turned on to discharge the battery to safe operating levels. A battery OVP most commonly occurs when the bq2426x returns to DEFAULT mode after a watchdog timer expiration or RESET bit written to '1'. In this condition, the VBATREG is reset and may be below the battery voltage. Other conditions may be when the input is initially plugged in before I2C communication is established or TS WARM conditions or when writing the VBATREG to less than the battery voltage. The battery OVP condition is cleared when the battery Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 19 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com voltage falls below the hysteresis of VBOVP either by the battery discharging or writing the VBATREG to a higher value. When a battery OVP event exists for tDGL(BOVP), the bq2426x turns the battery FET and BGATE on, sends a single 128μs pulse on the STAT / INT outputs and the STATx and FAULT_x bits are updated in the I2C. Once the BOVP fault is removed, the STATx bits are cleared and the device returns to normal operation. The FAULT_x bits are not cleared until they are read in the I2C after the BOVP condition no longer exists. Dynamic Power Path Management The bq2426x features a SYS output that powers the external system load connected to the battery. This output is active whenever a valid source is connected to IN or BAT. When VSYS > VSYSREG(LO), the SYS output is connected to VBAT. If the battery voltage falls to VMINSYS, VSYS is regulated to the VSYSREG(LO) threshold to maintain the system output even with a deeply discharged or absent battery. In this mode, the SYS output voltage is regulated by the buck converter and the battery FET is linearly regulated to regulate the charge current into the battery. The current from the supply is shared between charging the battery and powering the system load at SYS. The dynamic power path management (DPPM) circuitry of the bq2426x monitors the current limits continuously and if the SYS voltage falls to the VMINSYS threshold, it adjusts charge current to maintain the minimum system voltage and supply the load on SYS. If the charge current is reduced to zero and the load increases further, the bq2426x enters battery supplement mode. During supplement mode, the battery FET is turned on and VBAT = VSYS while the battery supplements the system load. 2000mA 1800mA ISYS 800mA 0mA 1500mA IIN ~850mA 0mA 1A IBAT 0mA –200mA 3.6V 3.5V DPPM loop active VSYS ~3.1V Supplement Mode Figure 25. Example DPPM Response (VSupply=5V, VBAT = 3.1V, 1.5A Input current limit) Battery Discharge FET (BGATE) The bq2426x contains a MOSFET driver to drive an external discharge FET between the battery and the system output. This external FET provides a low impedance path for supplying the system from the battery. Connect BGATE to the gate of the external discharge P-channel MOSFET. BGATE is on (low) under the following conditions: 1. No input supply connected. 2. HZ_MODE = 1 3. CD pin = 1 20 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 DEFAULT Mode DEFAULT mode is used when I2C communication is not available. DEFAULT mode is entered in the following situations: 1. When the charger is enabled and VBAT<VBATGD before I2C communication is established 2. When the watchdog timer expires without a reset from the I2C interface 3. The RESET bit is written in the I2C register In DEFAULT mode, the I2C registers are reset to the default values. The 2 minute safety timer is reset and starts when DEFAULT mode is entered if a charge cycle is underway. The default value for VBATREG is 3.6V for the BQ24260/1 and 4.2V for the bq24262A. The default value for ICHARGE is 1A. For the bq24260, the input current limit is determined by the D+/D– detection (See D+/D– Based Adapter Detection section). For the bq24261 and bq24262A, the input current limit in DEFAULT mode is set by PSEL. (See Power Source Selector Input section) DEFAULT mode is exited by writing to the I2C interface. Note that if termination is enabled and charging has terminated, a new charge cycle is NOT initiated when entering DEFAULT mode. Good Battery Monitor The bq2426x contains a good battery monitor circuit that places the bq2426x into high-z mode if the battery voltage is above the VBATGD threshold while in DEFAULT mode. This function is used to enable compliance to the battery charging standard that prevents charging from an un-enumerated USB host while the battery is above the good battery threshold. If the bq2426x is in HOST mode, it is assumed that USB host has been enumerated and the good battery circuit has no effect on charging. Any write to the i2c places the bq2426x in HOST mode and clears the high-impedance mode condition. The HZ_MODE bit is not updated during this condition. D+/D– Based Adapter Detection (D+/D–, bq24260 only) The bq24260 contains a D+/D- based adapter detection circuit that is used to program the input current limit for the input during DEFAULT mode. D+/D- is only performed in DEFAULT mode unless forced by the D+/D-_EN bit in host mode. By default the input current limit is set to 100mA. During DEFAULT mode, when the input source is connected, the bq24260 performs an adapter detection to determine if it is connected to a USB port or dedicated charger. The adapter detection starts with a connection detection as described in the USB Battery Charging Specification ver 1.2 (BC1.2). Once a connection is detected, the adapter detection is performed. If a connection is not detected within 500ms, the adapter detection begins. The adapter detection runs as described in BC1.2. If a CDP/DCP is detected, the input current limit is increased to 1.5A. If an SDP is detected, the current limit remains at 100mA, until changed in the I2C. D+/D- is initiated at any time by the host by setting the D+/D- EN bit in the I2C to 1. After detection is complete the D+/D- EN bit is automatically reset to 0 and the detection circuitry is disconnected from the D+ D- pins to avoid interference with USB data transfer. When a command is written to change the input current limit in the I2C, this overrides the current limit selected by D+/D- detection. Power Source Selector Input (PSEL, bq24261/2 only) The bq24261/2 contains a PSEL input that is used to program the input current limit during DEFAULT mode. Drive PSEL high to indicate a USB source is connected to the input and program the 100mA (bq24261) or 500mA (bq24262A) current limit for IN. Drive PSEL low to indicate that an AC Adapter is connected to the input. When PSEL is low, the IC starts up with a 1.5A input current limit. Once an I2C write is done and the device is in HOST mode, the PSEL has no effect on the input current limit until the watchdog timer expires and returns the bq2426x to DEFAULT mode. Safety Timer and Watchdog Timer in Charge Mode (bq24260/1 only) At the beginning of charging process, the bq24260/1 starts the safety timer. This timer is active during the entire charging process. If charging has not terminated before the safety timer expires, the IC enters suspend mode where charging is disabled. When a safety timer fault occurs, a single 128μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I2C. The CE bit, Hi-Z mode, or power must be toggled in order to clear the safety timer fault. The safety timer duration is selectable using the TMR_X bits in the Safety Timer Register/ NTC Monitor register. When the safety timer is active, changing the Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 21 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com safety timer duration resets the safety timer. The bq2426x also contains a 2X_TIMER bit that enables the 2x timer function to prevent premature safety timer expiration when the charge current is reduced by a load on SYS or a NTC condition. When 2X_TIMER is enabled, the timer runs at half speed when any loop is active other than CC or CV. This includes VINDPM, input current limit, or thermal regulation. The timer also runs at half speed during TS warm/cool conditions and when the LOW_CHG bit is set to '1'. In addition to the safety timer, the bq24260/1 contains a 30-second (tWATCHDOG) watchdog timer that monitors the host through the I2C interface. Once a write is performed on the I2C interface, a watchdog timer is started. The watchdog timer is reset by the host using the I2C interface. This is done by writing a “1” to the reset bit (TMR_RST) in the control register. The TMR_RST bit is automatically set to “0” when the watchdog timer is reset. This process must continue as long as the input is connected in order to maintain the register contents. If the watchdog timer expires, the IC enters DEFAULT mode where the default register values are loaded, the safety timer restarts at 2 minutes once charging continues. The I2C may be accessed again to reinitialize the desired values and restart the watchdog timer. The watchdog timer flow chart is shown in Figure 26. Start Safety Timer Yes Safety timer expired? Safety timer fault No Charging suspended Enter suspended mode Fault indicated in STAT registers STAT = Hi Update STAT bits Yes Charge Done? ICHG < ITERM No No 2 I C Write performed? Yes Start watchdog timer Charge Done? ICHG < ITERM Reset watchdog timer STAT = Hi Update STAT bits Yes No Yes Safety timer expired? Safety timer fault No Charging suspended Enter suspended mode Fault indicated in STAT registers WD timer expired? Yes No Yes Received software watchdog RESET? No Reset to default 2 values in I C register Restart 2 min safety timer Figure 26. The Watchdog Timer Flow Chart for bq24260 22 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 LDO Output (DRV) The bq24260 contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and other circuitry. Additionally, DRV supplies up to 10mA external loads to power the STAT LED or the USB transceiver circuitry. The maximum value of the DRV output is 5.3V so it ideal to protect voltage sensitive USB circuits. The LDO is on whenever a supply is connected to the input of the bq24260. The DRV is disabled under the following conditions: 1. VSUPPLY < UVLO 2. VSUPPLY < VBAT + VSLP 3. Thermal Shutdown External NTC Monitoring (TS) The I2C interface allows the user to easily implement the JEITA standard for systems where the battery pack thermistor is monitored by the host. Additionally, the bq24260 provides a flexible, voltage based TS input for monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a safe temperature during charging. The JEITA specification is shown in Figure 27. 1.0 C Charging Current 0.5 C Portion of spec not covered by TS Implementation on bq2426x 4.25 V VBAT 4.15 V 4.1 V T1 (0°C) T2 (10°C) T3 T4 (45°C) (50°C) Cold Cool Warm T5 (60°C) Hot Figure 27. Charge Current During TS Conditions To satisfy the JEITA requirements, four temperature thresholds are monitored; the cold battery threshold (TNTC < 0°C), the cool battery threshold (0°C < TNTC < 10°C), the warm battery threshold (45°C < TNTC < 60°C) and the hot battery threshold (TNTC > 60°C). These temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOT thresholds in the EC table. Charging is suspended and timers are suspended when VTS < VHOT or VTS > VCOLD. When VCOOL < VTS < VCOLD, the charging current is reduced to half of the programmed charge current. When VHOT < VTS < VWARM, the battery regulation voltage is reduced by 140mV from the programmed regulation threshold. The TS function is disabled by connecting TS directly to DRV (VTS > VTSOFF). The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TS connected to the center tap to set the threshold. The connections are shown in Figure 28. The resistor values are calculated using the following equations: Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 23 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com é 1 1 ù VDRV ´ RCOLD ´ RHOT ´ ê ú V V HOT û ë COLD RLO = éV ù é V ù RHOT ´ ê DRV - 1ú - RCOLD ´ ê DRV - 1ú ë VHOT û ë VCOLD û (1) VDRV -1 VCOLD RHI = 1 1 + RLO RCOLD (2) Where: VCOLD = 0.60 × VDRV VHOT = 0.30 × VDRV RLO ´ RHI ´ 0.564 RCOOL = RLO - RLO ´ 0.564 - RHI ´ 0.564 RLO ´ RHI ´ 0.383 RWARM = RLO - RLO ´ 0.383 - RHI ´ 0.383 (3) (4) Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold temperature. The WARM and COOL thresholds are not independently programmable. The COOL and WARM NTC resistances for a selected resistor divider are calculated using Equation 3 and Equation 4. DISABLE VBATREG – 140 mV 1 x Charge/ 0.5 x Charge VDRV TS COLD TS COOL + + TS WARM + VDRV TS HOT RHI + TS TEMP PACK+ bq2426x RLO PACK– Figure 28. TS Circuit 24 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 Thermal Regulation and Protection During the charging process, to prevent overheating in the chip, bq2426x monitors the junction temperature, TJ, of the die and reduces the input current once TJ reaches the thermal regulation threshold, TREG. The input current is reduced to zero when the junction temperature increases about 10°C above TREG. Once the input current is reduced to 0, the system current is reduced while the battery supplements the load to supply the system. When the input current is completely reduced to 0 and TJ>125°C, this is may cause a thermal shutdown of the bq2426x if the die temperature rises too high. At any state, if TJ exceeds TSHTDWN, bq24260 stops charging and disables the buck converter. During thermal shutdown mode, PWM is turned off, all timers are suspended, and a single 128μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I2C. The charge cycle resumes when TJ falls below TSHTDWN by approximately 10°C. Charge Status Outputs (STAT, INT) The STAT/INT output is used to indicate operation conditions for bq2426x. STAT/INT is pulled low during charging when EN_STAT bit in the control register is set to “1”. When charge is complete or disabled, STAT/INT is high impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of STAT/INT during different operation conditions is summarized in Table 1. STAT/INT drives an LED for visual indication or can be connected to the logic rail for host communication. The EN_STAT bit in the control register is used to enable/disable the charge status for STAT/INT. The interrupt pulses are unaffected by EN_STAT and will always be shown. Table 1. STAT Pin Summary CHARGE STATE STAT and INT BEHAVIOR Charge in progress and EN_STAT=1 Low Other normal conditions High-Impedance Charge mode faults: Timer faults, sleep mode, VIN over voltage, VIN < UVLO or Sleep mode, BOVP, thermal shutdown, No Battery and Battery Temperature faults 128-µs pulse, then High Impedance Boost Mode Operation In HOST mode, when the operation mode bit (BOOST_EN) in the control register is set to 1, bq2426x operates in boost mode and delivers 5V to IN to supply USB OTG devices connected to the USB connector. Boost operation can start with VBAT between 3.45V to 4.5V, and will maintain boost output until VBAT falls to 3.3V. IN supplies up to 1A to power these devices. It is not recommended to operate boost mode when the battery voltage is less than 3.3V. Proper operation is not guaranteed. Chip Disable Input During Boost Mode (CD) The bq2426x contains a CD input that is used to disable the IC and place the bq2426x into high-impedance mode. CD must be low to enter boost mode. Driving CD high during boost mode places the bq2426x into high-z mode and resets the BOOST_EN bit in the I2C. When CD is high, the buck converter is off, and the battery FET and BGATE are turned on. CD is internally pulled down to GND with a 100kΩ resistor. PWM Controller in Boost Mode Similar to charge mode operation, in boost mode the IC switches at 1.5MHz to regulate the voltage at IN to 5V. The voltage control loop is internally compensated to provide enough phase margin for stable operation with the full battery voltage range and up to 1A. In boost mode, the cycle-by-cycle current limit is set to 4A or 2A (depending on the I2C setting) to provide protection against short circuit conditions. If the cycle-by-cycle current limit is active for 8ms, an overload condition is detected and the device exits boost mode, and signals an over-current fault. Additionally, discharge current limit (ILIM(DISCHG)) is active to protect the battery from overload. Synchronous operation and burst mode are used to maximize efficiency over the full load range. The bq2426x will not enter boost mode unless the IN voltage is less than the UVLO. When the boost function is enabled, the bq2426x enters a linear mode to bring IN up to the battery voltage. Once VIN > (VBAT – 1V), the bq2426x begins switching and regulates IN up to 5V. If VIN does not rise to within 1V of VBAT within 8ms, an over-current event is detected and boost mode is exited and a boost mode over-current event is announced, the BOOST_EN bit is reset to ‘0’ and the STAT_x and FAULT_x bits in the Status/ Control register are updated. Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 25 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com Burst Mode during Light Load In boost mode, the IC operates using burst mode to improve light load efficiency and reduce power loss. During boost mode, the PWM converter is turned off when the device reaches minimum duty cycle and the output voltage rises to VBURST(ENT) threshold. This corresponds to approximately a 75mA inductor current. The converter then restarts when VIN falls to VBURST(EXT). See Figure TBD in the Typical Operating Characteristics for an example waveform. Watchdog Timer in Boost Mode During boost mode, the watchdog timer is active. The watchdog timer works the same as in charge mode. Write a “1” to the TMR_RST reset bit in the control register. If the watchdog timer expires, the IC resets the EN_BOOST bit to 0, signals the fault pulse on the STAT and INT pins. The FAULT_x bits read "Low Supply Fault" as this is a higher priority fault than the WD timer. STAT/ INT During Boost Mode During boost mode, the STAT and INT outputs are high impedance. Under fault conditions, a 128µs pulse is sent out to notify the host of the error condition. Protection in Boost Mode Output Over-Voltage Protection The bq2426x contains integrated over-voltage protection on the IN pin. During boost mode, if an overvoltage condition is detected (VIN > VBOOSTOVP), after deglitch tDGL(BOOST_OVP), the IC turns off the PWM converter, resets EN_BOOST bit to 0, sets fault status bits and sends out a fault pulse on STAT and INT. The converter does not restart when VIN drops to the normal level until the EN_BOOST bit is reset to 1. Output Over-Current Protection The bq2426x contains over current protection to prevent the device and battery damage when IN is overloaded. When an over-current condition occurs, the cycle-by-cycle current limit limits the current from the battery to the load. If the overload condition lasts for 8ms, the overload fault is detected. When an overload condition is detected, the bq2426x turns off the PWM converter, resets EN_BOOST bit to 0, sets the fault status bits and sends out the fault pulse on STAT and INT. The boost operation starts only after the fault is cleared and the EN_BOOST bit is reset to 1 using the I2C. Battery Voltage Protection During boost mode, when the battery voltage is below the minimum battery voltage threshold, VBATUVLO, the IC turns off the PWM converter, resets EN_BOOST bit to 0, sets fault status bits and sends out a fault pulse on STAT and INT. Once the battery voltage returns to the acceptable level, the boost starts only after the EN_BOOST bit is set to 1. Proper operation below 3.3V down to the VBATUVLOis not guaranteed. Serial Interface Description The bq24260 uses an I2C compatible interface to program charge parameters. I2C ™ is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor, see I2C-Bus Specification, Version 5, October 2012). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The bq2426x device works as a slave and supports the following data transfer modes, as defined in the I2C Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. The I2C circuitry is powered from IN when a supply is connected. If the IN supply is not connected, the I2C circuitry is powered from the battery through BAT. The battery voltage must stay above VBATUVLO with no input connected in order to maintain proper operation. 26 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the F/S-mode in this document. The bq24260/1/2 device only supports 7-bit addressing. The device 7-bit address is defined as ‘1101011’ (0x6Bh). To avoid I2C hang-ups, a timer (tI2CRESET) runs during I2C transactions. If the transaction takes longer than tI2CRESET, any additional commands are ignored and the I2C engine is reset. The timeout is reset with START and repeated START conditions and stops when a valid STOP condition is sent. F/S Mode Protocol The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 29. All I2C -compatible devices should recognize a start condition. DATA CLK S P START Condition STOP Condition Figure 29. START and STOP Condition The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 30). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 31Figure 11) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established. DATA CLK Data Line Stable; Data Valid Change of Data Allowed Figure 30. Bit Transfer on the Serial Interface The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the slave (R/W bit 1. In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 29). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the slave I2C logic from remaining in a incorrect state. Attempting to read data from register addresses not listed in this section will result in 0xFFh being read out. Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 27 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 9 8 2 Clock Pulse for Acknowledgement START Condition Figure 31. Acknowledge on the I2C Bus Recognize START or REPEATED START Condition Recognize STOP or REPEATED START Condition Generate ACKNOWLEDGE Signal P SDA Acknowledgement Signal From Slave MSB Sr Address R/W SCL S or Sr ACK ACK Sr or P Figure 32. Bus Protocol 28 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 Register Description Status/Control Register (READ/WRITE) Memory location: 00, Reset state: 00xx 0xxx BIT NAME READ/WRITE FUNCTION B7(MSB) TMR_RST Read/Write Write: TMR_RST function, write “1” to reset the watchdog timer (auto clear) Read: Always 0 (bq24260/1 only) B6 EN_BOOST Read/Write 0-Charger Mode 1-Boost Mode (default 0) B5 STAT_1 Read only B4 STAT_0 Read only 00-Ready 01-Charge in progress 10-Charge done 11-Fault B3 EN_SHIPMODE Read/Write 0-Normal Operation 1-Ship Mode Enabled (default 0) B2 FAULT_2 Read only B1 FAULT_1 Read only B0(LSB) FAULT_0 Read only 000-Normal 001-VIN > VOVP or Boost Mode OVP 010- Low Supply connected (VIN<VUVLO or VIN<VSLP) or Boost Mode Overcurrent 011- Thermal Shutdown 100-Battery Temperature Fault 101- Timer Fault (watchdog or safety timer) 110-Battery OVP 111-No Battery connected EN_BOOST Bit (Operation Mode) The EN_BOOST bit selects the operation mode for the bq2426x. Write a “1” to enable boost mode and regulate IN to 5V to supply OTG peripherals. See “Boost Mode Operation” section for more details. EN_SHIPMODE Bit Writing the EN_SHIPMODE bit to a “1” latches off the IC, battery FET and BGATE until a high to low transition on UVLO occurs. This means that if EN_SHIPMODE is written to a “1” while the input is connected, it must first be removed and then replaced before the battery FET turns on. This allows the end product with no load on the battery and the end user will enable the device by plugging it into the adapter. The EN_SHIPMODE bit can be cleared using the I2C interface as well. Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 29 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com Control Register (READ/WRITE) Memory location: 01, Reset state: 1xxx 1100 (bq24260/2), 1xxx 1110 (bq24261) BIT NAME READ/WRITE B7(MSB) RESET Write only Write: 1-Reset all registers to default values 0-No effect Read: always get “1” B6 IN_LIMIT_2 Read/Write B5 IN_LIMIT_1 Read/Write B4 IN_LIMIT _0 Read/Write 000-USB2.0 host with 100mA current limit 001-USB3.0 host with 150mA current limit 010 – USB2.0 host with 500mA current limit 011 – USB3.0 host/charger with 900mA current limit 100 – Charger with 1500mA current limit 101—Charger with 1950mA current limit 110 – Charger with 2500mA current limit 111- Charger with 2000mA current limit (default 000 (1)) B3 EN_STAT Read/Write 0-Disable STAT function (STAT only shows faults) 1-Enable STAT function (default 1) B2 TE Read/Write 0-Disable charge current termination 1-Enable charge current termination (default 1) B1 CE Read/Write 0-Charger enabled 1-Charger is disabled (default 0-bq24260 / 2, 1-bq24261) B0(LSB) HZ_MODE Read/Write 0-Not high impedance mode 1-High impedance mode (default 0) (1) FUNCTION When in DEFAULT mode, the PSEL (bq24261/2) determine the default input current limit. RESET Bit The RESET bit in the control register (0x01h) is used to reset all the charge parameters. Write “1” to RESET bit to reset all the registers to default values and place the bq2426x into DEFAULT mode and turn off the watchdog timer. The RESET bit is automatically cleared to zero once the bq2426x enters DEFAULT mode. CE Bit (Charge Enable) The CE bit is used to disable or enable the charge process. A low logic level (0) on this bit enables the charge and a high logic level (1) disables the charge. When charge is disabled, the SYS output regulates to VSYS(REG) and battery is disconnected from the SYS. Supplement mode is available if the system load demands cannot be met by the supply. HZ_MODE Bit (High Impedance Mode Enable) The HZ_MODE bit is used to disable or enable the high impedance mode. A low logic level (0) on this bit enables the IC and a high logic level (1) puts the IC in a low quiescent current state called high impedance mode. When in high impedance mode, the converter is off and the battery FET and BGATE are on. The load on SYS is supplied by the battery. BGATE is low (external FET turned on) while in high impedance mode. 30 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 Control/Battery Voltage Register (READ/WRITE) Memory location: 02, Reset state: 0001 0100 (BQ24260/1), 1000 1100 (bq24262A) BIT NAME READ/WRITE B7(MSB) VBREG5 Read/Write Battery Regulation Voltage: 640mV (default 0) FUNCTION B6 VBREG4 Read/Write Battery Regulation Voltage: 320mV (default 0) B5 VBREG3 Read/Write Battery Regulation Voltage: 160mV (default 0) B4 VBREG2 Read/Write Battery Regulation Voltage: 80mV (default 1) B3 VBREG1 Read/Write Battery Regulation Voltage: 40mV (default 0) B2 VBREG0 Read/Write Battery Regulation Voltage: 20mV (default 1) B1 MOD_FREQ1 Read/Write B0(LSB) MOD_FREQ0 Read/Write Modify Switching Frequency Target – 00 – No Change to Nominal Frequency Target 01 – +10% Change to Nominal Frequency 10 – -10% Change to Nominal Frequency 11 – NA (default 00) VBREG Bits (Battery Regulation Threshold setting) Use VBREG bits to set the battery regulation threshold. The VBATREG is calculated using the following equation: indent VBATREG = 3.5 V + VBREGCODE × 20 mV The charge voltage range is 3.5V to 4.44V with the offset of 3.5V and step of 20mV. The default setting is 3.6V for the BQ24260 and BQ24261. The default setting is 4.2V for the bq24262A. If a value greater than 4.44V is written, the setting goes to 4.44V. It is recommended to set VBATREG above VMINSYS. MOD_FREQx Bits (Frequency Modification) The MOD_FREQx bits are used to change the switching frequency by ±10%. This is used for applications where the 1.5MHz switching frequency noise interferes with other device operation. The frequency may be modified by ±10% of the nominal frequency. Vender/Part/Revision Register (READ only) Memory location: 03, Reset state: 0100 0010 (bq24262A), 0100 0110 (BQ24260/1) BIT NAME READ/WRITE B7(MSB) Vendor2 Read only Vender Code: bit 2 (default 0) FUNCTION B6 Vendor1 Read only Vender Code: bit 1 (default 1) B5 Vendor0 Read only Vender Code: bit 0 (default 0) B4 PN1 Read only For I2C Address 6Bh: 00 – bq24260 B3 PN0 Read only B2 NA Read only NA B1 NA Read only NA B0(LSB) NA Read only NA Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 31 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com Battery Termination/Fast Charge Current Register (READ/WRITE) Memory location: 04, Reset state: 0010 1010 BIT NAME READ/WRITE B7(MSB) ICHRG4 Read/Write Charge current 1600mA – (default 0) FUNCTION B6 ICHRG3 Read/Write Charge current: 800mA — (default 0) B5 ICHRG2 Read/Write Charge current: 400mA —(default 1) B4 ICHRG1 Read/Write Charge current: 200mA — (default 0) B3 ICHRG0 Read/Write Charge current: 100mA (default 1) B2 ITERM2 Read/Write Termination current sense: 200mA (default 0) B1 ITERM1 Read/Write Termination current sense voltage: 100mA (default 1) B0(LSB) ITERM0 Read/Write Termination current sense voltage: 50mA (default 0) ICHRG Bits (Charge Current Regulation Threshold setting) Use ICHRG bits to set the charge current regulation threshold. The charge current is programmable from 500mA to 3A in 100mA steps. The default is 1A. The ICHARGE is calculated using the following equation: indentICHARGE = 500 mA + ICHRGCODE × 100 mA Any setting programmed above 3A selects the 3A setting. ITERM Bits (Charge Current Termination Threshold setting) Use ITERM bits to set the charge current termination threshold. The termination threshold is programmable from 50mA to 300mA in 50mA steps. The default is 150mA. The ITERM is calculated using the following equation: indentITERM = 50 mA + ITERMCODE × 50 mA Any setting programmed above 300mA selects the 300mA setting. 32 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 VIN-DPM Voltage/ MINSYS Status Register Memory location: 05, Reset state: xx00 x000 • BIT NAME READ/WRITE B7(MSB) MINSYS_STATUS Read only 0 – Minimum System Voltage mode is not active 1 – Minimum System Voltage mode is active (low battery FUNCTION B6 VINDPM_STATUS Read only 0 – VIN-DPM mode is not active 1 – VIN-DPM mode is active B5 LOW_CHG Read/Write 0 – Normal charge current set by 04h 1 – Low charge current setting 300mA (default 0) B4 D+/D– EN Read/Write 0 – Bit returns to 0 after D+/D- detection is performed 1 – Force D+/D- detection (bq24260 only, default 0) B3 CD_STATUS Read Only 0 – CD low, IC enabled 1 – CD high, IC disabled B2 VINDPM2 Read/Write Input VIN-DPM voltage: VDPMOFF + 8% (default 0) B1 VINDPM1 Read/Write Input VIN-DPM voltage: VDPMOFF + 4% (default 0) B0(LSB) VINDPM0 Read/Write Input VIN-DPM voltage: VDPMOFF + 2% (default 0) VIN-DPM voltage offset is programmable using the VINDPM_OFF bit (bit 0 of register 0x06) and default VIN-DPM threshold is 4.2V. LOW_CHG Bit (Low Charge Mode Enable) The LOW_CHG bit is used to reduce the charge current to a minimum current. This feature is used by systems where battery NTC is monitored by the host and requires a reduced charge current setting or by systems that need a “preconditioning” current for low battery voltages. Write a “1” to this bit to charge at 300mA. Write a “0” to this bit to charge at the programmed charge current. VINDPM Bits (VINDPM Threshold setting) Use VINDPM bits to set the VINDPM regulation threshold. The VINDPM threshold is calculated using the following equation: indentVINDPM = VINDPM_OFF + VINDPMCODE × 2% × VINDPM_OFF Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 33 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com Safety Timer/ NTC Monitor Register (READ/WRITE) Memory location: 06, Reset state: 1001 1xx0 BIT NAME READ/WRITE B7(MSB) 2XTMR_EN Read/Write 0 – Timer not slowed at any time 1 – Timer slowed by 2x when in thermal regulation, VIN_DPM or input current limit (default 1) FUNCTION B6 TMR_1 Read/Write B5 TMR_2 Read/Write Safety Timer Time Limit – 00 – 1.25 minute fast charge 01 – 6 hour fast charge 10 – 9 hour fast charge 11 – Disable safety timers (default 00) (bq24260/1 only) B4 BOOST_ILIM Read/Write 0 – 500mA 1 – 1A (Default 1) B3 TS_EN Read/Write 0 – TS function disabled 1 – TS function enabled (default 1) B2 TS_FAULT1 Read only B1 TS_FAULT0 Read only TS Fault Mode: 00 – Normal, No TS fault 01 – TS temp < TCOLD or TS temp > THOT(Charging suspended) 10 – TCOOL > TS temp > TCOLD (Charge current reduced by half) 11 – TWARM < TS temp < THOT (Charge voltage reduced by 100mV) B0(LSB) VINDPM_OFF Read/Write 0 – 4.2V 1 – 10.1V (Default 0) BOOST_ILIM Bit (Boost current limit setting) The BOOST_ILIM bit programs the cycle by cycle current limit threshold for boost operation. The 1A setting sets the low side cycle by cycle current limit to 4A (typ). This ensures that at least 1A can be supplied from the boost converter over the entire battery range. The 500mA setting sets the current limit to 2A(typ) to ensure at least 500mA available from the boost converter. See the boost mode over-current section for more details. VINDPM_OFF Bit (VINDPM offset setting) The VINDPM_OFF bit programs the offset for the VINDPM function. The 4.2V setting is intended to work with a standard 5V output adapter. The 10.1V setting supports 12V adapters and the 12V output for the new USB Power Delivery specification (USB PD). 34 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 APPLICATION INFORMATION Output Inductor and Capacitor Selection Guidelines When selecting an inductor, several attributes must be examined to find the right part for the application. First, the inductance value should be selected. The bq2426x is designed to work with 1.5µH to 2.2µH inductors. The chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some efficiency gain is reached using the 2.2µH inductor, however, due to the physical size of the inductor, this may not be a viable option. The 1.5µH inductor provides a good tradeoff between size and efficiency. Once the inductance has been selected, the peak current must be calculated in order to choose the current rating of the inductor. Use Equation 5 to calculate the peak current. æ % ö IPEAK = ILOAD(MAX) ´ ç 1 + RIPPPLE ÷ 2 è ø (5) The inductor selected must have a saturation current rating greater than or equal to the calculated IPEAK. Due to the high currents possible with the bq2426x, a thermal analysis must also be done for the inductor. Many inductors have 40°C temperature rise rating. This is the DC current that will cause a 40°C temperature rise above the ambient temperature in the inductor. For this analysis, the typical load current may be used adjusted for the duty cycle of the load transients. For example, if the application requires a 1.5A DC load with peaks at 2.5A 20% of the time, a Δ40°C temperature rise current must be greater than 1.7A: ITEMPRISE = ILOAD + D × (IPEAK – ILOAD) = 1.5 A + 0.2 × (2.5 A – 1.5 A) = 1.7 A The bq2426x’s internal loop compensation is designed to be stable with 10µF to 150µF of local capacitance but requires at least 20µF total capacitance on the SYS rail (10µF local + ≥10µF distributed). The capacitance on the SYS rail can be higher than 150µF if distributed amongst the rail. To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 10µF and 47µF is recommended for local bypass to SYS. If greater than 100µF effective capacitance is on the SYS rail, place at least 10µF bypass on the BAT pin. Pay special attention to the DC bias characteristics of ceramic capacitors. For small case sizes, the capacitance can be derated as high as 70% at workable voltages. All capacitances specified in this datasheet are effective capacitance, not capacitor value. Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 35 bq24260 bq24261 bq24262A SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com PCB Layout Guidelines It is important to pay special attention to the PCB layout. Figure 33 provides a sample layout for the high current paths of the bq2426xYFF. Figure 34 provides a sample layout for the high current paths of the bq2426xRGE. PMID PMID and IN Cap Gnds Close together PGND IN Cap Close to IN Pin SW BOOT Thermal SYS Cap Close to Vias connect To PGND SYS Pins BAT Cap Close to BAT Pins Figure 33. Recommended bq2426x PCB Layout for WCSP Package sp PGND SW PMID PMID and IN Cap Gnds BOOT Close together SYS Cap IN Cap Close to Close to SYS Pins IN Pin BAT Cap Thermal Close to Vias connect BAT Pins To GND Figure 34. Recommended bq2426x PCB Layout for QFN Package 36 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 The following provides some guidelines: • Place 1µF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current loop area as small as possible. • Connect the GND of the PMID and IN caps as close as possible. • Place 4.7µF input capacitor as close to IN pin and PGND pin as possible to make high frequency current loop area as small as possible. • The local bypass capacitor from SYS to GND should be connected between the SYS pin and PGND of the IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the PGND pin. • Place all decoupling capacitors close to their respective IC pin and as close as to PGND as possible. Do not place components such that routing interrupts power stage currents. All small control signals should be routed away from the high current paths. • The PCB should have a ground plane (return) connected directly to the return of all components through vias. Two vias per capacitor for power-stage capacitors and one via per capacitor for small-signal components. It is also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noisecoupling and ground-bounce issues. A single ground plane for this design gives good results. • The high-current charge paths into IN, BAT, SYS and from the SW pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be connected to the ground plane to return current through the internal low-side FET. • For high-current applications, the balls for the power paths should be connected to as much copper in the board as possible. This allows better thermal performance as the board pulls heat away from the IC. spacer REVISION HISTORY Changes from Original (December 2013) to Revision A Page • Deleted "PREVIEW" from the bq24261RGE device in the Ordering Info table. ................................................................... 2 • Added specifications to Electrical Characteristics table pertaining to RGE package. .......................................................... 4 • Added separate lines for IINLIM current for YFF and RGE packages. ................................................................................... 5 • Changed VDO_DRV spec MAX voltage from "500 mV" to "450 mV" ....................................................................................... 5 • Changed VIN to VIN in the Input Over-Voltage Protection section. ...................................................................................... 17 • Changed text string in Battery Charging Process section from " IBATSHORT" to " IBATSHRT" for clarification. ......................... 18 • Changed several device references from "bq24260" to "bq2426x" in the Detailed Description section. ........................... 20 • Changed the wording of the Safety Timer description for clarification. .............................................................................. 22 • Changed text in the F/S Mode Protocol section from "...to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0" to "...to either transmit data to the slave (R/W bit 0) or receive data from the slave (R/W bit 1" for clarification. ................................................................................................................................................. 27 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq24260 bq24261 bq24262A Submit Documentation Feedback 37 PACKAGE OPTION ADDENDUM www.ti.com 12-Feb-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) BQ24260SYFFR PREVIEW DSBGA YFF 36 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24260S BQ24260SYFFT PREVIEW DSBGA YFF 36 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24260S BQ24261RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ24261RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ24261YFFR ACTIVE DSBGA YFF 36 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24261 BQ24261YFFT ACTIVE DSBGA YFF 36 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24261 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 12-Feb-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing BQ24260SYFFR DSBGA YFF 36 BQ24260SYFFT BQ24261RGER DSBGA YFF VQFN RGE BQ24261RGET VQFN BQ24261YFFR BQ24261YFFT SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 0 180.0 36 0 24 3000 RGE 24 DSBGA YFF DSBGA YFF B0 (mm) K0 (mm) P1 (mm) 8.4 2.54 2.54 0.76 4.0 180.0 8.4 2.54 2.54 0.76 330.0 12.4 4.25 4.25 1.15 250 180.0 12.4 4.25 4.25 36 3000 180.0 8.4 2.54 36 250 180.0 8.4 2.54 Pack Materials-Page 1 W Pin1 (mm) Quadrant 8.0 Q1 4.0 8.0 Q1 8.0 12.0 Q2 1.15 8.0 12.0 Q2 2.54 0.76 4.0 8.0 Q1 2.54 0.76 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24260SYFFR DSBGA YFF 36 0 210.0 185.0 35.0 BQ24260SYFFT DSBGA YFF 36 0 210.0 185.0 35.0 BQ24261RGER VQFN RGE 24 3000 367.0 367.0 35.0 BQ24261RGET VQFN RGE 24 250 210.0 185.0 35.0 BQ24261YFFR DSBGA YFF 36 3000 182.0 182.0 17.0 BQ24261YFFT DSBGA YFF 36 250 182.0 182.0 17.0 Pack Materials-Page 2 D: Max = 2.485 mm, Min =2.425 mm E: Max = 2.485 mm, Min =2.425 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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