TI1 LMH5401FFK/EM 6.5-ghz, low-noise, low-power, gain-configurable fully differential amplifier Datasheet

Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
LMH5401-SP
SBOS849 – DECEMBER 2017
LMH5401-SP 6.5-GHz, Low-Noise, Low-Power, Gain-Configurable
Fully Differential Amplifier
1 Features
2 Applications
•
•
•
•
•
•
•
QMLV (QML Class V) MIL-PRF-38535 Qualified,
SMD 5962-1721401VXC
– Single Event Latchup (SEL) Immune to
LET = 85 MeV-cm2/mg
– Qualified Over the Military Temperature Range
(–55°C to 125°C)
Gain Bandwidth Product (GBP): 6.5 GHz
Excellent Linearity Performance:
DC to 2 GHz;
Slew Rate: 17,500 V/µs
Low HD2, HD3 Distortion
(500 mVPP, 100 Ω, SE-DE, Gv = 17 dB)(1):
– 100 MHz: HD2 at –91 dBc, HD3 at –95 dBc
– 200 MHz: HD2 at –86 dBc, HD3 at –85 dBc
– 500 MHz: HD2 at –80 dBc, HD3 at –80 dBc
– 1 GHz: HD2 at –53 dBc, HD3 at –70 dBc
– 2 GHz: HD2 at –68 dBc, HD3 at –56 dBc
Low IMD2, IMD3 Distortion
(1 VPP, 100 Ω, SE-DE, Gv = 17 dB)(1):
– 500 MHz: IMD2 at –90 dBc, IMD3 at –79 dBc
– 1 GHz: IMD2 at –80 dBc, IMD3 at –61 dBc
– 2 GHz: IMD2 at –64 dBc, IMD3 at –42 dBc
High OIP2, OIP3. Gp = 8 dB(1)
– 500 MHz: OIP2 at 91 dBm, OIP3 at 47.7 dBm
– 1 GHz: OIP2 at 80 dBm, OIP3 at 37.5 dBm
Input Voltage Noise: 1.25 nV/√Hz
Input Current Noise: 3.5 pA/√Hz
Supports Single- and Dual-Supply Operation
Current Consumption: 60 mA
Power-Down Feature
1
•
•
•
•
•
•
•
•
•
•
•
(1)
Balun Replacement: DC to 2 GHz
GSPS ADC Drivers
DAC Buffers
IF, RF, and Baseband Gain Blocks
SAW Filter Buffers and Drivers
Level Shifters
3 Description
The LMH5401-SP is a very high-performance,
radiation hardened, differential amplifier optimized for
radio frequency (RF), intermediate frequency (IF), or
high-speed, dc-coupled, time-domain applications.
The device is ideal for dc- or ac-coupled applications
that may require a single-ended-to-differential (SEDE) conversion when driving an analog-to-digital
converter (ADC). The LMH5401-SP generates very
low levels of second- and third-order distortion when
operating in SE-DE or differential-to-differential (DEDE) mode.
Device Information(1)
PART NUMBER
GRADE
PACKAGE
5962-1721401VXC
QMLV
14-pin LCCC [FFK]
5.50 mm × 6.00 mm
LMH5401FFK\EM
Engineering
Samples
14-pin LCCC [FFK]
5.50 mm × 6.00 mm
LMH5401EVMCVAL
Ceramic Evaluation
Board
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
(2) They are processed to a noncompliant flow. These units are
not suitable for qualification, production, radiation testing or
flight use. Parts are not warranted for performance over the
full MIL specified temperature range of –55°C to 125°C or
operating life.
Power Gain (Gp) = 8 dB; Voltage Gain (Gv) = 17 dB; RLtotal =
200 Ω. See Output Reference Nodes and Gain Nomenclature
section for more details.
LMH5401-SP Small Signal Frequency Response
LMH5401-SP Driving an ADC12D1620QML
10
25
Gp = 8 dB, Gv = 17 dB
RT
Normalized Gain (dB)
5
50- ,
Single-Ended Input
RF
RG
FB+
10
IN±
OUT+
RO
±
0
+
±
LMH5401-SP
IN+
+
10
RG+RM
-5
RF
FB±
IN+
+
OUT_AMP
±
RO
Filter
ADC12D1620
IN±
OUT±
25
-10
CM
-15
-20
10
Copyright © 2017, Texas Instruments Incorporated
100
1k
Frequency (MHz)
10k
SBOS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
3
4
9
Detailed Description ............................................ 24
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
24
24
24
30
10 Application and Implementation........................ 31
10.1 Application Information.......................................... 31
10.2 Typical Application ................................................ 35
10.3 Do's and Don'ts .................................................... 44
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: VS = 5 V........................... 5
Electrical Characteristics: VS = 3.3 V........................ 7
Typical Characteristics: 5 V .................................... 10
Typical Characteristics: 3.3 V ................................. 15
11 Power Supply Recommendations ..................... 45
11.1
11.2
11.3
11.4
Supply Voltage ......................................................
Single Supply ........................................................
Split Supply ...........................................................
Supply Decoupling ................................................
45
45
45
45
12 Layout................................................................... 46
12.1 Layout Guidelines ................................................. 46
12.2 Layout Example .................................................... 46
Parameter Measurement Information ................ 19
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Output Reference Nodes and Gain Nomenclature . 19
ATE Testing and DC Measurements ...................... 20
Frequency Response .............................................. 20
S-Parameters .......................................................... 21
Frequency Response with Capacitive Load............ 21
Distortion ................................................................. 21
Noise Figure............................................................ 21
Pulse Response, Slew Rate, and Overdrive Recovery
................................................................................. 21
8.9 Power Down............................................................ 22
8.10 VCM Frequency Response .................................... 22
8.11 Test Schematics.................................................... 22
13 Device and Documentation Support ................. 47
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
47
47
47
47
48
48
48
14 Mechanical, Packaging, and Orderable
Information ........................................................... 48
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2017
*
Initial release.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
5 Description (continued)
The amplifier is optimized for use in both SE-DE and DE-DE systems. The device has unprecedented usable
bandwidth from dc to 2 GHz. The LMH5401-SP can be used for SE-DE conversions in the signal chain without
external baluns in a wide range of applications such as test and measurement, broadband communications, and
high-speed data acquisition.
A common-mode reference input pin is provided to align the amplifier output common-mode with the ADC input
requirements. Power supplies between 3.3 V and 5 V can be selected and dual-supply operation is supported
when required by the application. A power-down feature is also available for power savings.
This level of performance is achieved at a very low power level of 300 mW when a 5-V supply is used. The
device is fabricated in Texas Instruments' advanced complementary BiCMOS process and is available in a
space-saving, LCCC-14 package for higher performance.
6 Pin Configuration and Functions
FFK Package
14-Pin LCCC
Top View
VS±
CM
VS+
3
2
1
LMH5401-SP
25
FB+
4
IN±
5
±
IN+
6
+
FB±
7
14
GND
13
OUT+
12
OUT±
11
GND
10
10
25
8
9
10
VS±
PD
VS+
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CM
2
I
Input pin to set amplifier output common-mode voltage.
FB–
7
O
Negative output feedback component connection.
FB+
4
O
Positive output feedback component connection.
GND
11, 14
P
Printed circuit board (PCB) ground.
IN–
5
I
Negative input pin.
IN+
6
I
Positive input pin.
OUT–
12
O
Negative output pin.
OUT+
13
O
Positive output pin.
PD
9
I
Power-down (logic 1 = power down).
VS–
3, 8
P
Negative supply voltage.
VS+
1, 10
P
Positive supply voltage.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
3
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
MIN
MAX
Power supply
Voltage
Input voltage range
Current
(VS–) – 0.7
(VS+) + 0.7
Input current
10
Output current (sourcing or sinking) OUT+, OUT–
100
Continuous power dissipation
mA
150
Maximum junction temperature, continuous operation, long-term reliability
125
Storage, Tstg
(1)
V
See Thermal Information table
Maximum junction temperature, TJ
Temperature
UNIT
5.5
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
Supply voltage (VS = VS+ – VS–)
3.15
5
5.25
UNIT
V
Operating junction temperature, TJ
–55
125
°C
7.4 Thermal Information
LMH5401-SP
THERMAL METRIC
(1)
FFK (LCCC)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
92.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
106.2
°C/W
RθJB
Junction-to-board thermal resistance
71.9
°C/W
ψJT
Junction-to-top characterization parameter
64.8
°C/W
ψJB
Junction-to-board characterization parameter
68.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
63.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
7.5 Electrical Characteristics: VS = 5 V
The specifications shown below correspond to the respectively identified subgroup temperature (see Table 1), unless
otherwise noted. VS+ = 5.0 V; VS– = 0 V; VCM = 2.5 V; RLtotal = 200-Ω differential (1); Gp = 8 dB (Gv = 17 dB); single-ended
input, differential output, and RS = 50 Ω (unless otherwise noted) (2).
PARAMETER
TEST CONDITIONS
SUBGROUP (3)
MIN
TYP
MAX
UNIT
AC PERFORMANCE
GBP
Gain bandwidth product
Gp = 8 dB
6.5
GHz
SSBW
Small-signal, –3-dB
bandwidth
VL = 100 mVPP
4.2
GHz
LSBW
Large-signal, –3-dB
bandwidth
VL = 1.0 VPP
4.0
GHz
Bandwidth for +/- 0.5-dB
flatness
VL = 1.0 VPP
2.9
GHz
Slew rate
2-V step
17500
V/µs
Rise and fall time
1-V step, 10% to 90%
Overdrive recovery
Overdrive = ±0.5 V
300
ps
Output balance error
f = 1 GHz
–47
dBc
Output impedance
At dc, differential
0.1% settling time
2 V, RL = 200 Ω
SR
zo
Second-order harmonic
distortion
HD2
Third-order harmonic
distortion
HD3
IMD2
Second-order intermodulation
OIP2
Second-order output intercept
point
IMD3
Third-order intermodulation
OIP3
Third-order output intercept
point
80
[1, 2, 3]
13
20
ps
25
1
f = 100 MHz, VL = 1 VPP
–91
f = 200 MHz, VL = 1 VPP
–86
f = 500 MHz, VL = 1 VPP
–80
f = 1 GHz, VL = 1 VPP
–53
f = 2 GHz, VL = 1 VPP
-68
f = 100 MHz, VL = 1 VPP
–95
f = 200 MHz, VL = 1 VPP
–85
f = 500 MHz, VL = 1 VPP
–80
f = 1 GHz, VL = 1 VPP
–70
f = 2 GHz, VL = 1 VPP
-56
f = 500 MHz, VL = 1 VPP per tone
–90
f = 1 GHz, VL = 1 VPP per tone
–80
f = 2 GHz, VL = 1 VPP per tone
–64
f = 500 MHz, VL = 1 VPP, matched load
91
f = 1000 MHz, VL = 1 VPP, matched
load
80
f = 500 MHz, VL = 0.25 VPP per tone
–79
f = 1 GHz, VL = 0.25 VPP per tone
–61
f = 2 GHz, VL = 0.25 VPP per tone
–42
f = 500 MHz, VL = 1 VPP, unmatched
load
47.7
f = 1000 MHz, VL = 1 VPP, unmatched
load
37.5
Ω
ns
dBc
dBc
dBc
dBm
dBc
dBm
NOISE PERFORMANCE
en
Input voltage noise density
in
Input noise current
NF
Noise figure
RS = 50 Ω, SE-DE, 200 MHz
See Figure 53
1.25
nV/√Hz
3.5
pA/√Hz
9.6
dB
INPUT
VIO
Input offset voltage
[1, 2, 3]
±0.5
±5
mV
IIB
Input bias current
[1, 2, 3]
70
150
µA
IIO
Input offset current
[1, 2, 3]
±1
±20
µA
Differential resistance
VICL
(1)
(2)
(3)
Open-loop
Input common-mode
low voltage
4600
[1, 2, 3]
VS–
Ω
(VS–) +
0.41
V
Please see Output Reference Nodes and Gain Nomenclature.
The input resistance and corresponding gain are obtained with the external resistance added.
For subgroup definitions, please see Table 1.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
5
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
Electrical Characteristics: VS = 5 V (continued)
The specifications shown below correspond to the respectively identified subgroup temperature (see Table 1), unless
otherwise noted. VS+ = 5.0 V; VS– = 0 V; VCM = 2.5 V; RLtotal = 200-Ω differential(1); Gp = 8 dB (Gv = 17 dB); single-ended
input, differential output, and RS = 50 Ω (unless otherwise noted)(2).
PARAMETER
TEST CONDITIONS
SUBGROUP (3)
MIN
TYP
(VS+) – 1.41
(VS+) – 1.2
MAX
UNIT
VICH
Input common-mode
high voltage
CMRR
Common-mode rejection ratio
Differential, 1-VPP input shift, dc
VOCRH
Output voltage range, high
Measured single-ended
[1, 2, 3]
(VS+) – 1.3
(VS+) – 1.1
V
VOCRL
Output voltage range, low
Measured single-ended
[1, 2, 3]
(VS–) + 1.3
(VS–) + 1.1
V
VOD
Differential output voltage
swing
Differential
Differential output current
(4)
[1, 2, 3]
V
72
dBc
OUTPUT
IOD
VO = 0 V
[1, 2, 3]
40
5.8
VPP
50
mA
POWER SUPPLY
VS
Supply voltage
PSRR
Power-supply rejection ratio
IQ
Quiescent current
[1, 2, 3]
3.15
VS–
[1, 2, 3]
-44
–80
5.25
VS+
[1, 2, 3]
–48
–82
PD = 0
[1, 2, 3]
46
60
78
PD = 1
[1, 2, 3]
1
3
6
V
dB
mA
OUTPUT COMMON-MODE CONTROL PIN (VCM)
SSBW
VOCM
Small-signal bandwidth
VOCM = 100 mVPP
1.2
GHz
VCM slew rate
VOCM = 500 mVPP
2900
V/µs
VCM voltage range low
Differential gain shift < 1 dB
[1, 2, 3]
VCM voltage range high
Differential gain shift < 1 dB
[1, 2, 3]
(VS+) – 2.0
(VS+) – 1.4
VCM gain
VCM = 0 V
[1, 2, 3]
0.98
1.0
VOCM output common-mode
offset from VCM input voltage
VCM = 0 V
–27
mV
Common-mode offset voltage
Output-referred
0.4
mV
(VS–) + 1.4
(VS–) + 2.0
V
V
1.01
V/V
POWER DOWN (PD Pin)
VT
Enable or disable voltage
threshold
Device powers on below 0.8 V,
device powers down above 1.2 V
Power-down quiescent
current
(4)
6
[1, 2, 3]
0.9
1.1
1.2
[1, 2, 3]
1
3
6
mA
10
±100
µA
[1, 2, 3]
V
PD bias current
PD = 2.5 V
Turn-on time delay
Time to VO = 90% of final value
10
ns
Turn-off time delay
Time to VO = 10% of original value
10
ns
This test shorts the outputs to ground (mid supply) then sources or sinks 60 mA and measures the deviation from the initial condition.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
7.6 Electrical Characteristics: VS = 3.3 V
The specifications shown below correspond to the respectively identified subgroup temperature (see Table 1), unless
otherwise noted. VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V; RLtotal = 200-Ω differential (1); Gp = 8 dB (Gv = 17 dB); single-ended
input, differential output, and input and output referenced to midsupply (unless otherwise noted); measured using an EVM as
discussed in the Parameter Measurement Information section.
PARAMETER
TEST CONDITIONS
SUBGROUP (2)
MIN
TYP
MAX
UNIT
AC PERFORMANCE
GBP
Gain bandwidth product
Gp = 8 dB
SSBW
Small-signal, –3-dB
bandwidth
VL = 100 mVPP
LSBW
Large-signal, –3-dB
bandwidth
SR
zo
6.5
GHz
4
GHz
VL = 1 VPP
3.8
GHz
Bandwidth for ±0.5-dB
flatness
VL = 1 VPP
2.6
GHz
Slew rate
2-V step
17500
V/µs
Rise and fall time
1-V step, 10% to 90%
Overdrive recovery
Overdrive = ±0.5 V
400
ps
Output balance error
f = 1 GHz
–47
dBc
Output impedance
At dc
0.1% settling time
2 V, RL = 200 Ω
90
[1, 2, 3]
HD2
Third-order harmonic
distortion
HD3
IMD2
OIP2
IMD3
OIP3
Second-order intermodulation
distortion
Second-order output intercept
point
Third-order intermodulation
distortion
Third-order output intercept
point
20
25
1
f = 100 MHz, VL = 500 mVPP
Second-order harmonic
distortion
13
ps
Ω
ns
–93
f = 200 MHz, VL = 500 mVPP
–87
f = 500 MHz, VL = 500 mVPP
–75.2
f = 1 GHz, VL = 500 mVPP
–58
f = 100 MHz, VL = 500 m VPP
–83
f = 200 MHz, VL = 500 mVPP
–76
f = 500 MHz, VL = 500 mVPP
–59
f = 1 GHz, VL = 500 mVPP
–53
f = 500 MHz, VL = 0.25 VPP per tone
–94
f = 1 GHz, VL = 0.25 VPP per tone
–83
f = 2 GHz, VL = 0.25 VPP per tone
–68
f = 500 MHz, VL = 1 VPP, matched
load
70
f = 1000 MHz, VL = 1 VPP, matched
load
54
f = 500 MHz, VL = 0.25 VPP per tone
–74
f = 1 GHz, VL = 0.25 VPP per tone
–63
f = 2 GHz, VL = 0.25 VPP per tone
–49
dBc
dBc
dBc
dBm
f = 500 MHz, VL = 1 VPP, unmatched
load
dBc
33
dBm
f = 1000 MHz, VL = 1 VPP, unmatched
load
26.5
NOISE PERFORMANCE
en
Input voltage noise density
in
Input noise current
NF
Noise figure
RS = 50 Ω, SE-DE, G = 12 dB,
200 MHz
1.25
nV/√Hz
3.5
pA/√Hz
11.9
dB
INPUT
VIO
Input offset voltage
±0.5
±5
mV
IIB
Input bias current
70
150
µA
IIO
Input offset current
±1
±20
µA
Zid
Differential impedance
VICL
Input common-mode
low voltage
(1)
(2)
4600
[1, 2, 3]
(VS–)
Ω
(VS–) +
0.41
V
Please see Output Reference Nodes and Gain Nomenclature.
For subgroup definitions, please see Table 1.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
7
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
Electrical Characteristics: VS = 3.3 V (continued)
The specifications shown below correspond to the respectively identified subgroup temperature (see Table 1), unless
otherwise noted. VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V; RLtotal = 200-Ω differential(1); Gp = 8 dB (Gv = 17 dB); single-ended
input, differential output, and input and output referenced to midsupply (unless otherwise noted); measured using an EVM as
discussed in the Parameter Measurement Information section.
PARAMETER
TEST CONDITIONS
SUBGROUP (2)
MIN
TYP
(VS+) – 1.41
(VS+) – 1.2
MAX
UNIT
VICH
Input common-mode
high voltage
CMRR
Common-mode rejection ratio
Differential, 1-VPP input shift, dc
VOCRH
Output voltage range, high
Measured single-ended
[1, 2, 3]
(VS+) – 1.3
(VS+) – 1.1
V
VOCRL
Output voltage range, low
Measured single-ended
[1, 2, 3]
(VS–) + 1.3
(VS–) + 1.1
V
VOD
Differential output voltage
swing
Differential
Differential output current
(3)
[1, 2, 3]
V
–72
dBc
OUTPUT
IOD
VO = 0 V
[1, 2, 3]
30
2.8
VPP
40
mA
POWER SUPPLY
VS
Supply voltage
PSRR
Power-supply rejection ratio
IQ
Quiescent current
[1, 2, 3]
3.15
VS–
[1, 2, 3]
–44
–80
5.25
VS+
[1, 2, 3]
–48
–84
PD = 0
[1, 2, 3]
44
54
63
PD = 1
[1, 2, 3]
1
1.6
5
V
dB
mA
OUTPUT COMMON-MODE CONTROL PIN (VCM)
SSBW
VOCM
Small-signal bandwidth
VOCM = 200 mVPP
3
(VS–) +
1.35
GHz
(VS–) +
1.55
VCM voltage range low
Differential gain shift < 1 dB
[1, 2, 3]
V
VCM voltage range high
Differential gain shift < 1 dB
[1, 2, 3]
(VS+) – 1.55
(VS+) –
1.35
VCM gain
VCM = 0 V
[1, 2, 3]
0.98
1.0
VOCM output common-mode
offset from VCM input voltage
VCM = 0 V
–27
mV
Common-mode offset voltage
Output-referred
0.4
mV
V
1.01
V/V
POWER DOWN (PD Pin)
VT
Enable or disable voltage
threshold
Device powers on below 0.8 V,
device powers down above 1.2 V
Power-down quiescent
current
(3)
8
[1, 2, 3]
0.9
1.1
1.2
[1, 2, 3]
1
1.6
6
mA
10
±100
µA
[1, 2, 3]
V
PD bias current
PD = 2.5 V
Turn-on time delay
Time to VO = 90% of final value
10
ns
Turn-off time delay
Time to VO = 10% of original value
10
ns
This test shorts the outputs to ground (mid supply) then sources or sinks 60 mA and measures the deviation from the initial condition.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
Table 1. Quality Conformance Inspection (1)
(1)
SUBGROUP
DESCRIPTION
TEMPERATURE (°C)
1
Static tests at
25
2
Static tests at
125
3
Static tests at
–55
4
Dynamic tests at
25
5
Dynamic tests at
125
6
Dynamic tests at
–55
7
Functional tests at
25
8A
Functional tests at
125
8B
Functional tests at
–55
9
Switching tests at
25
10
Switching tests at
125
11
Switching tests at
–55
MIL-STD-883, Method 5005 - Group A
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
9
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
7.7 Typical Characteristics: 5 V
at TA = 25°C, VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V, RLtotal = 200-Ω differential (1) (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to mid supply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see Figure 50 to Figure 53)
10
5
5
Normalized Gain (dB)
10
Gain (dB)
0
-5
-10
-15
0
-5
-10
Gp = 3 dB, Gv = 12 dB
Gp = 5.6 dB, Gv = 14.6 dB
Gp = 8 dB, Gv = 17 dB
-15
Gp = 0 dB, Gv = 9 dB
-20
10
100
1k
Frequency (MHz)
-20
10
10k
100
SBOS
1k
Frequency (MHz)
10k
SBOS
See Stability, Noise Gain, and Signal Gain for more details.
Figure 2. SE-DE Small Signal Frequency Response vs Gain
10
10
5
5
Normalized Gain (dB)
Normalized Gain (dB)
Figure 1. SE-DE Small Signal Frequency Response for Low
Gain
0
-5
-10
-15
Rload = 70 :
Rload = 100 :
Rload = 120 :
Rload = 200 :
Rload = 400 :
-20
10
100
0
-5
-10
Cload = No Cap
Cload = 1 pF
Cload = 2.4 pF
Cload = 4.7 pF
-15
1k
Frequency (MHz)
-20
10
10k
100
SBOS
Figure 3. SE-DE Small Signal Frequency Response vs Rload
1k
Frequency (MHz)
10k
SBOS
Figure 4. SE-DE Small Signal Frequency Response vs Cload
20
10
10
0
S-Parameters (dB)
Normalized Gain (dB)
5
0
-5
-10
-15
-20
10
-55qC
-40qC
25qC
85qC
125qC
10
-20
-30
-40
-50
-60
Sds21
Sss11
Sdd22
Ssd12
-70
-80
100
1k
Frequency (MHz)
10k
-90
10
100
SBOS
Figure 5. SE-DE Small Signal Frequency Response vs
Temperature
(1)
-10
1k
Frequency (MHz)
10k
SBOS
Figure 6. SE-DE Small Signal S-Parameters
Please see Output Reference Nodes and Gain Nomenclature.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
Typical Characteristics: 5 V (continued)
at TA = 25°C, VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to mid supply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see Figure 50 to Figure 53)
210
Differential Output Phase (degrees)
Output Amplitude Imbalance (dB)
15
10
5
0
-5
-10
-15
10
100
1k
Frequency (MHz)
200
190
180
170
160
150
10
10k
100
SBOS
Figure 7. SE-DE Amplitude Imbalance
10k
SBOS
Figure 8. SE-DE Phase Imbalance
-10
0
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
-20
-30
-10
-40
HD2 (dBc)
Total Output Imbalance (dB)
1k
Frequency (MHz)
-20
-30
-50
-60
-70
-80
-90
-40
-100
-50
10
100
1k
Frequency (MHz)
-110
10
10k
Figure 9. SE-DE Total Imbalance
1k
SBOS
Figure 10. SE-DE 2nd Order Harmonic Distortion vs
Frequency
-10
-20
100
Frequency (MHz)
SBOS
-30
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
Frequency = 500 MHz
-40
-30
-50
HD2 (dBc)
HD3 (dBc)
-40
-50
-60
-70
-60
-70
-80
-80
-90
-90
-100
-100
-110
10
-110
100
Frequency (MHz)
0
1k
0.5
SBOS
Figure 11. SE-DE 3rd Order Harmonic Distortion vs
Frequency
1
1.5
2
2.5 3
3.5 4
VOUT_AMP (Vpp-diff)
4.5
5
5.5
SBOS
Figure 12. SE-DE 2nd Order Harmonic Distortion vs Vout
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
11
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
Typical Characteristics: 5 V (continued)
at TA = 25°C, VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to mid supply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see Figure 50 to Figure 53)
-30
Frequency = 500 MHz
-40
-60
HD2 (dBc)
HD3 (dBc)
-50
-70
-80
-90
-100
-110
0
0.5
1
1.5
2
2.5 3
3.5 4
VOUT_AMP (Vpp-diff)
4.5
5
5.5
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-2
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
-1.5
SBOS
Figure 13. SE-DE 3rd Order Harmonic Distortion vs Vout
-1
-0.5
0
0.5
VCMOUT (V)
1
1.5
2
SBOS
Figure 14. SE-DE 2nd Order Harmonic Distortion vs Output
Common Mode Voltage
-60
10
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
0
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
-65
-10
-70
HD2 (dBc)
HD3 (dBc)
-20
-30
-40
-50
-75
-80
-85
-60
-90
-70
-95
-80
-90
-2
-1.5
-1
-0.5
0
0.5
VCMOUT (V)
1
1.5
-100
-55
2
SBOS
Figure 15. SE-DE 3rd Order Harmonic Distortion vs Output
Common Mode Voltage
-25
5
35
65
Temperature (qC)
95
125
SBOS
Figure 16. SE-DE 2nd Order Harmonic Distortion vs
Temperature
-10
-50
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
-55
-20
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
-30
-60
IMD2 (dBc)
HD3 (dBc)
-40
-65
-70
-75
-50
-60
-70
-80
-80
-90
-85
-100
-90
-55
-25
5
35
65
Temperature (qC)
95
125
SBOS
Figure 17. SE-DE 3rd Order Harmonic Distortion vs
Temperature
12
-110
10
100
Frequency (MHz)
1k
SBOS
Figure 18. SE-DE 2nd Order Intermodulation Distortion vs
Frequency
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
Typical Characteristics: 5 V (continued)
at TA = 25°C, VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to mid supply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see Figure 50 to Figure 53)
-10
-20
120
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
100 : matched to 100-: load
110
-30
100
90
OIP2 (dBm)
HD3 (dBc)
-40
-50
-60
-70
80
70
-80
60
-90
50
-100
10
100
Frequency (MHz)
40
1k
0
SBOS
Figure 19. SE-DE 3rd Order Intermodulation Distortion vs
Frequency
1000
1500
2000
Frequency (MHz)
2500
3000
SBOS
Figure 20. SE-DE Output 2nd Order Intercept Point
50
10
0
2500 MHz
2000 MHz
1750 MHz
-30
40
OIP3 (dBm)
-20
1500 MHz
-40
1000 MHz
-50
750 MHz
-60
500 MHz
-70
100 : matched to 100-: load
20 : unmatched to 100-: load
45
-10
IMD3 (dBc)
500
35
30
25
100 MHz
-80
20
-90
15
-100
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3
Vout/tone (Vpp-diff) on 100 : (Matched)*
0
250
500
SBOS
* See Output Reference Nodes and Gain Nomenclature for more
details.
* See Output Reference Nodes and Gain Nomenclature for more
details.
Figure 22. SE-DE Output 3rd Order Intercept Point
Figure 21. SE-DE 3rd Order Intermodulation Distortion vs
Vout (Matched Load)
100
0
-10
2000 MHz
2500 MHz
2250 MHz
1750 MHz
-30
Voltage Noise (nV / Hz )
-20
IMD3 (dBc)
750 1000 1250 1500 1750 2000 2250 2500
Frequency (MHz)
SBOS
1500 MHz
-40
1000 MHz
-50
750 MHz
-60
500 MHz
-70
100 MHz
-80
-90
10
1
-100
-110
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Vout/tone (Vpp-diff) on 100 : (Unmatched)*
2
SBOS
0.1
100
1k
10k
100k
1M
Frequency (Hz)
Figure 23. SE-DE 3rd Order Intermodulation Distortion vs
Vout (Unmatched Load)
10M
C023
Figure 24. Input-Referred Voltage Noise
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
13
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
Typical Characteristics: 5 V (continued)
at TA = 25°C, VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to mid supply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see Figure 50 to Figure 53)
1.5
20
All external components included
1.0
VOUT_AMP (V)
18
NF (dB)
16
14
12
0.5
0.0
±0.5
±1.0
10
1-Vpp Pulse
2-Vpp Pulse
±1.5
8
10
100
Frequency (MHz)
1k
0
5
10
15
20
Time (ns)
SBOS
Figure 25. SE-DE Noise Figure vs Frequency
C025
Figure 26. SE-DE Output Signal Pulse Response
0.04
2.5
2.0
0.02
VOUT_AMP (V)
VOUT_AMP (V)
1.5
0.00
±0.02
±0.04
1.0
0.5
0.0
±0.5
±1.0
±0.06
1-Vpp Pulse
2-Vpp Pulse
±0.08
0
5
10
15
±2.0
0
20
Time (ns)
Vout
V
O
PD
±1.5
10
20
30
40
50
60
70
80
Time (ns)
C026
90
100
C027
VCM @ AMPOUT Node; VCM = (Vo+ + Vo–) / 2
Figure 27. SE-DE Output Common Mode Pulse Response
Figure 28. Power Down Timing
6
VO Ideal
4
VOUT_AMP (V)
VO Measured
2
0
±2
±4
±6
0.0
0.5
1.0
1.5
2.0
Time (ns)
2.5
C028
Figure 29. Overdrive Recovery
14
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
7.8 Typical Characteristics: 3.3 V
10
10
5
5
Normalized Gain (dB)
Normalized Gain (dB)
at TA = 25°C, VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V, RLtotal = 200-Ω differential (1) (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to midsupply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see Figure 50 to Figure 53)
0
-5
-10
-15
-20
10
Gp = 3 dB, Gv = 12 dB
Gp = 5.6 dB, Gv = 14.6 dB
Gp = 8 dB, Gv = 17 dB
100
1k
Frequency (MHz)
5
0
-5
-10
Cload = No Cap
Cload = 1 pF
Cload = 2.2 pF
Cload = 4.7 pF
1k
Frequency (MHz)
10k
SBOS
0
-5
-10
-15
-20
10
10k
SBOS
Figure 32. SE-DE Small Signal Frequency Response vs
Cload
-55qC
-40qC
25qC
85qC
125qC
100
1k
Frequency (MHz)
10k
SBOS
Figure 33. SE-DE Small Signal Frequency Response vs
Temperature
20
-10
10
-20
0
-30
-10
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
-40
HD2 (dBc)
-20
-30
-40
-50
-50
-60
-70
-80
-60
Sds21
Sss11
Sdd22
Ssd12
-70
-80
-90
10
1k
Frequency (MHz)
Figure 31. SE-DE Small Signal Frequency Response vs
Rload
5
100
100
SBOS
10
-20
10
Rload = 70 :
Rload = 100 :
Rload = 120 :
Rload = 200 :
Rload = 400 :
-20
10
10k
Normalized Gain (dB)
Normalized Gain (dB)
-10
10
-15
S-Parameters (dB)
-5
-15
Figure 30. SE-DE Small Signal Frequency Response vs Gain
100
1k
Frequency (MHz)
10k
-90
-100
-110
10
SBOS
Figure 34. SE-DE Small Signal S-Parameters
(1)
0
100
Frequency (MHz)
1k
SBOS
Figure 35. SE-DE 2nd Order Harmonic Distortion vs
Frequency
Please see Output Reference Nodes and Gain Nomenclature.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
15
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
Typical Characteristics: 3.3 V (continued)
at TA = 25°C, VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to midsupply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see Figure 50 to Figure 53)
-10
-20
-30
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
Frequency = 500 MHz
-40
-30
-50
HD2 (dBc)
HD3 (dBc)
-40
-50
-60
-70
-60
-70
-80
-90
-80
-100
-110
10
-90
100
Frequency (MHz)
1k
0
0.5
SBOS
1
1.5
2
2.5
VOUT_AMP (Vpp-diff)
3
3.5
4
SBOS
Vout = pk-pk voltage swing per tone on 100-Ω effective load
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
Figure 37. SE-DE 2nd Order Harmonic Distortion vs Vout
-10
Frequency = 500 MHz
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
-20
-30
HD2 (dBc)
HD3 (dBc)
Figure 36. SE-DE 3rd Order Harmonic Distortion vs
Frequency
-40
-50
-60
-70
-80
0
0.5
1
1.5
2
2.5
VOUT_AMP (Vpp-diff)
3
-90
-1
3.5
SBOS
-0.8 -0.6 -0.4 -0.2
0
0.2
VCMOUT (V)
0.4
0.6
0.8
1
SBOS
Vout = pk-pk voltage swing per tone on 100-Ω effective load
Figure 38. SE-DE 3rd Order Harmonic Distortion vs Vout
Figure 39. SE-DE 2nd Order Harmonic Distortion vs Output
Common Mode Voltage
-5
-10
-50
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
-55
-20
-60
-25
-65
HD2 (dBc)
HD3 (dBc)
-15
-30
-35
-40
-45
-70
-75
-80
-50
-85
-55
-60
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
VCMOUT (V)
0.4
0.6
0.8
SBOS
Figure 40. SE-DE 3rd Order Harmonic Distortion vs Output
Common Mode Voltage
16
-90
-55
-25
5
35
65
Temperature (qC)
95
125
SBOS
Figure 41. SE-DE 2nd Order Harmonic Distortion vs
Temperature
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
Typical Characteristics: 3.3 V (continued)
at TA = 25°C, VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to midsupply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see Figure 50 to Figure 53)
-32
-30
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
-40
-52
-45
-62
-50
-55
-72
-82
-60
-92
-65
-102
-70
-55
-25
5
35
65
Temperature (qC)
95
-112
10
125
100
Frequency (MHz)
SBOS
Figure 42. SE-DE 3rd Order Harmonic Distortion vs
Temperature
1k
SBOS
Figure 43. SE-DE 2nd Order Intermodulation Distortion vs
Frequency
-10
-20
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
-42
IMD2 (dBc)
HD3 (dBc)
-35
100
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
90
-30
80
OIP2 (dBm)
IMD3 (dBc)
-40
-50
-60
-70
-80
70
60
50
-90
40
-100
-110
10
30
100
Frequency (MHz)
1k
0
Figure 44. SE-DE 3rd Order Intermodulation Distortion vs
Frequency
1000
1500
2000
Frequency (MHz)
2500
3000
SBOS
Figure 45. SE-DE Output 2nd Order Intercept Point
1.5
50
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
1.0
VOUT_AMP (V)
40
OIP3 (dBm)
500
SBOS
30
20
0.5
0.0
±0.5
10
±1.0
0
±1.5
0
500
1000
1500
2000
Frequency (MHz)
2500
3000
1-Vpp Pulse
2-Vpp Pulse
0
Figure 46. SE-DE Output 3rd Order Intercept Point
5
10
15
Time (ns)
SBOS
20
C046
Figure 47. SE-DE Output Signal Pulse Response
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
17
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
Typical Characteristics: 3.3 V (continued)
at TA = 25°C, VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to midsupply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see Figure 50 to Figure 53)
0.06
0.04
VOUT_AMP (V)
0.02
0.00
±0.02
±0.04
±0.06
±0.08
1-Vpp Pulse
2-Vpp Pulse
±0.10
0
5
10
15
Time (ns)
20
C047
VCM @ AMPOUT Node; VCM = (Vo+ + Vo–) / 2
Figure 48. SE-DE Output Common Mode Pulse Response
18
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
8 Parameter Measurement Information
8.1 Output Reference Nodes and Gain Nomenclature
The LMH5401-SP is a fully-differential amplifier (FDA) configurable with external resistors for noise gain greater
than 3 V/V or 9.5 dB (GBP = 6.5 GHz). For most of this document, data are collected for Gv = 17 dB for both
single-ended-to-differential (SE-DE) and differential-to-differential (DE-DE) conversions in the diagrams illustrated
in the Test Schematics section. When matching the output to a 100-Ω load, the evaluation module (EVM) uses
external 40-Ω resistors to complete the output matching, as the device has an internal series 10 Ω on each
output. Having on-chip output resistors creates two potential reference points for measuring the output voltage.
The amplifier output pins create one output reference point (OUT_AMP). The other output reference point is
OUT_LOAD at the 100-Ω load impedance, RL. These points are illustrated in Figure 49; see also the Test
Schematics section.
RL
RLtotal
LMH5401
RT
Single-Ended
Input
RG
FB+
25 :
10 :
IN-
+
+
IN+
RG
RM
RO
CO
RO
+
+
Test Equipment
With 50-:
Source Impedance
RF
Test Equipment
With 50-:
Load Impedances
10 :
RF
25 :
FB-
CM
OUT_AMP
OUT_LOAD
Copyright © 2017, Texas Instruments Incorporated
Figure 49. Output Reference Nodes
Most measurements in the Electrical Characteristics tables and in the Typical Characteristics sections are
measured with reference to the OUT_AMP reference point. Equation 1 shows that the conversion between
reference points is a straightforward reduction of 3 dB for power and 6 dB for voltage in a matched condition
when Ro is set such that 20 Ω + 2 × Ro = RL. With Ro set to 40 Ω and RL set to 100 Ω-differential, the total load
impedance seen by the amplifier, RLtotal, is 200 Ω. This is considered a matched load condition as 100-Ω is
driving RL of 100 Ω. The device is also capable of driving lower impedances. By setting Ro to 0 Ω, RLtotal
becomes 120 Ω. This is considered an unmatched condition since 20 Ω is driving RL of 100 Ω. As explained in
the Application Curves section, efficiency is improved (losses reduced) in a mismatched condition which is
acceptable if transmission line reflections are avoided and proper termination practices are employed. As stated
previously, most measurements in this document are referenced to OUT_AMP node. However, there are some
typical characteristic plots that are measured with a fixed signal swing with respect to the OUT_LOAD reference
point; specifically, IMD3 Figure 21 and Figure 23 are referenced to the voltage swing at node OUT_LOAD.
VOUT_LOAD = (VOUT_AMP – 6 dB) and POUT_LOAD = (POUT_AMP – 6 dB)
(1)
This document makes references to both voltage gain, Gv, and power gain, Gp. Voltage gain is defined as the
ratio of the differential output voltage at node OUT_AMP to the differential, or single-ended, input voltage at the
node before Rg. Power gain, for the purposes of this document, is defined as the ratio of the power dissipated on
RL (100 Ω-differential) to the power transferred from a source to the input impedance of the amplifier. Whereas
voltage gain contains no input and load impedances in its calculation, power gain does depend on termination
impedances.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
19
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
8.2 ATE Testing and DC Measurements
All production testing and ensured dc parameters are measured on automated test equipment capable of dc
measurements only. Measurements such as output current sourcing and sinking are made in reference to the
device output pins. Some measurements (such as voltage gain) are referenced to the output of the internal
amplifier and do not include losses attributed to the on-chip output resistors. The Electrical Characteristics table
conditions specify these conditions. When the measurement is referred to the amplifier output, then the output
resistors are not included in the measurement. If the measurement is referred to the device pins, then the output
resistor loss is included in the measurement.
8.3 Frequency Response
This test is run with both single-ended inputs and differential inputs.
For tests with single-ended inputs, the standard EVM is used with no changes; see Figure 50. In order to provide
a matched input, the unused input requires a broadband 50-Ω termination to be connected. When using a fourport network analyzer, the unused input can either be terminated with a broadband load, or can be connected to
the unused input on the four-port analyzer. The network analyzer provides proper termination. A network
analyzer is connected to the input and output of the EVM with 50-Ω coaxial cables and is set to measure the
forward transfer function (s21). The input signal frequency is swept with the signal level set for the desired output
amplitude.
The LMH5401-SP is fully symmetrical, either input (IN+ or IN–) can be used for single-ended inputs. The unused
input must be terminated. RF, RG1, and RG2 determine the gain. RT and RM enable matching to the source
resistance. See the Test Schematics section for more information on setting these resistors per gain and source
impedance requirements. Bandwidth is dependant on gain settings because this device is a voltage feedback
amplifier. With a GBP of 6.5 GHz, the approximate bandwidth can be calculated for a specific application
requirement, as shown in Equation 2. Figure 51 illustrates a test schematic for differential input and output.
GBP (Hz) = BW (Hz) × Noise Gain
20
(2)
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
Frequency Response (continued)
For tests with differential inputs, the same setup for single-ended inputs is used except all four connectors are
connected to a network analyzer port. Measurements are made in either true differential mode on the Rohde &
Schwarz® network analyzer or in calculated differential mode. In both cases, the differential inputs are each
driven with a 50-Ω source. Table 2 and Table 3 list resistor values for various gain settings.
Table 2. Differential Input/Output
AV (V/V)
RG1, RG2 (Ω)
RF (Total / External, Ω)
RT (Ω)
2
100
199 / 174
100
4
49.9
199 / 174
N/A
6
49.9
300 / 274
N/A
8
49.9
400 / 375
N/A
10
49.9
500 / 475
N/A
Table 3. SE Input
AV (V/V)
RG1 (Ω)
RT (Ω)
RG2 (Ω)
RF (Total / External, Ω)
2
90.9
4
22.6
76.8
121
200 / 175
357
66.5
8
152 / 127
12.1
1100
60.4
250 / 225
10
9.76
1580
57.6
300 / 275
8.4 S-Parameters
The standard EVM is used for all s-parameter measurements. All four ports are used or are terminated with
50 Ω; see the Frequency Response section.
8.5 Frequency Response with Capacitive Load
The standard EVM is used and the capacitive load is soldered to the inside pads of the 40-Ω matching resistors
(on the DUT side). In this configuration, the on-chip, 10-Ω resistors isolate the capacitive load from the amplifier
output pins. The test schematic for capacitive load measurements is illustrated in Figure 52.
8.6 Distortion
The standard EVM is used for measuring single-tone harmonic distortion and two-tone intermodulation distortion.
All distortion is measured with single-ended input signals; see Figure 53. In order to interface with single-ended
test equipment, external baluns are required between the EVM output ports and the test equipment. The Typical
Characteristics plots are created with Marki™ baluns, model number BAL-0010. These baluns are used to
combine two tones in the two-tone test plots. For distortion measurements the same termination must be used on
both input pins. When a filter is used on the driven input port, the same filter and a broadband load are used to
terminate the other input. When the signal source is a broadband controlled impedance, then only a broadbandcontrolled impedance is required to terminate the unused input.
8.7 Noise Figure
The standard EVM is used with a single-ended input matched to 50-Ω and the Marki balun on the output similar
to the harmonic distortion test setup.
8.8 Pulse Response, Slew Rate, and Overdrive Recovery
The standard EVM is used for time-domain measurements. The input is single-ended with the differential outputs
routed directly to the oscilloscope inputs. The differential signal response is calculated from the two separate
oscilloscope inputs (Figure 24 to ). In addition, the common-mode response is also captured in this configuration.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
21
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
8.9 Power Down
The standard EVM is used with the shorting block on jumper JPD removed completely. A high-speed, 50-Ω pulse
generator is used to drive the PD pin when the output signal is measured by viewing the output signal (such as a
250-MHz sine-wave input).
8.10 VCM Frequency Response
The standard EVM is used with RCM+ and RCM– removed and a new resistor installed at RTCM = 49.9 Ω. The
49.9-Ω resistor is placed at R14 on the EVM schematic. A network analyzer is connected to the VCM input of the
EVM and the EVM outputs are connected to the network analyzer with 50-Ω coaxial cables. Set the network
analyzer analysis settings to single-ended input and differential output. Measure the output common-mode with
respect to the single-ended input (Scs21). The input signal frequency is swept with the signal level set for
100 mV (–16 dBm). Note that the common-mode control circuit gain is one.
8.11 Test Schematics
RT = 1100 :
LMH5401
50-:
Single-Ended
Input
+
-
10 :
IN-
-
OUT+ 40 :
+
+ OUT_LOAD
-
OUT_AMP
IN+
-
+
Test Equipment
With 50-:
Outputs
R1 = 12.1 :
Differential
Load = 200 :
25 :
RF = 200 :
R2 = 60 :
10 :
RF = 200 :
OUT-
40 :
25 :
CM
1 Test Equipment
With 50-:
2
Inputs
Test Equipment
Load = 100 :
PD
Copyright © 2017, Texas Instruments Incorporated
Figure 50. Test Schematic: Single-Ended Input, Differential Output, GV = 7 V/V
RL = 100 :
RLtotal = 200 :
RT = NA
LMH5401
Rin = 100-: diff
25 :
RF = 187 :
RG1 = 50 :
+
RG2 = 50 :
-
IN+
+
-
+
Test Equipment
With 50-:
Rs = 100-: diff
10 :
IN-
OUT_AMP
40 :
40 :
+
OUT_LOAD
1 Test Equipment
With 50-:
2
Inputs
10 :
RF = 187 :
25 :
Test Equipment
Load = 100 :
RT = NA
CM
PD
Copyright © 2017, Texas Instruments Incorporated
Figure 51. Test Schematic: Differential Input, Differential Output, GV = 4.25 V/V
22
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
Test Schematics (continued)
RL
RLtotal
LMH5401
RT
RF
Single-Ended
Input
RG
FB+
25 :
10 :
IN-
+
Test Equipment
With 50-:
Source Impedance
RO
+
RG
RM
CO
RO
+
+
IN+
Test Equipment
With 50-:
Load Impedances
10 :
RF
25 :
FB-
OUT_AMP
CM
OUT_LOAD
Copyright © 2017, Texas Instruments Incorporated
Figure 52. Test Schematic: Capacitive Load, GV = 7 V/V
RLtotal = 200 :
LMH5401
1100 :
50-:
Single-Ended
Input
25 :
200 :
12.1 :
IN-
10 :
+
+
IN+
OUT+
40 :
+
OUT_AMP
+
Test Equipment
With 50-:
Outputs
RL = 100 :
10 :
60 :
200 :
OUT-
40 :
BAL
0010
Test Equipment
With 50-:
Inputs
OUT_LOAD
25 :
CM
PD
Copyright © 2017, Texas Instruments Incorporated
Figure 53. Test Schematic for Noise Figure and Single-Ended Harmonic Distortion, GV = 7 V/V
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
23
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
9 Detailed Description
9.1 Overview
The LMH5401-SP is a very high-performance, differential amplifier optimized for radio frequency (RF) and
intermediate frequency (IF) or high-speed, time-domain applications for wide bandwidth applications as the GBP
is 6.5 GHz. The device is ideal for dc- or ac-coupled applications that may require a single-ended-to-differential
(SE-DE) conversion when driving an analog-to-digital converter (ADC). The necessary external feedback (RF)
and gain set (RG) resistors configure the gain of the device. For the EVM the standard gain is set to Gv = 17 dB
(for both DE and SE conversions) with RF = 200 Ω and RG = 12.1 Ω.
A common-mode reference input pin is provided to align the amplifier output common-mode with the ADC input
requirements. Power supplies between 3.3 V and 5 V can be selected and dual-supply operation is supported
when required by the application. A power-down feature is also available for power savings.
The LMH5401-SP offers two on-chip termination resistors, one for each output with values of 10 Ω each. For
most load conditions the 10-Ω resistors are only a partial termination. Consequently, external termination
resistors are required in most applications. See Table 4 for some common load values and the matching
resistors.
9.2 Functional Block Diagram
V+
+FB
25
+OUT
-IN
±
High-Aol +
Differential I/O
Amplifier ±
+IN
10
2.5 k
+
2.5 k
-OUT
10
-FB
25
V+
±
Vcm
Error
Amplifier
+
PD
GND
VCM
Compa
rator
NOTE: V- and GND are isolated.
V±
Copyright © 2017, Texas Instruments Incorporated
NOTE: V– and GND are isolated.
9.3 Feature Description
The LMH5401-SP includes the following features:
• Fully-differential amplifier
• Flexible gain configurations using external resistors
• Output common-mode control
• Single- or split-supply operation
• Gain bandwidth product (GBP) of 6.5 GHz
• Linear bandwidth of 2 GHz (Gv = 17 dB)
• Power down
24
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
Feature Description (continued)
9.3.1 Fully-Differential Amplifier
The LMH5401-SP is a voltage feedback (VFA)-based fully-differential amplifier (FDA) offering a GBP of 6.5 GHz
with flexible gain options using external resistors. The core differential amplifier is a slightly decompensated
voltage feedback design with a high slew rate and best-in-class linearity up to 2 GHz for Gv = 17 dB (SE-DE,
DE-DE).
As with all FDA devices, the output average voltage (common-mode) is controlled by a separate common-mode
loop. The target for this output average is set by the VCM input pin. The VOCM range extends from 1.1 V below the
midsupply voltage to 1.1 V above the midsupply voltage when using a 5-V supply. Note that on a 3.3-V supply
the output common-mode range is quite small. For applications using a 3.3-V supply voltage, the output
common-mode must remain very close to the midsupply voltage.
The input common-mode voltage offers more flexibility than the output common-mode voltage. The input
common-mode range extends from the negative rail to approximately 1 V above the midsupply voltage when
powered with a 5-V supply.
A power-down pin is included. This pin is referenced to the GND pins with a threshold voltage of approximately
1 V. Setting the PD pin voltage to more than the specified minimum voltage turns the device off, placing the
LMH5401-SP into a very low quiescent current state. Note that, when disabled, the signal path is still present
through the passive external resistors. Input signals applied to a disabled LMH5401-SP device still appear at the
outputs at some level through this passive resistor path, as with any disabled FDA device. The power-down pin
is biased to the logic low state with a 50-kΩ internal resistor.
9.3.2 Operations for Single-Ended to Differential Signals
One of the most useful features supported by the FDA device is the active balun configuration which provides an
easy conversion from a single-ended input to a differential output centered on a user-controlled, common-mode
level. Although the output side is relatively straightforward, the device input pins move in a common-mode sense
with the input signal. This feature acts to increase the apparent input impedance to be greater than the RG value.
However, this feature can cause input clipping if this common-mode signal moves beyond the input range. This
input active impedance issue applies to both ac- and dc-coupled designs, and requires somewhat more complex
solutions for the resistors to account for this active impedance, as described in this section.
9.3.2.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
When the signal path is ac coupled, the dc biasing for the LMH5401-SP becomes a relatively simple task. In all
designs, start by defining the output common-mode voltage. The ac-coupling issue can be separated for the
input and output sides of an FDA design. The input can be ac coupled and the output dc coupled, or the output
can be ac coupled and the input dc coupled, or they can both be ac coupled. One situation where the output can
be dc coupled (for an ac-coupled input), is when driving directly into an ADC where the VOCM control voltage
uses the ADC common-mode reference to directly bias the FDA output common-mode to the required ADC input
common-mode. The feedback path must always be dc-coupled. In any case, the design starts by setting the
desired VOCM. When an ac-coupled path follows the output pins, the best linearity is achieved by operating VOCM
at mid supply. The VOCM voltage must be within the linear range for the common-mode loop, as specified in the
headroom specifications. If the output path is also ac coupled, simply letting the VOCM control pin float is usually
preferred in order to obtain a midsupply default VOCM bias with no external elements. To limit noise, place a 0.1µF decoupling capacitor on the VOCM pin to ground. After VOCM is defined, check the target output voltage swing
to ensure that the VOCM positive or negative output swing on each side does not clip into the supplies. If the
desired output differential swing is defined as VOPP, divide by 4 to obtain the ±VP swing around VOCM at each of
the two output pins (each pin operates 180° out of phase with the other). Check that VOCM ±VP does not exceed
the output swing of this device. Going to the device input pins side, because both the source and balancing
resistor on the non-signal input side are dc blocked (see Figure 55), no common-mode current flows from the
output common-mode voltage, thus setting the input common-mode equal to the output common-mode voltage.
This input headroom also sets a limit for higher VOCM voltages. The minimum headroom for the input pins to the
positive supply overrides the headroom limit for the output VOCM because the input VICM is the output VOCM for
ac-coupled sources. Also, the input signal moves this input VICM around the dc bias point, as described in the
Resistor Design Equations for Single-to-Differential Applications subsection of the Fully-Differential Amplifier
section.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
25
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
Feature Description (continued)
9.3.2.2 DC-Coupled Input Signal Path Considerations for SE-DE Conversions
The output considerations remain the same as for the ac-coupled design. Again, the input can be dc coupled
when the output is ac coupled. A dc-coupled input with an ac-coupled output can have some advantages to
move the input VICM down if the source is ground referenced. When the source is dc coupled into the LMH5401SP (as shown in Figure 54), both sides of the input circuit must be dc coupled to retain differential balance.
Normally, the non-signal input side has an RG element biased to whatever the source midrange is expected to
be. Providing this mid-scale reference gives a balanced differential swing around VOCM at the outputs. Often, RG2
is simply grounded for dc-coupled, bipolar-input applications. This configuration gives a balanced differential
output if the source swings around ground. If the source swings from ground to some positive voltage, grounding
RG2 gives a unipolar output differential swing from both outputs at VOCM (when the input is at ground) to one
polarity of swing. Biasing RG2 to an expected midpoint for the input signal creates a differential output swing
around VOCM. One significant consideration for a dc-coupled input is that VOCM sets up a common-mode bias
current from the output back through RF and RG to the source on both sides of the feedback. Without inputbalancing networks, the source must sink or source this dc current. After the input signal range and biasing on
the other RG element is set, check that the voltage divider from VOCM to VI through RF and RG (and possibly RS)
establishes an input VICM at the device input pins that is in range.
50-: Input Match, Gain of 7 V/V
from RT, Single-Ended Source to
Differential Output
RLtotal = 200 :
RL = 100 :
LMH5401
50-:
Source
RT = 1100 :
RF = 200 :
RG1 = 12.1 :
C1 = 0.1 PF
+
-
25 :
10 :
IN-
-
+
-
IN+
+
RG2 = 60 :
OUT+
OUT_AMP
10 :
40 :
40 :
+
100 :
-
OUT-
RF = 200 :
25 :
CM
PD
Copyright © 2017, Texas Instruments Incorporated
Figure 54. DC-Coupled, Single-Ended-to-Differential, Gv = 7 V/V
9.3.2.3 Resistor Design Equations for Single-to-Differential Applications
Being familiar with the FDA resistor selection criteria is still important because the LMH5401-SP gain is
configured through external resistors. The design equations for setting the resistors around an FDA to convert
from a single-ended input signal to a differential output can be approached in several ways. In this section,
several critical assumptions are made to simplify the results:
• The feedback resistors are selected first and are set to be equal on the two sides of the device.
• The dc and ac impedances from the summing junctions back to the signal source and ground (or a bias
voltage on the non-signal input side) are set equal to retain the feedback divider balance on each side of the
FDA.
Both of these assumptions are typical and are aimed to deliver the best dynamic range through the FDA signal
path.
After the feedback resistor values are chosen, the aim is to solve for RT (a termination resistor to ground on the
signal input side), RG1 (the input gain resistor for the signal path), and RG2 (the matching gain resistor on the
non-signal input side); see Figure 55. This example uses the LMH5401-SP, an external resistor FDA. The same
resistor solutions can be applied to either ac- or dc-coupled paths. Adding blocking capacitors in the input-signal
chain is a simple option. Adding these blocking capacitors after the RT element (see Figure 55) has the
advantage of removing any dc currents in the feedback path from the output VOCM to ground.
26
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
Feature Description (continued)
50-: Input Match, Gain of 7 V/V
from RT, Single-Ended Source to
Differential Output
RLtotal = 200 :
RL = 100 :
LMH5401-SP
50-:
Source
RT = 1100 :
RF = 200 :
25 :
RG1 = 12.1 :
C1 = 0.1 PF
10 :
IN-
+
-
-
+
-
IN+
+
RG2 = 60 :
C2 = 0.1 PF
OUT+
OUT_AMP
10 :
40 :
40 :
+
100 :
-
OUT-
RF = 200 :
25 :
CM
PD
Figure 55. AC-Coupled, Single-Ended Source to a Differential Gain of a 7-V/V
Most FDA amplifiers use external resistors and have complete flexibility in the selected RF, however the
LMH5401-SP has small on-chip feedback resistors that are fixed at 25 Ω. The equations used in this section
apply with an additional 25 Ω to be added to the external RF resistors.
After the feedback resistor values are chosen, the aim is to solve for RT (a termination resistor to ground on the
signal input side), RG1 (the input gain resistor for the signal path), and RG2 (the matching gain resistor on the
non-signal input side). The same resistor solutions can be applied to either ac- or dc-coupled paths. Adding
blocking capacitors in the input-signal chain is a simple option. Adding these blocking capacitors after the RT
element has the advantage of removing any dc currents in the feedback path from the output VOCM to ground.
Earlier approaches to the solutions for RT and RG1 (when the input must be matched to a source impedance, RS)
follow an iterative approach. This complexity arises from the active input impedance at the RG1 input. When the
FDA is used to convert a single-ended signal to differential, the common-mode input voltage at the FDA inputs
must move with the input signal to generate the inverted output signal as a current in the RG2 element. A more
recent solution is shown as Equation 3, where a quadratic in RT can be solved for an exact required value. This
quadratic emerges from the simultaneous solution for a matched input impedance and target gain. The only
inputs required are:
1. The selected RF value.
2. The target voltage gain (AV) from the input of RT to the differential output voltage.
3. The desired input impedance at the junction of RT and RG1 to match RS.
Solving this quadratic for RT starts the solution sequence, as shown in Equation 3:
RS
§
·
2R S ¨ 2R F
A V2 ¸
2R F R S2 A V
2
©
¹
R T2 RT
0
2RF 2 A V
R S A V (4 A V ) 2RF 2 A V
R S A V (4 A V )
(3)
Being a quadratic, there are limits to the range of solutions. Specifically, after RF and RS are chosen, there is
physically a maximum gain beyond which Equation 3 starts to solve for negative RT values (if input matching is a
requirement). With RF selected, use Equation 4 to verify that the maximum gain is greater than the desired gain.
Av max
RF
RS
ª
«
2 ‡ «1
«
«
¬«
4
1
(
RF
RS
º
»
»
2 »
2) »
¼»
RF
RS
(4)
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
27
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
Feature Description (continued)
If the achievable AVmax is less than desired, increase the RF value. After RT is derived from Equation 3, the RG1
element is given by Equation 5:
R
2 F RS
AV
R G1
RS
1
RT
(5)
Then, the simplest approach is to use a single RG2 = RT || RS + RG1 on the non-signal input side. Often, this
approach is shown as the separate RG1 and RS elements. This approach can provide a better divider match on
the two feedback paths, but a single RG2 is often acceptable. A direct solution for RG2 is given as Equation 6:
R
2 F
AV
R G2
RS
1
RT
(6)
This design proceeds from a target input impedance matched to RS, signal gain AV, and a selected RF value. The
nominal RF value chosen for the LMH5401-SP characterization is 225 Ω (RFExternal + RFInternal, where RFInternal is
always 25 Ω). As discussed previously, this resistance is on-chip and cannot be changed. Refer to Table 2 and
Table 3 in the Frequency Response section, which list the value of resistors used for characterization in this
document.
9.3.2.4 Input Impedance Calculations
The designs so far have included a source impedance, RS, that must be matched by RT and RG1. The total
impedance with respect to the input at RG1 for the circuit of Figure 54 is the parallel combination of RT to ground
and ZA (active impedance) presented by the amplifier input at RG1. That expression, assuming RG2 is set to
obtain a differential divider balance, is given by Equation 7:
ZA
R G1
§
¨1
©
R G1 ·§
RF ·
¸¨ 1
¸
R G2 ¹©
R G1 ¹
RF
2
R G2
(7)
For designs that do not need impedance matching (but instead come from the low-impedance output of another
amplifier, for instance), RG1 = RG2 is the single-to-differential design used without RT to ground. Setting RG1 = RG2
= RG in Equation 7 gives the input impedance of a simple input FDA driving from a low-impedance, single-ended
source to a differential output.
9.3.3 Differential-to-Differential Signals
The LMH5401-SP can also be used to amplify differential input signals to differential output signals. In many
ways, this method is a much simpler way to operate the FDA from a design equations perspective. Again,
assuming the two sides of the circuit are balanced with equal RF and RG elements, the differential input
impedance is now just the sum of the two RG elements to a differential inverting summing junction. In these
designs, the input common-mode voltage at the summing junctions does not move with the signal, but must be
dc biased in the allowable range for the input pins with consideration given to the voltage headroom required to
each supply. Slightly different considerations apply to ac- or dc-coupled, differential-in to differential-out designs,
as described in this section.
28
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
Feature Description (continued)
9.3.3.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
When using the LMH5401-SP with an ac-coupled differential source, the input can be coupled in through two
blocking capacitors. An optional input differential termination resistor (RM) can be included to allow the input RG
resistors to be scaled up while still delivering lower differential input impedance to the source. In Figure 56, the
RG elements sum to show a 200-Ω differential impedance and the RM element combines in parallel to give a net
100-Ω, ac, differential impedance to the source. Again, the design proceeds ideally by selecting the RF element
values, then the RG to set the differential gain, then an RM element (if needed) to achieve a target input
impedance. Alternatively, the RM element can be eliminated, the RG elements set to the desired input impedance,
and RF set to the get the differential gain (= RF / RG). The dc biasing in Figure 56 is very simple. The output VOCM
is set by the input control voltage and, because there is no dc current path for the output common-mode voltage,
that dc bias also sets the input pins common-mode operating points.
RF1 = 402 :
C1
Downconverter Mixer
Differential
Output
RG1 = 100 :
RM = 200 :
C1
VOCM
FDA
RL = 200 :
RG2 = 100 :
RF2 = 402 :
Figure 56. Downconverting Mixer AC-Coupled to the LMH5401-SP (GV = 4 V/V)
9.3.3.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
Operating the LMH5401-SP with a dc-coupled input source simply requires that the input pins stay in range of
the dc common-mode operating voltage. Only RG values that are equal to the differential input impedance and
that set the correct RF values for the gain desired are required.
9.3.4 Output Common-Mode Voltage
The CM input controls the output common-mode voltage. CM has no internal biasing network and must be driven
by an external source or resistor divider network to the positive power supply. The CM input impedance is very
high and bias current is not critical. Also, the CM input has no internal reference and must be driven from an
external source. Using a bypass capacitor is also necessary. A capacitor value of 0.01 µF is recommended. For
best harmonic distortion, maintain the CM input within ±1 V of the midsupply voltage using a 5-V supply and
within ±0.5 V when using a 3.3-V supply. The CM input voltage can be operated outside this range if lower
output swing is used or distortion degradation is allowed. For more information, see Figure 20 and Figure 21.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
29
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
9.4 Device Functional Modes
9.4.1 Operation with a Split Supply
The LMH5401-SP can be operated using split supplies. One of the most common supply configurations is
±2.5 V. In this case, VS+ is connected to 2.5 V, VS– is connected to –2.5 V, and the GND pins are connected to
the system ground. As with any device, the LMH5401-SP is impervious to what the levels are named in the
system. In essence, using split supplies is simply a level shift of the power pins by –2.5 V. If everything else is
level-shifted by the same amount, the device does not detect any difference. With a ±2.5-V power supply, the
CM range is 0 V ±1 V; the input has a slightly larger range of –2.5 V to 1 V. This design has certain advantages
in systems where signals are referenced to ground, and as noted in the ADC Input Common-Mode Voltage
Considerations—DC-Coupled Input section, for driving ADCs with low input common-mode voltage requirements
in dc-coupled applications. With the GND pin connected to the system ground, the power-down threshold is
1.2 V, which is compatible with most logic levels from 1.5-V CMOS to 2.5-V CMOS.
As noted previously, the absolute supply voltage values are not critical. For example, using a 4-V VS+ and a
–1-V VS– still results in a 5-V supply condition. As long as the input and output common-mode voltages remain
in the optimum range, the amplifier can operate on any supply voltages from 3.3 V to 5.25 V. When considering
using supply voltages near the 3.3-V total supply, be very careful to make sure that the amplifier performance is
adequate. Setting appropriate common-mode voltages for large-signal swing conditions becomes difficult when
the supply voltage is below 4 V.
9.4.2 Operation with a Single Supply
As with split supplies, the LMH5410 can be operated from single-supply voltages from 3.3 V to 5.25 V. Singlesupply operation is most appropriate when the signal path is ac coupled and the input and output common-mode
voltages are set to mid supply by the CM pin and are preserved by coupling capacitors on the input and output.
30
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Stability, Noise Gain, and Signal Gain
Two types of gain are associated with amplifiers: noise gain (NG) and signal gain. Noise gain determines the
stability of an amplifier. The noise gain is the inverse of the voltage divider from the outputs back to the
differential inputs. This gain is calculated by NG = (RF / RIN) + 1. For the LMH5401-SP, NG > 3 creates a stable
circuit independent on how the signal gain is set. In Figure 57, for optimal performance choose RF within the
values noted in this document (see the Parameter Measurement Information section for further information).
Using too large of a resistance in the feedback path adds noise and can possibly have a negative affect on
bandwidth, depending on the parasitic capacitance of the board; too low of a resistance can load the output, thus
affecting distortion performance. When low signal gain stability is needed, the noise gain can be altered with the
addition of a dummy resistor (that is, RT in the differential configuration of Figure 57). By manipulating the noise
gain with this addition, the amplifier can be stabilized at lower signal gains. In Figure 57, RS and Rcomp in parallel
combination also affects the noise gain of the amplifier. RG and RF are the main gain-setting resistors and the
addition of Rcomp adjusts the noise gain for stability. Much of this stability can be simulated using the LMH5401SP TINA model, depending on the amplifier configuration. The example in Figure 57 uses the LMH5401-SP, a
signal gain of 2.8 V/V, and a noise gain of 3.65 V/V resulting in the frequency response shown in Figure 58.
RL
RLtotal
LMH5401
RT=1100 :
RF=200 :
Single-Ended
Input
+
10 :
IN-
RCOMP=100 :
25 :
+
IN+
RG
RM
RO
RO
+
+
Test Equipment
With 50-:
Source Impedance
RG
FB+
Test Equipment
With 50-:
Load Impedances
10 :
RF=200 :
FB-
25 :
CM = mid-supply
OUT_AMP
OUT_LOAD
Copyright © 2017, Texas Instruments Incorporated
Figure 57. Noise Gain Compensation for Stability at Gp = 0 dB
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
31
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
Application Information (continued)
10
5
Gain (dB)
0
-5
-10
-15
Gp = 0 dB, Gv = 9 dB
-20
10
100
1k
Frequency (MHz)
10k
SBOS
Figure 58. SE-DE Small Signal Frequency Response for Low Gain
10.1.2 Input and Output Headroom Considerations
The starting point for most designs is to assign an output common-mode voltage. For ac-coupled signal paths,
this starting point is often the default midsupply voltage to retain the most available output swing around the
output operating point, which is centered with VCM equal to the midsupply point. For dc-coupled designs, set this
voltage considering the required minimum headroom to the supplies listed in the Electrical Characteristics tables
for VCM control. From that target output, VCM, the next step is to verify that the desired output differential VPP
stays within the supplies. For any desired differential output voltage (VOPP) check the maximum possible signal
swing for each output pin. Make sure that each pin can swing to the voltage required by the application.
For instance, when driving the ADC12D1800RF with a 1.25-V common-mode and 0.8-VPP input swing, the
maximum output swing is set by the negative-going signal from 1.25 V to 0.2 V. The negative swing of the signal
is right at the edge of the output swing capability of the LMH5401-SP. In order to set the output common-mode to
an acceptable range, a negative power supply of at least –1 V is recommended. The ideal negative supply
voltage is the ADC VCM – 2.5 V for the negative supply and the ADC VCM + 2.5 V for the input swing. In order to
use the existing supply rails, deviating from the ideal voltage may be necessary.
With the output headroom confirmed, the input junctions must also stay within their operating range. Because the
input range extends nearly to the negative supply voltage, input range limitations only appear when approaching
the positive supply where a maximum 1.5-V headroom is required.
The input pins operate at voltages set by the external circuit design, the required output VOCM, and the input
signal characteristics. The operating voltage of the input pins depends on the external circuit design. With a
differential input, the input pins operate at a fixed input VICM, and the differential input signal does not influence
this common-mode operating voltage.
AC-coupled differential input designs have a VICM equal to the output VOCM. DC-coupled differential input designs
must check the voltage divider from the source VCM to the LMH5401-SP CM setting. That result solves to an
input VICM within the specified range. If the source VCM can vary over some voltage range, the validation
calculations must include this variation.
10.1.3 Noise Analysis
The first step in the output noise analysis is to reduce the application circuit to its simplest form with equal
feedback and gain setting elements to ground (as shown in Figure 59) with the FDA and resistor noise terms to
be considered.
32
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
Application Information (continued)
enRG2
enRF2
RG
RF
r
r
In+2
+
In±2
eno2
±
eni2
enRG2
enRF2
RG
RF
r
r
Figure 59. FDA Noise-Analysis Circuit
The noise powers are shown in Figure 59 for each term. When the RF and RG terms are matched on each side,
the total differential output noise is the root sum of squares (RSS) of these separate terms. Using NG (noise
gain) ≡ 1 + RF / RG, the total output noise is given by Equation 8. Each resistor noise term is a 4-kTR power.
eno
eniNG
2
2 inR F
2
2 4kTR FNG
(8)
The first term is simply the differential input spot noise times the noise gain. The second term is the input current
noise terms times the feedback resistor (and because there are two terms, the power is two times one of the
terms). The last term is the output noise resulting from both the RF and RG resistors, again times two, for the
output noise power of each side added together. Using the exact values for a 50-Ω, matched, single-ended to
differential gain, sweep with 2 Ω (plus an internal 25 Ω) and the intrinsic noise eni = 1.25 nV and in = 3.5 pA for
the LMH5401-SP, which gives an output spot noise from Equation 8. Then, dividing by the signal gain set
through internal resistors (AV), gives the input-referred, spot-noise voltage (ei) of 1.35 nV/√Hz. Note that for the
LMH5401-SP the current noise is an insignificant noise contributor because of the low value of RF.
10.1.4 Noise Figure
Noise figure (NF) is a helpful measurement in an RF system design. The basis of this calculation is to define how
much thermal noise the system (or even on the component) adds to this input signal. All systems are assumed to
have a starting thermal noise power of –174 dBm/√Hz at room temperature calculated from P(dBW) = 10 × log
(kTB), where T is temperature in Kelvin (290k), B is bandwidth in Hertz (1 Hz), and k is Boltzmann's constant
1.38 × 10–23 (J / K). Whenever an element is placed in a system, additional noise is added beyond the thermal
noise floor. The noise factor (F) helps calculate the noise figure and is the ratio between the input SNR and the
output SNR. Input SNR includes the noise contribution from the resistive part of the source impedance, ZS. NF is
relative to the source impedance used in the measurement or calculation because ideal capacitors and inductors
are known to be noiseless. NF can be calculated by Equation 9:
NF = 10 log (eno2 / enZs)
where
•
•
en(Zs) is the thermal noise of the source resistance and equal to 4 kTRS (GDT)2,
G is the voltage gain of the amplifier.
(9)
From Equation 10, NF is roughly equal to 10 dB which is the just above the actual value of 9.6 dB measured on
the bench at 200 MHz when referenced to 50 Ω and as illustrated in Figure 25.
RT
DT =
RS + RT
(10)
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
33
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
Application Information (continued)
For thermal noise calculations with different source resistance, Equation 11 can be used to calculate the NF
change with a new source resistance. For example, Equation 9 uses a source resistance of 50 Ω. By using a
source of 100 Ω, the new noise figure calculation (Equation 11) yields an NF with a 3-dB improved. This is
intuitive as the noise of source increases, the noise of the amplifier becomes less noticeable, and, hence, the NF
improves.
en(Zs) = kTRs
(11)
10.1.5 Thermal Considerations
The LMH5401-SP is packaged in a space-saving LCCC package that has a thermal coefficient (RθJC(bot)) of
63.8°C/W. Limit the total power dissipation in order to keep the device junction temperature below 150°C for
instantaneous power and below 125°C for continuous power.
34
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
10.2 Typical Application
The LMH5401-SP is designed as a single-ended-to-differential (SE-DE) and differential-to-differential (DE-DE)
gain block configured with external resistors and gain-stable single-ended to differential for NG ≥ 2 V/V . The
LMH5401-SP has no low-end frequency cutoff and has 6.5-GHz gain product bandwidth. The LMH5401-SP is a
very attractive substitute for a balun transformer in many applications.
The resistors labeled RO serve to match the filter impedance to the 20-Ω amplifier differential output impedance.
If no filter is used, these resistors may not be required if the ADC is located very close to the LMH5401-SP. If
there is a transmission line between the LMH5401-SP and the ADC then the RO resistors must be sized to match
the transmission line impedance. A typical application driving an ADC is shown in Figure 60.
25
RT
50- ,
Single-Ended Input
RF
RG
FB+
10
IN±
OUT+
RO
±
+
±
LMH5401-SP
IN+
+
10
RG+RM
RF
FB±
IN+
+
OUT_AMP
±
RO
Filter
ADC12D1620
IN±
OUT±
25
CM
Copyright © 2017, Texas Instruments Incorporated
Figure 60. Single-Ended Input ADC Driver
10.2.1 Design Requirements
The main design requirements are to keep the amplifier input and output common-mode voltages compatible
with the ADC requirements and the amplifier requirements. Using split power supplies may be required.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
35
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
Typical Application (continued)
10.2.2 Detailed Design Procedure
10.2.2.1 Driving Matched Loads
The LMH5401-SP has on-chip output resistors, however, for most load conditions additional resistance must be
added to the output to match a desired load. Table 4 lists the matching resistors for some common load
conditions.
Table 4. Load Component Values (1)
(1)
LOAD (RL)
RO+ AND RO– FOR A MATCHED
TERMINATION
TOTAL LOAD RESISTANCE AT
AMPLIFIER OUTPUT (RLtotal)
TERMINATION LOSS
50 Ω
15 Ω
100 Ω
6 dB
100 Ω
40 Ω
200 Ω
6 dB
200 Ω
90 Ω
400 Ω
6 dB
400 Ω
190 Ω
800 Ω
6 dB
1 kΩ
490 Ω
2000 Ω
6 dB
The total load includes termination resistors.
10.2.2.2 Driving Unmatched Loads For Lower Loss
When the LMH5401-SP and the load can be placed very close together, back-terminated transmission lines are
not required. In this case, the 6-dB loss can be reduced significantly. One example is shown in Figure 61.
VIN
Low-Pass Filter
200 :
12.1 :
8.4 nF
LMH5401-SP
1100 :
60 :
ADC12J4000
0.7 pF
8.4 nF
0.7 pF
200 :
NOTE: Amplitude gain = 17 dB and net gain to ADC = 15.5 dB.
Figure 61. Low-Loss ADC
10.2.2.3 Driving Capacitive Loads
With high-speed signal paths, capacitive loading is highly detrimental to the signal path, as shown in Figure 62.
Designers must make every effort to reduce parasitic loading on the amplifier output pins. The device on-chip
resistors are included in order to isolate the parasitic capacitance associated with the package and the PCB pads
that the device is soldered to. The LMH5401-SP is stable with most capacitive loads ≤ 10 pF; however,
bandwidth suffers with capacitive loading on the output.
10
Normalized Gain (dB)
5
0
-5
-10
-15
-20
10
Cload = No Cap
Cload = 1 pF
Cload = 2.4 pF
Cload = 4.7 pF
100
1k
Frequency (MHz)
10k
SBOS
Figure 62. Frequency Response with Capacitive Load
36
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
10.2.2.4 Driving ADCs
The LMH5401-SP is designed and optimized for the highest performance to drive differential input ADCs.
Figure 63 shows a generic block diagram of the LMH5401-SP driving an ADC. The primary interface circuit
between the amplifier and the ADC is usually a filter of some type for antialias purposes, and provides a means
to bias the signal to the input common-mode voltage required by the ADC. Filters range from single-order real
RC poles to higher-order LC filters, depending on the requirements of the application. Output resistors (RO) are
shown on the amplifier outputs to isolate the amplifier from any capacitive loading presented by the filter.
25
FB+
RF
RG
10
IN±
OUT+
RO
±
+
±
100Differential Input
LMH5401-SP
IN+
+
+
±
RG
OUT_AMP
10
RF
FB±
Filter
RO
IN+
IN±
ADC
OUT±
25
CM
Copyright © 2017, Texas Instruments Incorporated
Figure 63. Differential ADC Driver Block Diagram
The key points to consider for implementation are the SNR, SFDR, and ADC input considerations, as described
in this section.
10.2.2.4.1 SNR Considerations
The signal-to-noise ratio (SNR) of the amplifier and filter can be calculated from the amplitude of the signal and
the bandwidth of the filter. The noise from the amplifier is band-limited by the filter with the equivalent brick-wall
filter bandwidth. The amplifier and filter noise can be calculated using Equation 12:
SNRAMP+FILTER = 10 ´ log
V2O
= 20 ´ log
e2FILTEROUT
VO
eFILTEROUT
where:
•
•
•
•
eFILTEROUT = eNAMPOUT × √ENB,
eNAMPOUT = the output noise density of the LMH5401-SP,
ENB = the brick-wall equivalent noise bandwidth of the filter, and
VO = the amplifier output signal.
(12)
For example, with a first-order (N = 1) band-pass or low-pass filter with a 30-MHz cutoff, the ENB is 1.57 × f–3dB
= 1.57 × 30 MHz = 47.1 MHz. For second-order (N = 2) filters, the ENB is 1.22 × f–3dB. When filter order
increases, the ENB approaches f–3dB (N = 3 → ENB = 1.15 × f–3dB; N = 4 → ENB = 1.13 × f–3dB). Both VO and
eFILTEROUT are in RMS voltages. For example, with a 2-VPP (0.707 VRMS) output signal and a 30-MHz first-order
filter, the SNR of the amplifier and filter is 70.7 dB with eFILTEROUT = 5.81 nV/√Hz × √47.1 MHz = 39.9 μVRMS.
The SNR of the amplifier, filter, and ADC sum in RMS fashion is as shown in Equation 13 (SNR values in dB):
-SNRAMP+FILTER
SNRSYSTEM = -20 ´ log
10
10
-SNRADC
+ 10
10
(13)
This formula shows that if the SNR of the amplifier and filter equals the SNR of the ADC, the combined SNR is
3 dB lower (worse). Thus, for minimal degradation (< 1 dB) on the ADC SNR, the SNR of the amplifier and filter
must be ≥ 10 dB greater than the ADC SNR. The combined SNR calculated in this manner is usually accurate to
within ±1 dB of the actual implementation.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
37
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
10.2.2.4.2 SFDR Considerations
The SFDR of the amplifier is usually set by the second-order or third-order harmonic distortion for single-tone
inputs, and by the second-order or third-order intermodulation distortion for two-tone inputs. Harmonics and
second-order intermodulation distortion can be filtered to some degree, but third-order intermodulation spurs
cannot be filtered. The ADC generates the same distortion products as the amplifier, but as a result of the
sampling and clock feedthrough, additional spurs (not linearly related to the input signal) are included.
When the spurs from the amplifier and filter are known, each individual spur can be directly added to the same
spur from the ADC, as shown in Equation 14, to estimate the combined spur (spur amplitudes in dBc):
-HDxADC
-HDxAMP+FILTER
HDxSYSTEM = -20 ´ log 10
20
+ 10
20
(14)
This calculation assumes the spurs are in phase, but usually provides a good estimate of the final combined
distortion.
For example, if the spur of the amplifier and filter equals the spur of the ADC, then the combined spur is 6 dB
higher. To minimize the amplifier contribution (< 1 dB) to the overall system distortion, the spur from the amplifier
and filter must be approximately 19 dB lower in amplitude than that of the converter. The combined spur
calculated in this manner is usually accurate to within ±6 dB of the actual implementation; however, higher
variations can be detected as a result of phase shift in the filter, especially in second-order harmonic
performance.
This worst-case spur calculation assumes that the amplifier and filter spur of interest is in phase with the
corresponding spur in the ADC, such that the two spur amplitudes can be added linearly. There are two phaseshift mechanisms that cause the measured distortion performance of the amplifier-ADC chain to deviate from the
expected performance calculated using Equation 14: common-mode phase shift and differential phase shift.
Common-mode phase shift is the phase shift detected equally in both branches of the differential signal path
including the filter. Common-mode phase shift nullifies the basic assumption that the amplifier, filter, and ADC
spur sources are in phase. This phase shift can lead to better performance than predicted when the spurs
become phase shifted, and there is the potential for cancellation when the phase shift reaches 180°. However, a
significant challenge exists in designing an amplifier-ADC interface circuit to take advantage of a common-mode
phase shift for cancellation: the phase characteristic of the ADC spur sources are unknown, thus the necessary
phase shift in the filter and signal path for cancellation is also unknown.
Differential phase shift is the difference in the phase response between the two branches of the differential filter
signal path. Differential phase shift in the filter as a result of mismatched components caused by nominal
tolerance can severely degrade the even-order distortion of the amplifier-ADC chain. This effect has the same
result as mismatched path lengths for the two differential traces, and causes more phase shift in one path than
the other. Ideally, the phase response over frequency through the two sides of a differential signal path are
identical, such that even-order harmonics remain optimally out of phase and cancel when the signal is taken
differentially. However, if one side has more phase shift than the other, then the even-order harmonic
cancellation is not as effective.
Single-order RC filters cause very little differential phase shift with nominal tolerances of 5% or less, but higherorder LC filters are very sensitive to component mismatch. For instance, a third-order Butterworth band-pass
filter with a 100-MHz center frequency and a 20-MHz bandwidth creates as much as 20° of differential phase
imbalance in a SPICE Monte Carlo analysis with 2% component tolerances. Therefore, although a prototype may
work, production variance is unacceptable. In ac-coupled applications that require second- and higher-order
filters between the LMH5401-SP and the ADC, a transformer or balun is recommended at the ADC input to
restore the phase balance. For dc-coupled applications where a transformer or balun at the ADC input cannot be
used, using first- or second-order filters is recommended to minimize the effect of differential phase shift because
of the component tolerance.
38
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
10.2.2.4.3 ADC Input Common-Mode Voltage Considerations—AC-Coupled Input
The input common-mode voltage range of the ADC must be respected for proper operation. In an ac-coupled
application between the amplifier and the ADC, the input common-mode voltage bias of the ADC is
accomplished in different ways depending on the ADC. Some ADCs use internal bias networks such that the
analog inputs are automatically biased to the required input common-mode voltage if the inputs are ac-coupled
with capacitors (or if the filter between the amplifier and ADC is a band-pass filter). Other ADCs supply their
required input common-mode voltage from a reference voltage output pin (often called CM or VCM). With these
ADCs, the ac-coupled input signal can be re-biased to the input common-mode voltage by connecting resistors
from each input to the CM output of the ADC, as Figure 64 shows. However, the signal is attenuated because of
the voltage divider created by RCM and RO.
RO
RCM
AIN+
Amp
ADC
AIN-
RCM
CM
RO
Figure 64. Biasing AC-Coupled ADC Inputs Using the ADC CM Output
The signal can be re-biased when ac coupling; thus, the output common-mode voltage of the amplifier is a don’t
care for the ADC.
10.2.2.4.4 ADC Input Common-Mode Voltage Considerations—DC-Coupled Input
DC-coupled applications vary in complexity and requirements, depending on the ADC. One typical requirement is
resolving the mismatch between the common-mode voltage of the driving amplifier and the ADC. Devices such
as the ADS5424 require a nominal 2.4-V input common-mode, whereas other devices such as the ADS5485
require a nominal 3.1-V input common-mode; still others such as the ADS6149 and the ADS4149 require 1.5 V
and 0.95 V, respectively. As shown in Figure 65, a resistor network can be used to perform a common-mode
level shift. This resistor network consists of the amplifier series output resistors and pull-up or pull-down resistors
to a reference voltage. This resistor network introduces signal attenuation that may prevent the use of the fullscale input range of the ADC. ADCs with an input common-mode closer to the typical 2.5-V LMH5401-SP output
common-mode are easier to dc-couple, and require little or no level shifting.
VREF
VAMP+
RO
RP
ADC
VADC+
Amp
RIN
VAMP-
RO
RP
CIN
VADC-
VREF
Figure 65. Resistor Network to DC Level-Shift Common-Mode Voltage
For common-mode analysis of the circuit in Figure 65, assume that VAMP± = VCM and VADC± = VCM (the
specification for the ADC input common-mode voltage). VREF is chosen to be a voltage within the system higher
than VCM (such as the ADC or amplifier analog supply) or ground, depending on whether the voltage must be
pulled up or down, respectively; RO is chosen to be a reasonable value, such as 24.9 Ω. With these known
values, RP can be found by using Equation 15:
RP = RO
VADC - VREF
VAMP - VADC
(15)
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
39
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
Shifting the common-mode voltage with the resistor network comes at the expense of signal attenuation.
Modeling the ADC input as the parallel combination of a resistance (RIN) and capacitance (CIN) using values
taken from the ADC data sheet, the approximate differential input impedance (ZIN) for the ADC can be calculated
at the signal frequency. The effect of CIN on the overall calculation of gain is typically minimal and can be ignored
for simplicity (that is, ZIN = RIN). The ADC input impedance creates a divider with the resistor network; the gain
(attenuation) for this divider can be calculated by Equation 16:
GAIN =
2RP || ZIN
2RO + 2RP || ZIN
(16)
With ADCs that have internal resistors that bias the ADC input to the ADC input common-mode voltage, the
effective RIN is equal to twice the value of the bias resistor. For example, the ADS5485 has a 1-kΩ resistor tying
each input to the ADC VCM; therefore, the effective differential RIN is 2 kΩ.
The introduction of the RP resistors also modifies the effective load that must be driven by the amplifier.
Equation 17 shows the effective load created when using the RP resistors.
RL = 2RO + 2RP || ZIN
(17)
The RP resistors function in parallel to the ADC input such that the effective load (output current) at the amplifier
output is increased. Higher current loads limit the LMH5401-SP differential output swing.
By using the gain and knowing the full-scale input of the ADC (VADC
with the network can be calculated using Equation 18:
V
VAMP PP = ADC FS
GAIN
FS),
the required amplitude to drive the ADC
(18)
As with any design, testing is recommended to validate whether the specific design goals are met.
10.2.2.5 GSPS ADC Driver
The LMH5401-SP can drive the full Nyquist bandwidth of ADCs with sampling rates up to 4 GSPS, as shown in
Figure 66. If the front-end bandwidth of the ADC is more than 2 GHz, use a simple noise filter to improve SNR.
Otherwise, the ADC can be connected directly to the amplifier output pins. Matching resistors may not be
required, however allow space for matching resistors on the preliminary design.
25
LMH5401-SP
RT
50Single-Ended
Input
+
RF
RG
10
IN±
IN+
±
O
IN+
+
OUT_AMP
±
+
10
RG
RM
OUT+ R
±
RO
Filter
ADC12D1620QML-SP
IN±
OUT±
RF
25
CM
Copyright © 2017, Texas Instruments Incorporated
Figure 66. GSPS ADC Driver
40
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
10.2.2.6 Common-Mode Voltage Correction
The LMH5401-SP can set the output common-mode voltage to within a typical value of ±30 mV. If greater
accuracy is desired, a simple circuit can improve this accuracy by an order of magnitude. A precision, low-power
operational amplifier is used to sense the error in the output common-mode of the LMH5401-SP and corrects the
error by adjusting the voltage at the CM pin. In Figure 67, the precision of the op amp replaces the less accurate
precision of the LMH5401-SP common-mode control circuit while still using the LMH5401-SP common-mode
control circuit speed. The op amp in this circuit must have better than a 1-mV input-referred offset voltage and
low noise. Otherwise the specifications are not very critical because the LMH5401-SP is responsible for the
entire differential signal path.
OUT+
IN±
±
CM
IN+
FB+
5k
+
LMH5401-SP
±
+ FB±
5k
OUT±
10 nF
±
LMV771
+
Desired
VOCM
Copyright © 2017, Texas Instruments Incorporated
Figure 67. Common-Mode Correction Circuit
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
41
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
10.2.2.7 Active Balun
The LMH5401-SP is designed to convert single-ended signals to a differential output with very high bandwidth
and linearity, as shown in Figure 68. The LMH5401-SP can support dc coupling as well as ac coupling. The
LMH5401-SP is smaller than any balun with low-frequency response and has excellent amplitude and phase
balance over a wide frequency range. As shown in , the LMH5401-SP amplitude imbalance is near 0 dB up to 1
GHz when used with a 5-V supply. plots all S-parameters showing superior wideband input and output return
loss compared to many baluns.
RF
Single-Ended Input
25
LMH5401-SP
RT
RG
FB+
OUT+
10
IN±
RO
±
+
±
+
OUT_AMP
±
IN+
RO
Differential
Output
+
10
RG
RM
OUT±
RF
FB±
25
CM
Copyright © 2017, Texas Instruments Incorporated
Figure 68. Active Balun
210
Differential Output Phase (degrees)
Output Amplitude Imbalance (dB)
15
10
5
0
-5
-10
-15
10
100
1k
Frequency (MHz)
10k
200
190
180
170
160
150
10
SBOS
Figure 69. SE-DE Amplitude Imbalance
42
Submit Documentation Feedback
100
1k
Frequency (MHz)
10k
SBOS
Figure 70. SE-DE Phase Imbalance
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
20
10
S-Parameters (dB)
0
-10
-20
-30
-40
-50
-60
Sds21
Sss11
Sdd22
Ssd12
-70
-80
-90
10
100
1k
Frequency (MHz)
10k
SBOS
Figure 71. SE-DE Small Signal S-Parameters
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
43
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
10.2.3 Application Curves
7
17
6
16
15
5
Gain (dB)
Resistor Loss (dB)
The LMH5401-SP has on-chip series output resistors to isolate the output of the amplifier. These resistors
provide the LMH5401-SP extra phase margin in most applications. When the amplifier is used to drive a
terminated transmission line or a controlled impedance filter, additional external resistance is required to match
the transmission line of the filter. In these matched applications, there is a 6 dB loss of gain. When the
LMH5401-SP is used to drive loads that are not back-terminated, or matched, there is a loss in gain resulting
from the on-chip resistors. Figure 72 shows that loss for different load conditions. In most cases the loads are
between 50 Ω and 200 Ω, where the on-chip resistor losses are 1.6 dB and 0.42 dB, respectively. As an
example, if the LMH5401-SP were to drive an ADC with a differential input impedance of 100 ohms without any
matching components the signal loss would be 0.83dB compared to 6dB in a matched configuration. Of course,
this is only feasible if the LMH5401-SP and the ADC are placed in close proximity (< 1/4 wavelength of the
frequency of interest) so as to avoid standing waves from reflections due to the mismatch in impedances).
Figure 73 shows the net gain realized by the amplifier for a large range of load resistances when the LMH5401SP is configured for 16-dB gain.
4
3
2
14
13
12
11
1
10
0
9
10
100
1k
External Load (Ÿ)
10k
10
100
Figure 72. Gain Loss Resulting from On-Chip Output
Resistors
1k
External Load (Ÿ)
C072
10k
C073
Figure 73. Net Gain versus Load Resistance
10.3 Do's and Don'ts
10.3.1 Do:
• Include a thermal design at the beginning of the project.
• Use well-terminated transmission lines for all signals.
• Use solid metal layers for the power supplies.
• Keep signal lines as straight as possible.
• Use split supplies where required.
10.3.2 Don't:
• Use a lower supply voltage than necessary.
• Use thin metal traces to supply power.
• Forget about the common-mode response of filters and transmission lines.
44
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
11 Power Supply Recommendations
The LMH5401-SP can be used with either split or single-ended power supplies. The ideal supply voltage is a
5-V total supply, split around the desired common-mode of the output signal swing. For example, if the
LMH5401-SP is used to drive an ADC with a 1-V input common mode, then the ideal supply voltages are 3.5 V
and –1.5 V. The GND pin can then be connected to the system ground and the PD pin is ground referenced.
11.1 Supply Voltage
Using a 5-V power supply gives the best balance of performance and power dissipation. If power dissipation is a
critical design criteria, a power supply as low as 3.3 V (±1.65) can be used. When using a lower power supply,
the input common-mode and output swing capabilities are drastically reduced. Make sure to study the commonmode voltages required before deciding on a lower-voltage power supply. In most cases the extra performance
achieved with 5-V supplies is worth the power.
11.2 Single Supply
Single-supply voltages from 3.3 V to 5 V are supported. When using a single supply check both the input and
output common-mode voltages that are required by the system.
11.3 Split Supply
In general, split supplies allow the most flexibility in system design. To operate as split supply, apply the positive
supply voltage to VS+, the negative supply voltage to VS–, and the ground reference to GND. Note that supply
voltages do not need to be symmetrical. Provided the total supply voltage is between 3.3 V and 5.25 V, any
combination of positive and negative supply voltages is acceptable. This feature is often used when the output
common-mode voltage must be set to a particular value. For best performance, the power-supply voltages are
symmetrical around the desired output common-mode voltage. The input common-mode voltage range is much
more flexible than the output.
11.4 Supply Decoupling
Power-supply decoupling is critical to high-frequency performance. Onboard bypass capacitors are used on the
LMH5401-SPEVM; however, the most important component of the supply bypassing is provided by the PCB. As
illustrated in Figure 74, there are multiple vias connecting the LMH5401-SP power planes to the power-supply
traces. These vias connect the internal power planes to the LMH5401-SP. Both VS+ and VS– must be
connected to the internal power planes with several square centimeters of continuous plane in the immediate
vicinity of the amplifier. The capacitance between these power planes provides the bulk of the high-frequency
bypassing for the LMH5401-SP.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
45
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
12 Layout
12.1 Layout Guidelines
With a GBP of 6.5 GHz, layout for the LMH5401-SP is critical and nothing can be neglected. In order to simplify
board design, the LMH5401-SP has on-chip resistors that reduce the affect of off-chip capacitance. For this
reason, TI recommends that the ground layer below the LMH5401-SP not be cut. The recommendation not to cut
the ground plane under the amplifier input and output pins is different than many other high-speed amplifiers, but
the reason is that parasitic inductance is more harmful to the LMH5401-SP performance than parasitic
capacitance. By leaving the ground layer under the device intact, parasitic inductance of the output and power
traces is minimized. The DUT portion of the evaluation board layout is illustrated in Figure 74 and .
The EVM uses long-edge capacitors for the decoupling capacitors, which reduces series resistance and
increases the resonant frequency. Vias are also placed to the power planes before the bypass capacitors.
Although not evident in the top layer, two vias are used at the capacitor in addition to the two vias underneath the
device.
The output matching resistors are 0402 size and are placed very close to the amplifier output pins, which
reduces both parasitic inductance and capacitance. The use of 0603 output matching resistors produces a
measurable decrease in bandwidth.
When the signal is on a 50-Ω controlled impedance transmission line, the layout then becomes much less critical.
The transition from the 50-Ω transmission line to the amplifier pins is the most critical area.
The CM pin also requires a bypass capacitor. Place this capacitor near the device. Refer to the user guide
LMH5401EVM-CVAL Evaluation Module (SLOU478) for more details on board layout and design.
12.2 Layout Example
Figure 74. Layout Example
46
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
LMH5401-SP
www.ti.com
SBOS849 – DECEMBER 2017
13 Device and Documentation Support
13.1 Device Support
13.1.1 Device Nomenclature
Pin 1
YQFB THA
5962–
Q
SRN
1721401VXC
LMH5401
YYWWLLZ
\T/
YQ
B
F
THA
Q
SRN
YYWW
LL
Z
\T/
= DIFF DATE
= DIE REV. '–'FOR NO REV
= F/E CODE (2 DIGITS MAX)
= COUNTRY CODE
= QML
= SERIAL NUMBER
= SEAL DATE
= LOT WINDOW
= B/I SPLIT LOT
= TI LOGO
Figure 75. Device Marking Information
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• ADC12D1x00 12-Bit, 2.0/3.2 GSPS Ultra High-Speed ADC SNAS480
• ADC12D1620QMP-SP 12-Bit, Single or Dual, 3200- or 1600-MSPS RF Sampling ADC SNAS717
• Rad-Tolerant Class V, Wideband, Fully Differential Amplifier SLOS538
• Rad-Tolerant Class V, Wideband, Fully Differential Amplifier SLOS539
• LMH5401-SP TINA Modes
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
47
LMH5401-SP
SBOS849 – DECEMBER 2017
www.ti.com
13.5 Trademarks
E2E is a trademark of Texas Instruments.
Marki is a trademark of Marki Microwave, Inc.
Rohde & Schwarz is a registered trademark of Rohde & Schwarz.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
48
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMH5401-SP
PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-1721401VXC
ACTIVE
LCCC
FFK
14
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
59621721401VXC
LMH5401
LMH5401FFK/EM
ACTIVE
LCCC
FFK
14
1
TBD
Call TI
N / A for Pkg Type
25 to 25
LMH5401FFK
/EM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2017
OTHER QUALIFIED VERSIONS OF LMH5401-SP :
• Catalog: LMH5401
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated